1/** 2\defgroup pmu8_functions PMU Functions for Armv8.1-M 3\brief Functions that relate to the Performance Monitoring Unit. 4\details 5The following functions support the Performance Monitoring Unit (PMU) that is available on the Cortex-M55/M85 processors. 6 7The PMU is used to monitor events that occur during run-time of an application. 8 9<b>Example:</b> 10\code 11// Initialize counter variables 12 13unsigned int cycle_count = 0; 14unsigned int l1_dcache_miss_count = 0; 15unsigned int instructions_retired_count = 0; 16 17// Enable the PMU 18// Note: Before using the PMU, software needs to ensure 19// that trace is enabled via the Debug Exception Monitor Control Register, DEMCR: 20// CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; 21 22ARM_PMU_Enable(); 23 24// Configure Event Counter Register 0 to count instructions retired 25// Configure Event Counter Register 1 to count L1 D-Cache misses 26 27ARM_PMU_Set_EVTYPER(0, ARM_PMU_INST_RETIRED); 28ARM_PMU_Set_EVTYPER(1, ARM_PMU_L1D_CACHE_MISS_RD); 29 30// Reset Event Counters and Cycle Counter 31 32ARM_PMU_EVCNTR_ALL_Reset(); 33ARM_PMU_CYCCNT_Reset(); 34 35// Start incrementing Cycle Count Register and Event Counter Registers 0 & 1 36 37ARM_PMU_CNTR_Enable(PMU_CNTENSET_CCNTR_ENABLE_Msk|PMU_CNTENSET_CNT0_ENABLE_Msk|PMU_CNTENSET_CNT1_ENABLE_Msk); 38 39// Code you want to measure here 40 41// Stop incrementing Cycle Count Register and Event Counter Registers 0 & 1 42 43ARM_PMU_CNTR_Disable(PMU_CNTENCLR_CCNTR_ENABLE_Msk|PMU_CNTENCLR_CNT0_ENABLE_Msk|PMU_CNTENCLR_CNT1_ENABLE_Msk); 44 45// Get cycle count, number of instructions retired and number of L1 D-Cache misses (on read) 46 47cycle_count = cycle_count + ARM_PMU_Get_CCNTR(); 48instructions_retired_count = instructions_retired_count + ARM_PMU_Get_EVCNTR(0); 49l1_dcache_miss_count = l1_dcache_miss_count + ARM_PMU_Get_EVCNTR(1); // Note: D-Cache must be enabled using 50 // SCB_EnableDCache() for meaningful result. 51\endcode 52 53@{ 54*/ 55 56/** 57\defgroup pmu8_events_armv81 PMU Events for Armv8.1-M 58\ingroup pmu8_functions 59\brief IDs for Armv8.1-M architecture defined events. 60\details 61These events are available on all Armv8.1-M devices including a PMU. 62@{ 63*/ 64 65#define ARM_PMU_SW_INCR 0x0000 /*!< \brief Software update to the PMU_SWINC register, architecturally executed and condition code check pass */ 66#define ARM_PMU_L1I_CACHE_REFILL 0x0001 /*!< \brief L1 I-Cache refill */ 67#define ARM_PMU_L1D_CACHE_REFILL 0x0003 /*!< \brief L1 D-Cache refill */ 68#define ARM_PMU_L1D_CACHE 0x0004 /*!< \brief L1 D-Cache access */ 69#define ARM_PMU_LD_RETIRED 0x0006 /*!< \brief Memory-reading instruction architecturally executed and condition code check pass */ 70#define ARM_PMU_ST_RETIRED 0x0007 /*!< \brief Memory-writing instruction architecturally executed and condition code check pass */ 71#define ARM_PMU_INST_RETIRED 0x0008 /*!< \brief Instruction architecturally executed */ 72#define ARM_PMU_EXC_TAKEN 0x0009 /*!< \brief Exception entry */ 73#define ARM_PMU_EXC_RETURN 0x000A /*!< \brief Exception return instruction architecturally executed and the condition code check pass */ 74#define ARM_PMU_PC_WRITE_RETIRED 0x000C /*!< \brief Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass */ 75#define ARM_PMU_BR_IMMED_RETIRED 0x000D /*!< \brief Immediate branch architecturally executed */ 76#define ARM_PMU_BR_RETURN_RETIRED 0x000E /*!< \brief Function return instruction architecturally executed and the condition code check pass */ 77#define ARM_PMU_UNALIGNED_LDST_RETIRED 0x000F /*!< \brief Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass */ 78#define ARM_PMU_BR_MIS_PRED 0x0010 /*!< \brief Mispredicted or not predicted branch speculatively executed */ 79#define ARM_PMU_CPU_CYCLES 0x0011 /*!< \brief Cycle */ 80#define ARM_PMU_BR_PRED 0x0012 /*!< \brief Predictable branch speculatively executed */ 81#define ARM_PMU_MEM_ACCESS 0x0013 /*!< \brief Data memory access */ 82#define ARM_PMU_L1I_CACHE 0x0014 /*!< \brief Level 1 instruction cache access */ 83#define ARM_PMU_L1D_CACHE_WB 0x0015 /*!< \brief Level 1 data cache write-back */ 84#define ARM_PMU_L2D_CACHE 0x0016 /*!< \brief Level 2 data cache access */ 85#define ARM_PMU_L2D_CACHE_REFILL 0x0017 /*!< \brief Level 2 data cache refill */ 86#define ARM_PMU_L2D_CACHE_WB 0x0018 /*!< \brief Level 2 data cache write-back */ 87#define ARM_PMU_BUS_ACCESS 0x0019 /*!< \brief Bus access */ 88#define ARM_PMU_MEMORY_ERROR 0x001A /*!< \brief Local memory error */ 89#define ARM_PMU_INST_SPEC 0x001B /*!< \brief Instruction speculatively executed */ 90#define ARM_PMU_BUS_CYCLES 0x001D /*!< \brief Bus cycles */ 91#define ARM_PMU_CHAIN 0x001E /*!< \brief For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE */ 92#define ARM_PMU_L1D_CACHE_ALLOCATE 0x001F /*!< \brief Level 1 data cache allocation without refill */ 93#define ARM_PMU_L2D_CACHE_ALLOCATE 0x0020 /*!< \brief Level 2 data cache allocation without refill */ 94#define ARM_PMU_BR_RETIRED 0x0021 /*!< \brief Branch instruction architecturally executed */ 95#define ARM_PMU_BR_MIS_PRED_RETIRED 0x0022 /*!< \brief Mispredicted branch instruction architecturally executed */ 96#define ARM_PMU_STALL_FRONTEND 0x0023 /*!< \brief No operation issued because of the frontend */ 97#define ARM_PMU_STALL_BACKEND 0x0024 /*!< \brief No operation issued because of the backend */ 98#define ARM_PMU_L2I_CACHE 0x0027 /*!< \brief Level 2 instruction cache access */ 99#define ARM_PMU_L2I_CACHE_REFILL 0x0028 /*!< \brief Level 2 instruction cache refill */ 100#define ARM_PMU_L3D_CACHE_ALLOCATE 0x0029 /*!< \brief Level 3 data cache allocation without refill */ 101#define ARM_PMU_L3D_CACHE_REFILL 0x002A /*!< \brief Level 3 data cache refill */ 102#define ARM_PMU_L3D_CACHE 0x002B /*!< \brief Level 3 data cache access */ 103#define ARM_PMU_L3D_CACHE_WB 0x002C /*!< \brief Level 3 data cache write-back */ 104#define ARM_PMU_LL_CACHE_RD 0x0036 /*!< \brief Last level data cache read */ 105#define ARM_PMU_LL_CACHE_MISS_RD 0x0037 /*!< \brief Last level data cache read miss */ 106#define ARM_PMU_L1D_CACHE_MISS_RD 0x0039 /*!< \brief Level 1 data cache read miss */ 107#define ARM_PMU_OP_COMPLETE 0x003A /*!< \brief Operation retired */ 108#define ARM_PMU_OP_SPEC 0x003B /*!< \brief Operation speculatively executed */ 109#define ARM_PMU_STALL 0x003C /*!< \brief Stall cycle for instruction or operation not sent for execution */ 110#define ARM_PMU_STALL_OP_BACKEND 0x003D /*!< \brief Stall cycle for instruction or operation not sent for execution due to pipeline backend */ 111#define ARM_PMU_STALL_OP_FRONTEND 0x003E /*!< \brief Stall cycle for instruction or operation not sent for execution due to pipeline frontend */ 112#define ARM_PMU_STALL_OP 0x003F /*!< \brief Instruction or operation slots not occupied each cycle */ 113#define ARM_PMU_L1D_CACHE_RD 0x0040 /*!< \brief Level 1 data cache read */ 114#define ARM_PMU_LE_RETIRED 0x0100 /*!< \brief Loop end instruction executed */ 115#define ARM_PMU_LE_SPEC 0x0101 /*!< \brief Loop end instruction speculatively executed */ 116#define ARM_PMU_BF_RETIRED 0x0104 /*!< \brief Branch future instruction architecturally executed and condition code check pass */ 117#define ARM_PMU_BF_SPEC 0x0105 /*!< \brief Branch future instruction speculatively executed and condition code check pass */ 118#define ARM_PMU_LE_CANCEL 0x0108 /*!< \brief Loop end instruction not taken */ 119#define ARM_PMU_BF_CANCEL 0x0109 /*!< \brief Branch future instruction not taken */ 120#define ARM_PMU_SE_CALL_S 0x0114 /*!< \brief Call to secure function, resulting in Security state change */ 121#define ARM_PMU_SE_CALL_NS 0x0115 /*!< \brief Call to non-secure function, resulting in Security state change */ 122#define ARM_PMU_DWT_CMPMATCH0 0x0118 /*!< \brief DWT comparator 0 match */ 123#define ARM_PMU_DWT_CMPMATCH1 0x0119 /*!< \brief DWT comparator 1 match */ 124#define ARM_PMU_DWT_CMPMATCH2 0x011A /*!< \brief DWT comparator 2 match */ 125#define ARM_PMU_DWT_CMPMATCH3 0x011B /*!< \brief DWT comparator 3 match */ 126#define ARM_PMU_MVE_INST_RETIRED 0x0200 /*!< \brief MVE instruction architecturally executed */ 127#define ARM_PMU_MVE_INST_SPEC 0x0201 /*!< \brief MVE instruction speculatively executed */ 128#define ARM_PMU_MVE_FP_RETIRED 0x0204 /*!< \brief MVE floating-point instruction architecturally executed */ 129#define ARM_PMU_MVE_FP_SPEC 0x0205 /*!< \brief MVE floating-point instruction speculatively executed */ 130#define ARM_PMU_MVE_FP_HP_RETIRED 0x0208 /*!< \brief MVE half-precision floating-point instruction architecturally executed */ 131#define ARM_PMU_MVE_FP_HP_SPEC 0x0209 /*!< \brief MVE half-precision floating-point instruction speculatively executed */ 132#define ARM_PMU_MVE_FP_SP_RETIRED 0x020C /*!< \brief MVE single-precision floating-point instruction architecturally executed */ 133#define ARM_PMU_MVE_FP_SP_SPEC 0x020D /*!< \brief MVE single-precision floating-point instruction speculatively executed */ 134#define ARM_PMU_MVE_FP_MAC_RETIRED 0x0214 /*!< \brief MVE floating-point multiply or multiply-accumulate instruction architecturally executed */ 135#define ARM_PMU_MVE_FP_MAC_SPEC 0x0215 /*!< \brief MVE floating-point multiply or multiply-accumulate instruction speculatively executed */ 136#define ARM_PMU_MVE_INT_RETIRED 0x0224 /*!< \brief MVE integer instruction architecturally executed */ 137#define ARM_PMU_MVE_INT_SPEC 0x0225 /*!< \brief MVE integer instruction speculatively executed */ 138#define ARM_PMU_MVE_INT_MAC_RETIRED 0x0228 /*!< \brief MVE multiply or multiply-accumulate instruction architecturally executed */ 139#define ARM_PMU_MVE_INT_MAC_SPEC 0x0229 /*!< \brief MVE multiply or multiply-accumulate instruction speculatively executed */ 140#define ARM_PMU_MVE_LDST_RETIRED 0x0238 /*!< \brief MVE load or store instruction architecturally executed */ 141#define ARM_PMU_MVE_LDST_SPEC 0x0239 /*!< \brief MVE load or store instruction speculatively executed */ 142#define ARM_PMU_MVE_LD_RETIRED 0x023C /*!< \brief MVE load instruction architecturally executed */ 143#define ARM_PMU_MVE_LD_SPEC 0x023D /*!< \brief MVE load instruction speculatively executed */ 144#define ARM_PMU_MVE_ST_RETIRED 0x0240 /*!< \brief MVE store instruction architecturally executed */ 145#define ARM_PMU_MVE_ST_SPEC 0x0241 /*!< \brief MVE store instruction speculatively executed */ 146#define ARM_PMU_MVE_LDST_CONTIG_RETIRED 0x0244 /*!< \brief MVE contiguous load or store instruction architecturally executed */ 147#define ARM_PMU_MVE_LDST_CONTIG_SPEC 0x0245 /*!< \brief MVE contiguous load or store instruction speculatively executed */ 148#define ARM_PMU_MVE_LD_CONTIG_RETIRED 0x0248 /*!< \brief MVE contiguous load instruction architecturally executed */ 149#define ARM_PMU_MVE_LD_CONTIG_SPEC 0x0249 /*!< \brief MVE contiguous load instruction speculatively executed */ 150#define ARM_PMU_MVE_ST_CONTIG_RETIRED 0x024C /*!< \brief MVE contiguous store instruction architecturally executed */ 151#define ARM_PMU_MVE_ST_CONTIG_SPEC 0x024D /*!< \brief MVE contiguous store instruction speculatively executed */ 152#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED 0x0250 /*!< \brief MVE non-contiguous load or store instruction architecturally executed */ 153#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC 0x0251 /*!< \brief MVE non-contiguous load or store instruction speculatively executed */ 154#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED 0x0254 /*!< \brief MVE non-contiguous load instruction architecturally executed */ 155#define ARM_PMU_MVE_LD_NONCONTIG_SPEC 0x0255 /*!< \brief MVE non-contiguous load instruction speculatively executed */ 156#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED 0x0258 /*!< \brief MVE non-contiguous store instruction architecturally executed */ 157#define ARM_PMU_MVE_ST_NONCONTIG_SPEC 0x0259 /*!< \brief MVE non-contiguous store instruction speculatively executed */ 158#define ARM_PMU_MVE_LDST_MULTI_RETIRED 0x025C /*!< \brief MVE memory instruction targeting multiple registers architecturally executed */ 159#define ARM_PMU_MVE_LDST_MULTI_SPEC 0x025D /*!< \brief MVE memory instruction targeting multiple registers speculatively executed */ 160#define ARM_PMU_MVE_LD_MULTI_RETIRED 0x0260 /*!< \brief MVE memory load instruction targeting multiple registers architecturally executed */ 161#define ARM_PMU_MVE_LD_MULTI_SPEC 0x0261 /*!< \brief MVE memory load instruction targeting multiple registers speculatively executed */ 162#define ARM_PMU_MVE_ST_MULTI_RETIRED 0x0261 /*!< \brief MVE memory store instruction targeting multiple registers architecturally executed */ 163#define ARM_PMU_MVE_ST_MULTI_SPEC 0x0265 /*!< \brief MVE memory store instruction targeting multiple registers speculatively executed */ 164#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED 0x028C /*!< \brief MVE unaligned memory load or store instruction architecturally executed */ 165#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC 0x028D /*!< \brief MVE unaligned memory load or store instruction speculatively executed */ 166#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED 0x0290 /*!< \brief MVE unaligned load instruction architecturally executed */ 167#define ARM_PMU_MVE_LD_UNALIGNED_SPEC 0x0291 /*!< \brief MVE unaligned load instruction speculatively executed */ 168#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED 0x0294 /*!< \brief MVE unaligned store instruction architecturally executed */ 169#define ARM_PMU_MVE_ST_UNALIGNED_SPEC 0x0295 /*!< \brief MVE unaligned store instruction speculatively executed */ 170#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED 0x0298 /*!< \brief MVE unaligned noncontiguous load or store instruction architecturally executed */ 171#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC 0x0299 /*!< \brief MVE unaligned noncontiguous load or store instruction speculatively executed */ 172#define ARM_PMU_MVE_VREDUCE_RETIRED 0x02A0 /*!< \brief MVE vector reduction instruction architecturally executed */ 173#define ARM_PMU_MVE_VREDUCE_SPEC 0x02A1 /*!< \brief MVE vector reduction instruction speculatively executed */ 174#define ARM_PMU_MVE_VREDUCE_FP_RETIRED 0x02A4 /*!< \brief MVE floating-point vector reduction instruction architecturally executed */ 175#define ARM_PMU_MVE_VREDUCE_FP_SPEC 0x02A5 /*!< \brief MVE floating-point vector reduction instruction speculatively executed */ 176#define ARM_PMU_MVE_VREDUCE_INT_RETIRED 0x02A8 /*!< \brief MVE integer vector reduction instruction architecturally executed */ 177#define ARM_PMU_MVE_VREDUCE_INT_SPEC 0x02A9 /*!< \brief MVE integer vector reduction instruction speculatively executed */ 178#define ARM_PMU_MVE_PRED 0x02B8 /*!< \brief Cycles where one or more predicated beats architecturally executed */ 179#define ARM_PMU_MVE_STALL 0x02CC /*!< \brief Stall cycles caused by an MVE instruction */ 180#define ARM_PMU_MVE_STALL_RESOURCE 0x02CD /*!< \brief Stall cycles caused by an MVE instruction because of resource conflicts */ 181#define ARM_PMU_MVE_STALL_RESOURCE_MEM 0x02CE /*!< \brief Stall cycles caused by an MVE instruction because of memory resource conflicts */ 182#define ARM_PMU_MVE_STALL_RESOURCE_FP 0x02CF /*!< \brief Stall cycles caused by an MVE instruction because of floating-point resource conflicts */ 183#define ARM_PMU_MVE_STALL_RESOURCE_INT 0x02D0 /*!< \brief Stall cycles caused by an MVE instruction because of integer resource conflicts */ 184#define ARM_PMU_MVE_STALL_BREAK 0x02D3 /*!< \brief Stall cycles caused by an MVE chain break */ 185#define ARM_PMU_MVE_STALL_DEPENDENCY 0x02D4 /*!< \brief Stall cycles caused by MVE register dependency */ 186#define ARM_PMU_ITCM_ACCESS 0x4007 /*!< \brief Instruction TCM access */ 187#define ARM_PMU_DTCM_ACCESS 0x4008 /*!< \brief Data TCM access */ 188#define ARM_PMU_TRCEXTOUT0 0x4010 /*!< \brief ETM external output 0 */ 189#define ARM_PMU_TRCEXTOUT1 0x4011 /*!< \brief ETM external output 1 */ 190#define ARM_PMU_TRCEXTOUT2 0x4012 /*!< \brief ETM external output 2 */ 191#define ARM_PMU_TRCEXTOUT3 0x4013 /*!< \brief ETM external output 3 */ 192#define ARM_PMU_CTI_TRIGOUT4 0x4018 /*!< \brief Cross-trigger Interface output trigger 4 */ 193#define ARM_PMU_CTI_TRIGOUT5 0x4019 /*!< \brief Cross-trigger Interface output trigger 5 */ 194#define ARM_PMU_CTI_TRIGOUT6 0x401A /*!< \brief Cross-trigger Interface output trigger 6 */ 195#define ARM_PMU_CTI_TRIGOUT7 0x401B /*!< \brief Cross-trigger Interface output trigger 7 */ 196 197/** @} */ 198 199/** 200\defgroup pmu8_events_armcm55 PMU Events for Cortex-M55 201\ingroup pmu8_functions 202\brief IDs for additional events defined for Cortex-M55. 203\details 204These events are available on a Cortex-M55 device including a PMU. 205@{ 206*/ 207 208#define ARMCM55_PMU_ECC_ERR 0xC000 /*!< \brief Any ECC error */ 209#define ARMCM55_PMU_ECC_ERR_FATAL 0xC001 /*!< \brief Any fatal ECC error */ 210#define ARMCM55_PMU_ECC_ERR_DCACHE 0xC010 /*!< \brief Any ECC error in the data cache */ 211#define ARMCM55_PMU_ECC_ERR_ICACHE 0xC011 /*!< \brief Any ECC error in the instruction cache */ 212#define ARMCM55_PMU_ECC_ERR_FATAL_DCACHE 0xC012 /*!< \brief Any fatal ECC error in the data cache */ 213#define ARMCM55_PMU_ECC_ERR_FATAL_ICACHE 0xC013 /*!< \brief Any fatal ECC error in the instruction cache*/ 214#define ARMCM55_PMU_ECC_ERR_DTCM 0xC020 /*!< \brief Any ECC error in the DTCM */ 215#define ARMCM55_PMU_ECC_ERR_ITCM 0xC021 /*!< \brief Any ECC error in the ITCM */ 216#define ARMCM55_PMU_ECC_ERR_FATAL_DTCM 0xC022 /*!< \brief Any fatal ECC error in the DTCM */ 217#define ARMCM55_PMU_ECC_ERR_FATAL_ITCM 0xC023 /*!< \brief Any fatal ECC error in the ITCM */ 218#define ARMCM55_PMU_PF_LINEFILL 0xC100 /*!< \brief A prefetcher starts a line-fill */ 219#define ARMCM55_PMU_PF_CANCEL 0xC101 /*!< \brief A prefetcher stops prefetching */ 220#define ARMCM55_PMU_PF_DROP_LINEFILL 0xC102 /*!< \brief A linefill triggered by a prefetcher has been dropped because of lack of buffering */ 221#define ARMCM55_PMU_NWAMODE_ENTER 0xC200 /*!< \brief No write-allocate mode entry */ 222#define ARMCM55_PMU_NWAMODE 0xC201 /*!< \brief Write-allocate store is not allocated into the data cache due to no-write-allocate mode */ 223#define ARMCM55_PMU_SAHB_ACCESS 0xC300 /*!< \brief Read or write access on the S-AHB interface to the TCM */ 224#define ARMCM55_PMU_SAHB_ACCESS 0xC300 /*!< \brief Read or write access on the S-AHB interface to the TCM */ 225#define ARMCM55_PMU_PAHB_ACCESS 0xC301 /*!< \brief Read or write access on the P-AHB interface */ 226#define ARMCM55_PMU_AXI_WRITE_ACCESS 0xC302 /*!< \brief Any beat access to M-AXI write interface */ 227#define ARMCM55_PMU_AXI_READ_ACCESS 0xC303 /*!< \brief Any beat access to M-AXI read interface */ 228#define ARMCM55_PMU_DOSTIMEOUT_DOUBLE 0xC400 /*!< \brief Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */ 229#define ARMCM55_PMU_DOSTIMEOUT_TRIPLE 0xC401 /*!< \brief Denial of Service timeout has fired three times and blocked the LSU to force forward progress */ 230 231/** @} */ 232 233/** 234\defgroup pmu8_events_armcm85 PMU Events for Cortex-M85 235\ingroup pmu8_functions 236\brief IDs for additional events defined for Cortex-M85. 237\details 238These events are available on a Cortex-M85 device including a PMU. 239@{ 240*/ 241 242#define ARMCM85_PMU_ECC_ERR 0xC000 /*!< \brief Any ECC error */ 243#define ARMCM85_PMU_ECC_ERR_MBIT 0xC001 /*!< \brief Any multi-bit ECC error */ 244#define ARMCM85_PMU_ECC_ERR_DCACHE 0xC010 /*!< \brief Any ECC error in the data cache */ 245#define ARMCM85_PMU_ECC_ERR_ICACHE 0xC011 /*!< \brief Any ECC error in the instruction cache */ 246#define ARMCM85_PMU_ECC_ERR_MBIT_DCACHE 0xC012 /*!< \brief Any multi-bit ECC error in the data cache */ 247#define ARMCM85_PMU_ECC_ERR_MBIT_ICACHE 0xC013 /*!< \brief Any multi-biy ECC error in the instruction cache*/ 248#define ARMCM85_PMU_ECC_ERR_DTCM 0xC020 /*!< \brief Any ECC error in the DTCM */ 249#define ARMCM85_PMU_ECC_ERR_ITCM 0xC021 /*!< \brief Any ECC error in the ITCM */ 250#define ARMCM85_PMU_ECC_ERR_MBIT_DTCM 0xC022 /*!< \brief Any multi-bit ECC error in the DTCM */ 251#define ARMCM85_PMU_ECC_ERR_MBIT_ITCM 0xC023 /*!< \brief Any multi-bit ECC error in the ITCM */ 252#define ARMCM85_PMU_PF_LINEFILL 0xC100 /*!< \brief A prefetcher starts a line-fill */ 253#define ARMCM85_PMU_PF_CANCEL 0xC101 /*!< \brief A prefetcher stops prefetching */ 254#define ARMCM85_PMU_PF_DROP_LINEFILL 0xC102 /*!< \brief A linefill triggered by a prefetcher has been dropped because of lack of buffering */ 255#define ARMCM85_PMU_NWAMODE_ENTER 0xC200 /*!< \brief No write-allocate mode entry */ 256#define ARMCM85_PMU_NWAMODE 0xC201 /*!< \brief Write-allocate store is not allocated into the data cache due to no-write-allocate mode */ 257#define ARMCM85_PMU_SAHB_ACCESS 0xC300 /*!< \brief Read or write access on the S-AHB interface to the TCM */ 258#define ARMCM85_PMU_PAHB_ACCESS 0xC301 /*!< \brief Read or write access on the P-AHB interface */ 259#define ARMCM85_PMU_AXI_WRITE_ACCESS 0xC302 /*!< \brief Any beat access to M-AXI write interface */ 260#define ARMCM85_PMU_AXI_READ_ACCESS 0xC303 /*!< \brief Any beat access to M-AXI read interface */ 261#define ARMCM85_PMU_DOSTIMEOUT_DOUBLE 0xC400 /*!< \brief Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */ 262#define ARMCM85_PMU_DOSTIMEOUT_TRIPLE 0xC401 /*!< \brief Denial of Service timeout has fired three times and blocked the LSU to force forward progress */ 263 264/** @} */ 265 266 267/** 268 \brief Structure type to access the Performance Monitoring Unit (PMU). 269 */ 270typedef struct 271{ 272 __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) \brief PMU Event Counter Registers \details Two up to 31 event counters, see device specific \ref __PMU_NUM_EVENTCNT */ 273// uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; 274 __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) \brief PMU Cycle Counter Register */ 275// uint32_t RESERVED1[224]; 276 __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) \brief PMU Event Type and Filter Registers \details Two up to 31 event counters, see device specific \ref __PMU_NUM_EVENTCNT */ 277// uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; 278 __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) \brief PMU Cycle Counter Filter Register */ 279// uint32_t RESERVED3[480]; 280 __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) \brief PMU Count Enable Set Register */ 281// uint32_t RESERVED4[7]; 282 __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) \brief PMU Count Enable Clear Register */ 283// uint32_t RESERVED5[7]; 284 __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) \brief PMU Interrupt Enable Set Register */ 285// uint32_t RESERVED6[7]; 286 __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) \brief PMU Interrupt Enable Clear Register */ 287// uint32_t RESERVED7[7]; 288 __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) \brief PMU Overflow Flag Status Clear Register */ 289// uint32_t RESERVED8[7]; 290 __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) \brief PMU Software Increment Register */ 291// uint32_t RESERVED9[7]; 292 __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) \brief PMU Overflow Flag Status Set Register */ 293// uint32_t RESERVED10[79]; 294 __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) \brief PMU Type Register */ 295 __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) \brief PMU Control Register */ 296// uint32_t RESERVED11[108]; 297 __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) \brief PMU Authentication Status Register */ 298 __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) \brief PMU Device Architecture Register */ 299// uint32_t RESERVED12[4]; 300 __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) \brief PMU Device Type Register */ 301 __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) \brief PMU Peripheral Identification Register 4 */ 302// uint32_t RESERVED13[3]; 303 __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) \brief PMU Peripheral Identification Register 0 */ 304 __IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) \brief PMU Peripheral Identification Register 1 */ 305 __IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) \brief PMU Peripheral Identification Register 2 */ 306 __IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) \brief PMU Peripheral Identification Register 3 */ 307// uint32_t RESERVED14[3]; 308 __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) \brief PMU Component Identification Register 0 */ 309 __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) \brief PMU Component Identification Register 1 */ 310 __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) \brief PMU Component Identification Register 2 */ 311 __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) \brief PMU Component Identification Register 3 */ 312} PMU_Type; 313 314/** 315 \brief PMU configuration struct 316 \details 317 This macro can be used to access the PMU registers, directly. For the common tasks 318 one should prefer using the control functions. 319 320 Example: 321 <b>Example:</b> 322 \code 323 PMU->CTRL |= PMU_CTRL_ENABLE_Msk; // Enable PMU 324 \endcode 325*/ 326#define PMU 327 328/** 329 \brief Enable the PMU 330*/ 331__STATIC_INLINE void ARM_PMU_Enable(void); 332 333/** 334 \brief Disable the PMU 335*/ 336__STATIC_INLINE void ARM_PMU_Disable(void); 337 338/** 339 \brief Set event to count for PMU event counter 340 \param [in] num Event counter (0-30) to configure 341 \param [in] type Event to count 342*/ 343__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type); 344 345/** 346 \brief Reset cycle counter 347*/ 348__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void); 349 350/** 351 \brief Reset all event counters 352*/ 353__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void); 354 355/** 356 \brief Enable counters 357 \param [in] mask Counters to enable 358 \note Enables one or more of the following: 359 - event counters (0-30) 360 - cycle counter 361*/ 362__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask); 363 364/** 365 \brief Disable counters 366 \param [in] mask Counters to enable 367 \note Disables one or more of the following: 368 - event counters (0-30) 369 - cycle counter 370*/ 371__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask); 372 373/** 374 \brief Read cycle counter 375 \return Cycle count 376*/ 377__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void); 378 379/** 380 \brief Read event counter 381 \param [in] num Event counter (0-30) to read 382 \return Event count 383*/ 384__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num); 385 386/** 387 \brief Read counter overflow status 388 \return Counter overflow status bits for the following: 389 - event counters (0-30) 390 - cycle counter 391*/ 392__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void); 393 394/** 395 \brief Clear counter overflow status 396 \param [in] mask Counter overflow status bits to clear 397 \note Clears overflow status bits for one or more of the following: 398 - event counters (0-30) 399 - cycle counter 400*/ 401__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask); 402 403/** 404 \brief Enable counter overflow interrupt request 405 \param [in] mask Counter overflow interrupt request bits to set 406 \note Sets overflow interrupt request bits for one or more of the following: 407 - event counters (0-30) 408 - cycle counter 409*/ 410__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask); 411 412/** 413 \brief Disable counter overflow interrupt request 414 \param [in] mask Counter overflow interrupt request bits to clear 415 \note Clears overflow interrupt request bits for one or more of the following: 416 - event counters (0-30) 417 - cycle counter 418*/ 419__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask); 420 421/** 422 \brief Software increment event counter 423 \param [in] mask Counters to increment 424 \note Software increment bits for one or more event counters (0-30) 425*/ 426__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask); 427 428/** @} */ 429
