1/**
2\defgroup device_config Device capabilitiy defines
3\brief Defines to configure and check device capabilities.
4\details
5These defines are used by the \ref device_h_pg in order to enable or disable functionality provided by CMSIS-Core(M) dependent on the device capabilities.
6
7@{
8*/
9
10#define __CM0_REV                     /*!< \brief Cortex-M0 Core revision r0p1 \details ([15:8] revision number, [7:0] patch number) */
11#define __CM0PLUS_REV                 /*!< \brief Cortex-M0+ Core revision r0p1 \details ([15:8] revision number, [7:0] patch number) */
12#define __CM1_REV                     /*!< \brief Cortex-M1 Core revision r0p1 \details ([15:8] revision number, [7:0] patch number) */
13#define __CM3_REV                     /*!< \brief Cortex-M3 Core revision r0p1 \details ([15:8] revision number, [7:0] patch number) */
14#define __CM4_REV                     /*!< \brief Cortex-M4 Core revision r0p1 \details ([15:8] revision number, [7:0] patch number) */
15#define __CM7_REV                     /*!< \brief Cortex-M7 Core revision r0p1 \details ([15:8] revision number, [7:0] patch number) */
16#define __SC000_REV                   /*!< \brief SC000 Core revision r0p1 \details ([15:8] revision number, [7:0] patch number) */
17#define __SC300_REV                   /*!< \brief SC300 Core revision r0p1 \details ([15:8] revision number, [7:0] patch number) */
18#define __CM23_REV                    /*!< \brief Cortex-M23 Core revision r0p1 \details ([15:8] revision number, [7:0] patch number) */
19#define __CM33_REV                    /*!< \brief Cortex-M33 Core revision r0p1 \details ([15:8] revision number, [7:0] patch number) */
20#define __CM35P_REV                   /*!< \brief Cortex-M35P Core revision r0p1 \details ([15:8] revision number, [7:0] patch number) */
21#define __CM55_REV                    /*!< \brief Cortex-M55 Core revision r0p1 \details ([15:8] revision number, [7:0] patch number) */
22#define __CM85_REV                    /*!< \brief Cortex-M85 Core revision r0p1 \details ([15:8] revision number, [7:0] patch number) */
23#define __ARMv8MBL_REV                /*!< \brief Armv8-M Baseline device Core revision r0p1 \details ([15:8] revision number, [7:0] patch number) */
24#define __ARMv8MML_REV                /*!< \brief Armv8-M Mainline device Core revision r0p1 \details ([15:8] revision number, [7:0] patch number) */
25#define __ARMv81MML_REV               /*!< \brief Armv8.1-M Baseline device Core revision r0p1 \details ([15:8] revision number, [7:0] patch number) */
26#define __NVIC_PRIO_BITS              /*!< \brief Number of Bits used for Priority Levels */
27#define __Vendor_SysTickConfig        /*!< \brief Set to 1 if a venor specfic SysTick configuration is used.
28                                           \details If this define is set to 1, then the default \ref SysTick_Config function is excluded. In this
29                                                    case, the file device.h must contain a vendor specific implementation of this function. */
30#define __VTOR_PRESENT                /*!< \brief VTOR present or not \details See \ref SCB_Type::VTOR */
31#define __MPU_PRESENT                 /*!< \brief MPU present or not */
32
33/**
34  \brief FPU present or not
35  \details
36  The combination of the defines \ref __FPU_PRESENT and \ref __FPU_DP
37  determine the whether the FPU is with single or double precision as shown
38  in the table below.
39  <table class="cmtable" summary="">
40    <tr bgcolor="cyan">
41      <td>\ref __FPU_PRESENT</td>
42      <td>\ref __FPU_DP</td>
43      <td><b>Description</b></td>
44    </tr>
45    <tr>
46      <td align="center">0</td>
47      <td align="center"><i>ignored</i></td>
48      <td>Processor has no FPU. The value set for \ref __FPU_DP.</td>
49    </tr>
50    <tr>
51      <td align="center">1</td>
52      <td align="center">0</td>
53      <td>Processor with FPU with single precision.</td>
54    </tr>
55    <tr>
56      <td align="center">1</td>
57      <td align="center">1</td>
58      <td>Processor with FPU with double precision.</td>
59    </tr>
60  </table>
61*/
62#define __FPU_PRESENT               /*!< \brief FPU present \details The */
63
64/**
65  \brief Double precision FPU present
66  \details
67  The combination of the defines \ref __FPU_PRESENT and \ref __FPU_DP
68  determine the whether the FPU is with single or double precision as shown
69  in the table below.
70  <table class="cmtable" summary="">
71    <tr bgcolor="cyan">
72      <td>\ref __FPU_PRESENT</td>
73      <td>\ref __FPU_DP</td>
74      <td><b>Description</b></td>
75    </tr>
76    <tr>
77      <td align="center">0</td>
78      <td align="center"><i>ignored</i></td>
79      <td>Processor has no FPU. The value set for \ref __FPU_DP. </td>
80    </tr>
81    <tr>
82      <td align="center">1</td>
83      <td align="center">0</td>
84      <td>Processor with FPU with single precision.</td>
85    </tr>
86    <tr>
87      <td align="center">1</td>
88      <td align="center">1</td>
89      <td>Processor with FPU with double precision.</td>
90    </tr>
91  </table>
92*/
93#define __FPU_DP
94
95#define __DSP_PRESENT               /*!< \brief DSP extension present or not */
96#define __SAUREGION_PRESENT         /*!< \brief SAU regions present or not */
97#define __PMU_PRESENT               /*!< \brief PMU present or not */
98#define __PMU_NUM_EVENTCNT          /*!< \brief PMU Event Counters \details The number of Event counters if PMU is present (see \ref __PMU_PRESENT) */
99#define __ICACHE_PRESENT            /*!< \brief Instruction Cache present or not */
100#define __DCACHE_PRESENT            /*!< \brief Data Cache present or not */
101#define __DTCM_PRESENT              /*!< \brief Data Tightly Coupled Memory is present or not */
102/** @} */
103