1/**************************** Data Structures ***********************************************/ 2/** 3 \brief Union type to access the Application Program Status Register (APSR). 4 */ 5typedef union 6{ 7 struct 8 { 9#if (__CORTEX_M != 0x04) 10 uint32_t _reserved0:27; ///< bit: 0..26 Reserved 11#else 12 uint32_t _reserved0:16; ///< bit: 0..15 Reserved 13 uint32_t GE:4; ///< bit: 16..19 Greater than or Equal flags 14 uint32_t _reserved1:7; ///< bit: 20..26 Reserved 15#endif 16 uint32_t Q:1; ///< bit: 27 Saturation condition flag 17 uint32_t V:1; ///< bit: 28 Overflow condition code flag 18 uint32_t C:1; ///< bit: 29 Carry condition code flag 19 uint32_t Z:1; ///< bit: 30 Zero condition code flag 20 uint32_t N:1; ///< bit: 31 Negative condition code flag 21 } b; ///< Structure used for bit access 22 uint32_t w; ///< Type used for word access 23} APSR_Type; 24 25 26/**************************************************************************************************/ 27/** 28 \brief Union type to access the Interrupt Program Status Register (IPSR). 29 */ 30typedef union 31{ 32 struct 33 { 34 uint32_t ISR:9; ///< bit: 0.. 8 Exception number 35 uint32_t _reserved0:23; ///< bit: 9..31 Reserved 36 } b; ///< Structure used for bit access 37 uint32_t w; ///< Type used for word access 38} IPSR_Type; 39 40 41/**************************************************************************************************/ 42/** 43 \brief Union type to access the Special-Purpose Program Status Registers (xPSR). 44 */ 45typedef union 46{ 47 struct 48 { 49 uint32_t ISR:9; ///< bit: 0.. 8 Exception number 50#if (__CORTEX_M != 0x04) 51 uint32_t _reserved0:15; ///< bit: 9..23 Reserved 52#else 53 uint32_t _reserved0:7; ///< bit: 9..15 Reserved 54 uint32_t GE:4; ///< bit: 16..19 Greater than or Equal flags 55 uint32_t _reserved1:4; ///< bit: 20..23 Reserved 56#endif 57 uint32_t T:1; ///< bit: 24 Thumb bit (read 0) 58 uint32_t IT:2; ///< bit: 25..26 saved IT state (read 0) 59 uint32_t Q:1; ///< bit: 27 Saturation condition flag 60 uint32_t V:1; ///< bit: 28 Overflow condition code flag 61 uint32_t C:1; ///< bit: 29 Carry condition code flag 62 uint32_t Z:1; ///< bit: 30 Zero condition code flag 63 uint32_t N:1; ///< bit: 31 Negative condition code flag 64 } b; ///< Structure used for bit access 65 uint32_t w; ///< Type used for word access 66} xPSR_Type; 67 68 69/**************************************************************************************************/ 70/** 71 \brief Union type to access the Control Registers (CONTROL). 72 */ 73typedef union 74{ 75 struct 76 { 77 uint32_t nPRIV:1; ///< bit: 0 Execution privilege in Thread mode 78 uint32_t SPSEL:1; ///< bit: 1 Stack to be used 79 uint32_t FPCA:1; ///< bit: 2 FP extension active flag 80 uint32_t _reserved0:29; ///< bit: 3..31 Reserved 81 } b; ///< Structure used for bit access 82 uint32_t w; ///< Type used for word access 83} CONTROL_Type; 84 85 86/**************************************************************************************************/ 87/** 88 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). 89 */ 90typedef struct 91{ 92 __IOM uint32_t ISER[8]; ///< Offset: 0x000 (R/W) Interrupt Set Enable Register 93 uint32_t RESERVED0[24]; ///< Reserved 94 __IOM uint32_t ICER[8]; ///< Offset: 0x080 (R/W) Interrupt Clear Enable Register 95 uint32_t RSERVED1[24]; ///< Reserved 96 __IOM uint32_t ISPR[8]; ///< Offset: 0x100 (R/W) Interrupt Set Pending Register 97 uint32_t RESERVED2[24]; ///< Reserved 98 __IOM uint32_t ICPR[8]; ///< Offset: 0x180 (R/W) Interrupt Clear Pending Register 99 uint32_t RESERVED3[24]; ///< Reserved 100 __IOM uint32_t IABR[8]; ///< Offset: 0x200 (R/W) Interrupt Active bit Register 101 uint32_t RESERVED4[56]; ///< Reserved 102 __IOM uint8_t IPR[240]; ///< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) 103 uint32_t RESERVED5[644]; ///< Reserved 104 __OM uint32_t STIR; ///< Offset: 0xE00 ( /W) Software Trigger Interrupt Register 105} NVIC_Type; 106 107 108/**************************************************************************************************/ 109/** 110 \brief Structure type to access the System Control Block (SCB). 111 */ 112typedef struct 113{ 114 __IM uint32_t CPUID; ///< Offset: 0x000 (R/ ) CPUID Base Register 115 __IOM uint32_t ICSR; ///< Offset: 0x004 (R/W) Interrupt Control and State Register 116 __IOM uint32_t VTOR; ///< Offset: 0x008 (R/W) Vector Table Offset Register 117 __IOM uint32_t AIRCR; ///< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register 118 __IOM uint32_t SCR; ///< Offset: 0x010 (R/W) System Control Register 119 __IOM uint32_t CCR; ///< Offset: 0x014 (R/W) Configuration Control Register 120 __IOM uint8_t SHPR[12U]; ///< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) 121 __IOM uint32_t SHCSR; ///< Offset: 0x024 (R/W) System Handler Control and State Register 122 __IOM uint32_t CFSR; ///< Offset: 0x028 (R/W) Configurable Fault Status Register 123 __IOM uint32_t HFSR; ///< Offset: 0x02C (R/W) HardFault Status Register 124 __IOM uint32_t DFSR; ///< Offset: 0x030 (R/W) Debug Fault Status Register 125 __IOM uint32_t MMFAR; ///< Offset: 0x034 (R/W) MemManage Fault Address Register 126 __IOM uint32_t BFAR; ///< Offset: 0x038 (R/W) BusFault Address Register 127 __IOM uint32_t AFSR; ///< Offset: 0x03C (R/W) Auxiliary Fault Status Register 128 __IM uint32_t ID_PFR[2U]; ///< Offset: 0x040 (R/ ) Processor Feature Register 129 __IM uint32_t ID_DFR; ///< Offset: 0x048 (R/ ) Debug Feature Register 130 __IM uint32_t ID_AFR; ///< Offset: 0x04C (R/ ) Auxiliary Feature Register 131 __IM uint32_t ID_MMFR[4U]; ///< Offset: 0x050 (R/ ) Memory Model Feature Register 132 __IM uint32_t ID_ISAR[5U]; ///< Offset: 0x060 (R/ ) Instruction Set Attributes Register 133// uint32_t RESERVED0[5U]; 134 __IOM uint32_t CPACR; ///< Offset: 0x088 (R/W) Coprocessor Access Control Register 135// uint32_t RESERVED3[93U]; 136 __OM uint32_t STIR; ///< Offset: 0x200 ( /W) Software Triggered Interrupt Register 137} SCB_Type; 138 139 140/**************************************************************************************************/ 141/** 142 \brief Structure type to access the System Control and ID Register not in the SCB. 143 */ 144typedef struct 145{ 146 uint32_t RESERVED0[1]; /*!< Reserved */ 147 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register 148 \note available for Cortex-M3, Cortex-M4, Cortex-M7, Cortex-M33, Cortex-M33P, SecureCore SC300 */ 149 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register 150 \note available for Cortex-M1, Cortex-M3 , Cortex-M4, Cortex-M7, Cortex-M33, Cortex-M33P, SecureCore SC000, SecureCore SC300 */ 151 __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register 152 \note available for Cortex-M33, Cortex-M33P */ 153} SCnSCB_Type; 154 155 156/**************************************************************************************************/ 157/** 158 \brief Structure type to access the Implementation Control Block Register (ICB). 159 \note replaces SCnSCB_Type (only on Cortex-M55/M85) 160 */ 161typedef struct 162{ 163 uint32_t RESERVED0[1U]; 164 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ 165 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ 166 __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ 167} ICB_Type; 168 169 170/**************************************************************************************************/ 171/** \brief Structure type to access the System Timer (SysTick). 172 */ 173typedef struct 174{ 175 __IOM uint32_t CTRL; ///< Offset: 0x000 (R/W) SysTick Control and Status Register 176 __IOM uint32_t LOAD; ///< Offset: 0x004 (R/W) SysTick Reload Value Register 177 __IOM uint32_t VAL; ///< Offset: 0x008 (R/W) SysTick Current Value Register 178 __IM uint32_t CALIB; ///< Offset: 0x00C (R/ ) SysTick Calibration Register 179} SysTick_Type; 180 181 182/**************************************************************************************************/ 183/** 184 \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). 185 */ 186typedef struct 187{ 188 __OM union 189 { 190 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ 191 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ 192 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ 193 } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ 194// uint32_t RESERVED0[864U]; 195 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ 196// uint32_t RESERVED1[15U]; 197 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ 198// uint32_t RESERVED2[15U]; 199 __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ 200// uint32_t RESERVED3[29U]; 201 __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ 202 __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ 203 __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ 204// uint32_t RESERVED4[43U]; 205 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ 206 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ 207// uint32_t RESERVED5[1U]; 208 __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register (Cortex-M33 only) */ 209// uint32_t RESERVED6[4U]; 210} ITM_Type; 211 212 213/**************************************************************************************************/ 214/** 215 \brief Structure type to access the Memory Protection Unit (MPU). 216 */ 217typedef struct 218{ 219 __IM uint32_t TYPE; ///< Offset: 0x000 (R/ ) MPU Type Register 220 __IOM uint32_t CTRL; ///< Offset: 0x004 (R/W) MPU Control Register 221 __IOM uint32_t RNR; ///< Offset: 0x008 (R/W) MPU Region RNRber Register 222 __IOM uint32_t RBAR; ///< Offset: 0x00C (R/W) MPU Region Base Address Register 223 __IOM uint32_t RASR; ///< Offset: 0x010 (R/W) MPU Region Attribute and Size Register 224 __IOM uint32_t RBAR_A1; ///< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register 225 __IOM uint32_t RASR_A1; ///< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register 226 __IOM uint32_t RBAR_A2; ///< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register 227 __IOM uint32_t RASR_A2; ///< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register 228 __IOM uint32_t RBAR_A3; ///< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register 229 __IOM uint32_t RASR_A3; ///< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register 230} MPU_Type; 231 232 233/**************************************************************************************************/ 234/** 235 \brief Structure type to access the Floating Point Unit (FPU). 236 */ 237typedef struct 238{ 239// uint32_t RESERVED0[1]; ///< Reserved 240 __IOM uint32_t FPCCR; ///< Offset: 0x004 (R/W) Floating-Point Context Control Register 241 __IOM uint32_t FPCAR; ///< Offset: 0x008 (R/W) Floating-Point Context Address Register 242 __IOM uint32_t FPDSCR; ///< Offset: 0x00C (R/W) Floating-Point Default Status Control Register 243 __IM uint32_t MVFR0; ///< Offset: 0x010 (R/ ) Media and FP Feature Register 0 244 __IM uint32_t MVFR1; ///< Offset: 0x014 (R/ ) Media and FP Feature Register 1 245} FPU_Type; 246 247 248/**************************************************************************************************/ 249/** 250 \brief Structure type to access the Debug Control Block Registers (DCB). 251 */ 252typedef struct 253{ 254 __IOM uint32_t DHCSR; ///< Offset: 0x000 (R/W) Debug Halting Control and Status Register 255 __OM uint32_t DCRSR; ///< Offset: 0x004 ( /W) Debug Core Register Selector Register 256 __IOM uint32_t DCRDR; ///< Offset: 0x008 (R/W) Debug Core Register Data Register 257 __IOM uint32_t DEMCR; ///< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register 258 __OM uint32_t DSCEMCR; ///< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register (Armv8.1-M only) 259 __IOM uint32_t DAUTHCTRL; ///< Offset: 0x014 (R/W) Debug Authentication Control Register (Armv8-M only) 260 __IOM uint32_t DSCSR; ///< Offset: 0x018 (R/W) Debug Security Control and Status Register (Armv8-M only) 261} DCB_Type; 262 263 264/**************************************************************************************************/ 265/** 266 \brief Structure type to access the Data Watchpoint and Trace Register (DWT). 267 */ 268typedef struct 269{ 270 __IOM uint32_t CTRL; ///< Offset: 0x000 (R/W) Control Register 271 __IOM uint32_t CYCCNT; ///< Offset: 0x004 (R/W) Cycle Count Register 272 __IOM uint32_t CPICNT; ///< Offset: 0x008 (R/W) CPI Count Register 273 __IOM uint32_t EXCCNT; ///< Offset: 0x00C (R/W) Exception Overhead Count Register 274 __IOM uint32_t SLEEPCNT; ///< Offset: 0x010 (R/W) Sleep Count Register 275 __IOM uint32_t LSUCNT; ///< Offset: 0x014 (R/W) LSU Count Register 276 __IOM uint32_t FOLDCNT; ///< Offset: 0x018 (R/W) Folded-instruction Count Register 277 __IM uint32_t PCSR; ///< Offset: 0x01C (R/ ) Program Counter Sample Register 278 __IOM uint32_t COMP0; ///< Offset: 0x020 (R/W) Comparator Register 0 279 __IOM uint32_t MASK0; ///< Offset: 0x024 (R/W) Mask Register 0 280 __IOM uint32_t FUNCTION0; ///< Offset: 0x028 (R/W) Function Register 0 281// uint32_t RESERVED0[1]; ///< Reserved 282 __IOM uint32_t COMP1; ///< Offset: 0x030 (R/W) Comparator Register 1 283 __IOM uint32_t MASK1; ///< Offset: 0x034 (R/W) Mask Register 1 284 __IOM uint32_t FUNCTION1; ///< Offset: 0x038 (R/W) Function Register 1 285// uint32_t RESERVED1[1]; ///< Reserved 286 __IOM uint32_t COMP2; ///< Offset: 0x040 (R/W) Comparator Register 2 287 __IOM uint32_t MASK2; ///< Offset: 0x044 (R/W) Mask Register 2 288 __IOM uint32_t FUNCTION2; ///< Offset: 0x048 (R/W) Function Register 2 289// uint32_t RESERVED2[1]; ///< Reserved 290 __IOM uint32_t COMP3; ///< Offset: 0x050 (R/W) Comparator Register 3 291 __IOM uint32_t MASK3; ///< Offset: 0x054 (R/W) Mask Register 3 292 __IOM uint32_t FUNCTION3; ///< Offset: 0x058 (R/W) Function Register 3 293} DWT_Type; 294 295 296/**************************************************************************************************/ 297/** 298 \brief Structure type to access the Trace Port Interface Register (TPI). 299 */ 300typedef struct 301{ 302 __IOM uint32_t SSPSR; ///< Offset: 0x000 (R/ ) Supported Parallel Port Size Register 303 __IOM uint32_t CSPSR; ///< Offset: 0x004 (R/W) Current Parallel Port Size Register 304// uint32_t RESERVED0[2]; ///< Reserved 305 __IOM uint32_t ACPR; ///< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register 306// uint32_t RESERVED1[55]; ///< Reserved 307 __IOM uint32_t SPPR; ///< Offset: 0x0F0 (R/W) Selected Pin Protocol Register 308// uint32_t RESERVED2[131]; ///< Reserved 309 __IM uint32_t FFSR; ///< Offset: 0x300 (R/ ) Formatter and Flush Status Register 310 __IOM uint32_t FFCR; ///< Offset: 0x304 (R/W) Formatter and Flush Control Register 311 __IM uint32_t FSCR; ///< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register 312// uint32_t RESERVED3[759]; ///< Reserved 313 __IM uint32_t TRIGGER; ///< Offset: 0xEE8 (R/ ) TRIGGER 314 __IM uint32_t FIFO0; ///< Offset: 0xEEC (R/ ) Integration ETM Data 315 __IM uint32_t ITATBCTR2; ///< Offset: 0xEF0 (R/ ) ITATBCTR2 316// uint32_t RESERVED4[1]; ///< Reserved 317 __IM uint32_t ITATBCTR0; ///< Offset: 0xEF8 (R/ ) ITATBCTR0 318 __IM uint32_t FIFO1; ///< Offset: 0xEFC (R/ ) Integration ITM Data 319 __IOM uint32_t ITCTRL; ///< Offset: 0xF00 (R/W) Integration Mode Control 320// uint32_t RESERVED5[39]; ///< Reserved 321 __IOM uint32_t CLAIMSET; ///< Offset: 0xFA0 (R/W) Claim tag set 322 __IOM uint32_t CLAIMCLR; ///< Offset: 0xFA4 (R/W) Claim tag clear 323// uint32_t RESERVED7[8]; ///< Reserved 324 __IM uint32_t DEVID; ///< Offset: 0xFC8 (R/ ) TPIU_DEVID 325 __IM uint32_t DEVTYPE; ///< Offset: 0xFCC (R/ ) TPIU_DEVTYPE 326} TPIU_Type; 327 328 329/**************************************************************************************************/ 330/** 331 \brief Structure type to access the Performance Monitoring Unit (PMU). 332 */ 333typedef struct 334{ 335 __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; ///< Offset: 0x0 (R/W) Event Counter Registers 336//#if __PMU_NUM_EVENTCNT<31 337// uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; 338//#endif 339 __IOM uint32_t CCNTR; ///< Offset: 0x7C (R/W) Cycle Counter Register 340// uint32_t RESERVED1[224]; 341 __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; ///< Offset: 0x400 (R/W) Event Type and Filter Registers 342//#if __PMU_NUM_EVENTCNT<31 343// uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; 344//#endif 345 __IOM uint32_t CCFILTR; ///< Offset: 0x47C (R/W) Cycle Counter Filter Register 346// uint32_t RESERVED3[480]; 347 __IOM uint32_t CNTENSET; ///< Offset: 0xC00 (R/W) Count Enable Set Register 348// uint32_t RESERVED4[7]; 349 __IOM uint32_t CNTENCLR; ///< Offset: 0xC20 (R/W) Count Enable Clear Register 350// uint32_t RESERVED5[7]; 351 __IOM uint32_t INTENSET; ///< Offset: 0xC40 (R/W) Interrupt Enable Set Register 352// uint32_t RESERVED6[7]; 353 __IOM uint32_t INTENCLR; ///< Offset: 0xC60 (R/W) Interrupt Enable Clear Register 354// uint32_t RESERVED7[7]; 355 __IOM uint32_t OVSCLR; ///< Offset: 0xC80 (R/W) Overflow Flag Status Clear Register 356// uint32_t RESERVED8[7]; 357 __IOM uint32_t SWINC; ///< Offset: 0xCA0 (R/W) Software Increment Register 358// uint32_t RESERVED9[7]; 359 __IOM uint32_t OVSSET; ///< Offset: 0xCC0 (R/W) Overflow Flag Status Set Register 360// uint32_t RESERVED10[79]; 361 __IOM uint32_t TYPE; ///< Offset: 0xE00 (R/W) Type Register 362 __IOM uint32_t CTRL; ///< Offset: 0xE04 (R/W) Control Register 363// uint32_t RESERVED11[108]; 364 __IOM uint32_t AUTHSTATUS; ///< Offset: 0xFB8 (R/W) Authentication Status Register 365 __IOM uint32_t DEVARCH; ///< Offset: 0xFBC (R/W) Device Architecture Register 366// uint32_t RESERVED12[3]; 367 __IOM uint32_t DEVTYPE; ///< Offset: 0xFCC (R/W) Device Type Register 368} PMU_Type; 369 370 371/**************************************************************************************************/ 372/** 373 \brief Structure type to access the External Wakeup Interrupt Controller Registers (EWIC). 374 */ 375typedef struct 376{ 377 __IOM uint32_t EWIC_CR; ///< Offset: 0x000 (R/W) EWIC Control Register 378 __IOM uint32_t EWIC_ASCR; ///< Offset: 0x004 (R/W) EWIC Automatic Sequence Control Register 379 __OM uint32_t EWIC_CLRMASK; ///< Offset: 0x008 ( /W) EWIC Clear Mask Register 380 __IM uint32_t EWIC_NUMID; ///< Offset: 0x00C (R/ ) EWIC Event Number ID Register 381// uint32_t RESERVED0[124U]; 382 __IOM uint32_t EWIC_MASKA; ///< Offset: 0x200 (R/W) EWIC MaskA Register 383 __IOM uint32_t EWIC_MASKn[15]; ///< Offset: 0x204 (R/W) EWIC Maskn Registers 384// uint32_t RESERVED1[112U]; 385 __IM uint32_t EWIC_PENDA; ///< Offset: 0x400 (R/ ) EWIC PendA Event Register 386 __IOM uint32_t EWIC_PENDn[15]; ///< Offset: 0x404 (R/W) EWIC Pendn Event Registers 387// uint32_t RESERVED2[112U]; 388 __IM uint32_t EWIC_PSR; ///< Offset: 0x600 (R/ ) EWIC Pend Summary Register 389} EWIC_Type; 390 391 392/** 393 \brief Structure type to access the Debug Identification Block Registers (DIB). 394 */ 395typedef struct 396{ 397// uint32_t RESERVED0[2U]; 398 __IM uint32_t DAUTHSTATUS; ///< Offset: 0x008 (R/ ) Debug Authentication Status Register 399 __IM uint32_t DDEVARCH; ///< Offset: 0x00C (R/ ) SCS Device Architecture Register 400// uint32_t RESERVED1[3U]; 401 __IM uint32_t DDEVTYPE; ///< Offset: 0x01C (R/ ) SCS Device Type Register 402} DIB_Type; 403
