1# Device Header File <Device.h> {#device_h_pg}
2
3The Device Header File contains the following functionalities that are device-specific:
4 - \ref interrupt_number_sec provides interrupt numbers (IRQn) for all exceptions and interrupts of the device.
5 - \ref core_config_sect reflect the features of the device.
6 - \ref device_access provides definitions for the \ref peripheral_gr to all device peripherals. It contains all data structures and the address mapping for device-specific peripherals.
7 - **Access Functions for Peripherals (optional)** provide additional helper functions for peripherals that are useful for programming of these peripherals. Access Functions may be provided as inline functions or can be extern references to a device-specific library provided by the silicon vendor.
8
9[API Reference](modules.html) describes the standard features and functions of the \ref device_h_pg in details.
10
11## Interrupt Number Definition {#interrupt_number_sec}
12
13\ref device_h_pg contains the enumeration \ref IRQn_Type that defines all exceptions and interrupts of the device.
14 - Negative IRQn values represent processor core exceptions (internal interrupts).
15 - Positive IRQn values represent device-specific exceptions (external interrupts). The first device-specific interrupt has the IRQn value 0.
16   The IRQn values needs extension to reflect the device-specific interrupt vector table in the \ref startup_c_pg.
17
18**Example:**
19
20The following example shows the extension of the interrupt vector table for the LPC1100 device family.
21
22```c
23typedef enum IRQn
24{
25/******  Cortex-M0 Processor Exceptions Numbers ***************************************************/
26  NonMaskableInt_IRQn           = -14,      /*!< 2 Non Maskable Interrupt                         */
27  HardFault_IRQn                = -13,      /*!< 3 Cortex-M0 Hard Fault Interrupt                 */
28  SVCall_IRQn                   = -5,       /*!< 11 Cortex-M0 SVC Interrupt                       */
29  PendSV_IRQn                   = -2,       /*!< 14 Cortex-M0 PendSV Interrupt                    */
30  SysTick_IRQn                  = -1,       /*!< 15 Cortex-M0 System Tick Interrupt               */
31
32/******  LPC11xx/LPC11Cxx Specific Interrupt Numbers **********************************************/
33  WAKEUP0_IRQn                  = 0,        /*!< All I/O pins can be used as wakeup source.       */
34  WAKEUP1_IRQn                  = 1,        /*!< There are 13 pins in total for LPC11xx           */
35  WAKEUP2_IRQn                  = 2,
36                 :       :
37                 :       :
38  EINT1_IRQn                    = 30,       /*!< External Interrupt 1 Interrupt                   */
39  EINT0_IRQn                    = 31,       /*!< External Interrupt 0 Interrupt                   */
40} IRQn_Type;
41```
42
43## Configuration of the Processor and Core Peripherals {#core_config_sect}
44
45The \ref device_h_pg  configures the Cortex-M or SecurCore processors and the core peripherals with `#define` directives
46that are set prior to including the file `core_<cpu>.h`.
47
48The following tables list the <i>\#defines</i> along with the possible values for each processor core.
49If these <i>\#defines</i> are missing default values are used.
50
51**Cortex-M0 core** (core_cm0.h)
52<table class="cmtable">
53    <tr>
54      <th>\#define</th>
55      <th>Value Range</th>
56      <th>Default</th>
57      <th>Description</th>
58    </tr>
59    <tr>
60      <td>\ref __CM0_REV</td>
61      <td>0x0000</td>
62      <td>0x0000</td>
63      <td>Core revision number ([15:8] revision number, [7:0] patch number)</td>
64    </tr>
65    <tr>
66      <td>\ref __NVIC_PRIO_BITS</td>
67      <td>2</td>
68      <td>2</td>
69      <td>Number of priority bits implemented in the NVIC (device specific)</td>
70    </tr>
71    <tr>
72      <td>\ref __Vendor_SysTickConfig</td>
73      <td>0 .. 1</td>
74      <td>0</td>
75      <td>Vendor defined <b>SysTick_Config</b> function.</td>
76    </tr>
77</table>
78
79**Cortex-M0+ core** (core_cm0plus.h)
80<table class="cmtable">
81    <tr>
82      <th>\#define</th>
83      <th>Value Range</th>
84      <th>Default</th>
85      <th>Description</th>
86    </tr>
87    <tr>
88      <td>\ref __CM0PLUS_REV</td>
89      <td>0x0000</td>
90      <td>0x0000</td>
91      <td>Core revision number ([15:8] revision number, [7:0] patch number)</td>
92    </tr>
93    <tr>
94      <td>\ref __VTOR_PRESENT</td>
95      <td>0 .. 1</td>
96      <td>0</td>
97      <td>Defines if a VTOR register is present or not</td>
98    </tr>
99    <tr>
100      <td>\ref __NVIC_PRIO_BITS</td>
101      <td>2</td>
102      <td>2</td>
103      <td>Number of priority bits implemented in the NVIC (device specific)</td>
104    </tr>
105    <tr>
106      <td>\ref __Vendor_SysTickConfig</td>
107      <td>0 .. 1</td>
108      <td>0</td>
109      <td>Vendor defined <b>SysTick_Config</b> function.</td>
110    </tr>
111</table>
112
113**Cortex-M3 core** (core_cm3.h)
114<table class="cmtable">
115    <tr>
116      <th>\#define</th>
117      <th>Value Range</th>
118      <th>Default</th>
119      <th>Description</th>
120    </tr>
121    <tr>
122      <td>\ref __CM3_REV</td>
123      <td>0x0101 | 0x0200</td>
124      <td>0x0200</td>
125      <td>Core revision number ([15:8] revision number, [7:0] patch number)</td>
126    </tr>
127    <tr>
128      <td>\ref __VTOR_PRESENT</td>
129      <td>0 .. 1</td>
130      <td>1</td>
131      <td>Defines if a VTOR register is present or not</td>
132    </tr>
133    <tr>
134      <td>\ref __NVIC_PRIO_BITS</td>
135      <td>2 .. 8</td>
136      <td>4</td>
137      <td>Number of priority bits implemented in the NVIC (device specific)</td>
138    </tr>
139    <tr>
140      <td>\ref __MPU_PRESENT</td>
141      <td>0 .. 1</td>
142      <td>0</td>
143      <td>Defines if a MPU is present or not</td>
144    </tr>
145    <tr>
146      <td>\ref __Vendor_SysTickConfig</td>
147      <td>0 .. 1</td>
148      <td>0</td>
149      <td>Vendor defined <b>SysTick_Config</b> function.</td>
150    </tr>
151</table>
152
153**Cortex-M4 core** (core_cm4.h)
154<table class="cmtable">
155    <tr>
156      <th>\#define</th>
157      <th>Value Range</th>
158      <th>Default</th>
159      <th>Description</th>
160    </tr>
161    <tr>
162      <td>\ref __CM4_REV</td>
163      <td>0x0000</td>
164      <td>0x0000</td>
165      <td>Core revision number ([15:8] revision number, [7:0] patch number)</td>
166    </tr>
167    <tr>
168      <td>\ref __VTOR_PRESENT</td>
169      <td>0 .. 1</td>
170      <td>1</td>
171      <td>Defines if a VTOR register is present or not</td>
172    </tr>
173    <tr>
174      <td>\ref __NVIC_PRIO_BITS</td>
175      <td>2 .. 8</td>
176      <td>4</td>
177      <td>Number of priority bits implemented in the NVIC (device specific)</td>
178    </tr>
179    <tr>
180      <td>\ref __MPU_PRESENT</td>
181      <td>0 .. 1</td>
182      <td>0</td>
183      <td>Defines if a MPU is present or not</td>
184    </tr>
185    <tr>
186      <td>\ref __FPU_PRESENT</td>
187      <td>0 .. 1</td>
188      <td>0</td>
189      <td>Defines if a FPU is present or not</td>
190    </tr>
191    <tr>
192      <td>\ref __Vendor_SysTickConfig</td>
193      <td>0 .. 1</td>
194      <td>0</td>
195      <td>Vendor defined <b>SysTick_Config</b> function.</td>
196    </tr>
197</table>
198
199**Cortex-M7 core** (core_cm7.h)
200<table class="cmtable" summary="">
201    <tr>
202      <th>\#define</th>
203      <th>Value Range</th>
204      <th>Default</th>
205      <th>Description</th>
206    </tr>
207    <tr>
208      <td>\ref __CM7_REV</td>
209      <td>0x0000</td>
210      <td>0x0000</td>
211      <td>Core revision number ([15:8] revision number, [7:0] patch number)</td>
212    </tr>
213    <tr>
214      <td>\ref __MPU_PRESENT</td>
215      <td>0 .. 1</td>
216      <td>0</td>
217      <td>Defines if a MPU is present or not</td>
218    </tr>
219    <tr>
220      <td>\ref __VTOR_PRESENT</td>
221      <td>0 .. 1</td>
222      <td>1</td>
223      <td>Defines if a VTOR register is present or not</td>
224    </tr>
225    <tr>
226      <td>\ref __NVIC_PRIO_BITS</td>
227      <td>2 .. 8</td>
228      <td>4</td>
229      <td>Number of priority bits implemented in the NVIC (device specific)</td>
230    </tr>
231    <tr>
232      <td>\ref __Vendor_SysTickConfig</td>
233      <td>0 .. 1</td>
234      <td>0</td>
235      <td>
236        If this define is set to 1, then the default <b>SysTick_Config</b> function
237        is excluded. In this case, the file <i><b>device.h</b></i>
238        must contain a vendor specific implementation of this function.
239      </td>
240    </tr>
241    <tr>
242      <td>\ref __FPU_PRESENT</td>
243      <td>0 .. 1</td>
244      <td>0</td>
245      <td>Defines if a FPU is present or not.</td>
246    </tr>
247    <tr>
248      <td>\ref __FPU_DP</td>
249      <td>0 .. 1</td>
250      <td>0</td>
251      <td>
252        The combination of the defines \ref __FPU_PRESENT and \ref __FPU_DP
253       determine whether the FPU is with single or double precision.
254      </td>
255    </tr>
256    <tr>
257      <td>\ref __ICACHE_PRESENT</td>
258      <td>0 .. 1</td>
259      <td>1</td>
260      <td>Instruction Chache present or not</td>
261    </tr>
262    <tr>
263      <td>\ref __DCACHE_PRESENT</td>
264      <td>0 .. 1</td>
265      <td>1</td>
266      <td>Data Chache present or not</td>
267    </tr>
268    <tr>
269      <td>\ref __DTCM_PRESENT</td>
270      <td>0 .. 1</td>
271      <td>1</td>
272      <td>Data Tightly Coupled Memory is present or not</td>
273    </tr>
274</table>
275
276\if ARMSC
277**SecurCore SC000 core** (core_sc000.h)
278<table class="cmtable">
279    <tr>
280      <th>\#define</th>
281      <th>Value Range</th>
282      <th>Default</th>
283      <th>Description</th>
284    </tr>
285    <tr>
286      <td>\ref __SC000_REV</td>
287      <td>0x0000</td>
288      <td>0x0000</td>
289      <td>Core revision number ([15:8] revision number, [7:0] patch number)</td>
290    </tr>
291    <tr>
292      <td>\ref __VTOR_PRESENT</td>
293      <td>0 .. 1</td>
294      <td>0</td>
295      <td>Defines if a VTOR register is present or not</td>
296    </tr>
297    <tr>
298      <td>\ref __NVIC_PRIO_BITS</td>
299      <td>2</td>
300      <td>2</td>
301      <td>Number of priority bits implemented in the NVIC (device specific)</td>
302    </tr>
303    <tr>
304      <td>\ref __MPU_PRESENT</td>
305      <td>0 .. 1</td>
306      <td>0</td>
307      <td>Defines if a MPU is present or not</td>
308    </tr>
309    <tr>
310      <td>\ref __Vendor_SysTickConfig</td>
311      <td>0 .. 1</td>
312      <td>0</td>
313      <td>Vendor defined <b>SysTick_Config</b> function.</td>
314    </tr>
315</table>
316\endif
317
318\if ARMSC
319**SecurCore SC300 core** (core_sc300.h)
320<table class="cmtable">
321    <tr>
322      <th>\#define</th>
323      <th>Value Range</th>
324      <th>Default</th>
325      <th>Description</th>
326    </tr>
327    <tr>
328      <td>\ref __SC300_REV</td>
329      <td>0x0000</td>
330      <td>0x0000</td>
331      <td>Core revision number ([15:8] revision number, [7:0] patch number)</td>
332    </tr>
333    <tr>
334      <td>\ref __VTOR_PRESENT</td>
335      <td>0 .. 1</td>
336      <td>1</td>
337      <td>Defines if a VTOR register is present or not</td>
338    </tr>
339    <tr>
340      <td>\ref __NVIC_PRIO_BITS</td>
341      <td>2 .. 8</td>
342      <td>4</td>
343      <td>Number of priority bits implemented in the NVIC (device specific)</td>
344    </tr>
345    <tr>
346      <td>\ref __MPU_PRESENT</td>
347      <td>0 .. 1</td>
348      <td>0</td>
349      <td>Defines if a MPU is present or not</td>
350    </tr>
351    <tr>
352      <td>\ref __Vendor_SysTickConfig</td>
353      <td>0 .. 1</td>
354      <td>0</td>
355      <td>Vendor defined <b>SysTick_Config</b> function.</td>
356    </tr>
357</table>
358\endif
359
360\if ARMv8M
361**Cortex-M23 core, Armv8-M Baseline core** (core_cm23.h , core_armv8mbl.h)
362<table class="cmtable">
363    <tr>
364      <th>\#define</th>
365      <th>Value Range</th>
366      <th>Default</th>
367      <th>Description</th>
368    </tr>
369    <tr>
370      <td>\ref __ARMv8MBL_REV or \ref __CM23_REV</td>
371      <td>0x0000</td>
372      <td>0x0000</td>
373      <td>Core revision number ([15:8] revision number, [7:0] patch number)</td>
374    </tr>
375    <tr>
376      <td>\ref __MPU_PRESENT</td>
377      <td>0 .. 1</td>
378      <td>0</td>
379      <td>Defines if a MPU is present or not</td>
380    </tr>
381    <tr>
382      <td>\ref __SAUREGION_PRESENT</td>
383      <td>0 .. 1</td>
384      <td>0</td>
385      <td>Defines if SAU regions are present or not</td>
386    </tr>
387    <tr>
388      <td>\ref __VTOR_PRESENT</td>
389      <td>0 .. 1</td>
390      <td>0</td>
391      <td>Defines if a VTOR register is present or not</td>
392    </tr>
393    <tr>
394      <td>\ref __NVIC_PRIO_BITS</td>
395      <td>2</td>
396      <td>2</td>
397      <td>Number of priority bits implemented in the NVIC (device specific)</td>
398    </tr>
399    <tr>
400      <td>\ref __Vendor_SysTickConfig</td>
401      <td>0 .. 1</td>
402      <td>0</td>
403      <td>Vendor defined <b>SysTick_Config</b> function.</td>
404    </tr>
405</table>
406\endif
407
408\if ARMv8M
409**Cortex-M33, Cortex-M35P, Armv8-M Mainline core** (core_cm33.h, core_cm35p.h, core_armv8mml.h)
410<table class="cmtable">
411    <tr>
412      <th>\#define</th>
413      <th>Value Range</th>
414      <th>Default</th>
415      <th>Description</th>
416    </tr>
417    <tr>
418      <td>\ref __ARMv8MML_REV or \ref __CM33_REV or \ref __CM35P_REV</td>
419      <td>0x0000</td>
420      <td>0x0000</td>
421      <td>Core revision number ([15:8] revision number, [7:0] patch number)</td>
422    </tr>
423    <tr>
424      <td>\ref __MPU_PRESENT</td>
425      <td>0 .. 1</td>
426      <td>0</td>
427      <td>Defines if a MPU is present or not</td>
428    </tr>
429    <tr>
430      <td>\ref __SAUREGION_PRESENT</td>
431      <td>0 .. 1</td>
432      <td>0</td>
433      <td>Defines if SAU regions are present or not</td>
434    </tr>
435    <tr>
436      <td>\ref __FPU_PRESENT</td>
437      <td>0 .. 1</td>
438      <td>0</td>
439      <td>Defines if a FPU is present or not</td>
440    </tr>
441    <tr>
442      <td>\ref __VTOR_PRESENT</td>
443      <td>0 .. 1</td>
444      <td>1</td>
445      <td>Defines if a VTOR register is present or not</td>
446    </tr>
447    <tr>
448      <td>\ref __NVIC_PRIO_BITS</td>
449      <td>2 .. 8</td>
450      <td>3</td>
451      <td>Number of priority bits implemented in the NVIC (device specific)</td>
452    </tr>
453    <tr>
454      <td>\ref __Vendor_SysTickConfig</td>
455      <td>0 .. 1</td>
456      <td>0</td>
457      <td>Vendor defined <b>SysTick_Config</b> function.</td>
458    </tr>
459</table>
460\endif
461
462\if ARMv8M
463**Cortex-M55 core, Armv8.1-M Mainline core** (core_cm55.h, core_armv81mml.h)
464<table class="cmtable">
465    <tr>
466      <th>\#define</th>
467      <th>Value Range</th>
468      <th>Default</th>
469      <th>Description</th>
470    </tr>
471    <tr>
472      <td>\ref __ARMv81MML_REV or \ref __CM55_REV</td>
473      <td>0x0000</td>
474      <td>0x0000</td>
475      <td>Core revision number ([15:8] revision number, [7:0] patch number)</td>
476    </tr>
477    <tr>
478      <td>\ref __MPU_PRESENT</td>
479      <td>0 .. 1</td>
480      <td>0</td>
481      <td>Defines if a MPU is present or not</td>
482    </tr>
483    <tr>
484      <td>\ref __SAUREGION_PRESENT</td>
485      <td>0 .. 1</td>
486      <td>0</td>
487      <td>Defines if SAU regions are present or not</td>
488    </tr>
489    <tr>
490      <td>\ref __FPU_PRESENT</td>
491      <td>0 .. 1</td>
492      <td>0</td>
493      <td>Defines if a FPU is present or not</td>
494    </tr>
495    <tr>
496      <td>\ref __FPU_DP</td>
497      <td>0 .. 1</td>
498      <td>0</td>
499      <td>
500        The combination of the defines \ref __FPU_PRESENT and \ref __FPU_DP determine
501        whether the FPU is with single or double precision.
502      </td>
503    </tr>
504    <tr>
505      <td>\ref __ICACHE_PRESENT</td>
506      <td>0 .. 1</td>
507      <td>1</td>
508      <td>Instruction Chache present or not</td>
509    </tr>
510    <tr>
511      <td>\ref __DCACHE_PRESENT</td>
512      <td>0 .. 1</td>
513      <td>1</td>
514      <td>Data Chache present or not</td>
515    </tr>
516    <tr>
517      <td>\ref __VTOR_PRESENT</td>
518      <td>0 .. 1</td>
519      <td>1</td>
520      <td>Defines if a VTOR register is present or not</td>
521    </tr>
522    <tr>
523      <td>\ref __NVIC_PRIO_BITS</td>
524      <td>2 .. 8</td>
525      <td>3</td>
526      <td>Number of priority bits implemented in the NVIC (device specific)</td>
527    </tr>
528    <tr>
529      <td>\ref __Vendor_SysTickConfig</td>
530      <td>0 .. 1</td>
531      <td>0</td>
532      <td>Vendor defined <b>SysTick_Config</b> function.</td>
533    </tr>
534</table>
535\endif
536
537\if ARMv8M
538**Cortex-M85 core** (core_cm85.h)
539<table class="cmtable">
540    <tr>
541      <th>\#define</th>
542      <th>Value Range</th>
543      <th>Default</th>
544      <th>Description</th>
545    </tr>
546    <tr>
547      <td>\ref __CM85_REV</td>
548      <td>0x0001</td>
549      <td>0x0001</td>
550      <td>Core revision number ([15:8] revision number, [7:0] patch number)</td>
551    </tr>
552    <tr>
553      <td>\ref __MPU_PRESENT</td>
554      <td>0 .. 1</td>
555      <td>0</td>
556      <td>Defines if a MPU is present or not</td>
557    </tr>
558    <tr>
559      <td>\ref __SAUREGION_PRESENT</td>
560      <td>0 .. 1</td>
561      <td>0</td>
562      <td>Defines if SAU regions are present or not</td>
563    </tr>
564    <tr>
565      <td>\ref __FPU_PRESENT</td>
566      <td>0 .. 1</td>
567      <td>0</td>
568      <td>Defines if a FPU is present or not</td>
569    </tr>
570    <tr>
571      <td>\ref __FPU_DP</td>
572      <td>0 .. 1</td>
573      <td>0</td>
574      <td>
575        The combination of the defines \ref __FPU_PRESENT and \ref __FPU_DP determine
576        whether the FPU is with single or double precision.
577      </td>
578    </tr>
579    <tr>
580      <td>\ref __ICACHE_PRESENT</td>
581      <td>0 .. 1</td>
582      <td>1</td>
583      <td>Instruction Chache present or not</td>
584    </tr>
585    <tr>
586      <td>\ref __DCACHE_PRESENT</td>
587      <td>0 .. 1</td>
588      <td>1</td>
589      <td>Data Chache present or not</td>
590    </tr>
591    <tr>
592      <td>\ref __VTOR_PRESENT</td>
593      <td>0 .. 1</td>
594      <td>1</td>
595      <td>Defines if a VTOR register is present or not</td>
596    </tr>
597    <tr>
598      <td>\ref __NVIC_PRIO_BITS</td>
599      <td>2 .. 8</td>
600      <td>3</td>
601      <td>Number of priority bits implemented in the NVIC (device specific)</td>
602    </tr>
603    <tr>
604      <td>\ref __Vendor_SysTickConfig</td>
605      <td>0 .. 1</td>
606      <td>0</td>
607      <td>Vendor defined <b>SysTick_Config</b> function.</td>
608    </tr>
609</table>
610\endif
611
612**Example**
613
614The following code exemplifies the configuration of the Cortex-M4 Processor and Core Peripherals.
615
616```c
617#define __CM4_REV                 0x0001U   /* Core revision r0p1                                 */
618#define __MPU_PRESENT             1U        /* MPU present or not                                 */
619#define __VTOR_PRESENT            1U        /* VTOR present */
620#define __NVIC_PRIO_BITS          3U        /* Number of Bits used for Priority Levels            */
621#define __Vendor_SysTickConfig    0U        /* Set to 1 if different SysTick Config is used       */
622#define __FPU_PRESENT             1U        /* FPU present or not                                 */
623.
624.
625#include <core_cm4.h>                       /* Cortex-M4 processor and core peripherals           */
626#include "system_<Device>.h"                /* Device System Header                               */
627```
628
629## Device Peripheral Access Layer {#device_access}
630
631The \ref device_h_pg contains for each peripheral:
632 - Register Layout Typedef
633 - Base Address
634 - Access Definitions
635
636The section \ref peripheral_gr shows examples for peripheral definitions.
637
638## Device.h Template File {#device_h_sec}
639
640CMSIS-Core \ref cmsis_template_files include `Device.h` file that can be used as a starting point for chip vendors to implement the device-specific features required in a Device header file as described above. But the may also contain other functions to access device-specific peripherals.
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