1 // Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14
15 #include <stdbool.h>
16 #include <stdint.h>
17 #include <stddef.h>
18 #include <stdlib.h>
19 #include "esp32/rom/ets_sys.h"
20 #include "esp32/rom/rtc.h"
21 #include "esp32/rom/uart.h"
22 #include "esp32/rom/gpio.h"
23 #include "soc/rtc.h"
24 #include "soc/rtc_periph.h"
25 #include "soc/sens_periph.h"
26 #include "soc/dport_reg.h"
27 #include "soc/efuse_periph.h"
28 #include "soc/apb_ctrl_reg.h"
29 #include "regi2c_ctrl.h"
30 #include "soc_log.h"
31 #include "sdkconfig.h"
32 #include "xtensa/core-macros.h"
33 #include "rtc_clk_common.h"
34
35 /* Frequency of the 8M oscillator is 8.5MHz +/- 5%, at the default DCAP setting */
36 #define RTC_FAST_CLK_FREQ_8M 8500000
37 #define RTC_SLOW_CLK_FREQ_150K 150000
38 #define RTC_SLOW_CLK_FREQ_8MD256 (RTC_FAST_CLK_FREQ_8M / 256)
39 #define RTC_SLOW_CLK_FREQ_32K 32768
40
41 /* BBPLL configuration values */
42 #define BBPLL_ENDIV5_VAL_320M 0x43
43 #define BBPLL_BBADC_DSMP_VAL_320M 0x84
44 #define BBPLL_ENDIV5_VAL_480M 0xc3
45 #define BBPLL_BBADC_DSMP_VAL_480M 0x74
46 #define BBPLL_IR_CAL_DELAY_VAL 0x18
47 #define BBPLL_IR_CAL_EXT_CAP_VAL 0x20
48 #define BBPLL_OC_ENB_FCAL_VAL 0x9a
49 #define BBPLL_OC_ENB_VCON_VAL 0x00
50 #define BBPLL_BBADC_CAL_7_0_VAL 0x00
51
52 #define APLL_SDM_STOP_VAL_1 0x09
53 #define APLL_SDM_STOP_VAL_2_REV0 0x69
54 #define APLL_SDM_STOP_VAL_2_REV1 0x49
55
56 #define APLL_CAL_DELAY_1 0x0f
57 #define APLL_CAL_DELAY_2 0x3f
58 #define APLL_CAL_DELAY_3 0x1f
59
60 #define XTAL_32K_DAC_VAL 3
61 #define XTAL_32K_DRES_VAL 3
62 #define XTAL_32K_DBIAS_VAL 0
63
64 #define XTAL_32K_BOOTSTRAP_DAC_VAL 3
65 #define XTAL_32K_BOOTSTRAP_DRES_VAL 3
66 #define XTAL_32K_BOOTSTRAP_DBIAS_VAL 0
67 #define XTAL_32K_BOOTSTRAP_TIME_US 7
68
69 #define XTAL_32K_EXT_DAC_VAL 2
70 #define XTAL_32K_EXT_DRES_VAL 3
71 #define XTAL_32K_EXT_DBIAS_VAL 1
72
73 /* Delays for various clock sources to be enabled/switched.
74 * All values are in microseconds.
75 * TODO: some of these are excessive, and should be reduced.
76 */
77 #define DELAY_PLL_DBIAS_RAISE 3
78 #define DELAY_PLL_ENABLE_WITH_150K 80
79 #define DELAY_PLL_ENABLE_WITH_32K 160
80 #define DELAY_FAST_CLK_SWITCH 3
81 #define DELAY_SLOW_CLK_SWITCH 300
82 #define DELAY_8M_ENABLE 50
83
84 /* Core voltage needs to be increased in two cases:
85 * 1. running at 240 MHz
86 * 2. running with 80MHz Flash frequency
87 *
88 * There is a record in efuse which indicates the proper voltage for these two cases.
89 */
90 #define RTC_CNTL_DBIAS_HP_VOLT (RTC_CNTL_DBIAS_1V25 - (REG_GET_FIELD(EFUSE_BLK0_RDATA5_REG, EFUSE_RD_VOL_LEVEL_HP_INV)))
91 #ifdef CONFIG_ESPTOOLPY_FLASHFREQ_80M
92 #define DIG_DBIAS_80M_160M RTC_CNTL_DBIAS_HP_VOLT
93 #else
94 #define DIG_DBIAS_80M_160M RTC_CNTL_DBIAS_1V10
95 #endif
96 #define DIG_DBIAS_240M RTC_CNTL_DBIAS_HP_VOLT
97 #define DIG_DBIAS_XTAL RTC_CNTL_DBIAS_1V10
98 #define DIG_DBIAS_2M RTC_CNTL_DBIAS_1V00
99
100 #define RTC_PLL_FREQ_320M 320
101 #define RTC_PLL_FREQ_480M 480
102
103 static void rtc_clk_cpu_freq_to_8m(void);
104 static void rtc_clk_bbpll_disable(void);
105 static void rtc_clk_bbpll_enable(void);
106 static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz);
107
108 // Current PLL frequency, in MHZ (320 or 480). Zero if PLL is not enabled.
109 static int s_cur_pll_freq;
110
111 static const char* TAG = "rtc_clk";
112
rtc_clk_32k_enable_common(int dac,int dres,int dbias)113 static void rtc_clk_32k_enable_common(int dac, int dres, int dbias)
114 {
115 CLEAR_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG,
116 RTC_IO_X32P_RDE | RTC_IO_X32P_RUE | RTC_IO_X32N_RUE |
117 RTC_IO_X32N_RDE | RTC_IO_X32N_FUN_IE | RTC_IO_X32P_FUN_IE);
118 SET_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_X32N_MUX_SEL | RTC_IO_X32P_MUX_SEL);
119 /* Set the parameters of xtal
120 dac --> current
121 dres --> resistance
122 dbias --> bais voltage
123 */
124 REG_SET_FIELD(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_DAC_XTAL_32K, dac);
125 REG_SET_FIELD(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_DRES_XTAL_32K, dres);
126 REG_SET_FIELD(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_DBIAS_XTAL_32K, dbias);
127
128 #ifdef CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT
129 /* TOUCH sensor can provide additional current to external XTAL.
130 In some case, X32N and X32P PAD don't have enough drive capability to start XTAL */
131 SET_PERI_REG_MASK(RTC_IO_TOUCH_CFG_REG, RTC_IO_TOUCH_XPD_BIAS_M);
132 /* Tie PAD Touch8 to VDD
133 NOTE: TOUCH8 and TOUCH9 register settings are reversed except for DAC, so we set RTC_IO_TOUCH_PAD9_REG here instead
134 */
135 SET_PERI_REG_MASK(RTC_IO_TOUCH_PAD9_REG, RTC_IO_TOUCH_PAD9_TIE_OPT_M);
136 /* Set the current used to compensate TOUCH PAD8 */
137 SET_PERI_REG_BITS(RTC_IO_TOUCH_PAD8_REG, RTC_IO_TOUCH_PAD8_DAC, 4, RTC_IO_TOUCH_PAD8_DAC_S);
138 /* Power up TOUCH8
139 So the Touch DAC start to drive some current from VDD to TOUCH8(which is also XTAL-N)
140 */
141 SET_PERI_REG_MASK(RTC_IO_TOUCH_PAD9_REG, RTC_IO_TOUCH_PAD9_XPD_M);
142 #endif // CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT
143 /* Power up external xtal */
144 SET_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_XPD_XTAL_32K_M);
145 }
146
rtc_clk_32k_enable(bool enable)147 void rtc_clk_32k_enable(bool enable)
148 {
149 if (enable) {
150 rtc_clk_32k_enable_common(XTAL_32K_DAC_VAL, XTAL_32K_DRES_VAL, XTAL_32K_DBIAS_VAL);
151 } else {
152 /* Disable X32N and X32P pad drive external xtal */
153 CLEAR_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_XPD_XTAL_32K_M);
154 CLEAR_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_X32N_MUX_SEL | RTC_IO_X32P_MUX_SEL);
155
156 #ifdef CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT
157 /* Power down TOUCH */
158 CLEAR_PERI_REG_MASK(RTC_IO_TOUCH_PAD9_REG, RTC_IO_TOUCH_PAD9_XPD_M);
159 #endif // CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT
160 }
161 }
162
rtc_clk_32k_enable_external(void)163 void rtc_clk_32k_enable_external(void)
164 {
165 rtc_clk_32k_enable_common(XTAL_32K_EXT_DAC_VAL, XTAL_32K_EXT_DRES_VAL, XTAL_32K_EXT_DBIAS_VAL);
166 }
167
168 /* Helping external 32kHz crystal to start up.
169 * External crystal connected to outputs GPIO32 GPIO33.
170 * Forms N pulses with a frequency of about 32KHz on the outputs of the crystal.
171 */
rtc_clk_32k_bootstrap(uint32_t cycle)172 void rtc_clk_32k_bootstrap(uint32_t cycle)
173 {
174 if (cycle){
175 const uint32_t pin_32 = 32;
176 const uint32_t pin_33 = 33;
177 const uint32_t mask_32 = (1 << (pin_32 - 32));
178 const uint32_t mask_33 = (1 << (pin_33 - 32));
179
180 gpio_pad_select_gpio(pin_32);
181 gpio_pad_select_gpio(pin_33);
182 gpio_output_set_high(mask_32, mask_33, mask_32 | mask_33, 0);
183
184 const uint32_t delay_us = (1000000 / RTC_SLOW_CLK_FREQ_32K / 2);
185 while(cycle){
186 gpio_output_set_high(mask_32, mask_33, mask_32 | mask_33, 0);
187 ets_delay_us(delay_us);
188 gpio_output_set_high(mask_33, mask_32, mask_32 | mask_33, 0);
189 ets_delay_us(delay_us);
190 cycle--;
191 }
192 gpio_output_set_high(0, 0, 0, mask_32 | mask_33); // disable pins
193 }
194
195 CLEAR_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_XPD_XTAL_32K);
196 SET_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_X32P_RUE | RTC_IO_X32N_RDE);
197 ets_delay_us(XTAL_32K_BOOTSTRAP_TIME_US);
198
199 rtc_clk_32k_enable_common(XTAL_32K_BOOTSTRAP_DAC_VAL,
200 XTAL_32K_BOOTSTRAP_DRES_VAL, XTAL_32K_BOOTSTRAP_DBIAS_VAL);
201 }
202
rtc_clk_32k_enabled(void)203 bool rtc_clk_32k_enabled(void)
204 {
205 return GET_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_XPD_XTAL_32K) != 0;
206 }
207
rtc_clk_8m_enable(bool clk_8m_en,bool d256_en)208 void rtc_clk_8m_enable(bool clk_8m_en, bool d256_en)
209 {
210 if (clk_8m_en) {
211 CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M);
212 /* no need to wait once enabled by software */
213 REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, 1);
214 if (d256_en) {
215 CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV);
216 } else {
217 SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV);
218 }
219 ets_delay_us(DELAY_8M_ENABLE);
220 } else {
221 SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M);
222 REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CNTL_CK8M_WAIT_DEFAULT);
223 }
224 }
225
rtc_clk_8m_enabled(void)226 bool rtc_clk_8m_enabled(void)
227 {
228 return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M) == 0;
229 }
230
rtc_clk_8md256_enabled(void)231 bool rtc_clk_8md256_enabled(void)
232 {
233 return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV) == 0;
234 }
235
rtc_clk_apll_enable(bool enable,uint32_t sdm0,uint32_t sdm1,uint32_t sdm2,uint32_t o_div)236 void rtc_clk_apll_enable(bool enable, uint32_t sdm0, uint32_t sdm1, uint32_t sdm2, uint32_t o_div)
237 {
238 REG_SET_FIELD(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD, enable ? 0 : 1);
239 REG_SET_FIELD(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PU, enable ? 1 : 0);
240
241 if (!enable &&
242 REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL) != RTC_CNTL_SOC_CLK_SEL_PLL) {
243 REG_SET_BIT(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FORCE_PD);
244 } else {
245 REG_CLR_BIT(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FORCE_PD);
246 }
247
248 if (enable) {
249 uint8_t sdm_stop_val_2 = APLL_SDM_STOP_VAL_2_REV1;
250 uint32_t is_rev0 = (GET_PERI_REG_BITS2(EFUSE_BLK0_RDATA3_REG, 1, 15) == 0);
251 if (is_rev0) {
252 sdm0 = 0;
253 sdm1 = 0;
254 sdm_stop_val_2 = APLL_SDM_STOP_VAL_2_REV0;
255 }
256 REGI2C_WRITE_MASK(I2C_APLL, I2C_APLL_DSDM2, sdm2);
257 REGI2C_WRITE_MASK(I2C_APLL, I2C_APLL_DSDM0, sdm0);
258 REGI2C_WRITE_MASK(I2C_APLL, I2C_APLL_DSDM1, sdm1);
259 REGI2C_WRITE(I2C_APLL, I2C_APLL_SDM_STOP, APLL_SDM_STOP_VAL_1);
260 REGI2C_WRITE(I2C_APLL, I2C_APLL_SDM_STOP, sdm_stop_val_2);
261 REGI2C_WRITE_MASK(I2C_APLL, I2C_APLL_OR_OUTPUT_DIV, o_div);
262
263 /* calibration */
264 REGI2C_WRITE(I2C_APLL, I2C_APLL_IR_CAL_DELAY, APLL_CAL_DELAY_1);
265 REGI2C_WRITE(I2C_APLL, I2C_APLL_IR_CAL_DELAY, APLL_CAL_DELAY_2);
266 REGI2C_WRITE(I2C_APLL, I2C_APLL_IR_CAL_DELAY, APLL_CAL_DELAY_3);
267
268 /* wait for calibration end */
269 while (!(REGI2C_READ_MASK(I2C_APLL, I2C_APLL_OR_CAL_END))) {
270 /* use esp_rom_delay_us so the RTC bus doesn't get flooded */
271 ets_delay_us(1);
272 }
273 }
274 }
275
rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq)276 void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq)
277 {
278 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL, slow_freq);
279
280 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN,
281 (slow_freq == RTC_SLOW_FREQ_32K_XTAL) ? 1 : 0);
282
283 ets_delay_us(DELAY_SLOW_CLK_SWITCH);
284 }
285
rtc_clk_slow_freq_get(void)286 rtc_slow_freq_t rtc_clk_slow_freq_get(void)
287 {
288 return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL);
289 }
290
rtc_clk_slow_freq_get_hz(void)291 uint32_t rtc_clk_slow_freq_get_hz(void)
292 {
293 switch(rtc_clk_slow_freq_get()) {
294 case RTC_SLOW_FREQ_RTC: return RTC_SLOW_CLK_FREQ_150K;
295 case RTC_SLOW_FREQ_32K_XTAL: return RTC_SLOW_CLK_FREQ_32K;
296 case RTC_SLOW_FREQ_8MD256: return RTC_SLOW_CLK_FREQ_8MD256;
297 }
298 return 0;
299 }
300
rtc_clk_fast_freq_set(rtc_fast_freq_t fast_freq)301 void rtc_clk_fast_freq_set(rtc_fast_freq_t fast_freq)
302 {
303 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL, fast_freq);
304 ets_delay_us(DELAY_FAST_CLK_SWITCH);
305 }
306
rtc_clk_fast_freq_get(void)307 rtc_fast_freq_t rtc_clk_fast_freq_get(void)
308 {
309 return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL);
310 }
311
rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq,int pll_freq)312 void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq)
313 {
314 uint8_t div_ref;
315 uint8_t div7_0;
316 uint8_t div10_8;
317 uint8_t lref;
318 uint8_t dcur;
319 uint8_t bw;
320
321 if (pll_freq == RTC_PLL_FREQ_320M) {
322 /* Raise the voltage, if needed */
323 REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_80M_160M);
324 /* Configure 320M PLL */
325 switch (xtal_freq) {
326 case RTC_XTAL_FREQ_40M:
327 div_ref = 0;
328 div7_0 = 32;
329 div10_8 = 0;
330 lref = 0;
331 dcur = 6;
332 bw = 3;
333 break;
334 case RTC_XTAL_FREQ_26M:
335 div_ref = 12;
336 div7_0 = 224;
337 div10_8 = 4;
338 lref = 1;
339 dcur = 0;
340 bw = 1;
341 break;
342 case RTC_XTAL_FREQ_24M:
343 div_ref = 11;
344 div7_0 = 224;
345 div10_8 = 4;
346 lref = 1;
347 dcur = 0;
348 bw = 1;
349 break;
350 default:
351 div_ref = 12;
352 div7_0 = 224;
353 div10_8 = 4;
354 lref = 0;
355 dcur = 0;
356 bw = 0;
357 break;
358 }
359 REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_ENDIV5, BBPLL_ENDIV5_VAL_320M);
360 REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_BBADC_DSMP, BBPLL_BBADC_DSMP_VAL_320M);
361 } else {
362 /* Raise the voltage */
363 REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_240M);
364 ets_delay_us(DELAY_PLL_DBIAS_RAISE);
365 /* Configure 480M PLL */
366 switch (xtal_freq) {
367 case RTC_XTAL_FREQ_40M:
368 div_ref = 0;
369 div7_0 = 28;
370 div10_8 = 0;
371 lref = 0;
372 dcur = 6;
373 bw = 3;
374 break;
375 case RTC_XTAL_FREQ_26M:
376 div_ref = 12;
377 div7_0 = 144;
378 div10_8 = 4;
379 lref = 1;
380 dcur = 0;
381 bw = 1;
382 break;
383 case RTC_XTAL_FREQ_24M:
384 div_ref = 11;
385 div7_0 = 144;
386 div10_8 = 4;
387 lref = 1;
388 dcur = 0;
389 bw = 1;
390 break;
391 default:
392 div_ref = 12;
393 div7_0 = 224;
394 div10_8 = 4;
395 lref = 0;
396 dcur = 0;
397 bw = 0;
398 break;
399 }
400 REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_ENDIV5, BBPLL_ENDIV5_VAL_480M);
401 REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_BBADC_DSMP, BBPLL_BBADC_DSMP_VAL_480M);
402 }
403
404 uint8_t i2c_bbpll_lref = (lref << 7) | (div10_8 << 4) | (div_ref);
405 uint8_t i2c_bbpll_div_7_0 = div7_0;
406 uint8_t i2c_bbpll_dcur = (bw << 6) | dcur;
407 REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_LREF, i2c_bbpll_lref);
408 REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_DIV_7_0, i2c_bbpll_div_7_0);
409 REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_DCUR, i2c_bbpll_dcur);
410 uint32_t delay_pll_en = (rtc_clk_slow_freq_get() == RTC_SLOW_FREQ_RTC) ?
411 DELAY_PLL_ENABLE_WITH_150K : DELAY_PLL_ENABLE_WITH_32K;
412 ets_delay_us(delay_pll_en);
413 s_cur_pll_freq = pll_freq;
414 }
415
416 /**
417 * Switch to XTAL frequency. Does not disable the PLL.
418 */
rtc_clk_cpu_freq_to_xtal(int freq,int div)419 void rtc_clk_cpu_freq_to_xtal(int freq, int div)
420 {
421 ets_update_cpu_frequency(freq);
422 /* set divider from XTAL to APB clock */
423 REG_SET_FIELD(APB_CTRL_SYSCLK_CONF_REG, APB_CTRL_PRE_DIV_CNT, div - 1);
424 /* adjust ref_tick */
425 REG_WRITE(APB_CTRL_XTAL_TICK_CONF_REG, freq * MHZ / REF_CLK_FREQ - 1);
426 /* switch clock source */
427 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, RTC_CNTL_SOC_CLK_SEL_XTL);
428 rtc_clk_apb_freq_update(freq * MHZ);
429 /* lower the voltage */
430 if (freq <= 2) {
431 REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_2M);
432 } else {
433 REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_XTAL);
434 }
435 }
436
rtc_clk_cpu_freq_to_8m(void)437 static void rtc_clk_cpu_freq_to_8m(void)
438 {
439 ets_update_cpu_frequency(8);
440 REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_XTAL);
441 REG_SET_FIELD(APB_CTRL_SYSCLK_CONF_REG, APB_CTRL_PRE_DIV_CNT, 0);
442 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, RTC_CNTL_SOC_CLK_SEL_8M);
443 rtc_clk_apb_freq_update(RTC_FAST_CLK_FREQ_8M);
444 }
445
rtc_clk_bbpll_disable(void)446 static void rtc_clk_bbpll_disable(void)
447 {
448 SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG,
449 RTC_CNTL_BB_I2C_FORCE_PD | RTC_CNTL_BBPLL_FORCE_PD |
450 RTC_CNTL_BBPLL_I2C_FORCE_PD);
451 s_cur_pll_freq = 0;
452
453 /* is APLL under force power down? */
454 uint32_t apll_fpd = REG_GET_FIELD(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD);
455 if (apll_fpd) {
456 /* then also power down the internal I2C bus */
457 SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FORCE_PD);
458 }
459 }
460
rtc_clk_bbpll_enable(void)461 static void rtc_clk_bbpll_enable(void)
462 {
463 CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG,
464 RTC_CNTL_BIAS_I2C_FORCE_PD | RTC_CNTL_BB_I2C_FORCE_PD |
465 RTC_CNTL_BBPLL_FORCE_PD | RTC_CNTL_BBPLL_I2C_FORCE_PD);
466
467 /* reset BBPLL configuration */
468 REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_IR_CAL_DELAY, BBPLL_IR_CAL_DELAY_VAL);
469 REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_IR_CAL_EXT_CAP, BBPLL_IR_CAL_EXT_CAP_VAL);
470 REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_ENB_FCAL, BBPLL_OC_ENB_FCAL_VAL);
471 REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_ENB_VCON, BBPLL_OC_ENB_VCON_VAL);
472 REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_BBADC_CAL_7_0, BBPLL_BBADC_CAL_7_0_VAL);
473 }
474
475 /**
476 * Switch to one of PLL-based frequencies. Current frequency can be XTAL or PLL.
477 * PLL must already be enabled.
478 * @param cpu_freq new CPU frequency
479 */
rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz)480 static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz)
481 {
482 int dbias = DIG_DBIAS_80M_160M;
483 int per_conf = DPORT_CPUPERIOD_SEL_80;
484 if (cpu_freq_mhz == 80) {
485 /* nothing to do */
486 } else if (cpu_freq_mhz == 160) {
487 per_conf = DPORT_CPUPERIOD_SEL_160;
488 } else if (cpu_freq_mhz == 240) {
489 dbias = DIG_DBIAS_240M;
490 per_conf = DPORT_CPUPERIOD_SEL_240;
491 } else {
492 SOC_LOGE(TAG, "invalid frequency");
493 abort();
494 }
495 DPORT_REG_WRITE(DPORT_CPU_PER_CONF_REG, per_conf);
496 REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, dbias);
497 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, RTC_CNTL_SOC_CLK_SEL_PLL);
498 rtc_clk_apb_freq_update(80 * MHZ);
499 ets_update_cpu_frequency(cpu_freq_mhz);
500 rtc_clk_wait_for_slow_cycle();
501 }
502
rtc_clk_cpu_freq_set_xtal(void)503 void rtc_clk_cpu_freq_set_xtal(void)
504 {
505 int freq_mhz = (int) rtc_clk_xtal_freq_get();
506
507 rtc_clk_cpu_freq_to_xtal(freq_mhz, 1);
508 rtc_clk_wait_for_slow_cycle();
509 rtc_clk_bbpll_disable();
510 }
511
rtc_clk_cpu_freq_to_config(rtc_cpu_freq_t cpu_freq,rtc_cpu_freq_config_t * out_config)512 void rtc_clk_cpu_freq_to_config(rtc_cpu_freq_t cpu_freq, rtc_cpu_freq_config_t* out_config)
513 {
514 uint32_t source_freq_mhz = 0;
515 rtc_cpu_freq_src_t source = 0;
516 uint32_t freq_mhz = 0;
517 uint32_t divider = 0;
518
519 switch (cpu_freq) {
520 case RTC_CPU_FREQ_XTAL:
521 case RTC_CPU_FREQ_2M:
522 source_freq_mhz = rtc_clk_xtal_freq_get();
523 source = RTC_CPU_FREQ_SRC_XTAL;
524 if (cpu_freq == RTC_CPU_FREQ_2M) {
525 freq_mhz = 2;
526 divider = source_freq_mhz / 2;
527 } else {
528 freq_mhz = source_freq_mhz;
529 divider = 1;
530 }
531 break;
532 case RTC_CPU_FREQ_80M:
533 source = RTC_CPU_FREQ_SRC_PLL;
534 source_freq_mhz = RTC_PLL_FREQ_320M;
535 divider = 4;
536 freq_mhz = 80;
537 break;
538 case RTC_CPU_FREQ_160M:
539 source = RTC_CPU_FREQ_SRC_PLL;
540 source_freq_mhz = RTC_PLL_FREQ_320M;
541 divider = 2;
542 freq_mhz = 160;
543 break;
544 case RTC_CPU_FREQ_240M:
545 source = RTC_CPU_FREQ_SRC_PLL;
546 source_freq_mhz = RTC_PLL_FREQ_480M;
547 divider = 2;
548 freq_mhz = 240;
549 break;
550 default:
551 SOC_LOGE(TAG, "invalid rtc_cpu_freq_t value");
552 abort();
553 }
554
555 *out_config = (rtc_cpu_freq_config_t) {
556 .source = source,
557 .source_freq_mhz = source_freq_mhz,
558 .div = divider,
559 .freq_mhz = freq_mhz
560 };
561 }
562
rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz,rtc_cpu_freq_config_t * out_config)563 bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t* out_config)
564 {
565 uint32_t source_freq_mhz = 0;
566 rtc_cpu_freq_src_t source = 0;
567 uint32_t divider = 0;
568 uint32_t real_freq_mhz = 0;
569
570 uint32_t xtal_freq = (uint32_t) rtc_clk_xtal_freq_get();
571 if (freq_mhz <= xtal_freq) {
572 divider = xtal_freq / freq_mhz;
573 real_freq_mhz = (xtal_freq + divider / 2) / divider; /* round */
574 if (real_freq_mhz != freq_mhz) {
575 // no suitable divider
576 return false;
577 }
578
579 source_freq_mhz = xtal_freq;
580 source = RTC_CPU_FREQ_SRC_XTAL;
581 } else if (freq_mhz == 80) {
582 real_freq_mhz = freq_mhz;
583 source = RTC_CPU_FREQ_SRC_PLL;
584 source_freq_mhz = RTC_PLL_FREQ_320M;
585 divider = 4;
586 } else if (freq_mhz == 160) {
587 real_freq_mhz = freq_mhz;
588 source = RTC_CPU_FREQ_SRC_PLL;
589 source_freq_mhz = RTC_PLL_FREQ_320M;
590 divider = 2;
591 } else if (freq_mhz == 240) {
592 real_freq_mhz = freq_mhz;
593 source = RTC_CPU_FREQ_SRC_PLL;
594 source_freq_mhz = RTC_PLL_FREQ_480M;
595 divider = 2;
596 } else {
597 // unsupported frequency
598 return false;
599 }
600 *out_config = (rtc_cpu_freq_config_t) {
601 .source = source,
602 .div = divider,
603 .source_freq_mhz = source_freq_mhz,
604 .freq_mhz = real_freq_mhz
605 };
606 return true;
607 }
608
rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t * config)609 void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t* config)
610 {
611 rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
612 uint32_t soc_clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL);
613 if (soc_clk_sel != RTC_CNTL_SOC_CLK_SEL_XTL) {
614 rtc_clk_cpu_freq_to_xtal(xtal_freq, 1);
615 rtc_clk_wait_for_slow_cycle();
616 }
617 if (soc_clk_sel == RTC_CNTL_SOC_CLK_SEL_PLL) {
618 rtc_clk_bbpll_disable();
619 }
620 if (config->source == RTC_CPU_FREQ_SRC_XTAL) {
621 if (config->div > 1) {
622 rtc_clk_cpu_freq_to_xtal(config->freq_mhz, config->div);
623 }
624 } else if (config->source == RTC_CPU_FREQ_SRC_PLL) {
625 rtc_clk_bbpll_enable();
626 rtc_clk_wait_for_slow_cycle();
627 rtc_clk_bbpll_configure(rtc_clk_xtal_freq_get(), config->source_freq_mhz);
628 rtc_clk_cpu_freq_to_pll_mhz(config->freq_mhz);
629 } else if (config->source == RTC_CPU_FREQ_SRC_8M) {
630 rtc_clk_cpu_freq_to_8m();
631 }
632 }
633
rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t * out_config)634 void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t* out_config)
635 {
636 rtc_cpu_freq_src_t source = 0;
637 uint32_t source_freq_mhz = 0;
638 uint32_t div = 0;
639 uint32_t freq_mhz = 0;
640 uint32_t soc_clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL);
641 switch (soc_clk_sel) {
642 case RTC_CNTL_SOC_CLK_SEL_XTL: {
643 source = RTC_CPU_FREQ_SRC_XTAL;
644 div = REG_GET_FIELD(APB_CTRL_SYSCLK_CONF_REG, APB_CTRL_PRE_DIV_CNT) + 1;
645 source_freq_mhz = (uint32_t) rtc_clk_xtal_freq_get();
646 freq_mhz = source_freq_mhz / div;
647 }
648 break;
649 case RTC_CNTL_SOC_CLK_SEL_PLL: {
650 source = RTC_CPU_FREQ_SRC_PLL;
651 uint32_t cpuperiod_sel = DPORT_REG_GET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL);
652 if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_80) {
653 source_freq_mhz = RTC_PLL_FREQ_320M;
654 div = 4;
655 freq_mhz = 80;
656 } else if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_160) {
657 source_freq_mhz = RTC_PLL_FREQ_320M;
658 div = 2;
659 freq_mhz = 160;
660 } else if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_240) {
661 source_freq_mhz = RTC_PLL_FREQ_480M;
662 div = 2;
663 freq_mhz = 240;
664 } else {
665 SOC_LOGE(TAG, "unsupported frequency configuration");
666 abort();
667 }
668 break;
669 }
670 case RTC_CNTL_SOC_CLK_SEL_8M:
671 source = RTC_CPU_FREQ_SRC_8M;
672 source_freq_mhz = 8;
673 div = 1;
674 freq_mhz = source_freq_mhz;
675 break;
676 case RTC_CNTL_SOC_CLK_SEL_APLL:
677 default:
678 SOC_LOGE(TAG, "unsupported frequency configuration");
679 abort();
680 }
681 *out_config = (rtc_cpu_freq_config_t) {
682 .source = source,
683 .source_freq_mhz = source_freq_mhz,
684 .div = div,
685 .freq_mhz = freq_mhz
686 };
687 }
688
rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t * config)689 void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t* config)
690 {
691 if (config->source == RTC_CPU_FREQ_SRC_XTAL) {
692 rtc_clk_cpu_freq_to_xtal(config->freq_mhz, config->div);
693 } else if (config->source == RTC_CPU_FREQ_SRC_PLL &&
694 s_cur_pll_freq == config->source_freq_mhz) {
695 rtc_clk_cpu_freq_to_pll_mhz(config->freq_mhz);
696 } else {
697 /* fallback */
698 rtc_clk_cpu_freq_set_config(config);
699 }
700 }
701
rtc_clk_xtal_freq_get(void)702 rtc_xtal_freq_t rtc_clk_xtal_freq_get(void)
703 {
704 /* We may have already written XTAL value into RTC_XTAL_FREQ_REG */
705 uint32_t xtal_freq_reg = READ_PERI_REG(RTC_XTAL_FREQ_REG);
706 if (!clk_val_is_valid(xtal_freq_reg)) {
707 return RTC_XTAL_FREQ_AUTO;
708 }
709 return reg_val_to_clk_val(xtal_freq_reg & ~RTC_DISABLE_ROM_LOG);
710 }
711
rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq)712 void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq)
713 {
714 uint32_t reg = READ_PERI_REG(RTC_XTAL_FREQ_REG) & RTC_DISABLE_ROM_LOG;
715 if (reg == RTC_DISABLE_ROM_LOG) {
716 xtal_freq |= 1;
717 }
718 WRITE_PERI_REG(RTC_XTAL_FREQ_REG, clk_val_to_reg_val(xtal_freq));
719 }
720
rtc_clk_apb_freq_update(uint32_t apb_freq)721 void rtc_clk_apb_freq_update(uint32_t apb_freq)
722 {
723 WRITE_PERI_REG(RTC_APB_FREQ_REG, clk_val_to_reg_val(apb_freq >> 12));
724 }
725
rtc_clk_apb_freq_get(void)726 uint32_t rtc_clk_apb_freq_get(void)
727 {
728 uint32_t freq_hz = reg_val_to_clk_val(READ_PERI_REG(RTC_APB_FREQ_REG)) << 12;
729 // round to the nearest MHz
730 freq_hz += MHZ / 2;
731 uint32_t remainder = freq_hz % MHZ;
732 return freq_hz - remainder;
733 }
734
735 /* Name used in libphy.a:phy_chip_v7.o
736 * TODO: update the library to use rtc_clk_xtal_freq_get
737 */
738 rtc_xtal_freq_t rtc_get_xtal(void) __attribute__((alias("rtc_clk_xtal_freq_get")));
739
