1 /**
2 ******************************************************************************
3 * @file system_stm32h5xx.c
4 * @author MCD Application Team
5 * @brief CMSIS Cortex-M33 Device Peripheral Access Layer System Source File
6 *
7 * This file provides two functions and one global variable to be called from
8 * user application:
9 * - SystemInit(): This function is called at startup just after reset and
10 * before branch to main program. This call is made inside
11 * the "startup_stm32h5xx.s" file.
12 *
13 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
14 * by the user application to setup the SysTick
15 * timer or configure other parameters.
16 *
17 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
18 * be called whenever the core clock is changed
19 * during program execution.
20 *
21 * After each device reset the MSI (4 MHz) is used as system clock source.
22 * Then SystemInit() function is called, in "startup_stm32h5xx.s" file, to
23 * configure the system clock before to branch to main program.
24 *
25 ******************************************************************************
26 * @attention
27 *
28 * Copyright (c) 2023 STMicroelectronics.
29 * All rights reserved.
30 *
31 * This software component is licensed by ST under BSD 3-Clause license,
32 * the "License"; You may not use this file except in compliance with the
33 * License. You may obtain a copy of the License at:
34 * opensource.org/licenses/BSD-3-Clause
35 *
36 ******************************************************************************
37 */
38
39 /** @addtogroup CMSIS
40 * @{
41 */
42
43 /** @addtogroup STM32H5xx_system
44 * @{
45 */
46
47 /** @addtogroup STM32H5xx_System_Private_Includes
48 * @{
49 */
50
51 #include "stm32h5xx.h"
52 #include <math.h>
53
54 /**
55 * @}
56 */
57
58 /** @addtogroup STM32H5xx_System_Private_TypesDefinitions
59 * @{
60 */
61
62 #if defined ( __ICCARM__ )
63 # define CMSE_NS_ENTRY __cmse_nonsecure_entry
64 #else
65 # define CMSE_NS_ENTRY __attribute((cmse_nonsecure_entry))
66 #endif
67 /**
68 * @}
69 */
70
71 /** @addtogroup STM32H5xx_System_Private_Defines
72 * @{
73 */
74
75 #if !defined (HSE_VALUE)
76 #define HSE_VALUE (25000000U) /*!< Value of the External oscillator in Hz */
77 #endif /* HSE_VALUE */
78
79 #if !defined (CSI_VALUE)
80 #define CSI_VALUE (4000000U) /*!< Value of the Internal oscillator in Hz*/
81 #endif /* MSI_VALUE */
82
83 #if !defined (HSI_VALUE)
84 #define HSI_VALUE (64000000U) /*!< Value of the Internal oscillator in Hz */
85 #endif /* HSI_VALUE */
86
87 /************************* Miscellaneous Configuration ************************/
88 /*!< Uncomment the following line if you need to relocate your vector Table in
89 Internal SRAM. */
90 /* #define VECT_TAB_SRAM */
91 #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
92 This value must be a multiple of 0x200. */
93 /******************************************************************************/
94
95 /**
96 * @}
97 */
98
99 /** @addtogroup STM32H5xx_System_Private_Macros
100 * @{
101 */
102
103 /**
104 * @}
105 */
106
107 /** @addtogroup STM32H5xx_System_Private_Variables
108 * @{
109 */
110 /* The SystemCoreClock variable is updated in three ways:
111 1) by calling CMSIS function SystemCoreClockUpdate()
112 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
113 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
114 Note: If you use this function to configure the system clock; then there
115 is no need to call the 2 first functions listed above, since SystemCoreClock
116 variable is updated automatically.
117 */
118 uint32_t SystemCoreClock = 64000000U;
119
120 const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
121 const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
122 /**
123 * @}
124 */
125
126 /** @addtogroup STM32H5xx_System_Private_FunctionPrototypes
127 * @{
128 */
129
130 /**
131 * @}
132 */
133
134 /** @addtogroup STM32H5xx_System_Private_Functions
135 * @{
136 */
137
138 /**
139 * @brief Setup the microcontroller system.
140 * @param None
141 * @retval None
142 */
143
SystemInit(void)144 void SystemInit(void)
145 {
146 /* FPU settings ------------------------------------------------------------*/
147 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
148 SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */
149 SCB_NS->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */
150 #endif
151 }
152
153 /**
154 * @brief Update SystemCoreClock variable according to Clock Register Values.
155 * The SystemCoreClock variable contains the core clock (HCLK), it can
156 * be used by the user application to setup the SysTick timer or configure
157 * other parameters.
158 *
159 * @note Depending on secure or non-secure compilation, the adequate RCC peripheral
160 * memory are is accessed thanks to RCC alias defined in stm32h5xxxx.h device file
161 * so either from RCC_S peripheral register mapped memory in secure or from
162 * RCC_NS peripheral register mapped memory in non-secure.
163 *
164 * @note Each time the core clock (HCLK) changes, this function must be called
165 * to update SystemCoreClock variable value. Otherwise, any configuration
166 * based on this variable will be incorrect.
167 *
168 * @note - The system frequency computed by this function is not the real
169 * frequency in the chip. It is calculated based on the predefined
170 * constant and the selected clock source:
171 *
172 * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
173 *
174 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
175 *
176 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
177 *
178 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
179 * or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
180 *
181 * (*) MSI_VALUE is a constant defined in stm32h5xx_hal.h file (default value
182 * 4 MHz) but the real value may vary depending on the variations
183 * in voltage and temperature.
184 *
185 * (**) HSI_VALUE is a constant defined in stm32h5xx_hal.h file (default value
186 * 16 MHz) but the real value may vary depending on the variations
187 * in voltage and temperature.
188 *
189 * (***) HSE_VALUE is a constant defined in stm32h5xx_hal.h file (default value
190 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
191 * frequency of the crystal used. Otherwise, this function may
192 * have wrong result.
193 *
194 * - The result of this function could be not correct when using fractional
195 * value for HSE crystal.
196 *
197 * @param None
198 * @retval None
199 */
SystemCoreClockUpdate(void)200 void SystemCoreClockUpdate(void)
201 {
202 uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp;
203 float_t fracn1, pllvco;
204
205
206 /* Get SYSCLK source -------------------------------------------------------*/
207 switch (RCC->CFGR1 & RCC_CFGR1_SWS)
208 {
209 case 0x00: /* MSI used as system clock source */
210 SystemCoreClock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
211 break;
212
213 case 0x08: /* CSI used as system clock source */
214 SystemCoreClock = CSI_VALUE;
215 break;
216
217 case 0x10: /* HSE used as system clock source */
218 SystemCoreClock = HSE_VALUE;
219 break;
220
221 case 0x18: /* PLL1 used as system clock source */
222 /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
223 SYSCLK = PLL_VCO / PLLR
224 */
225 pllsource = (RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC);
226 pllm = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M)>> RCC_PLL1CFGR_PLL1M_Pos);
227 pllfracen = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1FRACEN)>>RCC_PLL1CFGR_PLL1FRACEN_Pos);
228 fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_PLL1FRACN)>> RCC_PLL1FRACR_PLL1FRACN_Pos));
229
230 switch (pllsource)
231 {
232 case 0x00: /* No clock sent to PLL*/
233 pllvco = 0U;
234 break;
235
236 case 0x01: /* HSI used as PLL clock source */
237 hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ;
238 pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + (fracn1/(float_t)0x2000) +(float_t)1 );
239 break;
240
241 case 0x02: /* HSI used as PLL clock source */
242 pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + (fracn1/(float_t)0x2000) +(float_t)1 );
243 break;
244
245 case 0x03: /* HSE used as PLL clock source */
246 pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + (fracn1/(float_t)0x2000) +(float_t)1 );
247 break;
248
249 default: /* MSI used as PLL clock source */
250 pllvco = 0U;
251
252 break;
253 }
254
255 pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1P) >>RCC_PLL1DIVR_PLL1P_Pos) + 1U ) ;
256 SystemCoreClock = (uint32_t)(float_t)(pllvco/(float_t)pllp);
257
258 break;
259
260 default:
261 SystemCoreClock = HSI_VALUE;
262 break;
263 }
264 /* Compute HCLK clock frequency --------------------------------------------*/
265 /* Get HCLK prescaler */
266 tmp = AHBPrescTable[((RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos)];
267 /* HCLK clock frequency */
268 SystemCoreClock >>= tmp;
269
270 }
271
272 /**
273 * @brief Secure Non-Secure-Callable function to return the current
274 * SystemCoreClock value after SystemCoreClock update.
275 * The SystemCoreClock variable contains the core clock (HCLK), it can
276 * be used by the user application to setup the SysTick timer or configure
277 * other parameters.
278 * @retval SystemCoreClock value (HCLK)
279
280 CMSE_NS_ENTRY uint32_t SECURE_SystemCoreClockUpdate(void)
281 {
282 SystemCoreClockUpdate();
283
284 return SystemCoreClock;
285 }*/
286
287 /**
288 * @}
289 */
290
291 /**
292 * @}
293 */
294
295 /**
296 * @}
297 */
298
