1/*
2 * Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
3 * an affiliate of Cypress Semiconductor Corporation
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8#include <zephyr/dt-bindings/gpio/gpio.h>
9#include <zephyr/dt-bindings/pinctrl/ifx_cat1-pinctrl.h>
10#include "psoc6_01.dtsi"
11
12/ {
13	soc {
14		/delete-node/ gpio@40320100; // gpio_prt2
15		/delete-node/ gpio@40320180; // gpio_prt3
16		/delete-node/ gpio@40320200; // gpio_prt4
17		/delete-node/ gpio@40320680; // gpio_prt13
18
19		pinctrl: pinctrl@40310000 {
20			/* scb_i2c_scl */
21			/omit-if-no-ref/ p0_2_scb0_i2c_scl: p0_2_scb0_i2c_scl {
22				pinmux = <DT_CAT1_PINMUX(0, 2, HSIOM_SEL_ACT_7)>;
23			};
24			/omit-if-no-ref/ p1_0_scb7_i2c_scl: p1_0_scb7_i2c_scl {
25				pinmux = <DT_CAT1_PINMUX(1, 0, HSIOM_SEL_ACT_7)>;
26			};
27			/omit-if-no-ref/ p5_0_scb5_i2c_scl: p5_0_scb5_i2c_scl {
28				pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_7)>;
29			};
30			/omit-if-no-ref/ p6_0_scb3_i2c_scl: p6_0_scb3_i2c_scl {
31				pinmux = <DT_CAT1_PINMUX(6, 0, HSIOM_SEL_ACT_7)>;
32			};
33			/omit-if-no-ref/ p6_0_scb8_i2c_scl: p6_0_scb8_i2c_scl {
34				pinmux = <DT_CAT1_PINMUX(6, 0, HSIOM_SEL_DS_2)>;
35			};
36			/omit-if-no-ref/ p6_4_scb6_i2c_scl: p6_4_scb6_i2c_scl {
37				pinmux = <DT_CAT1_PINMUX(6, 4, HSIOM_SEL_ACT_7)>;
38			};
39			/omit-if-no-ref/ p6_4_scb8_i2c_scl: p6_4_scb8_i2c_scl {
40				pinmux = <DT_CAT1_PINMUX(6, 4, HSIOM_SEL_DS_2)>;
41			};
42			/omit-if-no-ref/ p7_0_scb4_i2c_scl: p7_0_scb4_i2c_scl {
43				pinmux = <DT_CAT1_PINMUX(7, 0, HSIOM_SEL_ACT_7)>;
44			};
45			/omit-if-no-ref/ p8_0_scb4_i2c_scl: p8_0_scb4_i2c_scl {
46				pinmux = <DT_CAT1_PINMUX(8, 0, HSIOM_SEL_ACT_7)>;
47			};
48			/omit-if-no-ref/ p9_0_scb2_i2c_scl: p9_0_scb2_i2c_scl {
49				pinmux = <DT_CAT1_PINMUX(9, 0, HSIOM_SEL_ACT_7)>;
50			};
51			/omit-if-no-ref/ p10_0_scb1_i2c_scl: p10_0_scb1_i2c_scl {
52				pinmux = <DT_CAT1_PINMUX(10, 0, HSIOM_SEL_ACT_7)>;
53			};
54			/omit-if-no-ref/ p11_0_scb5_i2c_scl: p11_0_scb5_i2c_scl {
55				pinmux = <DT_CAT1_PINMUX(11, 0, HSIOM_SEL_ACT_7)>;
56			};
57			/omit-if-no-ref/ p12_0_scb6_i2c_scl: p12_0_scb6_i2c_scl {
58				pinmux = <DT_CAT1_PINMUX(12, 0, HSIOM_SEL_ACT_7)>;
59			};
60
61			/* scb_i2c_sda */
62			/omit-if-no-ref/ p0_3_scb0_i2c_sda: p0_3_scb0_i2c_sda {
63				pinmux = <DT_CAT1_PINMUX(0, 3, HSIOM_SEL_ACT_7)>;
64			};
65			/omit-if-no-ref/ p1_1_scb7_i2c_sda: p1_1_scb7_i2c_sda {
66				pinmux = <DT_CAT1_PINMUX(1, 1, HSIOM_SEL_ACT_7)>;
67			};
68			/omit-if-no-ref/ p5_1_scb5_i2c_sda: p5_1_scb5_i2c_sda {
69				pinmux = <DT_CAT1_PINMUX(5, 1, HSIOM_SEL_ACT_7)>;
70			};
71			/omit-if-no-ref/ p6_1_scb3_i2c_sda: p6_1_scb3_i2c_sda {
72				pinmux = <DT_CAT1_PINMUX(6, 1, HSIOM_SEL_ACT_7)>;
73			};
74			/omit-if-no-ref/ p6_1_scb8_i2c_sda: p6_1_scb8_i2c_sda {
75				pinmux = <DT_CAT1_PINMUX(6, 1, HSIOM_SEL_DS_2)>;
76			};
77			/omit-if-no-ref/ p6_5_scb6_i2c_sda: p6_5_scb6_i2c_sda {
78				pinmux = <DT_CAT1_PINMUX(6, 5, HSIOM_SEL_ACT_7)>;
79			};
80			/omit-if-no-ref/ p6_5_scb8_i2c_sda: p6_5_scb8_i2c_sda {
81				pinmux = <DT_CAT1_PINMUX(6, 5, HSIOM_SEL_DS_2)>;
82			};
83			/omit-if-no-ref/ p7_1_scb4_i2c_sda: p7_1_scb4_i2c_sda {
84				pinmux = <DT_CAT1_PINMUX(7, 1, HSIOM_SEL_ACT_7)>;
85			};
86			/omit-if-no-ref/ p8_1_scb4_i2c_sda: p8_1_scb4_i2c_sda {
87				pinmux = <DT_CAT1_PINMUX(8, 1, HSIOM_SEL_ACT_7)>;
88			};
89			/omit-if-no-ref/ p9_1_scb2_i2c_sda: p9_1_scb2_i2c_sda {
90				pinmux = <DT_CAT1_PINMUX(9, 1, HSIOM_SEL_ACT_7)>;
91			};
92			/omit-if-no-ref/ p10_1_scb1_i2c_sda: p10_1_scb1_i2c_sda {
93				pinmux = <DT_CAT1_PINMUX(10, 1, HSIOM_SEL_ACT_7)>;
94			};
95			/omit-if-no-ref/ p11_1_scb5_i2c_sda: p11_1_scb5_i2c_sda {
96				pinmux = <DT_CAT1_PINMUX(11, 1, HSIOM_SEL_ACT_7)>;
97			};
98			/omit-if-no-ref/ p12_1_scb6_i2c_sda: p12_1_scb6_i2c_sda {
99				pinmux = <DT_CAT1_PINMUX(12, 1, HSIOM_SEL_ACT_7)>;
100			};
101
102			/* scb_uart_cts */
103			/omit-if-no-ref/ p0_5_scb0_uart_cts: p0_5_scb0_uart_cts {
104				pinmux = <DT_CAT1_PINMUX(0, 5, HSIOM_SEL_ACT_6)>;
105			};
106			/omit-if-no-ref/ p5_3_scb5_uart_cts: p5_3_scb5_uart_cts {
107				pinmux = <DT_CAT1_PINMUX(5, 3, HSIOM_SEL_ACT_6)>;
108			};
109			/omit-if-no-ref/ p6_3_scb3_uart_cts: p6_3_scb3_uart_cts {
110				pinmux = <DT_CAT1_PINMUX(6, 3, HSIOM_SEL_ACT_6)>;
111			};
112			/omit-if-no-ref/ p6_7_scb6_uart_cts: p6_7_scb6_uart_cts {
113				pinmux = <DT_CAT1_PINMUX(6, 7, HSIOM_SEL_ACT_6)>;
114			};
115			/omit-if-no-ref/ p7_3_scb4_uart_cts: p7_3_scb4_uart_cts {
116				pinmux = <DT_CAT1_PINMUX(7, 3, HSIOM_SEL_ACT_6)>;
117			};
118			/omit-if-no-ref/ p8_3_scb4_uart_cts: p8_3_scb4_uart_cts {
119				pinmux = <DT_CAT1_PINMUX(8, 3, HSIOM_SEL_ACT_6)>;
120			};
121			/omit-if-no-ref/ p9_3_scb2_uart_cts: p9_3_scb2_uart_cts {
122				pinmux = <DT_CAT1_PINMUX(9, 3, HSIOM_SEL_ACT_6)>;
123			};
124			/omit-if-no-ref/ p11_3_scb5_uart_cts: p11_3_scb5_uart_cts {
125				pinmux = <DT_CAT1_PINMUX(11, 3, HSIOM_SEL_ACT_6)>;
126			};
127			/omit-if-no-ref/ p12_3_scb6_uart_cts: p12_3_scb6_uart_cts {
128				pinmux = <DT_CAT1_PINMUX(12, 3, HSIOM_SEL_ACT_6)>;
129			};
130
131			/* scb_uart_rts */
132			/omit-if-no-ref/ p0_4_scb0_uart_rts: p0_4_scb0_uart_rts {
133				pinmux = <DT_CAT1_PINMUX(0, 4, HSIOM_SEL_ACT_6)>;
134			};
135			/omit-if-no-ref/ p5_2_scb5_uart_rts: p5_2_scb5_uart_rts {
136				pinmux = <DT_CAT1_PINMUX(5, 2, HSIOM_SEL_ACT_6)>;
137			};
138			/omit-if-no-ref/ p6_2_scb3_uart_rts: p6_2_scb3_uart_rts {
139				pinmux = <DT_CAT1_PINMUX(6, 2, HSIOM_SEL_ACT_6)>;
140			};
141			/omit-if-no-ref/ p6_6_scb6_uart_rts: p6_6_scb6_uart_rts {
142				pinmux = <DT_CAT1_PINMUX(6, 6, HSIOM_SEL_ACT_6)>;
143			};
144			/omit-if-no-ref/ p7_2_scb4_uart_rts: p7_2_scb4_uart_rts {
145				pinmux = <DT_CAT1_PINMUX(7, 2, HSIOM_SEL_ACT_6)>;
146			};
147			/omit-if-no-ref/ p8_2_scb4_uart_rts: p8_2_scb4_uart_rts {
148				pinmux = <DT_CAT1_PINMUX(8, 2, HSIOM_SEL_ACT_6)>;
149			};
150			/omit-if-no-ref/ p9_2_scb2_uart_rts: p9_2_scb2_uart_rts {
151				pinmux = <DT_CAT1_PINMUX(9, 2, HSIOM_SEL_ACT_6)>;
152			};
153			/omit-if-no-ref/ p11_2_scb5_uart_rts: p11_2_scb5_uart_rts {
154				pinmux = <DT_CAT1_PINMUX(11, 2, HSIOM_SEL_ACT_6)>;
155			};
156			/omit-if-no-ref/ p12_2_scb6_uart_rts: p12_2_scb6_uart_rts {
157				pinmux = <DT_CAT1_PINMUX(12, 2, HSIOM_SEL_ACT_6)>;
158			};
159
160			/* scb_uart_rx */
161			/omit-if-no-ref/ p0_2_scb0_uart_rx: p0_2_scb0_uart_rx {
162				pinmux = <DT_CAT1_PINMUX(0, 2, HSIOM_SEL_ACT_6)>;
163			};
164			/omit-if-no-ref/ p1_0_scb7_uart_rx: p1_0_scb7_uart_rx {
165				pinmux = <DT_CAT1_PINMUX(1, 0, HSIOM_SEL_ACT_6)>;
166			};
167			/omit-if-no-ref/ p5_0_scb5_uart_rx: p5_0_scb5_uart_rx {
168				pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_6)>;
169			};
170			/omit-if-no-ref/ p6_0_scb3_uart_rx: p6_0_scb3_uart_rx {
171				pinmux = <DT_CAT1_PINMUX(6, 0, HSIOM_SEL_ACT_6)>;
172			};
173			/omit-if-no-ref/ p6_4_scb6_uart_rx: p6_4_scb6_uart_rx {
174				pinmux = <DT_CAT1_PINMUX(6, 4, HSIOM_SEL_ACT_6)>;
175			};
176			/omit-if-no-ref/ p7_0_scb4_uart_rx: p7_0_scb4_uart_rx {
177				pinmux = <DT_CAT1_PINMUX(7, 0, HSIOM_SEL_ACT_6)>;
178			};
179			/omit-if-no-ref/ p8_0_scb4_uart_rx: p8_0_scb4_uart_rx {
180				pinmux = <DT_CAT1_PINMUX(8, 0, HSIOM_SEL_ACT_6)>;
181			};
182			/omit-if-no-ref/ p9_0_scb2_uart_rx: p9_0_scb2_uart_rx {
183				pinmux = <DT_CAT1_PINMUX(9, 0, HSIOM_SEL_ACT_6)>;
184			};
185			/omit-if-no-ref/ p10_0_scb1_uart_rx: p10_0_scb1_uart_rx {
186				pinmux = <DT_CAT1_PINMUX(10, 0, HSIOM_SEL_ACT_6)>;
187			};
188			/omit-if-no-ref/ p11_0_scb5_uart_rx: p11_0_scb5_uart_rx {
189				pinmux = <DT_CAT1_PINMUX(11, 0, HSIOM_SEL_ACT_6)>;
190			};
191			/omit-if-no-ref/ p12_0_scb6_uart_rx: p12_0_scb6_uart_rx {
192				pinmux = <DT_CAT1_PINMUX(12, 0, HSIOM_SEL_ACT_6)>;
193			};
194
195			/* scb_uart_tx */
196			/omit-if-no-ref/ p0_3_scb0_uart_tx: p0_3_scb0_uart_tx {
197				pinmux = <DT_CAT1_PINMUX(0, 3, HSIOM_SEL_ACT_6)>;
198			};
199			/omit-if-no-ref/ p1_1_scb7_uart_tx: p1_1_scb7_uart_tx {
200				pinmux = <DT_CAT1_PINMUX(1, 1, HSIOM_SEL_ACT_6)>;
201			};
202			/omit-if-no-ref/ p5_1_scb5_uart_tx: p5_1_scb5_uart_tx {
203				pinmux = <DT_CAT1_PINMUX(5, 1, HSIOM_SEL_ACT_6)>;
204			};
205			/omit-if-no-ref/ p6_1_scb3_uart_tx: p6_1_scb3_uart_tx {
206				pinmux = <DT_CAT1_PINMUX(6, 1, HSIOM_SEL_ACT_6)>;
207			};
208			/omit-if-no-ref/ p6_5_scb6_uart_tx: p6_5_scb6_uart_tx {
209				pinmux = <DT_CAT1_PINMUX(6, 5, HSIOM_SEL_ACT_6)>;
210			};
211			/omit-if-no-ref/ p7_1_scb4_uart_tx: p7_1_scb4_uart_tx {
212				pinmux = <DT_CAT1_PINMUX(7, 1, HSIOM_SEL_ACT_6)>;
213			};
214			/omit-if-no-ref/ p8_1_scb4_uart_tx: p8_1_scb4_uart_tx {
215				pinmux = <DT_CAT1_PINMUX(8, 1, HSIOM_SEL_ACT_6)>;
216			};
217			/omit-if-no-ref/ p9_1_scb2_uart_tx: p9_1_scb2_uart_tx {
218				pinmux = <DT_CAT1_PINMUX(9, 1, HSIOM_SEL_ACT_6)>;
219			};
220			/omit-if-no-ref/ p10_1_scb1_uart_tx: p10_1_scb1_uart_tx {
221				pinmux = <DT_CAT1_PINMUX(10, 1, HSIOM_SEL_ACT_6)>;
222			};
223			/omit-if-no-ref/ p11_1_scb5_uart_tx: p11_1_scb5_uart_tx {
224				pinmux = <DT_CAT1_PINMUX(11, 1, HSIOM_SEL_ACT_6)>;
225			};
226			/omit-if-no-ref/ p12_1_scb6_uart_tx: p12_1_scb6_uart_tx {
227				pinmux = <DT_CAT1_PINMUX(12, 1, HSIOM_SEL_ACT_6)>;
228			};
229
230		};
231	};
232};
233