1 /*
2 * Copyright 2023-2024 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 /***********************************************************************************************************************
8 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
9 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
10 **********************************************************************************************************************/
11 /*
12 * How to set up clock using clock driver functions:
13 *
14 * 1. Setup clock sources.
15 *
16 * 2. Set up all selectors to provide selected clocks.
17 *
18 * 3. Set up all dividers.
19 */
20
21 #include "fsl_clock.h"
22 #include "clock_config.h"
23 #include "fsl_power.h"
24
25 /*******************************************************************************
26 * Definitions
27 ******************************************************************************/
28
29 /*******************************************************************************
30 * Variables
31 ******************************************************************************/
32 /* System clock frequency. */
33 extern uint32_t SystemCoreClock;
34
35 /*PLL 528MHZ*/
36 const clock_main_pll_config_t g_mainPllConfig_BOARD_BootClockRUN = {
37 .main_pll_src = kCLOCK_MainPllOscClk, /* OSC clock */
38 .numerator = 0, /* Numerator of the SYSPLL0 fractional loop divider is 0 */
39 .denominator = 1, /* Denominator of the SYSPLL0 fractional loop divider is 1 */
40 .main_pll_mult = kCLOCK_MainPllMult22 /* Divide by 22 */
41 };
42
43 const clock_audio_pll_config_t g_audioPllConfig_BOARD_BootClockRUN = {
44 .audio_pll_src = kCLOCK_AudioPllOscClk, /* OSC clock */
45 .numerator = 5040, /* Numerator of the Audio PLL fractional loop divider is 0 */
46 .denominator = 27000, /* Denominator of the Audio PLL fractional loop divider is 1 */
47 .audio_pll_mult = kCLOCK_AudioPllMult22, /* Divide by 22 */
48 .enableVcoOut = true
49 };
50 /*******************************************************************************
51 ************************ BOARD_InitBootClocks function ************************
52 ******************************************************************************/
53 /*FUNCTION**********************************************************************
54 *
55 * Function Name : BOARD_XspiClockSafeConfig
56 * Description : XSPI clock source safe configuration weak function.
57 * Called before clock source(Such as PLL, Main clock) configuration.
58 * Note : Users need override this function to change XSPI clock source to stable source when executing
59 * code on XSPI memory(XIP). If XIP, the function should runs in RAM and move the XSPI clock
60 *source to an stable clock to avoid instruction/data fetch issue during clock updating.
61 *END**************************************************************************/
BOARD_XspiClockSafeConfig(void)62 __attribute__((weak)) void BOARD_XspiClockSafeConfig(void)
63 {
64 }
65
BOARD_SetXspiClock(XSPI_Type * base,uint32_t src,uint32_t divider)66 __attribute__((weak)) void BOARD_SetXspiClock(XSPI_Type *base, uint32_t src, uint32_t divider)
67 {
68 }
69
BOARD_InitBootClocks(void)70 void BOARD_InitBootClocks(void)
71 {
72 BOARD_BootClockRUN();
73 }
74
75 /*******************************************************************************
76 ********************** Configuration BOARD_BootClockRUN ***********************
77 ******************************************************************************/
78
79 /*******************************************************************************
80 * Variables for BOARD_BootClockRUN configuration
81 ******************************************************************************/
82
83 /*******************************************************************************
84 * Code for BOARD_BootClockRUN configuration
85 ******************************************************************************/
BOARD_BootClockRUN(void)86 void BOARD_BootClockRUN(void)
87 {
88 const clock_fro_config_t froAutotrimCfg = {
89 .targetFreq = 300000000U,
90 .range = 50U,
91 .trim1DelayUs = 15U,
92 .trim2DelayUs = 150U,
93 .refDiv = 1U,
94 .enableInt = 0U,
95 .coarseTrimEn = true,
96 };
97
98 POWER_DisablePD(kPDRUNCFG_PD_LPOSC);
99
100 /* Power up OSC */
101 POWER_DisablePD(kPDRUNCFG_PD_SYSXTAL);
102 CLOCK_EnableSysOscClk(true, true, BOARD_SYSOSC_SETTLING_US); /* Enable system OSC */
103 CLOCK_SetXtalFreq(BOARD_XTAL_SYS_CLK_HZ); /* Sets external XTAL OSC freq */
104
105 POWER_DisablePD(kPDRUNCFG_PD_FRO1); /* Make sure FRO1 is enabled. */
106
107 /* Switch to FRO1 for safe configure. */
108 CLOCK_AttachClk(kFRO1_DIV1_to_COMPUTE_BASE);
109 CLOCK_AttachClk(kCOMPUTE_BASE_to_COMPUTE_MAIN);
110 CLOCK_SetClkDiv(kCLOCK_DivCmptMainClk, 1U);
111 CLOCK_AttachClk(kFRO1_DIV1_to_RAM);
112 CLOCK_SetClkDiv(kCLOCK_DivComputeRamClk, 1U);
113 CLOCK_AttachClk(kFRO1_DIV1_to_COMMON_BASE);
114 CLOCK_AttachClk(kCOMMON_BASE_to_COMMON_VDDN);
115 CLOCK_SetClkDiv(kCLOCK_DivCommonVddnClk, 1U);
116
117 BOARD_XspiClockSafeConfig(); /*Change to common_base clock(Sourced by FRO1). */
118
119 /* Ungate all FRO clock. */
120 POWER_DisablePD(kPDRUNCFG_GATE_FRO0);
121 CLOCK_EnableFroClkFreqCloseLoop(FRO0, &froAutotrimCfg, kCLOCK_FroAllOutEn); /* Use close loop mode. */
122 CLOCK_EnableFro0ClkForDomain(kCLOCK_AllDomainEnable); /* Enable FRO0 MAX clock for all domains. */
123
124 CLOCK_InitMainPll(&g_mainPllConfig_BOARD_BootClockRUN);
125 CLOCK_InitMainPfd(kCLOCK_Pfd0, 20U); /* 475MHz */
126 CLOCK_InitMainPfd(kCLOCK_Pfd1, 24U); /* 396MHz */
127 CLOCK_InitMainPfd(kCLOCK_Pfd2, 18U); /* 528MHz */
128 CLOCK_InitMainPfd(kCLOCK_Pfd3, 19U); /* Main PLL kCLOCK_Pfd3 (528 * 18 / 19) = 500MHz -need 2 div -> 250MHz*/
129
130 CLOCK_EnableMainPllPfdClkForDomain(kCLOCK_Pfd0, kCLOCK_AllDomainEnable);
131 CLOCK_EnableMainPllPfdClkForDomain(kCLOCK_Pfd1, kCLOCK_AllDomainEnable);
132 CLOCK_EnableMainPllPfdClkForDomain(kCLOCK_Pfd2, kCLOCK_AllDomainEnable);
133 CLOCK_EnableMainPllPfdClkForDomain(kCLOCK_Pfd3, kCLOCK_AllDomainEnable);
134
135 CLOCK_SetClkDiv(kCLOCK_DivCmptMainClk, 2U);
136 CLOCK_AttachClk(kMAIN_PLL_PFD0_to_COMPUTE_MAIN); /* Switch to PLL 230MHZ */
137
138 CLOCK_SetClkDiv(kCLOCK_DivMediaMainClk, 2U);
139 CLOCK_AttachClk(kMAIN_PLL_PFD0_to_MEDIA_MAIN); /* Switch to PLL 230MHZ */
140
141 CLOCK_SetClkDiv(kCLOCK_DivMediaVddnClk, 2U);
142 CLOCK_AttachClk(kMAIN_PLL_PFD0_to_MEDIA_VDDN); /* Switch to PLL 230MHZ */
143
144 CLOCK_SetClkDiv(kCLOCK_DivComputeRamClk, 2U);
145 CLOCK_AttachClk(kMAIN_PLL_PFD0_to_RAM); /* Switch to PLL 230MHZ */
146
147 CLOCK_SetClkDiv(kCLOCK_DivCommonVddnClk, 2U);
148 CLOCK_AttachClk(kMAIN_PLL_PFD3_to_COMMON_VDDN); /* Switch to 250MHZ */
149
150 /* Configure Audio PLL clock source. */
151 CLOCK_InitAudioPll(&g_audioPllConfig_BOARD_BootClockRUN); /* 532.48MHZ */
152 CLOCK_InitAudioPfd(kCLOCK_Pfd1, 24U); /* 399.36MHz */
153 CLOCK_InitAudioPfd(kCLOCK_Pfd3, 26U); /* Enable Audio PLL PFD3 clock to 368.64MHZ */
154 CLOCK_EnableAudioPllPfdClkForDomain(kCLOCK_Pfd1, kCLOCK_AllDomainEnable);
155 CLOCK_EnableAudioPllPfdClkForDomain(kCLOCK_Pfd3, kCLOCK_AllDomainEnable);
156
157 /* Call function BOARD_SetXspiClock() to set user configured clock source/divider for XSPI. */
158 BOARD_SetXspiClock(XSPI0, 3U, 1U); /* Main PLL PDF1 DIV1. */
159
160 SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
161 }
162
