1;/*
2; * Copyright (c) 2022 Arm Limited. All rights reserved.
3; *
4; * Licensed under the Apache License, Version 2.0 (the "License");
5; * you may not use this file except in compliance with the License.
6; * You may obtain a copy of the License at
7; *
8; *     http://www.apache.org/licenses/LICENSE-2.0
9; *
10; * Unless required by applicable law or agreed to in writing, software
11; * distributed under the License is distributed on an "AS IS" BASIS,
12; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13; * See the License for the specific language governing permissions and
14; * limitations under the License.
15; *
16; *
17; * This file is derivative of CMSIS V5.00 gcc_arm.ld
18; */
19
20/* Linker script to configure memory regions. */
21/* This file will be run trough the pre-processor. */
22
23#include "region_defs.h"
24
25MEMORY
26{
27    FLASH (rx)  : ORIGIN = BL2_CODE_START, LENGTH = BL2_CODE_SIZE
28    RAM   (rwx) : ORIGIN = BL2_DATA_START, LENGTH = BL2_DATA_SIZE
29}
30
31__heap_size__  = BL2_HEAP_SIZE;
32__msp_stack_size__ = BL2_MSP_STACK_SIZE;
33
34/* Library configurations */
35GROUP(libgcc.a libc.a libm.a libnosys.a)
36
37ENTRY(Reset_Handler)
38
39SECTIONS
40{
41    .text :
42    {
43        KEEP(*(.vectors))
44        __Vectors_End = .;
45        __Vectors_Size = __Vectors_End - __Vectors;
46        __end__ = .;
47
48        *(.text*)
49
50        KEEP(*(.init))
51        KEEP(*(.fini))
52
53
54        /* .ctors */
55        *crtbegin.o(.ctors)
56        *crtbegin?.o(.ctors)
57        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
58        *(SORT(.ctors.*))
59        *(.ctors)
60
61        /* .dtors */
62         *crtbegin.o(.dtors)
63         *crtbegin?.o(.dtors)
64         *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
65         *(SORT(.dtors.*))
66         *(.dtors)
67
68        *(.rodata*)
69
70        KEEP(*(.eh_frame*))
71    } > FLASH
72
73    .ARM.extab :
74    {
75        *(.ARM.extab* .gnu.linkonce.armextab.*)
76    } > FLASH
77
78    __exidx_start = .;
79    .ARM.exidx :
80    {
81        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
82    } > FLASH
83    __exidx_end = .;
84
85    .copy.table :
86    {
87        . = ALIGN(4);
88        __copy_table_start__ = .;
89#ifdef CODE_SHARING
90        LONG (LOADADDR(.tfm_shared_symbols))
91        LONG (ADDR(.tfm_shared_symbols))
92        LONG (SIZEOF(.tfm_shared_symbols) / 4)
93#endif
94        LONG (LOADADDR(.data))
95        LONG (ADDR(.data))
96        LONG (SIZEOF(.data) / 4)
97        __copy_table_end__ = .;
98    } > FLASH
99
100    .zero.table :
101    {
102        . = ALIGN(4);
103        __zero_table_start__ = .;
104        LONG (ADDR(.bss))
105        LONG (SIZEOF(.bss) / 4)
106        __zero_table_end__ = .;
107    } > FLASH
108
109#ifdef CODE_SHARING
110    /* The code sharing between bootloader and runtime firmware requires to
111     * share the global variables. Section size must be equal with
112     * SHARED_SYMBOL_AREA_SIZE defined in region_defs.h
113     */
114    .tfm_shared_symbols : ALIGN(4)
115    {
116        *(.data.mbedtls_calloc_func)
117        *(.data.mbedtls_free_func)
118        *(.data.mbedtls_exit)
119        *(.data.memset_func)
120        . = ALIGN(SHARED_SYMBOL_AREA_SIZE);
121    } > RAM AT > FLASH
122
123    ASSERT(SHARED_SYMBOL_AREA_SIZE % 4 == 0, "SHARED_SYMBOL_AREA_SIZE must be divisible by 4")
124#endif
125
126    .tfm_bl2_shared_data : ALIGN(32)
127    {
128        . += BOOT_TFM_SHARED_DATA_SIZE;
129    } > RAM
130    Image$$SHARED_DATA$$RW$$Base = ADDR(.tfm_bl2_shared_data);
131    Image$$SHARED_DATA$$RW$$Limit = ADDR(.tfm_bl2_shared_data) + SIZEOF(.tfm_bl2_shared_data);
132
133    .data : ALIGN(4)
134    {
135        *(vtable)
136        *(.data*)
137
138        . = ALIGN(4);
139        /* preinit data */
140        PROVIDE_HIDDEN (__preinit_array_start = .);
141        KEEP(*(.preinit_array))
142        PROVIDE_HIDDEN (__preinit_array_end = .);
143
144        . = ALIGN(4);
145        /* init data */
146        PROVIDE_HIDDEN (__init_array_start = .);
147        KEEP(*(SORT(.init_array.*)))
148        KEEP(*(.init_array))
149        PROVIDE_HIDDEN (__init_array_end = .);
150
151
152        . = ALIGN(4);
153        /* finit data */
154        PROVIDE_HIDDEN (__fini_array_start = .);
155        KEEP(*(SORT(.fini_array.*)))
156        KEEP(*(.fini_array))
157        PROVIDE_HIDDEN (__fini_array_end = .);
158
159        KEEP(*(.jcr*))
160        . = ALIGN(4);
161
162    } > RAM AT > FLASH
163    Image$$ER_DATA$$Base = ADDR(.data);
164
165    .bss : ALIGN(4)
166    {
167        . = ALIGN(4);
168        __bss_start__ = .;
169        *(.bss*)
170        *(COMMON)
171        . = ALIGN(4);
172        __bss_end__ = .;
173    } > RAM
174
175    .msp_stack (NOLOAD) : ALIGN(32)
176    {
177        . += __msp_stack_size__;
178    } > RAM
179    Image$$ARM_LIB_STACK$$ZI$$Base = ADDR(.msp_stack);
180    Image$$ARM_LIB_STACK$$ZI$$Limit = ADDR(.msp_stack) + SIZEOF(.msp_stack);
181
182    .heap (NOLOAD): ALIGN(8)
183    {
184        . = ALIGN(8);
185        __end__ = .;
186        PROVIDE(end = .);
187        __HeapBase = .;
188        . += __heap_size__;
189        __HeapLimit = .;
190        __heap_limit = .; /* Add for _sbrk */
191    } > RAM
192    Image$$ARM_LIB_HEAP$$ZI$$Limit = ADDR(.heap) + SIZEOF(.heap);
193
194    PROVIDE(__stack = Image$$ARM_LIB_STACK$$ZI$$Limit);
195}
196