1 /**
2 ******************************************************************************
3 * @file stm32l4xx_hal_spi.c
4 * @author MCD Application Team
5 * @brief SPI HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Serial Peripheral Interface (SPI) peripheral:
8 * + Initialization and de-initialization functions
9 * + IO operation functions
10 * + Peripheral Control functions
11 * + Peripheral State functions
12 *
13 @verbatim
14 ==============================================================================
15 ##### How to use this driver #####
16 ==============================================================================
17 [..]
18 The SPI HAL driver can be used as follows:
19
20 (#) Declare a SPI_HandleTypeDef handle structure, for example:
21 SPI_HandleTypeDef hspi;
22
23 (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
24 (##) Enable the SPIx interface clock
25 (##) SPI pins configuration
26 (+++) Enable the clock for the SPI GPIOs
27 (+++) Configure these SPI pins as alternate function push-pull
28 (##) NVIC configuration if you need to use interrupt process
29 (+++) Configure the SPIx interrupt priority
30 (+++) Enable the NVIC SPI IRQ handle
31 (##) DMA Configuration if you need to use DMA process
32 (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel
33 (+++) Enable the DMAx clock
34 (+++) Configure the DMA handle parameters
35 (+++) Configure the DMA Tx or Rx Stream/Channel
36 (+++) Associate the initialized hdma_tx(or _rx) handle to the hspi DMA Tx or Rx handle
37 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel
38
39 (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
40 management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
41
42 (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
43 (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
44 by calling the customized HAL_SPI_MspInit() API.
45 [..]
46 Circular mode restriction:
47 (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
48 (##) Master 2Lines RxOnly
49 (##) Master 1Line Rx
50 (#) The CRC feature is not managed when the DMA circular mode is enabled
51 (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
52 the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
53 [..]
54 Master Receive mode restriction:
55 (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=1) or
56 bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI
57 does not initiate a new transfer the following procedure has to be respected:
58 (##) HAL_SPI_DeInit()
59 (##) HAL_SPI_Init()
60 [..]
61 Callback registration:
62
63 (#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1U
64 allows the user to configure dynamically the driver callbacks.
65 Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback.
66
67 Function HAL_SPI_RegisterCallback() allows to register following callbacks:
68 (+) TxCpltCallback : SPI Tx Completed callback
69 (+) RxCpltCallback : SPI Rx Completed callback
70 (+) TxRxCpltCallback : SPI TxRx Completed callback
71 (+) TxHalfCpltCallback : SPI Tx Half Completed callback
72 (+) RxHalfCpltCallback : SPI Rx Half Completed callback
73 (+) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
74 (+) ErrorCallback : SPI Error callback
75 (+) AbortCpltCallback : SPI Abort callback
76 (+) MspInitCallback : SPI Msp Init callback
77 (+) MspDeInitCallback : SPI Msp DeInit callback
78 This function takes as parameters the HAL peripheral handle, the Callback ID
79 and a pointer to the user callback function.
80
81
82 (#) Use function HAL_SPI_UnRegisterCallback to reset a callback to the default
83 weak function.
84 HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle,
85 and the Callback ID.
86 This function allows to reset following callbacks:
87 (+) TxCpltCallback : SPI Tx Completed callback
88 (+) RxCpltCallback : SPI Rx Completed callback
89 (+) TxRxCpltCallback : SPI TxRx Completed callback
90 (+) TxHalfCpltCallback : SPI Tx Half Completed callback
91 (+) RxHalfCpltCallback : SPI Rx Half Completed callback
92 (+) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
93 (+) ErrorCallback : SPI Error callback
94 (+) AbortCpltCallback : SPI Abort callback
95 (+) MspInitCallback : SPI Msp Init callback
96 (+) MspDeInitCallback : SPI Msp DeInit callback
97
98 By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET
99 all callbacks are set to the corresponding weak functions:
100 examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback().
101 Exception done for MspInit and MspDeInit functions that are
102 reset to the legacy weak functions in the HAL_SPI_Init()/ HAL_SPI_DeInit() only when
103 these callbacks are null (not registered beforehand).
104 If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit()
105 keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
106
107 Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only.
108 Exception done MspInit/MspDeInit functions that can be registered/unregistered
109 in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state,
110 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
111 Then, the user first registers the MspInit/MspDeInit user callbacks
112 using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit()
113 or HAL_SPI_Init() function.
114
115 When The compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or
116 not defined, the callback registering feature is not available
117 and weak (surcharged) callbacks are used.
118
119 [..]
120 Using the HAL it is not possible to reach all supported SPI frequency with the differents SPI Modes,
121 the following table resume the max SPI frequency reached with data size 8bits/16bits,
122 according to frequency of the APBx Peripheral Clock (fPCLK) used by the SPI instance.
123
124 @endverbatim
125
126 Additional table :
127
128 DataSize = SPI_DATASIZE_8BIT:
129 +----------------------------------------------------------------------------------------------+
130 | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
131 | Process | Tranfert mode |---------------------|----------------------|----------------------|
132 | | | Master | Slave | Master | Slave | Master | Slave |
133 |==============================================================================================|
134 | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA |
135 | X |----------------|----------|----------|-----------|----------|-----------|----------|
136 | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA |
137 | R |----------------|----------|----------|-----------|----------|-----------|----------|
138 | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
139 |=========|================|==========|==========|===========|==========|===========|==========|
140 | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 |
141 | |----------------|----------|----------|-----------|----------|-----------|----------|
142 | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 |
143 | X |----------------|----------|----------|-----------|----------|-----------|----------|
144 | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 |
145 |=========|================|==========|==========|===========|==========|===========|==========|
146 | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 |
147 | |----------------|----------|----------|-----------|----------|-----------|----------|
148 | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 |
149 | X |----------------|----------|----------|-----------|----------|-----------|----------|
150 | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 |
151 +----------------------------------------------------------------------------------------------+
152
153 DataSize = SPI_DATASIZE_16BIT:
154 +----------------------------------------------------------------------------------------------+
155 | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
156 | Process | Tranfert mode |---------------------|----------------------|----------------------|
157 | | | Master | Slave | Master | Slave | Master | Slave |
158 |==============================================================================================|
159 | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA |
160 | X |----------------|----------|----------|-----------|----------|-----------|----------|
161 | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA |
162 | R |----------------|----------|----------|-----------|----------|-----------|----------|
163 | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
164 |=========|================|==========|==========|===========|==========|===========|==========|
165 | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 |
166 | |----------------|----------|----------|-----------|----------|-----------|----------|
167 | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 |
168 | X |----------------|----------|----------|-----------|----------|-----------|----------|
169 | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 |
170 |=========|================|==========|==========|===========|==========|===========|==========|
171 | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 |
172 | |----------------|----------|----------|-----------|----------|-----------|----------|
173 | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 |
174 | X |----------------|----------|----------|-----------|----------|-----------|----------|
175 | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 |
176 +----------------------------------------------------------------------------------------------+
177 @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits),
178 SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
179 @note
180 (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
181 (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
182 (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
183
184 ******************************************************************************
185 * @attention
186 *
187 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
188 *
189 * Redistribution and use in source and binary forms, with or without modification,
190 * are permitted provided that the following conditions are met:
191 * 1. Redistributions of source code must retain the above copyright notice,
192 * this list of conditions and the following disclaimer.
193 * 2. Redistributions in binary form must reproduce the above copyright notice,
194 * this list of conditions and the following disclaimer in the documentation
195 * and/or other materials provided with the distribution.
196 * 3. Neither the name of STMicroelectronics nor the names of its contributors
197 * may be used to endorse or promote products derived from this software
198 * without specific prior written permission.
199 *
200 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
201 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
202 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
203 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
204 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
205 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
206 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
207 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
208 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
209 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
210 *
211 ******************************************************************************
212 */
213
214 /* Includes ------------------------------------------------------------------*/
215 #include "stm32l4xx_hal.h"
216
217 /** @addtogroup STM32L4xx_HAL_Driver
218 * @{
219 */
220
221 /** @defgroup SPI SPI
222 * @brief SPI HAL module driver
223 * @{
224 */
225 #ifdef HAL_SPI_MODULE_ENABLED
226
227 /* Private typedef -----------------------------------------------------------*/
228 /* Private defines -----------------------------------------------------------*/
229 /** @defgroup SPI_Private_Constants SPI Private Constants
230 * @{
231 */
232 #define SPI_DEFAULT_TIMEOUT 100U
233 /**
234 * @}
235 */
236
237 /* Private macros ------------------------------------------------------------*/
238 /* Private variables ---------------------------------------------------------*/
239 /* Private function prototypes -----------------------------------------------*/
240 /** @defgroup SPI_Private_Functions SPI Private Functions
241 * @{
242 */
243 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
244 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
245 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
246 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
247 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
248 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
249 static void SPI_DMAError(DMA_HandleTypeDef *hdma);
250 static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
251 static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
252 static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
253 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
254 uint32_t Timeout, uint32_t Tickstart);
255 static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
256 uint32_t Timeout, uint32_t Tickstart);
257 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
258 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
259 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
260 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
261 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
262 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
263 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
264 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
265 #if (USE_SPI_CRC != 0U)
266 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
267 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
268 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
269 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
270 #endif /* USE_SPI_CRC */
271 static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi);
272 static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi);
273 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
274 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
275 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
276 static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
277 static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
278 /**
279 * @}
280 */
281
282 /* Exported functions --------------------------------------------------------*/
283 /** @defgroup SPI_Exported_Functions SPI Exported Functions
284 * @{
285 */
286
287 /** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
288 * @brief Initialization and Configuration functions
289 *
290 @verbatim
291 ===============================================================================
292 ##### Initialization and de-initialization functions #####
293 ===============================================================================
294 [..] This subsection provides a set of functions allowing to initialize and
295 de-initialize the SPIx peripheral:
296
297 (+) User must implement HAL_SPI_MspInit() function in which he configures
298 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
299
300 (+) Call the function HAL_SPI_Init() to configure the selected device with
301 the selected configuration:
302 (++) Mode
303 (++) Direction
304 (++) Data Size
305 (++) Clock Polarity and Phase
306 (++) NSS Management
307 (++) BaudRate Prescaler
308 (++) FirstBit
309 (++) TIMode
310 (++) CRC Calculation
311 (++) CRC Polynomial if CRC enabled
312 (++) CRC Length, used only with Data8 and Data16
313 (++) FIFO reception threshold
314
315 (+) Call the function HAL_SPI_DeInit() to restore the default configuration
316 of the selected SPIx peripheral.
317
318 @endverbatim
319 * @{
320 */
321
322 /**
323 * @brief Initialize the SPI according to the specified parameters
324 * in the SPI_InitTypeDef and initialize the associated handle.
325 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
326 * the configuration information for SPI module.
327 * @retval HAL status
328 */
HAL_SPI_Init(SPI_HandleTypeDef * hspi)329 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
330 {
331 uint32_t frxth;
332
333 /* Check the SPI handle allocation */
334 if (hspi == NULL)
335 {
336 return HAL_ERROR;
337 }
338
339 /* Check the parameters */
340 assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
341 assert_param(IS_SPI_MODE(hspi->Init.Mode));
342 assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
343 assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
344 assert_param(IS_SPI_NSS(hspi->Init.NSS));
345 assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
346 assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
347 assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
348 assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
349 if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
350 {
351 assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
352 assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
353 }
354 #if (USE_SPI_CRC != 0U)
355 assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
356 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
357 {
358 assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
359 assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
360 }
361 #else
362 hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
363 #endif /* USE_SPI_CRC */
364
365 if (hspi->State == HAL_SPI_STATE_RESET)
366 {
367 /* Allocate lock resource and initialize it */
368 hspi->Lock = HAL_UNLOCKED;
369
370 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
371 /* Init the SPI Callback settings */
372 hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */
373 hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */
374 hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
375 hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
376 hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
377 hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
378 hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */
379 hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
380
381 if (hspi->MspInitCallback == NULL)
382 {
383 hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
384 }
385
386 /* Init the low level hardware : GPIO, CLOCK, NVIC... */
387 hspi->MspInitCallback(hspi);
388 #else
389 /* Init the low level hardware : GPIO, CLOCK, NVIC... */
390 HAL_SPI_MspInit(hspi);
391 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
392 }
393
394 hspi->State = HAL_SPI_STATE_BUSY;
395
396 /* Disable the selected SPI peripheral */
397 __HAL_SPI_DISABLE(hspi);
398
399 /* Align by default the rs fifo threshold on the data size */
400 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
401 {
402 frxth = SPI_RXFIFO_THRESHOLD_HF;
403 }
404 else
405 {
406 frxth = SPI_RXFIFO_THRESHOLD_QF;
407 }
408
409 /* CRC calculation is valid only for 16Bit and 8 Bit */
410 if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT))
411 {
412 /* CRC must be disabled */
413 hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
414 }
415
416 /* Align the CRC Length on the data size */
417 if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
418 {
419 /* CRC Length aligned on the data size : value set by default */
420 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
421 {
422 hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;
423 }
424 else
425 {
426 hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;
427 }
428 }
429
430 /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
431 /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
432 Communication speed, First bit and CRC calculation state */
433 WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction |
434 hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
435 hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation));
436 #if (USE_SPI_CRC != 0U)
437 /* Configure : CRC Length */
438 if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
439 {
440 hspi->Instance->CR1 |= SPI_CR1_CRCL;
441 }
442 #endif /* USE_SPI_CRC */
443
444 /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */
445 WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode |
446 hspi->Init.NSSPMode | hspi->Init.DataSize) | frxth);
447
448 #if (USE_SPI_CRC != 0U)
449 /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
450 /* Configure : CRC Polynomial */
451 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
452 {
453 WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);
454 }
455 #endif /* USE_SPI_CRC */
456
457 #if defined(SPI_I2SCFGR_I2SMOD)
458 /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
459 CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
460 #endif /* SPI_I2SCFGR_I2SMOD */
461
462 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
463 hspi->State = HAL_SPI_STATE_READY;
464
465 return HAL_OK;
466 }
467
468 /**
469 * @brief De-Initialize the SPI peripheral.
470 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
471 * the configuration information for SPI module.
472 * @retval HAL status
473 */
HAL_SPI_DeInit(SPI_HandleTypeDef * hspi)474 HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
475 {
476 /* Check the SPI handle allocation */
477 if (hspi == NULL)
478 {
479 return HAL_ERROR;
480 }
481
482 /* Check SPI Instance parameter */
483 assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
484
485 hspi->State = HAL_SPI_STATE_BUSY;
486
487 /* Disable the SPI Peripheral Clock */
488 __HAL_SPI_DISABLE(hspi);
489
490 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
491 if (hspi->MspDeInitCallback == NULL)
492 {
493 hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
494 }
495
496 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
497 hspi->MspDeInitCallback(hspi);
498 #else
499 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
500 HAL_SPI_MspDeInit(hspi);
501 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
502
503 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
504 hspi->State = HAL_SPI_STATE_RESET;
505
506 /* Release Lock */
507 __HAL_UNLOCK(hspi);
508
509 return HAL_OK;
510 }
511
512 /**
513 * @brief Initialize the SPI MSP.
514 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
515 * the configuration information for SPI module.
516 * @retval None
517 */
HAL_SPI_MspInit(SPI_HandleTypeDef * hspi)518 __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
519 {
520 /* Prevent unused argument(s) compilation warning */
521 UNUSED(hspi);
522
523 /* NOTE : This function should not be modified, when the callback is needed,
524 the HAL_SPI_MspInit should be implemented in the user file
525 */
526 }
527
528 /**
529 * @brief De-Initialize the SPI MSP.
530 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
531 * the configuration information for SPI module.
532 * @retval None
533 */
HAL_SPI_MspDeInit(SPI_HandleTypeDef * hspi)534 __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
535 {
536 /* Prevent unused argument(s) compilation warning */
537 UNUSED(hspi);
538
539 /* NOTE : This function should not be modified, when the callback is needed,
540 the HAL_SPI_MspDeInit should be implemented in the user file
541 */
542 }
543
544 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
545 /**
546 * @brief Register a User SPI Callback
547 * To be used instead of the weak predefined callback
548 * @param hspi Pointer to a SPI_HandleTypeDef structure that contains
549 * the configuration information for the specified SPI.
550 * @param CallbackID ID of the callback to be registered
551 * @param pCallback pointer to the Callback function
552 * @retval HAL status
553 */
HAL_SPI_RegisterCallback(SPI_HandleTypeDef * hspi,HAL_SPI_CallbackIDTypeDef CallbackID,pSPI_CallbackTypeDef pCallback)554 HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback)
555 {
556 HAL_StatusTypeDef status = HAL_OK;
557
558 if (pCallback == NULL)
559 {
560 /* Update the error code */
561 hspi->ErrorCode |= HAL_SPI_ERROR_INVALID_CALLBACK;
562
563 return HAL_ERROR;
564 }
565 /* Process locked */
566 __HAL_LOCK(hspi);
567
568 if (HAL_SPI_STATE_READY == hspi->State)
569 {
570 switch (CallbackID)
571 {
572 case HAL_SPI_TX_COMPLETE_CB_ID :
573 hspi->TxCpltCallback = pCallback;
574 break;
575
576 case HAL_SPI_RX_COMPLETE_CB_ID :
577 hspi->RxCpltCallback = pCallback;
578 break;
579
580 case HAL_SPI_TX_RX_COMPLETE_CB_ID :
581 hspi->TxRxCpltCallback = pCallback;
582 break;
583
584 case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
585 hspi->TxHalfCpltCallback = pCallback;
586 break;
587
588 case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
589 hspi->RxHalfCpltCallback = pCallback;
590 break;
591
592 case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
593 hspi->TxRxHalfCpltCallback = pCallback;
594 break;
595
596 case HAL_SPI_ERROR_CB_ID :
597 hspi->ErrorCallback = pCallback;
598 break;
599
600 case HAL_SPI_ABORT_CB_ID :
601 hspi->AbortCpltCallback = pCallback;
602 break;
603
604 case HAL_SPI_MSPINIT_CB_ID :
605 hspi->MspInitCallback = pCallback;
606 break;
607
608 case HAL_SPI_MSPDEINIT_CB_ID :
609 hspi->MspDeInitCallback = pCallback;
610 break;
611
612 default :
613 /* Update the error code */
614 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
615
616 /* Return error status */
617 status = HAL_ERROR;
618 break;
619 }
620 }
621 else if (HAL_SPI_STATE_RESET == hspi->State)
622 {
623 switch (CallbackID)
624 {
625 case HAL_SPI_MSPINIT_CB_ID :
626 hspi->MspInitCallback = pCallback;
627 break;
628
629 case HAL_SPI_MSPDEINIT_CB_ID :
630 hspi->MspDeInitCallback = pCallback;
631 break;
632
633 default :
634 /* Update the error code */
635 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
636
637 /* Return error status */
638 status = HAL_ERROR;
639 break;
640 }
641 }
642 else
643 {
644 /* Update the error code */
645 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
646
647 /* Return error status */
648 status = HAL_ERROR;
649 }
650
651 /* Release Lock */
652 __HAL_UNLOCK(hspi);
653 return status;
654 }
655
656 /**
657 * @brief Unregister an SPI Callback
658 * SPI callback is redirected to the weak predefined callback
659 * @param hspi Pointer to a SPI_HandleTypeDef structure that contains
660 * the configuration information for the specified SPI.
661 * @param CallbackID ID of the callback to be unregistered
662 * @retval HAL status
663 */
HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef * hspi,HAL_SPI_CallbackIDTypeDef CallbackID)664 HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID)
665 {
666 HAL_StatusTypeDef status = HAL_OK;
667
668 /* Process locked */
669 __HAL_LOCK(hspi);
670
671 if (HAL_SPI_STATE_READY == hspi->State)
672 {
673 switch (CallbackID)
674 {
675 case HAL_SPI_TX_COMPLETE_CB_ID :
676 hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */
677 break;
678
679 case HAL_SPI_RX_COMPLETE_CB_ID :
680 hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */
681 break;
682
683 case HAL_SPI_TX_RX_COMPLETE_CB_ID :
684 hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
685 break;
686
687 case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
688 hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
689 break;
690
691 case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
692 hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
693 break;
694
695 case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
696 hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
697 break;
698
699 case HAL_SPI_ERROR_CB_ID :
700 hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */
701 break;
702
703 case HAL_SPI_ABORT_CB_ID :
704 hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
705 break;
706
707 case HAL_SPI_MSPINIT_CB_ID :
708 hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
709 break;
710
711 case HAL_SPI_MSPDEINIT_CB_ID :
712 hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
713 break;
714
715 default :
716 /* Update the error code */
717 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
718
719 /* Return error status */
720 status = HAL_ERROR;
721 break;
722 }
723 }
724 else if (HAL_SPI_STATE_RESET == hspi->State)
725 {
726 switch (CallbackID)
727 {
728 case HAL_SPI_MSPINIT_CB_ID :
729 hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
730 break;
731
732 case HAL_SPI_MSPDEINIT_CB_ID :
733 hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
734 break;
735
736 default :
737 /* Update the error code */
738 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
739
740 /* Return error status */
741 status = HAL_ERROR;
742 break;
743 }
744 }
745 else
746 {
747 /* Update the error code */
748 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
749
750 /* Return error status */
751 status = HAL_ERROR;
752 }
753
754 /* Release Lock */
755 __HAL_UNLOCK(hspi);
756 return status;
757 }
758 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
759 /**
760 * @}
761 */
762
763 /** @defgroup SPI_Exported_Functions_Group2 IO operation functions
764 * @brief Data transfers functions
765 *
766 @verbatim
767 ==============================================================================
768 ##### IO operation functions #####
769 ===============================================================================
770 [..]
771 This subsection provides a set of functions allowing to manage the SPI
772 data transfers.
773
774 [..] The SPI supports master and slave mode :
775
776 (#) There are two modes of transfer:
777 (++) Blocking mode: The communication is performed in polling mode.
778 The HAL status of all data processing is returned by the same function
779 after finishing transfer.
780 (++) No-Blocking mode: The communication is performed using Interrupts
781 or DMA, These APIs return the HAL status.
782 The end of the data processing will be indicated through the
783 dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
784 using DMA mode.
785 The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
786 will be executed respectively at the end of the transmit or Receive process
787 The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
788
789 (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
790 exist for 1Line (simplex) and 2Lines (full duplex) modes.
791
792 @endverbatim
793 * @{
794 */
795
796 /**
797 * @brief Transmit an amount of data in blocking mode.
798 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
799 * the configuration information for SPI module.
800 * @param pData pointer to data buffer
801 * @param Size amount of data to be sent
802 * @param Timeout Timeout duration
803 * @retval HAL status
804 */
HAL_SPI_Transmit(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size,uint32_t Timeout)805 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
806 {
807 uint32_t tickstart;
808 HAL_StatusTypeDef errorcode = HAL_OK;
809 uint16_t initial_TxXferCount;
810
811 /* Check Direction parameter */
812 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
813
814 /* Process Locked */
815 __HAL_LOCK(hspi);
816
817 /* Init tickstart for timeout management*/
818 tickstart = HAL_GetTick();
819 initial_TxXferCount = Size;
820
821 if (hspi->State != HAL_SPI_STATE_READY)
822 {
823 errorcode = HAL_BUSY;
824 goto error;
825 }
826
827 if ((pData == NULL) || (Size == 0U))
828 {
829 errorcode = HAL_ERROR;
830 goto error;
831 }
832
833 /* Set the transaction information */
834 hspi->State = HAL_SPI_STATE_BUSY_TX;
835 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
836 hspi->pTxBuffPtr = (uint8_t *)pData;
837 hspi->TxXferSize = Size;
838 hspi->TxXferCount = Size;
839
840 /*Init field not used in handle to zero */
841 hspi->pRxBuffPtr = (uint8_t *)NULL;
842 hspi->RxXferSize = 0U;
843 hspi->RxXferCount = 0U;
844 hspi->TxISR = NULL;
845 hspi->RxISR = NULL;
846
847 /* Configure communication direction : 1Line */
848 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
849 {
850 SPI_1LINE_TX(hspi);
851 }
852
853 #if (USE_SPI_CRC != 0U)
854 /* Reset CRC Calculation */
855 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
856 {
857 SPI_RESET_CRC(hspi);
858 }
859 #endif /* USE_SPI_CRC */
860
861 /* Check if the SPI is already enabled */
862 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
863 {
864 /* Enable SPI peripheral */
865 __HAL_SPI_ENABLE(hspi);
866 }
867
868 /* Transmit data in 16 Bit mode */
869 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
870 {
871 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
872 {
873 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
874 hspi->pTxBuffPtr += sizeof(uint16_t);
875 hspi->TxXferCount--;
876 }
877 /* Transmit data in 16 Bit mode */
878 while (hspi->TxXferCount > 0U)
879 {
880 /* Wait until TXE flag is set to send data */
881 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
882 {
883 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
884 hspi->pTxBuffPtr += sizeof(uint16_t);
885 hspi->TxXferCount--;
886 }
887 else
888 {
889 /* Timeout management */
890 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
891 {
892 errorcode = HAL_TIMEOUT;
893 goto error;
894 }
895 }
896 }
897 }
898 /* Transmit data in 8 Bit mode */
899 else
900 {
901 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
902 {
903 if (hspi->TxXferCount > 1U)
904 {
905 /* write on the data register in packing mode */
906 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
907 hspi->pTxBuffPtr += sizeof(uint16_t);
908 hspi->TxXferCount -= 2U;
909 }
910 else
911 {
912 *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
913 hspi->pTxBuffPtr ++;
914 hspi->TxXferCount--;
915 }
916 }
917 while (hspi->TxXferCount > 0U)
918 {
919 /* Wait until TXE flag is set to send data */
920 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
921 {
922 if (hspi->TxXferCount > 1U)
923 {
924 /* write on the data register in packing mode */
925 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
926 hspi->pTxBuffPtr += sizeof(uint16_t);
927 hspi->TxXferCount -= 2U;
928 }
929 else
930 {
931 *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
932 hspi->pTxBuffPtr++;
933 hspi->TxXferCount--;
934 }
935 }
936 else
937 {
938 /* Timeout management */
939 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
940 {
941 errorcode = HAL_TIMEOUT;
942 goto error;
943 }
944 }
945 }
946 }
947 #if (USE_SPI_CRC != 0U)
948 /* Enable CRC Transmission */
949 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
950 {
951 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
952 }
953 #endif /* USE_SPI_CRC */
954
955 /* Check the end of the transaction */
956 if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
957 {
958 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
959 }
960
961 /* Clear overrun flag in 2 Lines communication mode because received is not read */
962 if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
963 {
964 __HAL_SPI_CLEAR_OVRFLAG(hspi);
965 }
966
967 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
968 {
969 errorcode = HAL_ERROR;
970 }
971
972 error:
973 hspi->State = HAL_SPI_STATE_READY;
974 /* Process Unlocked */
975 __HAL_UNLOCK(hspi);
976 return errorcode;
977 }
978
979 /**
980 * @brief Receive an amount of data in blocking mode.
981 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
982 * the configuration information for SPI module.
983 * @param pData pointer to data buffer
984 * @param Size amount of data to be received
985 * @param Timeout Timeout duration
986 * @retval HAL status
987 */
HAL_SPI_Receive(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size,uint32_t Timeout)988 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
989 {
990 uint32_t tickstart;
991 HAL_StatusTypeDef errorcode = HAL_OK;
992
993 if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
994 {
995 hspi->State = HAL_SPI_STATE_BUSY_RX;
996 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
997 return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
998 }
999
1000 /* Process Locked */
1001 __HAL_LOCK(hspi);
1002
1003 /* Init tickstart for timeout management*/
1004 tickstart = HAL_GetTick();
1005
1006 if (hspi->State != HAL_SPI_STATE_READY)
1007 {
1008 errorcode = HAL_BUSY;
1009 goto error;
1010 }
1011
1012 if ((pData == NULL) || (Size == 0U))
1013 {
1014 errorcode = HAL_ERROR;
1015 goto error;
1016 }
1017
1018 /* Set the transaction information */
1019 hspi->State = HAL_SPI_STATE_BUSY_RX;
1020 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1021 hspi->pRxBuffPtr = (uint8_t *)pData;
1022 hspi->RxXferSize = Size;
1023 hspi->RxXferCount = Size;
1024
1025 /*Init field not used in handle to zero */
1026 hspi->pTxBuffPtr = (uint8_t *)NULL;
1027 hspi->TxXferSize = 0U;
1028 hspi->TxXferCount = 0U;
1029 hspi->RxISR = NULL;
1030 hspi->TxISR = NULL;
1031
1032 #if (USE_SPI_CRC != 0U)
1033 /* Reset CRC Calculation */
1034 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1035 {
1036 SPI_RESET_CRC(hspi);
1037 /* this is done to handle the CRCNEXT before the latest data */
1038 hspi->RxXferCount--;
1039 }
1040 #endif /* USE_SPI_CRC */
1041
1042 /* Set the Rx Fifo threshold */
1043 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1044 {
1045 /* Set RX Fifo threshold according the reception data length: 16bit */
1046 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1047 }
1048 else
1049 {
1050 /* Set RX Fifo threshold according the reception data length: 8bit */
1051 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1052 }
1053
1054 /* Configure communication direction: 1Line */
1055 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1056 {
1057 SPI_1LINE_RX(hspi);
1058 }
1059
1060 /* Check if the SPI is already enabled */
1061 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1062 {
1063 /* Enable SPI peripheral */
1064 __HAL_SPI_ENABLE(hspi);
1065 }
1066
1067 /* Receive data in 8 Bit mode */
1068 if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
1069 {
1070 /* Transfer loop */
1071 while (hspi->RxXferCount > 0U)
1072 {
1073 /* Check the RXNE flag */
1074 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
1075 {
1076 /* read the received data */
1077 (* (uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
1078 hspi->pRxBuffPtr += sizeof(uint8_t);
1079 hspi->RxXferCount--;
1080 }
1081 else
1082 {
1083 /* Timeout management */
1084 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
1085 {
1086 errorcode = HAL_TIMEOUT;
1087 goto error;
1088 }
1089 }
1090 }
1091 }
1092 else
1093 {
1094 /* Transfer loop */
1095 while (hspi->RxXferCount > 0U)
1096 {
1097 /* Check the RXNE flag */
1098 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
1099 {
1100 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
1101 hspi->pRxBuffPtr += sizeof(uint16_t);
1102 hspi->RxXferCount--;
1103 }
1104 else
1105 {
1106 /* Timeout management */
1107 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
1108 {
1109 errorcode = HAL_TIMEOUT;
1110 goto error;
1111 }
1112 }
1113 }
1114 }
1115
1116 #if (USE_SPI_CRC != 0U)
1117 /* Handle the CRC Transmission */
1118 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1119 {
1120 /* freeze the CRC before the latest data */
1121 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
1122
1123 /* Read the latest data */
1124 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1125 {
1126 /* the latest data has not been received */
1127 errorcode = HAL_TIMEOUT;
1128 goto error;
1129 }
1130
1131 /* Receive last data in 16 Bit mode */
1132 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1133 {
1134 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
1135 }
1136 /* Receive last data in 8 Bit mode */
1137 else
1138 {
1139 (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
1140 }
1141
1142 /* Wait the CRC data */
1143 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1144 {
1145 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1146 errorcode = HAL_TIMEOUT;
1147 goto error;
1148 }
1149
1150 /* Read CRC to Flush DR and RXNE flag */
1151 if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
1152 {
1153 /* Read 16bit CRC */
1154 READ_REG(hspi->Instance->DR);
1155 }
1156 else
1157 {
1158 /* Read 8bit CRC */
1159 READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
1160
1161 if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
1162 {
1163 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1164 {
1165 /* Error on the CRC reception */
1166 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1167 errorcode = HAL_TIMEOUT;
1168 goto error;
1169 }
1170 /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
1171 READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
1172 }
1173 }
1174 }
1175 #endif /* USE_SPI_CRC */
1176
1177 /* Check the end of the transaction */
1178 if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK)
1179 {
1180 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
1181 }
1182
1183 #if (USE_SPI_CRC != 0U)
1184 /* Check if CRC error occurred */
1185 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
1186 {
1187 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1188 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
1189 }
1190 #endif /* USE_SPI_CRC */
1191
1192 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
1193 {
1194 errorcode = HAL_ERROR;
1195 }
1196
1197 error :
1198 hspi->State = HAL_SPI_STATE_READY;
1199 __HAL_UNLOCK(hspi);
1200 return errorcode;
1201 }
1202
1203 /**
1204 * @brief Transmit and Receive an amount of data in blocking mode.
1205 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1206 * the configuration information for SPI module.
1207 * @param pTxData pointer to transmission data buffer
1208 * @param pRxData pointer to reception data buffer
1209 * @param Size amount of data to be sent and received
1210 * @param Timeout Timeout duration
1211 * @retval HAL status
1212 */
HAL_SPI_TransmitReceive(SPI_HandleTypeDef * hspi,uint8_t * pTxData,uint8_t * pRxData,uint16_t Size,uint32_t Timeout)1213 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
1214 uint32_t Timeout)
1215 {
1216 uint16_t initial_TxXferCount;
1217 uint16_t initial_RxXferCount;
1218 uint32_t tmp_mode;
1219 HAL_SPI_StateTypeDef tmp_state;
1220 uint32_t tickstart;
1221 #if (USE_SPI_CRC != 0U)
1222 uint32_t spi_cr1;
1223 uint32_t spi_cr2;
1224 #endif /* USE_SPI_CRC */
1225
1226 /* Variable used to alternate Rx and Tx during transfer */
1227 uint32_t txallowed = 1U;
1228 HAL_StatusTypeDef errorcode = HAL_OK;
1229
1230 /* Check Direction parameter */
1231 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
1232
1233 /* Process Locked */
1234 __HAL_LOCK(hspi);
1235
1236 /* Init tickstart for timeout management*/
1237 tickstart = HAL_GetTick();
1238
1239 /* Init temporary variables */
1240 tmp_state = hspi->State;
1241 tmp_mode = hspi->Init.Mode;
1242 initial_TxXferCount = Size;
1243 initial_RxXferCount = Size;
1244 #if (USE_SPI_CRC != 0U)
1245 spi_cr1 = READ_REG(hspi->Instance->CR1);
1246 spi_cr2 = READ_REG(hspi->Instance->CR2);
1247 #endif /* USE_SPI_CRC */
1248
1249 if (!((tmp_state == HAL_SPI_STATE_READY) || \
1250 ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
1251 {
1252 errorcode = HAL_BUSY;
1253 goto error;
1254 }
1255
1256 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
1257 {
1258 errorcode = HAL_ERROR;
1259 goto error;
1260 }
1261
1262 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
1263 if (hspi->State != HAL_SPI_STATE_BUSY_RX)
1264 {
1265 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
1266 }
1267
1268 /* Set the transaction information */
1269 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1270 hspi->pRxBuffPtr = (uint8_t *)pRxData;
1271 hspi->RxXferCount = Size;
1272 hspi->RxXferSize = Size;
1273 hspi->pTxBuffPtr = (uint8_t *)pTxData;
1274 hspi->TxXferCount = Size;
1275 hspi->TxXferSize = Size;
1276
1277 /*Init field not used in handle to zero */
1278 hspi->RxISR = NULL;
1279 hspi->TxISR = NULL;
1280
1281 #if (USE_SPI_CRC != 0U)
1282 /* Reset CRC Calculation */
1283 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1284 {
1285 SPI_RESET_CRC(hspi);
1286 }
1287 #endif /* USE_SPI_CRC */
1288
1289 /* Set the Rx Fifo threshold */
1290 if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (initial_RxXferCount > 1U))
1291 {
1292 /* Set fiforxthreshold according the reception data length: 16bit */
1293 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1294 }
1295 else
1296 {
1297 /* Set fiforxthreshold according the reception data length: 8bit */
1298 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1299 }
1300
1301 /* Check if the SPI is already enabled */
1302 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1303 {
1304 /* Enable SPI peripheral */
1305 __HAL_SPI_ENABLE(hspi);
1306 }
1307
1308 /* Transmit and Receive data in 16 Bit mode */
1309 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1310 {
1311 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
1312 {
1313 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
1314 hspi->pTxBuffPtr += sizeof(uint16_t);
1315 hspi->TxXferCount--;
1316 }
1317 while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
1318 {
1319 /* Check TXE flag */
1320 if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
1321 {
1322 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
1323 hspi->pTxBuffPtr += sizeof(uint16_t);
1324 hspi->TxXferCount--;
1325 /* Next Data is a reception (Rx). Tx not allowed */
1326 txallowed = 0U;
1327
1328 #if (USE_SPI_CRC != 0U)
1329 /* Enable CRC Transmission */
1330 if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
1331 {
1332 /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
1333 if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP))
1334 {
1335 SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
1336 }
1337 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
1338 }
1339 #endif /* USE_SPI_CRC */
1340 }
1341
1342 /* Check RXNE flag */
1343 if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
1344 {
1345 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
1346 hspi->pRxBuffPtr += sizeof(uint16_t);
1347 hspi->RxXferCount--;
1348 /* Next Data is a Transmission (Tx). Tx is allowed */
1349 txallowed = 1U;
1350 }
1351 if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY))
1352 {
1353 errorcode = HAL_TIMEOUT;
1354 goto error;
1355 }
1356 }
1357 }
1358 /* Transmit and Receive data in 8 Bit mode */
1359 else
1360 {
1361 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
1362 {
1363 if (hspi->TxXferCount > 1U)
1364 {
1365 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
1366 hspi->pTxBuffPtr += sizeof(uint16_t);
1367 hspi->TxXferCount -= 2U;
1368 }
1369 else
1370 {
1371 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
1372 hspi->pTxBuffPtr++;
1373 hspi->TxXferCount--;
1374 }
1375 }
1376 while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
1377 {
1378 /* Check TXE flag */
1379 if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
1380 {
1381 if (hspi->TxXferCount > 1U)
1382 {
1383 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
1384 hspi->pTxBuffPtr += sizeof(uint16_t);
1385 hspi->TxXferCount -= 2U;
1386 }
1387 else
1388 {
1389 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
1390 hspi->pTxBuffPtr++;
1391 hspi->TxXferCount--;
1392 }
1393 /* Next Data is a reception (Rx). Tx not allowed */
1394 txallowed = 0U;
1395
1396 #if (USE_SPI_CRC != 0U)
1397 /* Enable CRC Transmission */
1398 if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
1399 {
1400 /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
1401 if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP))
1402 {
1403 SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
1404 }
1405 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
1406 }
1407 #endif /* USE_SPI_CRC */
1408 }
1409
1410 /* Wait until RXNE flag is reset */
1411 if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
1412 {
1413 if (hspi->RxXferCount > 1U)
1414 {
1415 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
1416 hspi->pRxBuffPtr += sizeof(uint16_t);
1417 hspi->RxXferCount -= 2U;
1418 if (hspi->RxXferCount <= 1U)
1419 {
1420 /* Set RX Fifo threshold before to switch on 8 bit data size */
1421 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1422 }
1423 }
1424 else
1425 {
1426 (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
1427 hspi->pRxBuffPtr++;
1428 hspi->RxXferCount--;
1429 }
1430 /* Next Data is a Transmission (Tx). Tx is allowed */
1431 txallowed = 1U;
1432 }
1433 if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U))
1434 {
1435 errorcode = HAL_TIMEOUT;
1436 goto error;
1437 }
1438 }
1439 }
1440
1441 #if (USE_SPI_CRC != 0U)
1442 /* Read CRC from DR to close CRC calculation process */
1443 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1444 {
1445 /* Wait until TXE flag */
1446 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1447 {
1448 /* Error on the CRC reception */
1449 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1450 errorcode = HAL_TIMEOUT;
1451 goto error;
1452 }
1453 /* Read CRC */
1454 if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
1455 {
1456 /* Read 16bit CRC */
1457 READ_REG(hspi->Instance->DR);
1458 }
1459 else
1460 {
1461 /* Read 8bit CRC */
1462 READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
1463
1464 if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
1465 {
1466 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1467 {
1468 /* Error on the CRC reception */
1469 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1470 errorcode = HAL_TIMEOUT;
1471 goto error;
1472 }
1473 /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
1474 READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
1475 }
1476 }
1477 }
1478
1479 /* Check if CRC error occurred */
1480 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
1481 {
1482 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1483 /* Clear CRC Flag */
1484 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
1485
1486 errorcode = HAL_ERROR;
1487 }
1488 #endif /* USE_SPI_CRC */
1489
1490 /* Check the end of the transaction */
1491 if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
1492 {
1493 errorcode = HAL_ERROR;
1494 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
1495 }
1496
1497 error :
1498 hspi->State = HAL_SPI_STATE_READY;
1499 __HAL_UNLOCK(hspi);
1500 return errorcode;
1501 }
1502
1503 /**
1504 * @brief Transmit an amount of data in non-blocking mode with Interrupt.
1505 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1506 * the configuration information for SPI module.
1507 * @param pData pointer to data buffer
1508 * @param Size amount of data to be sent
1509 * @retval HAL status
1510 */
HAL_SPI_Transmit_IT(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size)1511 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1512 {
1513 HAL_StatusTypeDef errorcode = HAL_OK;
1514
1515 /* Check Direction parameter */
1516 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
1517
1518 /* Process Locked */
1519 __HAL_LOCK(hspi);
1520
1521 if ((pData == NULL) || (Size == 0U))
1522 {
1523 errorcode = HAL_ERROR;
1524 goto error;
1525 }
1526
1527 if (hspi->State != HAL_SPI_STATE_READY)
1528 {
1529 errorcode = HAL_BUSY;
1530 goto error;
1531 }
1532
1533 /* Set the transaction information */
1534 hspi->State = HAL_SPI_STATE_BUSY_TX;
1535 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1536 hspi->pTxBuffPtr = (uint8_t *)pData;
1537 hspi->TxXferSize = Size;
1538 hspi->TxXferCount = Size;
1539
1540 /* Init field not used in handle to zero */
1541 hspi->pRxBuffPtr = (uint8_t *)NULL;
1542 hspi->RxXferSize = 0U;
1543 hspi->RxXferCount = 0U;
1544 hspi->RxISR = NULL;
1545
1546 /* Set the function for IT treatment */
1547 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1548 {
1549 hspi->TxISR = SPI_TxISR_16BIT;
1550 }
1551 else
1552 {
1553 hspi->TxISR = SPI_TxISR_8BIT;
1554 }
1555
1556 /* Configure communication direction : 1Line */
1557 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1558 {
1559 SPI_1LINE_TX(hspi);
1560 }
1561
1562 #if (USE_SPI_CRC != 0U)
1563 /* Reset CRC Calculation */
1564 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1565 {
1566 SPI_RESET_CRC(hspi);
1567 }
1568 #endif /* USE_SPI_CRC */
1569
1570 /* Enable TXE and ERR interrupt */
1571 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
1572
1573
1574 /* Check if the SPI is already enabled */
1575 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1576 {
1577 /* Enable SPI peripheral */
1578 __HAL_SPI_ENABLE(hspi);
1579 }
1580
1581 error :
1582 __HAL_UNLOCK(hspi);
1583 return errorcode;
1584 }
1585
1586 /**
1587 * @brief Receive an amount of data in non-blocking mode with Interrupt.
1588 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1589 * the configuration information for SPI module.
1590 * @param pData pointer to data buffer
1591 * @param Size amount of data to be sent
1592 * @retval HAL status
1593 */
HAL_SPI_Receive_IT(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size)1594 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1595 {
1596 HAL_StatusTypeDef errorcode = HAL_OK;
1597
1598 if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
1599 {
1600 hspi->State = HAL_SPI_STATE_BUSY_RX;
1601 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
1602 return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
1603 }
1604
1605 /* Process Locked */
1606 __HAL_LOCK(hspi);
1607
1608 if (hspi->State != HAL_SPI_STATE_READY)
1609 {
1610 errorcode = HAL_BUSY;
1611 goto error;
1612 }
1613
1614 if ((pData == NULL) || (Size == 0U))
1615 {
1616 errorcode = HAL_ERROR;
1617 goto error;
1618 }
1619
1620 /* Set the transaction information */
1621 hspi->State = HAL_SPI_STATE_BUSY_RX;
1622 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1623 hspi->pRxBuffPtr = (uint8_t *)pData;
1624 hspi->RxXferSize = Size;
1625 hspi->RxXferCount = Size;
1626
1627 /* Init field not used in handle to zero */
1628 hspi->pTxBuffPtr = (uint8_t *)NULL;
1629 hspi->TxXferSize = 0U;
1630 hspi->TxXferCount = 0U;
1631 hspi->TxISR = NULL;
1632
1633 /* Check the data size to adapt Rx threshold and the set the function for IT treatment */
1634 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1635 {
1636 /* Set RX Fifo threshold according the reception data length: 16 bit */
1637 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1638 hspi->RxISR = SPI_RxISR_16BIT;
1639 }
1640 else
1641 {
1642 /* Set RX Fifo threshold according the reception data length: 8 bit */
1643 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1644 hspi->RxISR = SPI_RxISR_8BIT;
1645 }
1646
1647 /* Configure communication direction : 1Line */
1648 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1649 {
1650 SPI_1LINE_RX(hspi);
1651 }
1652
1653 #if (USE_SPI_CRC != 0U)
1654 /* Reset CRC Calculation */
1655 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1656 {
1657 hspi->CRCSize = 1U;
1658 if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
1659 {
1660 hspi->CRCSize = 2U;
1661 }
1662 SPI_RESET_CRC(hspi);
1663 }
1664 else
1665 {
1666 hspi->CRCSize = 0U;
1667 }
1668 #endif /* USE_SPI_CRC */
1669
1670 /* Enable TXE and ERR interrupt */
1671 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
1672
1673 /* Note : The SPI must be enabled after unlocking current process
1674 to avoid the risk of SPI interrupt handle execution before current
1675 process unlock */
1676
1677 /* Check if the SPI is already enabled */
1678 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1679 {
1680 /* Enable SPI peripheral */
1681 __HAL_SPI_ENABLE(hspi);
1682 }
1683
1684 error :
1685 /* Process Unlocked */
1686 __HAL_UNLOCK(hspi);
1687 return errorcode;
1688 }
1689
1690 /**
1691 * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt.
1692 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1693 * the configuration information for SPI module.
1694 * @param pTxData pointer to transmission data buffer
1695 * @param pRxData pointer to reception data buffer
1696 * @param Size amount of data to be sent and received
1697 * @retval HAL status
1698 */
HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef * hspi,uint8_t * pTxData,uint8_t * pRxData,uint16_t Size)1699 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
1700 {
1701 uint32_t tmp_mode;
1702 HAL_SPI_StateTypeDef tmp_state;
1703 HAL_StatusTypeDef errorcode = HAL_OK;
1704
1705 /* Check Direction parameter */
1706 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
1707
1708 /* Process locked */
1709 __HAL_LOCK(hspi);
1710
1711 /* Init temporary variables */
1712 tmp_state = hspi->State;
1713 tmp_mode = hspi->Init.Mode;
1714
1715 if (!((tmp_state == HAL_SPI_STATE_READY) || \
1716 ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
1717 {
1718 errorcode = HAL_BUSY;
1719 goto error;
1720 }
1721
1722 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
1723 {
1724 errorcode = HAL_ERROR;
1725 goto error;
1726 }
1727
1728 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
1729 if (hspi->State != HAL_SPI_STATE_BUSY_RX)
1730 {
1731 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
1732 }
1733
1734 /* Set the transaction information */
1735 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1736 hspi->pTxBuffPtr = (uint8_t *)pTxData;
1737 hspi->TxXferSize = Size;
1738 hspi->TxXferCount = Size;
1739 hspi->pRxBuffPtr = (uint8_t *)pRxData;
1740 hspi->RxXferSize = Size;
1741 hspi->RxXferCount = Size;
1742
1743 /* Set the function for IT treatment */
1744 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1745 {
1746 hspi->RxISR = SPI_2linesRxISR_16BIT;
1747 hspi->TxISR = SPI_2linesTxISR_16BIT;
1748 }
1749 else
1750 {
1751 hspi->RxISR = SPI_2linesRxISR_8BIT;
1752 hspi->TxISR = SPI_2linesTxISR_8BIT;
1753 }
1754
1755 #if (USE_SPI_CRC != 0U)
1756 /* Reset CRC Calculation */
1757 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1758 {
1759 hspi->CRCSize = 1U;
1760 if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
1761 {
1762 hspi->CRCSize = 2U;
1763 }
1764 SPI_RESET_CRC(hspi);
1765 }
1766 else
1767 {
1768 hspi->CRCSize = 0U;
1769 }
1770 #endif /* USE_SPI_CRC */
1771
1772 /* Check if packing mode is enabled and if there is more than 2 data to receive */
1773 if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (Size >= 2U))
1774 {
1775 /* Set RX Fifo threshold according the reception data length: 16 bit */
1776 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1777 }
1778 else
1779 {
1780 /* Set RX Fifo threshold according the reception data length: 8 bit */
1781 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1782 }
1783
1784 /* Enable TXE, RXNE and ERR interrupt */
1785 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
1786
1787 /* Check if the SPI is already enabled */
1788 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1789 {
1790 /* Enable SPI peripheral */
1791 __HAL_SPI_ENABLE(hspi);
1792 }
1793
1794 error :
1795 /* Process Unlocked */
1796 __HAL_UNLOCK(hspi);
1797 return errorcode;
1798 }
1799
1800 /**
1801 * @brief Transmit an amount of data in non-blocking mode with DMA.
1802 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1803 * the configuration information for SPI module.
1804 * @param pData pointer to data buffer
1805 * @param Size amount of data to be sent
1806 * @retval HAL status
1807 */
HAL_SPI_Transmit_DMA(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size)1808 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1809 {
1810 HAL_StatusTypeDef errorcode = HAL_OK;
1811
1812 /* Check tx dma handle */
1813 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
1814
1815 /* Check Direction parameter */
1816 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
1817
1818 /* Process Locked */
1819 __HAL_LOCK(hspi);
1820
1821 if (hspi->State != HAL_SPI_STATE_READY)
1822 {
1823 errorcode = HAL_BUSY;
1824 goto error;
1825 }
1826
1827 if ((pData == NULL) || (Size == 0U))
1828 {
1829 errorcode = HAL_ERROR;
1830 goto error;
1831 }
1832
1833 /* Set the transaction information */
1834 hspi->State = HAL_SPI_STATE_BUSY_TX;
1835 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1836 hspi->pTxBuffPtr = (uint8_t *)pData;
1837 hspi->TxXferSize = Size;
1838 hspi->TxXferCount = Size;
1839
1840 /* Init field not used in handle to zero */
1841 hspi->pRxBuffPtr = (uint8_t *)NULL;
1842 hspi->TxISR = NULL;
1843 hspi->RxISR = NULL;
1844 hspi->RxXferSize = 0U;
1845 hspi->RxXferCount = 0U;
1846
1847 /* Configure communication direction : 1Line */
1848 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1849 {
1850 SPI_1LINE_TX(hspi);
1851 }
1852
1853 #if (USE_SPI_CRC != 0U)
1854 /* Reset CRC Calculation */
1855 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1856 {
1857 SPI_RESET_CRC(hspi);
1858 }
1859 #endif /* USE_SPI_CRC */
1860
1861 /* Set the SPI TxDMA Half transfer complete callback */
1862 hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
1863
1864 /* Set the SPI TxDMA transfer complete callback */
1865 hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
1866
1867 /* Set the DMA error callback */
1868 hspi->hdmatx->XferErrorCallback = SPI_DMAError;
1869
1870 /* Set the DMA AbortCpltCallback */
1871 hspi->hdmatx->XferAbortCallback = NULL;
1872
1873 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
1874 /* Packing mode is enabled only if the DMA setting is HALWORD */
1875 if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
1876 {
1877 /* Check the even/odd of the data size + crc if enabled */
1878 if ((hspi->TxXferCount & 0x1U) == 0U)
1879 {
1880 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
1881 hspi->TxXferCount = (hspi->TxXferCount >> 1U);
1882 }
1883 else
1884 {
1885 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
1886 hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
1887 }
1888 }
1889
1890 /* Enable the Tx DMA Stream/Channel */
1891 if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount))
1892 {
1893 /* Update SPI error code */
1894 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
1895 errorcode = HAL_ERROR;
1896
1897 hspi->State = HAL_SPI_STATE_READY;
1898 goto error;
1899 }
1900
1901 /* Check if the SPI is already enabled */
1902 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1903 {
1904 /* Enable SPI peripheral */
1905 __HAL_SPI_ENABLE(hspi);
1906 }
1907
1908 /* Enable the SPI Error Interrupt Bit */
1909 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
1910
1911 /* Enable Tx DMA Request */
1912 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
1913
1914 error :
1915 /* Process Unlocked */
1916 __HAL_UNLOCK(hspi);
1917 return errorcode;
1918 }
1919
1920 /**
1921 * @brief Receive an amount of data in non-blocking mode with DMA.
1922 * @note In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined.
1923 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1924 * the configuration information for SPI module.
1925 * @param pData pointer to data buffer
1926 * @note When the CRC feature is enabled the pData Length must be Size + 1.
1927 * @param Size amount of data to be sent
1928 * @retval HAL status
1929 */
HAL_SPI_Receive_DMA(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size)1930 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1931 {
1932 HAL_StatusTypeDef errorcode = HAL_OK;
1933
1934 /* Check rx dma handle */
1935 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
1936
1937 if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
1938 {
1939 hspi->State = HAL_SPI_STATE_BUSY_RX;
1940
1941 /* Check tx dma handle */
1942 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
1943
1944 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
1945 return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
1946 }
1947
1948 /* Process Locked */
1949 __HAL_LOCK(hspi);
1950
1951 if (hspi->State != HAL_SPI_STATE_READY)
1952 {
1953 errorcode = HAL_BUSY;
1954 goto error;
1955 }
1956
1957 if ((pData == NULL) || (Size == 0U))
1958 {
1959 errorcode = HAL_ERROR;
1960 goto error;
1961 }
1962
1963 /* Set the transaction information */
1964 hspi->State = HAL_SPI_STATE_BUSY_RX;
1965 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1966 hspi->pRxBuffPtr = (uint8_t *)pData;
1967 hspi->RxXferSize = Size;
1968 hspi->RxXferCount = Size;
1969
1970 /*Init field not used in handle to zero */
1971 hspi->RxISR = NULL;
1972 hspi->TxISR = NULL;
1973 hspi->TxXferSize = 0U;
1974 hspi->TxXferCount = 0U;
1975
1976 /* Configure communication direction : 1Line */
1977 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1978 {
1979 SPI_1LINE_RX(hspi);
1980 }
1981
1982 #if (USE_SPI_CRC != 0U)
1983 /* Reset CRC Calculation */
1984 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1985 {
1986 SPI_RESET_CRC(hspi);
1987 }
1988 #endif /* USE_SPI_CRC */
1989
1990
1991 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
1992 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1993 {
1994 /* Set RX Fifo threshold according the reception data length: 16bit */
1995 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1996 }
1997 else
1998 {
1999 /* Set RX Fifo threshold according the reception data length: 8bit */
2000 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
2001
2002 if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
2003 {
2004 /* Set RX Fifo threshold according the reception data length: 16bit */
2005 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
2006
2007 if ((hspi->RxXferCount & 0x1U) == 0x0U)
2008 {
2009 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
2010 hspi->RxXferCount = hspi->RxXferCount >> 1U;
2011 }
2012 else
2013 {
2014 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
2015 hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
2016 }
2017 }
2018 }
2019
2020 /* Set the SPI RxDMA Half transfer complete callback */
2021 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
2022
2023 /* Set the SPI Rx DMA transfer complete callback */
2024 hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
2025
2026 /* Set the DMA error callback */
2027 hspi->hdmarx->XferErrorCallback = SPI_DMAError;
2028
2029 /* Set the DMA AbortCpltCallback */
2030 hspi->hdmarx->XferAbortCallback = NULL;
2031
2032 /* Enable the Rx DMA Stream/Channel */
2033 if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount))
2034 {
2035 /* Update SPI error code */
2036 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2037 errorcode = HAL_ERROR;
2038
2039 hspi->State = HAL_SPI_STATE_READY;
2040 goto error;
2041 }
2042
2043 /* Check if the SPI is already enabled */
2044 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
2045 {
2046 /* Enable SPI peripheral */
2047 __HAL_SPI_ENABLE(hspi);
2048 }
2049
2050 /* Enable the SPI Error Interrupt Bit */
2051 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
2052
2053 /* Enable Rx DMA Request */
2054 SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
2055
2056 error:
2057 /* Process Unlocked */
2058 __HAL_UNLOCK(hspi);
2059 return errorcode;
2060 }
2061
2062 /**
2063 * @brief Transmit and Receive an amount of data in non-blocking mode with DMA.
2064 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2065 * the configuration information for SPI module.
2066 * @param pTxData pointer to transmission data buffer
2067 * @param pRxData pointer to reception data buffer
2068 * @note When the CRC feature is enabled the pRxData Length must be Size + 1
2069 * @param Size amount of data to be sent
2070 * @retval HAL status
2071 */
HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef * hspi,uint8_t * pTxData,uint8_t * pRxData,uint16_t Size)2072 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
2073 uint16_t Size)
2074 {
2075 uint32_t tmp_mode;
2076 HAL_SPI_StateTypeDef tmp_state;
2077 HAL_StatusTypeDef errorcode = HAL_OK;
2078
2079 /* Check rx & tx dma handles */
2080 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
2081 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
2082
2083 /* Check Direction parameter */
2084 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
2085
2086 /* Process locked */
2087 __HAL_LOCK(hspi);
2088
2089 /* Init temporary variables */
2090 tmp_state = hspi->State;
2091 tmp_mode = hspi->Init.Mode;
2092
2093 if (!((tmp_state == HAL_SPI_STATE_READY) ||
2094 ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
2095 {
2096 errorcode = HAL_BUSY;
2097 goto error;
2098 }
2099
2100 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
2101 {
2102 errorcode = HAL_ERROR;
2103 goto error;
2104 }
2105
2106 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
2107 if (hspi->State != HAL_SPI_STATE_BUSY_RX)
2108 {
2109 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
2110 }
2111
2112 /* Set the transaction information */
2113 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
2114 hspi->pTxBuffPtr = (uint8_t *)pTxData;
2115 hspi->TxXferSize = Size;
2116 hspi->TxXferCount = Size;
2117 hspi->pRxBuffPtr = (uint8_t *)pRxData;
2118 hspi->RxXferSize = Size;
2119 hspi->RxXferCount = Size;
2120
2121 /* Init field not used in handle to zero */
2122 hspi->RxISR = NULL;
2123 hspi->TxISR = NULL;
2124
2125 #if (USE_SPI_CRC != 0U)
2126 /* Reset CRC Calculation */
2127 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
2128 {
2129 SPI_RESET_CRC(hspi);
2130 }
2131 #endif /* USE_SPI_CRC */
2132
2133 /* Reset the threshold bit */
2134 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX);
2135
2136 /* The packing mode management is enabled by the DMA settings according the spi data size */
2137 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
2138 {
2139 /* Set fiforxthreshold according the reception data length: 16bit */
2140 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
2141 }
2142 else
2143 {
2144 /* Set RX Fifo threshold according the reception data length: 8bit */
2145 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
2146
2147 if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
2148 {
2149 if ((hspi->TxXferSize & 0x1U) == 0x0U)
2150 {
2151 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
2152 hspi->TxXferCount = hspi->TxXferCount >> 1U;
2153 }
2154 else
2155 {
2156 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
2157 hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
2158 }
2159 }
2160
2161 if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
2162 {
2163 /* Set RX Fifo threshold according the reception data length: 16bit */
2164 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
2165
2166 if ((hspi->RxXferCount & 0x1U) == 0x0U)
2167 {
2168 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
2169 hspi->RxXferCount = hspi->RxXferCount >> 1U;
2170 }
2171 else
2172 {
2173 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
2174 hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
2175 }
2176 }
2177 }
2178
2179 /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
2180 if (hspi->State == HAL_SPI_STATE_BUSY_RX)
2181 {
2182 /* Set the SPI Rx DMA Half transfer complete callback */
2183 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
2184 hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
2185 }
2186 else
2187 {
2188 /* Set the SPI Tx/Rx DMA Half transfer complete callback */
2189 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
2190 hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
2191 }
2192
2193 /* Set the DMA error callback */
2194 hspi->hdmarx->XferErrorCallback = SPI_DMAError;
2195
2196 /* Set the DMA AbortCpltCallback */
2197 hspi->hdmarx->XferAbortCallback = NULL;
2198
2199 /* Enable the Rx DMA Stream/Channel */
2200 if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount))
2201 {
2202 /* Update SPI error code */
2203 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2204 errorcode = HAL_ERROR;
2205
2206 hspi->State = HAL_SPI_STATE_READY;
2207 goto error;
2208 }
2209
2210 /* Enable Rx DMA Request */
2211 SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
2212
2213 /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
2214 is performed in DMA reception complete callback */
2215 hspi->hdmatx->XferHalfCpltCallback = NULL;
2216 hspi->hdmatx->XferCpltCallback = NULL;
2217 hspi->hdmatx->XferErrorCallback = NULL;
2218 hspi->hdmatx->XferAbortCallback = NULL;
2219
2220 /* Enable the Tx DMA Stream/Channel */
2221 if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount))
2222 {
2223 /* Update SPI error code */
2224 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2225 errorcode = HAL_ERROR;
2226
2227 hspi->State = HAL_SPI_STATE_READY;
2228 goto error;
2229 }
2230
2231 /* Check if the SPI is already enabled */
2232 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
2233 {
2234 /* Enable SPI peripheral */
2235 __HAL_SPI_ENABLE(hspi);
2236 }
2237 /* Enable the SPI Error Interrupt Bit */
2238 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
2239
2240 /* Enable Tx DMA Request */
2241 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
2242
2243 error :
2244 /* Process Unlocked */
2245 __HAL_UNLOCK(hspi);
2246 return errorcode;
2247 }
2248
2249 /**
2250 * @brief Abort ongoing transfer (blocking mode).
2251 * @param hspi SPI handle.
2252 * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
2253 * started in Interrupt or DMA mode.
2254 * This procedure performs following operations :
2255 * - Disable SPI Interrupts (depending of transfer direction)
2256 * - Disable the DMA transfer in the peripheral register (if enabled)
2257 * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
2258 * - Set handle State to READY
2259 * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
2260 * @retval HAL status
2261 */
HAL_SPI_Abort(SPI_HandleTypeDef * hspi)2262 HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
2263 {
2264 HAL_StatusTypeDef errorcode;
2265 __IO uint32_t count, resetcount;
2266
2267 /* Initialized local variable */
2268 errorcode = HAL_OK;
2269 resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
2270 count = resetcount;
2271
2272 /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
2273 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
2274 {
2275 hspi->TxISR = SPI_AbortTx_ISR;
2276 /* Wait HAL_SPI_STATE_ABORT state */
2277 do
2278 {
2279 if (count == 0U)
2280 {
2281 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2282 break;
2283 }
2284 count--;
2285 }
2286 while (hspi->State != HAL_SPI_STATE_ABORT);
2287 /* Reset Timeout Counter */
2288 count = resetcount;
2289 }
2290
2291 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
2292 {
2293 hspi->RxISR = SPI_AbortRx_ISR;
2294 /* Wait HAL_SPI_STATE_ABORT state */
2295 do
2296 {
2297 if (count == 0U)
2298 {
2299 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2300 break;
2301 }
2302 count--;
2303 }
2304 while (hspi->State != HAL_SPI_STATE_ABORT);
2305 /* Reset Timeout Counter */
2306 count = resetcount;
2307 }
2308
2309 /* Clear ERRIE interrupts in case of DMA Mode */
2310 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
2311
2312 /* Disable the SPI DMA Tx or SPI DMA Rx request if enabled */
2313 if ((READ_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN))) == (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN))
2314 {
2315 /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */
2316 if (hspi->hdmatx != NULL)
2317 {
2318 /* Set the SPI DMA Abort callback :
2319 will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
2320 hspi->hdmatx->XferAbortCallback = NULL;
2321
2322 /* Abort DMA Tx Handle linked to SPI Peripheral */
2323 if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK)
2324 {
2325 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2326 }
2327
2328 /* Disable Tx DMA Request */
2329 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN));
2330
2331 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
2332 {
2333 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2334 }
2335
2336 /* Disable SPI Peripheral */
2337 __HAL_SPI_DISABLE(hspi);
2338
2339 /* Empty the FRLVL fifo */
2340 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
2341 {
2342 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2343 }
2344 }
2345 /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */
2346 if (hspi->hdmarx != NULL)
2347 {
2348 /* Set the SPI DMA Abort callback :
2349 will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
2350 hspi->hdmarx->XferAbortCallback = NULL;
2351
2352 /* Abort DMA Rx Handle linked to SPI Peripheral */
2353 if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK)
2354 {
2355 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2356 }
2357
2358 /* Disable peripheral */
2359 __HAL_SPI_DISABLE(hspi);
2360
2361 /* Control the BSY flag */
2362 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
2363 {
2364 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2365 }
2366
2367 /* Empty the FRLVL fifo */
2368 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
2369 {
2370 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2371 }
2372
2373 /* Disable Rx DMA Request */
2374 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN));
2375 }
2376 }
2377 /* Reset Tx and Rx transfer counters */
2378 hspi->RxXferCount = 0U;
2379 hspi->TxXferCount = 0U;
2380
2381 /* Check error during Abort procedure */
2382 if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
2383 {
2384 /* return HAL_Error in case of error during Abort procedure */
2385 errorcode = HAL_ERROR;
2386 }
2387 else
2388 {
2389 /* Reset errorCode */
2390 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
2391 }
2392
2393 /* Clear the Error flags in the SR register */
2394 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2395 __HAL_SPI_CLEAR_FREFLAG(hspi);
2396
2397 /* Restore hspi->state to ready */
2398 hspi->State = HAL_SPI_STATE_READY;
2399
2400 return errorcode;
2401 }
2402
2403 /**
2404 * @brief Abort ongoing transfer (Interrupt mode).
2405 * @param hspi SPI handle.
2406 * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
2407 * started in Interrupt or DMA mode.
2408 * This procedure performs following operations :
2409 * - Disable SPI Interrupts (depending of transfer direction)
2410 * - Disable the DMA transfer in the peripheral register (if enabled)
2411 * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
2412 * - Set handle State to READY
2413 * - At abort completion, call user abort complete callback
2414 * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
2415 * considered as completed only when user abort complete callback is executed (not when exiting function).
2416 * @retval HAL status
2417 */
HAL_SPI_Abort_IT(SPI_HandleTypeDef * hspi)2418 HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
2419 {
2420 HAL_StatusTypeDef errorcode;
2421 uint32_t abortcplt ;
2422 __IO uint32_t count, resetcount;
2423
2424 /* Initialized local variable */
2425 errorcode = HAL_OK;
2426 abortcplt = 1U;
2427 resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
2428 count = resetcount;
2429
2430 /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */
2431 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
2432 {
2433 hspi->TxISR = SPI_AbortTx_ISR;
2434 /* Wait HAL_SPI_STATE_ABORT state */
2435 do
2436 {
2437 if (count == 0U)
2438 {
2439 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2440 break;
2441 }
2442 count--;
2443 }
2444 while (hspi->State != HAL_SPI_STATE_ABORT);
2445 /* Reset Timeout Counter */
2446 count = resetcount;
2447 }
2448
2449 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
2450 {
2451 hspi->RxISR = SPI_AbortRx_ISR;
2452 /* Wait HAL_SPI_STATE_ABORT state */
2453 do
2454 {
2455 if (count == 0U)
2456 {
2457 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2458 break;
2459 }
2460 count--;
2461 }
2462 while (hspi->State != HAL_SPI_STATE_ABORT);
2463 /* Reset Timeout Counter */
2464 count = resetcount;
2465 }
2466
2467 /* Clear ERRIE interrupts in case of DMA Mode */
2468 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
2469
2470 /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised
2471 before any call to DMA Abort functions */
2472 /* DMA Tx Handle is valid */
2473 if (hspi->hdmatx != NULL)
2474 {
2475 /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
2476 Otherwise, set it to NULL */
2477 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
2478 {
2479 hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;
2480 }
2481 else
2482 {
2483 hspi->hdmatx->XferAbortCallback = NULL;
2484 }
2485 }
2486 /* DMA Rx Handle is valid */
2487 if (hspi->hdmarx != NULL)
2488 {
2489 /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
2490 Otherwise, set it to NULL */
2491 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
2492 {
2493 hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;
2494 }
2495 else
2496 {
2497 hspi->hdmarx->XferAbortCallback = NULL;
2498 }
2499 }
2500
2501 /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
2502 if ((READ_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN))) == (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN))
2503 {
2504 /* Abort the SPI DMA Tx Stream/Channel */
2505 if (hspi->hdmatx != NULL)
2506 {
2507 /* Abort DMA Tx Handle linked to SPI Peripheral */
2508 if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
2509 {
2510 hspi->hdmatx->XferAbortCallback = NULL;
2511 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2512 }
2513 else
2514 {
2515 abortcplt = 0U;
2516 }
2517 }
2518 /* Abort the SPI DMA Rx Stream/Channel */
2519 if (hspi->hdmarx != NULL)
2520 {
2521 /* Abort DMA Rx Handle linked to SPI Peripheral */
2522 if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK)
2523 {
2524 hspi->hdmarx->XferAbortCallback = NULL;
2525 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2526 abortcplt = 1U;
2527 }
2528 else
2529 {
2530 abortcplt = 0U;
2531 }
2532 }
2533 }
2534
2535 /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
2536 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
2537 {
2538 /* Abort the SPI DMA Tx Stream/Channel */
2539 if (hspi->hdmatx != NULL)
2540 {
2541 /* Abort DMA Tx Handle linked to SPI Peripheral */
2542 if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
2543 {
2544 hspi->hdmatx->XferAbortCallback = NULL;
2545 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2546 }
2547 else
2548 {
2549 abortcplt = 0U;
2550 }
2551 }
2552 }
2553 /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
2554 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
2555 {
2556 /* Abort the SPI DMA Rx Stream/Channel */
2557 if (hspi->hdmarx != NULL)
2558 {
2559 /* Abort DMA Rx Handle linked to SPI Peripheral */
2560 if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK)
2561 {
2562 hspi->hdmarx->XferAbortCallback = NULL;
2563 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2564 }
2565 else
2566 {
2567 abortcplt = 0U;
2568 }
2569 }
2570 }
2571
2572 if (abortcplt == 1U)
2573 {
2574 /* Reset Tx and Rx transfer counters */
2575 hspi->RxXferCount = 0U;
2576 hspi->TxXferCount = 0U;
2577
2578 /* Check error during Abort procedure */
2579 if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
2580 {
2581 /* return HAL_Error in case of error during Abort procedure */
2582 errorcode = HAL_ERROR;
2583 }
2584 else
2585 {
2586 /* Reset errorCode */
2587 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
2588 }
2589
2590 /* Clear the Error flags in the SR register */
2591 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2592 __HAL_SPI_CLEAR_FREFLAG(hspi);
2593
2594 /* Restore hspi->State to Ready */
2595 hspi->State = HAL_SPI_STATE_READY;
2596
2597 /* As no DMA to be aborted, call directly user Abort complete callback */
2598 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2599 hspi->AbortCpltCallback(hspi);
2600 #else
2601 HAL_SPI_AbortCpltCallback(hspi);
2602 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2603 }
2604
2605 return errorcode;
2606 }
2607
2608 /**
2609 * @brief Pause the DMA Transfer.
2610 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2611 * the configuration information for the specified SPI module.
2612 * @retval HAL status
2613 */
HAL_SPI_DMAPause(SPI_HandleTypeDef * hspi)2614 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
2615 {
2616 /* Process Locked */
2617 __HAL_LOCK(hspi);
2618
2619 /* Disable the SPI DMA Tx & Rx requests */
2620 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
2621
2622 /* Process Unlocked */
2623 __HAL_UNLOCK(hspi);
2624
2625 return HAL_OK;
2626 }
2627
2628 /**
2629 * @brief Resume the DMA Transfer.
2630 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2631 * the configuration information for the specified SPI module.
2632 * @retval HAL status
2633 */
HAL_SPI_DMAResume(SPI_HandleTypeDef * hspi)2634 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
2635 {
2636 /* Process Locked */
2637 __HAL_LOCK(hspi);
2638
2639 /* Enable the SPI DMA Tx & Rx requests */
2640 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
2641
2642 /* Process Unlocked */
2643 __HAL_UNLOCK(hspi);
2644
2645 return HAL_OK;
2646 }
2647
2648 /**
2649 * @brief Stop the DMA Transfer.
2650 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2651 * the configuration information for the specified SPI module.
2652 * @retval HAL status
2653 */
HAL_SPI_DMAStop(SPI_HandleTypeDef * hspi)2654 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
2655 {
2656 HAL_StatusTypeDef errorcode = HAL_OK;
2657 /* The Lock is not implemented on this API to allow the user application
2658 to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
2659 when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
2660 and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
2661 */
2662
2663 /* Abort the SPI DMA tx Stream/Channel */
2664 if (hspi->hdmatx != NULL)
2665 {
2666 if (HAL_OK != HAL_DMA_Abort(hspi->hdmatx))
2667 {
2668 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2669 errorcode = HAL_ERROR;
2670 }
2671 }
2672 /* Abort the SPI DMA rx Stream/Channel */
2673 if (hspi->hdmarx != NULL)
2674 {
2675 if (HAL_OK != HAL_DMA_Abort(hspi->hdmarx))
2676 {
2677 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2678 errorcode = HAL_ERROR;
2679 }
2680 }
2681
2682 /* Disable the SPI DMA Tx & Rx requests */
2683 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
2684 hspi->State = HAL_SPI_STATE_READY;
2685 return errorcode;
2686 }
2687
2688 /**
2689 * @brief Handle SPI interrupt request.
2690 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2691 * the configuration information for the specified SPI module.
2692 * @retval None
2693 */
HAL_SPI_IRQHandler(SPI_HandleTypeDef * hspi)2694 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
2695 {
2696 uint32_t itsource = hspi->Instance->CR2;
2697 uint32_t itflag = hspi->Instance->SR;
2698
2699 /* SPI in mode Receiver ----------------------------------------------------*/
2700 if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) == RESET) &&
2701 (SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXNE) != RESET))
2702 {
2703 hspi->RxISR(hspi);
2704 return;
2705 }
2706
2707 /* SPI in mode Transmitter -------------------------------------------------*/
2708 if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_TXE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_TXE) != RESET))
2709 {
2710 hspi->TxISR(hspi);
2711 return;
2712 }
2713
2714 /* SPI in Error Treatment --------------------------------------------------*/
2715 if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET))
2716 {
2717 /* SPI Overrun error interrupt occurred ----------------------------------*/
2718 if (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
2719 {
2720 if (hspi->State != HAL_SPI_STATE_BUSY_TX)
2721 {
2722 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
2723 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2724 }
2725 else
2726 {
2727 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2728 return;
2729 }
2730 }
2731
2732 /* SPI Mode Fault error interrupt occurred -------------------------------*/
2733 if (SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET)
2734 {
2735 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
2736 __HAL_SPI_CLEAR_MODFFLAG(hspi);
2737 }
2738
2739 /* SPI Frame error interrupt occurred ------------------------------------*/
2740 if (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)
2741 {
2742 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
2743 __HAL_SPI_CLEAR_FREFLAG(hspi);
2744 }
2745
2746 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
2747 {
2748 /* Disable all interrupts */
2749 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
2750
2751 hspi->State = HAL_SPI_STATE_READY;
2752 /* Disable the SPI DMA requests if enabled */
2753 if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN)))
2754 {
2755 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));
2756
2757 /* Abort the SPI DMA Rx channel */
2758 if (hspi->hdmarx != NULL)
2759 {
2760 /* Set the SPI DMA Abort callback :
2761 will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
2762 hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
2763 if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx))
2764 {
2765 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2766 }
2767 }
2768 /* Abort the SPI DMA Tx channel */
2769 if (hspi->hdmatx != NULL)
2770 {
2771 /* Set the SPI DMA Abort callback :
2772 will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
2773 hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
2774 if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx))
2775 {
2776 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2777 }
2778 }
2779 }
2780 else
2781 {
2782 /* Call user error callback */
2783 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2784 hspi->ErrorCallback(hspi);
2785 #else
2786 HAL_SPI_ErrorCallback(hspi);
2787 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2788 }
2789 }
2790 return;
2791 }
2792 }
2793
2794 /**
2795 * @brief Tx Transfer completed callback.
2796 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2797 * the configuration information for SPI module.
2798 * @retval None
2799 */
HAL_SPI_TxCpltCallback(SPI_HandleTypeDef * hspi)2800 __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
2801 {
2802 /* Prevent unused argument(s) compilation warning */
2803 UNUSED(hspi);
2804
2805 /* NOTE : This function should not be modified, when the callback is needed,
2806 the HAL_SPI_TxCpltCallback should be implemented in the user file
2807 */
2808 }
2809
2810 /**
2811 * @brief Rx Transfer completed callback.
2812 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2813 * the configuration information for SPI module.
2814 * @retval None
2815 */
HAL_SPI_RxCpltCallback(SPI_HandleTypeDef * hspi)2816 __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
2817 {
2818 /* Prevent unused argument(s) compilation warning */
2819 UNUSED(hspi);
2820
2821 /* NOTE : This function should not be modified, when the callback is needed,
2822 the HAL_SPI_RxCpltCallback should be implemented in the user file
2823 */
2824 }
2825
2826 /**
2827 * @brief Tx and Rx Transfer completed callback.
2828 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2829 * the configuration information for SPI module.
2830 * @retval None
2831 */
HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef * hspi)2832 __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
2833 {
2834 /* Prevent unused argument(s) compilation warning */
2835 UNUSED(hspi);
2836
2837 /* NOTE : This function should not be modified, when the callback is needed,
2838 the HAL_SPI_TxRxCpltCallback should be implemented in the user file
2839 */
2840 }
2841
2842 /**
2843 * @brief Tx Half Transfer completed callback.
2844 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2845 * the configuration information for SPI module.
2846 * @retval None
2847 */
HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef * hspi)2848 __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
2849 {
2850 /* Prevent unused argument(s) compilation warning */
2851 UNUSED(hspi);
2852
2853 /* NOTE : This function should not be modified, when the callback is needed,
2854 the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
2855 */
2856 }
2857
2858 /**
2859 * @brief Rx Half Transfer completed callback.
2860 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2861 * the configuration information for SPI module.
2862 * @retval None
2863 */
HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef * hspi)2864 __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
2865 {
2866 /* Prevent unused argument(s) compilation warning */
2867 UNUSED(hspi);
2868
2869 /* NOTE : This function should not be modified, when the callback is needed,
2870 the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
2871 */
2872 }
2873
2874 /**
2875 * @brief Tx and Rx Half Transfer callback.
2876 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2877 * the configuration information for SPI module.
2878 * @retval None
2879 */
HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef * hspi)2880 __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
2881 {
2882 /* Prevent unused argument(s) compilation warning */
2883 UNUSED(hspi);
2884
2885 /* NOTE : This function should not be modified, when the callback is needed,
2886 the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
2887 */
2888 }
2889
2890 /**
2891 * @brief SPI error callback.
2892 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2893 * the configuration information for SPI module.
2894 * @retval None
2895 */
HAL_SPI_ErrorCallback(SPI_HandleTypeDef * hspi)2896 __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
2897 {
2898 /* Prevent unused argument(s) compilation warning */
2899 UNUSED(hspi);
2900
2901 /* NOTE : This function should not be modified, when the callback is needed,
2902 the HAL_SPI_ErrorCallback should be implemented in the user file
2903 */
2904 /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
2905 and user can use HAL_SPI_GetError() API to check the latest error occurred
2906 */
2907 }
2908
2909 /**
2910 * @brief SPI Abort Complete callback.
2911 * @param hspi SPI handle.
2912 * @retval None
2913 */
HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef * hspi)2914 __weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
2915 {
2916 /* Prevent unused argument(s) compilation warning */
2917 UNUSED(hspi);
2918
2919 /* NOTE : This function should not be modified, when the callback is needed,
2920 the HAL_SPI_AbortCpltCallback can be implemented in the user file.
2921 */
2922 }
2923
2924 /**
2925 * @}
2926 */
2927
2928 /** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
2929 * @brief SPI control functions
2930 *
2931 @verbatim
2932 ===============================================================================
2933 ##### Peripheral State and Errors functions #####
2934 ===============================================================================
2935 [..]
2936 This subsection provides a set of functions allowing to control the SPI.
2937 (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
2938 (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
2939 @endverbatim
2940 * @{
2941 */
2942
2943 /**
2944 * @brief Return the SPI handle state.
2945 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2946 * the configuration information for SPI module.
2947 * @retval SPI state
2948 */
HAL_SPI_GetState(SPI_HandleTypeDef * hspi)2949 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
2950 {
2951 /* Return SPI handle state */
2952 return hspi->State;
2953 }
2954
2955 /**
2956 * @brief Return the SPI error code.
2957 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2958 * the configuration information for SPI module.
2959 * @retval SPI error code in bitmap format
2960 */
HAL_SPI_GetError(SPI_HandleTypeDef * hspi)2961 uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
2962 {
2963 /* Return SPI ErrorCode */
2964 return hspi->ErrorCode;
2965 }
2966
2967 /**
2968 * @}
2969 */
2970
2971 /**
2972 * @}
2973 */
2974
2975 /** @addtogroup SPI_Private_Functions
2976 * @brief Private functions
2977 * @{
2978 */
2979
2980 /**
2981 * @brief DMA SPI transmit process complete callback.
2982 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
2983 * the configuration information for the specified DMA module.
2984 * @retval None
2985 */
SPI_DMATransmitCplt(DMA_HandleTypeDef * hdma)2986 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
2987 {
2988 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
2989 uint32_t tickstart;
2990
2991 /* Init tickstart for timeout managment*/
2992 tickstart = HAL_GetTick();
2993
2994 /* DMA Normal Mode */
2995 if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
2996 {
2997 /* Disable ERR interrupt */
2998 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
2999
3000 /* Disable Tx DMA Request */
3001 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
3002
3003 /* Check the end of the transaction */
3004 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3005 {
3006 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3007 }
3008
3009 /* Clear overrun flag in 2 Lines communication mode because received data is not read */
3010 if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
3011 {
3012 __HAL_SPI_CLEAR_OVRFLAG(hspi);
3013 }
3014
3015 hspi->TxXferCount = 0U;
3016 hspi->State = HAL_SPI_STATE_READY;
3017
3018 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
3019 {
3020 /* Call user error callback */
3021 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3022 hspi->ErrorCallback(hspi);
3023 #else
3024 HAL_SPI_ErrorCallback(hspi);
3025 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3026 return;
3027 }
3028 }
3029 /* Call user Tx complete callback */
3030 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3031 hspi->TxCpltCallback(hspi);
3032 #else
3033 HAL_SPI_TxCpltCallback(hspi);
3034 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3035 }
3036
3037 /**
3038 * @brief DMA SPI receive process complete callback.
3039 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3040 * the configuration information for the specified DMA module.
3041 * @retval None
3042 */
SPI_DMAReceiveCplt(DMA_HandleTypeDef * hdma)3043 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
3044 {
3045 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3046 uint32_t tickstart;
3047
3048 /* Init tickstart for timeout management*/
3049 tickstart = HAL_GetTick();
3050
3051 /* DMA Normal Mode */
3052 if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
3053 {
3054 /* Disable ERR interrupt */
3055 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
3056
3057 #if (USE_SPI_CRC != 0U)
3058 /* CRC handling */
3059 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3060 {
3061 /* Wait until RXNE flag */
3062 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3063 {
3064 /* Error on the CRC reception */
3065 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3066 }
3067 /* Read CRC */
3068 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
3069 {
3070 /* Read 16bit CRC */
3071 READ_REG(hspi->Instance->DR);
3072 }
3073 else
3074 {
3075 /* Read 8bit CRC */
3076 READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
3077
3078 if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
3079 {
3080 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3081 {
3082 /* Error on the CRC reception */
3083 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3084 }
3085 /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
3086 READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
3087 }
3088 }
3089 }
3090 #endif /* USE_SPI_CRC */
3091
3092 /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
3093 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
3094
3095 /* Check the end of the transaction */
3096 if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3097 {
3098 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
3099 }
3100
3101 hspi->RxXferCount = 0U;
3102 hspi->State = HAL_SPI_STATE_READY;
3103
3104 #if (USE_SPI_CRC != 0U)
3105 /* Check if CRC error occurred */
3106 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
3107 {
3108 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3109 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
3110 }
3111 #endif /* USE_SPI_CRC */
3112
3113 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
3114 {
3115 /* Call user error callback */
3116 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3117 hspi->ErrorCallback(hspi);
3118 #else
3119 HAL_SPI_ErrorCallback(hspi);
3120 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3121 return;
3122 }
3123 }
3124 /* Call user Rx complete callback */
3125 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3126 hspi->RxCpltCallback(hspi);
3127 #else
3128 HAL_SPI_RxCpltCallback(hspi);
3129 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3130 }
3131
3132 /**
3133 * @brief DMA SPI transmit receive process complete callback.
3134 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3135 * the configuration information for the specified DMA module.
3136 * @retval None
3137 */
SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef * hdma)3138 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
3139 {
3140 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3141 uint32_t tickstart;
3142
3143 /* Init tickstart for timeout management*/
3144 tickstart = HAL_GetTick();
3145
3146 /* DMA Normal Mode */
3147 if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
3148 {
3149 /* Disable ERR interrupt */
3150 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
3151
3152 #if (USE_SPI_CRC != 0U)
3153 /* CRC handling */
3154 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3155 {
3156 if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))
3157 {
3158 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT,
3159 tickstart) != HAL_OK)
3160 {
3161 /* Error on the CRC reception */
3162 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3163 }
3164 /* Read CRC to Flush DR and RXNE flag */
3165 READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
3166 }
3167 else
3168 {
3169 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3170 {
3171 /* Error on the CRC reception */
3172 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3173 }
3174 /* Read CRC to Flush DR and RXNE flag */
3175 READ_REG(hspi->Instance->DR);
3176 }
3177 }
3178 #endif /* USE_SPI_CRC */
3179
3180 /* Check the end of the transaction */
3181 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3182 {
3183 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3184 }
3185
3186 /* Disable Rx/Tx DMA Request */
3187 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
3188
3189 hspi->TxXferCount = 0U;
3190 hspi->RxXferCount = 0U;
3191 hspi->State = HAL_SPI_STATE_READY;
3192
3193 #if (USE_SPI_CRC != 0U)
3194 /* Check if CRC error occurred */
3195 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
3196 {
3197 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3198 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
3199 }
3200 #endif /* USE_SPI_CRC */
3201
3202 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
3203 {
3204 /* Call user error callback */
3205 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3206 hspi->ErrorCallback(hspi);
3207 #else
3208 HAL_SPI_ErrorCallback(hspi);
3209 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3210 return;
3211 }
3212 }
3213 /* Call user TxRx complete callback */
3214 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3215 hspi->TxRxCpltCallback(hspi);
3216 #else
3217 HAL_SPI_TxRxCpltCallback(hspi);
3218 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3219 }
3220
3221 /**
3222 * @brief DMA SPI half transmit process complete callback.
3223 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3224 * the configuration information for the specified DMA module.
3225 * @retval None
3226 */
SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef * hdma)3227 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
3228 {
3229 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3230
3231 /* Call user Tx half complete callback */
3232 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3233 hspi->TxHalfCpltCallback(hspi);
3234 #else
3235 HAL_SPI_TxHalfCpltCallback(hspi);
3236 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3237 }
3238
3239 /**
3240 * @brief DMA SPI half receive process complete callback
3241 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3242 * the configuration information for the specified DMA module.
3243 * @retval None
3244 */
SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef * hdma)3245 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
3246 {
3247 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3248
3249 /* Call user Rx half complete callback */
3250 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3251 hspi->RxHalfCpltCallback(hspi);
3252 #else
3253 HAL_SPI_RxHalfCpltCallback(hspi);
3254 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3255 }
3256
3257 /**
3258 * @brief DMA SPI half transmit receive process complete callback.
3259 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3260 * the configuration information for the specified DMA module.
3261 * @retval None
3262 */
SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef * hdma)3263 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
3264 {
3265 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3266
3267 /* Call user TxRx half complete callback */
3268 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3269 hspi->TxRxHalfCpltCallback(hspi);
3270 #else
3271 HAL_SPI_TxRxHalfCpltCallback(hspi);
3272 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3273 }
3274
3275 /**
3276 * @brief DMA SPI communication error callback.
3277 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3278 * the configuration information for the specified DMA module.
3279 * @retval None
3280 */
SPI_DMAError(DMA_HandleTypeDef * hdma)3281 static void SPI_DMAError(DMA_HandleTypeDef *hdma)
3282 {
3283 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3284
3285 /* Stop the disable DMA transfer on SPI side */
3286 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
3287
3288 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
3289 hspi->State = HAL_SPI_STATE_READY;
3290 /* Call user error callback */
3291 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3292 hspi->ErrorCallback(hspi);
3293 #else
3294 HAL_SPI_ErrorCallback(hspi);
3295 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3296 }
3297
3298 /**
3299 * @brief DMA SPI communication abort callback, when initiated by HAL services on Error
3300 * (To be called at end of DMA Abort procedure following error occurrence).
3301 * @param hdma DMA handle.
3302 * @retval None
3303 */
SPI_DMAAbortOnError(DMA_HandleTypeDef * hdma)3304 static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
3305 {
3306 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3307 hspi->RxXferCount = 0U;
3308 hspi->TxXferCount = 0U;
3309
3310 /* Call user error callback */
3311 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3312 hspi->ErrorCallback(hspi);
3313 #else
3314 HAL_SPI_ErrorCallback(hspi);
3315 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3316 }
3317
3318 /**
3319 * @brief DMA SPI Tx communication abort callback, when initiated by user
3320 * (To be called at end of DMA Tx Abort procedure following user abort request).
3321 * @note When this callback is executed, User Abort complete call back is called only if no
3322 * Abort still ongoing for Rx DMA Handle.
3323 * @param hdma DMA handle.
3324 * @retval None
3325 */
SPI_DMATxAbortCallback(DMA_HandleTypeDef * hdma)3326 static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
3327 {
3328 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3329
3330 hspi->hdmatx->XferAbortCallback = NULL;
3331
3332 /* Disable Tx DMA Request */
3333 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
3334
3335 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
3336 {
3337 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
3338 }
3339
3340 /* Disable SPI Peripheral */
3341 __HAL_SPI_DISABLE(hspi);
3342
3343 /* Empty the FRLVL fifo */
3344 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
3345 {
3346 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
3347 }
3348
3349 /* Check if an Abort process is still ongoing */
3350 if (hspi->hdmarx != NULL)
3351 {
3352 if (hspi->hdmarx->XferAbortCallback != NULL)
3353 {
3354 return;
3355 }
3356 }
3357
3358 /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
3359 hspi->RxXferCount = 0U;
3360 hspi->TxXferCount = 0U;
3361
3362 /* Check no error during Abort procedure */
3363 if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
3364 {
3365 /* Reset errorCode */
3366 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
3367 }
3368
3369 /* Clear the Error flags in the SR register */
3370 __HAL_SPI_CLEAR_OVRFLAG(hspi);
3371 __HAL_SPI_CLEAR_FREFLAG(hspi);
3372
3373 /* Restore hspi->State to Ready */
3374 hspi->State = HAL_SPI_STATE_READY;
3375
3376 /* Call user Abort complete callback */
3377 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3378 hspi->AbortCpltCallback(hspi);
3379 #else
3380 HAL_SPI_AbortCpltCallback(hspi);
3381 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3382 }
3383
3384 /**
3385 * @brief DMA SPI Rx communication abort callback, when initiated by user
3386 * (To be called at end of DMA Rx Abort procedure following user abort request).
3387 * @note When this callback is executed, User Abort complete call back is called only if no
3388 * Abort still ongoing for Tx DMA Handle.
3389 * @param hdma DMA handle.
3390 * @retval None
3391 */
SPI_DMARxAbortCallback(DMA_HandleTypeDef * hdma)3392 static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
3393 {
3394 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3395
3396 /* Disable SPI Peripheral */
3397 __HAL_SPI_DISABLE(hspi);
3398
3399 hspi->hdmarx->XferAbortCallback = NULL;
3400
3401 /* Disable Rx DMA Request */
3402 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
3403
3404 /* Control the BSY flag */
3405 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
3406 {
3407 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
3408 }
3409
3410 /* Empty the FRLVL fifo */
3411 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
3412 {
3413 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
3414 }
3415
3416 /* Check if an Abort process is still ongoing */
3417 if (hspi->hdmatx != NULL)
3418 {
3419 if (hspi->hdmatx->XferAbortCallback != NULL)
3420 {
3421 return;
3422 }
3423 }
3424
3425 /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
3426 hspi->RxXferCount = 0U;
3427 hspi->TxXferCount = 0U;
3428
3429 /* Check no error during Abort procedure */
3430 if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
3431 {
3432 /* Reset errorCode */
3433 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
3434 }
3435
3436 /* Clear the Error flags in the SR register */
3437 __HAL_SPI_CLEAR_OVRFLAG(hspi);
3438 __HAL_SPI_CLEAR_FREFLAG(hspi);
3439
3440 /* Restore hspi->State to Ready */
3441 hspi->State = HAL_SPI_STATE_READY;
3442
3443 /* Call user Abort complete callback */
3444 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3445 hspi->AbortCpltCallback(hspi);
3446 #else
3447 HAL_SPI_AbortCpltCallback(hspi);
3448 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3449 }
3450
3451 /**
3452 * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
3453 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3454 * the configuration information for SPI module.
3455 * @retval None
3456 */
SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef * hspi)3457 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
3458 {
3459 /* Receive data in packing mode */
3460 if (hspi->RxXferCount > 1U)
3461 {
3462 *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
3463 hspi->pRxBuffPtr += sizeof(uint16_t);
3464 hspi->RxXferCount -= 2U;
3465 if (hspi->RxXferCount == 1U)
3466 {
3467 /* Set RX Fifo threshold according the reception data length: 8bit */
3468 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
3469 }
3470 }
3471 /* Receive data in 8 Bit mode */
3472 else
3473 {
3474 *hspi->pRxBuffPtr = *((__IO uint8_t *)&hspi->Instance->DR);
3475 hspi->pRxBuffPtr++;
3476 hspi->RxXferCount--;
3477 }
3478
3479 /* Check end of the reception */
3480 if (hspi->RxXferCount == 0U)
3481 {
3482 #if (USE_SPI_CRC != 0U)
3483 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3484 {
3485 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
3486 hspi->RxISR = SPI_2linesRxISR_8BITCRC;
3487 return;
3488 }
3489 #endif /* USE_SPI_CRC */
3490
3491 /* Disable RXNE and ERR interrupt */
3492 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
3493
3494 if (hspi->TxXferCount == 0U)
3495 {
3496 SPI_CloseRxTx_ISR(hspi);
3497 }
3498 }
3499 }
3500
3501 #if (USE_SPI_CRC != 0U)
3502 /**
3503 * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
3504 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3505 * the configuration information for SPI module.
3506 * @retval None
3507 */
SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef * hspi)3508 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
3509 {
3510 /* Read 8bit CRC to flush Data Regsiter */
3511 READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
3512
3513 hspi->CRCSize--;
3514
3515 /* Check end of the reception */
3516 if (hspi->CRCSize == 0U)
3517 {
3518 /* Disable RXNE and ERR interrupt */
3519 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
3520
3521 if (hspi->TxXferCount == 0U)
3522 {
3523 SPI_CloseRxTx_ISR(hspi);
3524 }
3525 }
3526 }
3527 #endif /* USE_SPI_CRC */
3528
3529 /**
3530 * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode.
3531 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3532 * the configuration information for SPI module.
3533 * @retval None
3534 */
SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef * hspi)3535 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
3536 {
3537 /* Transmit data in packing Bit mode */
3538 if (hspi->TxXferCount >= 2U)
3539 {
3540 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
3541 hspi->pTxBuffPtr += sizeof(uint16_t);
3542 hspi->TxXferCount -= 2U;
3543 }
3544 /* Transmit data in 8 Bit mode */
3545 else
3546 {
3547 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
3548 hspi->pTxBuffPtr++;
3549 hspi->TxXferCount--;
3550 }
3551
3552 /* Check the end of the transmission */
3553 if (hspi->TxXferCount == 0U)
3554 {
3555 #if (USE_SPI_CRC != 0U)
3556 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3557 {
3558 /* Set CRC Next Bit to send CRC */
3559 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3560 /* Disable TXE interrupt */
3561 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3562 return;
3563 }
3564 #endif /* USE_SPI_CRC */
3565
3566 /* Disable TXE interrupt */
3567 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3568
3569 if (hspi->RxXferCount == 0U)
3570 {
3571 SPI_CloseRxTx_ISR(hspi);
3572 }
3573 }
3574 }
3575
3576 /**
3577 * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode.
3578 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3579 * the configuration information for SPI module.
3580 * @retval None
3581 */
SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef * hspi)3582 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
3583 {
3584 /* Receive data in 16 Bit mode */
3585 *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
3586 hspi->pRxBuffPtr += sizeof(uint16_t);
3587 hspi->RxXferCount--;
3588
3589 if (hspi->RxXferCount == 0U)
3590 {
3591 #if (USE_SPI_CRC != 0U)
3592 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3593 {
3594 hspi->RxISR = SPI_2linesRxISR_16BITCRC;
3595 return;
3596 }
3597 #endif /* USE_SPI_CRC */
3598
3599 /* Disable RXNE interrupt */
3600 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
3601
3602 if (hspi->TxXferCount == 0U)
3603 {
3604 SPI_CloseRxTx_ISR(hspi);
3605 }
3606 }
3607 }
3608
3609 #if (USE_SPI_CRC != 0U)
3610 /**
3611 * @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
3612 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3613 * the configuration information for SPI module.
3614 * @retval None
3615 */
SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef * hspi)3616 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
3617 {
3618 /* Read 16bit CRC to flush Data Regsiter */
3619 READ_REG(hspi->Instance->DR);
3620
3621 /* Disable RXNE interrupt */
3622 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
3623
3624 SPI_CloseRxTx_ISR(hspi);
3625 }
3626 #endif /* USE_SPI_CRC */
3627
3628 /**
3629 * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode.
3630 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3631 * the configuration information for SPI module.
3632 * @retval None
3633 */
SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef * hspi)3634 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
3635 {
3636 /* Transmit data in 16 Bit mode */
3637 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
3638 hspi->pTxBuffPtr += sizeof(uint16_t);
3639 hspi->TxXferCount--;
3640
3641 /* Enable CRC Transmission */
3642 if (hspi->TxXferCount == 0U)
3643 {
3644 #if (USE_SPI_CRC != 0U)
3645 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3646 {
3647 /* Set CRC Next Bit to send CRC */
3648 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3649 /* Disable TXE interrupt */
3650 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3651 return;
3652 }
3653 #endif /* USE_SPI_CRC */
3654
3655 /* Disable TXE interrupt */
3656 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3657
3658 if (hspi->RxXferCount == 0U)
3659 {
3660 SPI_CloseRxTx_ISR(hspi);
3661 }
3662 }
3663 }
3664
3665 #if (USE_SPI_CRC != 0U)
3666 /**
3667 * @brief Manage the CRC 8-bit receive in Interrupt context.
3668 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3669 * the configuration information for SPI module.
3670 * @retval None
3671 */
SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef * hspi)3672 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
3673 {
3674 /* Read 8bit CRC to flush Data Register */
3675 READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
3676
3677 hspi->CRCSize--;
3678
3679 if (hspi->CRCSize == 0U)
3680 {
3681 SPI_CloseRx_ISR(hspi);
3682 }
3683 }
3684 #endif /* USE_SPI_CRC */
3685
3686 /**
3687 * @brief Manage the receive 8-bit in Interrupt context.
3688 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3689 * the configuration information for SPI module.
3690 * @retval None
3691 */
SPI_RxISR_8BIT(struct __SPI_HandleTypeDef * hspi)3692 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
3693 {
3694 *hspi->pRxBuffPtr = (*(__IO uint8_t *)&hspi->Instance->DR);
3695 hspi->pRxBuffPtr++;
3696 hspi->RxXferCount--;
3697
3698 #if (USE_SPI_CRC != 0U)
3699 /* Enable CRC Transmission */
3700 if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
3701 {
3702 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3703 }
3704 #endif /* USE_SPI_CRC */
3705
3706 if (hspi->RxXferCount == 0U)
3707 {
3708 #if (USE_SPI_CRC != 0U)
3709 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3710 {
3711 hspi->RxISR = SPI_RxISR_8BITCRC;
3712 return;
3713 }
3714 #endif /* USE_SPI_CRC */
3715 SPI_CloseRx_ISR(hspi);
3716 }
3717 }
3718
3719 #if (USE_SPI_CRC != 0U)
3720 /**
3721 * @brief Manage the CRC 16-bit receive in Interrupt context.
3722 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3723 * the configuration information for SPI module.
3724 * @retval None
3725 */
SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef * hspi)3726 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
3727 {
3728 /* Read 16bit CRC to flush Data Register */
3729 READ_REG(hspi->Instance->DR);
3730
3731 /* Disable RXNE and ERR interrupt */
3732 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
3733
3734 SPI_CloseRx_ISR(hspi);
3735 }
3736 #endif /* USE_SPI_CRC */
3737
3738 /**
3739 * @brief Manage the 16-bit receive in Interrupt context.
3740 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3741 * the configuration information for SPI module.
3742 * @retval None
3743 */
SPI_RxISR_16BIT(struct __SPI_HandleTypeDef * hspi)3744 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
3745 {
3746 *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
3747 hspi->pRxBuffPtr += sizeof(uint16_t);
3748 hspi->RxXferCount--;
3749
3750 #if (USE_SPI_CRC != 0U)
3751 /* Enable CRC Transmission */
3752 if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
3753 {
3754 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3755 }
3756 #endif /* USE_SPI_CRC */
3757
3758 if (hspi->RxXferCount == 0U)
3759 {
3760 #if (USE_SPI_CRC != 0U)
3761 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3762 {
3763 hspi->RxISR = SPI_RxISR_16BITCRC;
3764 return;
3765 }
3766 #endif /* USE_SPI_CRC */
3767 SPI_CloseRx_ISR(hspi);
3768 }
3769 }
3770
3771 /**
3772 * @brief Handle the data 8-bit transmit in Interrupt mode.
3773 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3774 * the configuration information for SPI module.
3775 * @retval None
3776 */
SPI_TxISR_8BIT(struct __SPI_HandleTypeDef * hspi)3777 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
3778 {
3779 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
3780 hspi->pTxBuffPtr++;
3781 hspi->TxXferCount--;
3782
3783 if (hspi->TxXferCount == 0U)
3784 {
3785 #if (USE_SPI_CRC != 0U)
3786 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3787 {
3788 /* Enable CRC Transmission */
3789 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3790 }
3791 #endif /* USE_SPI_CRC */
3792 SPI_CloseTx_ISR(hspi);
3793 }
3794 }
3795
3796 /**
3797 * @brief Handle the data 16-bit transmit in Interrupt mode.
3798 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3799 * the configuration information for SPI module.
3800 * @retval None
3801 */
SPI_TxISR_16BIT(struct __SPI_HandleTypeDef * hspi)3802 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
3803 {
3804 /* Transmit data in 16 Bit mode */
3805 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
3806 hspi->pTxBuffPtr += sizeof(uint16_t);
3807 hspi->TxXferCount--;
3808
3809 if (hspi->TxXferCount == 0U)
3810 {
3811 #if (USE_SPI_CRC != 0U)
3812 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3813 {
3814 /* Enable CRC Transmission */
3815 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3816 }
3817 #endif /* USE_SPI_CRC */
3818 SPI_CloseTx_ISR(hspi);
3819 }
3820 }
3821
3822 /**
3823 * @brief Handle SPI Communication Timeout.
3824 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3825 * the configuration information for SPI module.
3826 * @param Flag SPI flag to check
3827 * @param State flag state to check
3828 * @param Timeout Timeout duration
3829 * @param Tickstart tick start value
3830 * @retval HAL status
3831 */
SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef * hspi,uint32_t Flag,FlagStatus State,uint32_t Timeout,uint32_t Tickstart)3832 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
3833 uint32_t Timeout, uint32_t Tickstart)
3834 {
3835 while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
3836 {
3837 if (Timeout != HAL_MAX_DELAY)
3838 {
3839 if (((HAL_GetTick() - Tickstart) >= Timeout) || (Timeout == 0U))
3840 {
3841 /* Disable the SPI and reset the CRC: the CRC value should be cleared
3842 on both master and slave sides in order to resynchronize the master
3843 and slave for their respective CRC calculation */
3844
3845 /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
3846 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
3847
3848 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
3849 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
3850 {
3851 /* Disable SPI peripheral */
3852 __HAL_SPI_DISABLE(hspi);
3853 }
3854
3855 /* Reset CRC Calculation */
3856 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3857 {
3858 SPI_RESET_CRC(hspi);
3859 }
3860
3861 hspi->State = HAL_SPI_STATE_READY;
3862
3863 /* Process Unlocked */
3864 __HAL_UNLOCK(hspi);
3865
3866 return HAL_TIMEOUT;
3867 }
3868 }
3869 }
3870
3871 return HAL_OK;
3872 }
3873
3874 /**
3875 * @brief Handle SPI FIFO Communication Timeout.
3876 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3877 * the configuration information for SPI module.
3878 * @param Fifo Fifo to check
3879 * @param State Fifo state to check
3880 * @param Timeout Timeout duration
3881 * @param Tickstart tick start value
3882 * @retval HAL status
3883 */
SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef * hspi,uint32_t Fifo,uint32_t State,uint32_t Timeout,uint32_t Tickstart)3884 static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
3885 uint32_t Timeout, uint32_t Tickstart)
3886 {
3887 while ((hspi->Instance->SR & Fifo) != State)
3888 {
3889 if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
3890 {
3891 /* Read 8bit CRC to flush Data Register */
3892 READ_REG(*((__IO uint8_t *)&hspi->Instance->DR));
3893 }
3894
3895 if (Timeout != HAL_MAX_DELAY)
3896 {
3897 if (((HAL_GetTick() - Tickstart) >= Timeout) || (Timeout == 0U))
3898 {
3899 /* Disable the SPI and reset the CRC: the CRC value should be cleared
3900 on both master and slave sides in order to resynchronize the master
3901 and slave for their respective CRC calculation */
3902
3903 /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
3904 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
3905
3906 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
3907 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
3908 {
3909 /* Disable SPI peripheral */
3910 __HAL_SPI_DISABLE(hspi);
3911 }
3912
3913 /* Reset CRC Calculation */
3914 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3915 {
3916 SPI_RESET_CRC(hspi);
3917 }
3918
3919 hspi->State = HAL_SPI_STATE_READY;
3920
3921 /* Process Unlocked */
3922 __HAL_UNLOCK(hspi);
3923
3924 return HAL_TIMEOUT;
3925 }
3926 }
3927 }
3928
3929 return HAL_OK;
3930 }
3931
3932 /**
3933 * @brief Handle the check of the RX transaction complete.
3934 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3935 * the configuration information for SPI module.
3936 * @param Timeout Timeout duration
3937 * @param Tickstart tick start value
3938 * @retval HAL status
3939 */
SPI_EndRxTransaction(SPI_HandleTypeDef * hspi,uint32_t Timeout,uint32_t Tickstart)3940 static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
3941 {
3942 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
3943 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
3944 {
3945 /* Disable SPI peripheral */
3946 __HAL_SPI_DISABLE(hspi);
3947 }
3948
3949 /* Control the BSY flag */
3950 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
3951 {
3952 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3953 return HAL_TIMEOUT;
3954 }
3955
3956 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
3957 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
3958 {
3959 /* Empty the FRLVL fifo */
3960 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
3961 {
3962 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3963 return HAL_TIMEOUT;
3964 }
3965 }
3966 return HAL_OK;
3967 }
3968
3969 /**
3970 * @brief Handle the check of the RXTX or TX transaction complete.
3971 * @param hspi SPI handle
3972 * @param Timeout Timeout duration
3973 * @param Tickstart tick start value
3974 * @retval HAL status
3975 */
SPI_EndRxTxTransaction(SPI_HandleTypeDef * hspi,uint32_t Timeout,uint32_t Tickstart)3976 static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
3977 {
3978 /* Control if the TX fifo is empty */
3979 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
3980 {
3981 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3982 return HAL_TIMEOUT;
3983 }
3984
3985 /* Control the BSY flag */
3986 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
3987 {
3988 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3989 return HAL_TIMEOUT;
3990 }
3991
3992 /* Control if the RX fifo is empty */
3993 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
3994 {
3995 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3996 return HAL_TIMEOUT;
3997 }
3998
3999 return HAL_OK;
4000 }
4001
4002 /**
4003 * @brief Handle the end of the RXTX transaction.
4004 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
4005 * the configuration information for SPI module.
4006 * @retval None
4007 */
SPI_CloseRxTx_ISR(SPI_HandleTypeDef * hspi)4008 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
4009 {
4010 uint32_t tickstart;
4011
4012 /* Init tickstart for timeout managment*/
4013 tickstart = HAL_GetTick();
4014
4015 /* Disable ERR interrupt */
4016 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
4017
4018 /* Check the end of the transaction */
4019 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
4020 {
4021 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4022 }
4023
4024 #if (USE_SPI_CRC != 0U)
4025 /* Check if CRC error occurred */
4026 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
4027 {
4028 hspi->State = HAL_SPI_STATE_READY;
4029 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
4030 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
4031 /* Call user error callback */
4032 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4033 hspi->ErrorCallback(hspi);
4034 #else
4035 HAL_SPI_ErrorCallback(hspi);
4036 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4037 }
4038 else
4039 {
4040 #endif /* USE_SPI_CRC */
4041 if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
4042 {
4043 if (hspi->State == HAL_SPI_STATE_BUSY_RX)
4044 {
4045 hspi->State = HAL_SPI_STATE_READY;
4046 /* Call user Rx complete callback */
4047 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4048 hspi->RxCpltCallback(hspi);
4049 #else
4050 HAL_SPI_RxCpltCallback(hspi);
4051 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4052 }
4053 else
4054 {
4055 hspi->State = HAL_SPI_STATE_READY;
4056 /* Call user TxRx complete callback */
4057 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4058 hspi->TxRxCpltCallback(hspi);
4059 #else
4060 HAL_SPI_TxRxCpltCallback(hspi);
4061 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4062 }
4063 }
4064 else
4065 {
4066 hspi->State = HAL_SPI_STATE_READY;
4067 /* Call user error callback */
4068 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4069 hspi->ErrorCallback(hspi);
4070 #else
4071 HAL_SPI_ErrorCallback(hspi);
4072 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4073 }
4074 #if (USE_SPI_CRC != 0U)
4075 }
4076 #endif /* USE_SPI_CRC */
4077 }
4078
4079 /**
4080 * @brief Handle the end of the RX transaction.
4081 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
4082 * the configuration information for SPI module.
4083 * @retval None
4084 */
SPI_CloseRx_ISR(SPI_HandleTypeDef * hspi)4085 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
4086 {
4087 /* Disable RXNE and ERR interrupt */
4088 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
4089
4090 /* Check the end of the transaction */
4091 if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4092 {
4093 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4094 }
4095 hspi->State = HAL_SPI_STATE_READY;
4096
4097 #if (USE_SPI_CRC != 0U)
4098 /* Check if CRC error occurred */
4099 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
4100 {
4101 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
4102 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
4103 /* Call user error callback */
4104 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4105 hspi->ErrorCallback(hspi);
4106 #else
4107 HAL_SPI_ErrorCallback(hspi);
4108 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4109 }
4110 else
4111 {
4112 #endif /* USE_SPI_CRC */
4113 if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
4114 {
4115 /* Call user Rx complete callback */
4116 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4117 hspi->RxCpltCallback(hspi);
4118 #else
4119 HAL_SPI_RxCpltCallback(hspi);
4120 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4121 }
4122 else
4123 {
4124 /* Call user error callback */
4125 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4126 hspi->ErrorCallback(hspi);
4127 #else
4128 HAL_SPI_ErrorCallback(hspi);
4129 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4130 }
4131 #if (USE_SPI_CRC != 0U)
4132 }
4133 #endif /* USE_SPI_CRC */
4134 }
4135
4136 /**
4137 * @brief Handle the end of the TX transaction.
4138 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
4139 * the configuration information for SPI module.
4140 * @retval None
4141 */
SPI_CloseTx_ISR(SPI_HandleTypeDef * hspi)4142 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
4143 {
4144 uint32_t tickstart;
4145
4146 /* Init tickstart for timeout management*/
4147 tickstart = HAL_GetTick();
4148
4149 /* Disable TXE and ERR interrupt */
4150 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
4151
4152 /* Check the end of the transaction */
4153 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
4154 {
4155 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4156 }
4157
4158 /* Clear overrun flag in 2 Lines communication mode because received is not read */
4159 if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
4160 {
4161 __HAL_SPI_CLEAR_OVRFLAG(hspi);
4162 }
4163
4164 hspi->State = HAL_SPI_STATE_READY;
4165 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
4166 {
4167 /* Call user error callback */
4168 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4169 hspi->ErrorCallback(hspi);
4170 #else
4171 HAL_SPI_ErrorCallback(hspi);
4172 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4173 }
4174 else
4175 {
4176 /* Call user Rx complete callback */
4177 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4178 hspi->TxCpltCallback(hspi);
4179 #else
4180 HAL_SPI_TxCpltCallback(hspi);
4181 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4182 }
4183 }
4184
4185 /**
4186 * @brief Handle abort a Rx transaction.
4187 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
4188 * the configuration information for SPI module.
4189 * @retval None
4190 */
SPI_AbortRx_ISR(SPI_HandleTypeDef * hspi)4191 static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
4192 {
4193 __IO uint32_t count;
4194
4195 /* Disable SPI Peripheral */
4196 __HAL_SPI_DISABLE(hspi);
4197
4198 count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
4199
4200 /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
4201 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));
4202
4203 /* Check RXNEIE is disabled */
4204 do
4205 {
4206 if (count == 0U)
4207 {
4208 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
4209 break;
4210 }
4211 count--;
4212 }
4213 while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
4214
4215 /* Control the BSY flag */
4216 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4217 {
4218 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4219 }
4220
4221 /* Empty the FRLVL fifo */
4222 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4223 {
4224 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4225 }
4226
4227 hspi->State = HAL_SPI_STATE_ABORT;
4228 }
4229
4230 /**
4231 * @brief Handle abort a Tx or Rx/Tx transaction.
4232 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
4233 * the configuration information for SPI module.
4234 * @retval None
4235 */
SPI_AbortTx_ISR(SPI_HandleTypeDef * hspi)4236 static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)
4237 {
4238 __IO uint32_t count;
4239
4240 count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
4241
4242 /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
4243 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));
4244
4245 /* Check TXEIE is disabled */
4246 do
4247 {
4248 if (count == 0U)
4249 {
4250 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
4251 break;
4252 }
4253 count--;
4254 }
4255 while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE));
4256
4257 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4258 {
4259 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4260 }
4261
4262 /* Disable SPI Peripheral */
4263 __HAL_SPI_DISABLE(hspi);
4264
4265 /* Empty the FRLVL fifo */
4266 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4267 {
4268 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4269 }
4270
4271 hspi->State = HAL_SPI_STATE_ABORT;
4272 }
4273
4274 /**
4275 * @}
4276 */
4277
4278 #endif /* HAL_SPI_MODULE_ENABLED */
4279
4280 /**
4281 * @}
4282 */
4283
4284 /**
4285 * @}
4286 */
4287
4288 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
4289
