1 /**
2 ******************************************************************************
3 * @file stm32l4xx_hal_pwr_ex.c
4 * @author MCD Application Team
5 * @brief Extended PWR HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Power Controller (PWR) peripheral:
8 * + Extended Initialization and de-initialization functions
9 * + Extended Peripheral Control functions
10 *
11 ******************************************************************************
12 * @attention
13 *
14 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
15 *
16 * Redistribution and use in source and binary forms, with or without modification,
17 * are permitted provided that the following conditions are met:
18 * 1. Redistributions of source code must retain the above copyright notice,
19 * this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright notice,
21 * this list of conditions and the following disclaimer in the documentation
22 * and/or other materials provided with the distribution.
23 * 3. Neither the name of STMicroelectronics nor the names of its contributors
24 * may be used to endorse or promote products derived from this software
25 * without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
28 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
30 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
33 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
34 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
35 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 *
38 ******************************************************************************
39 */
40
41 /* Includes ------------------------------------------------------------------*/
42 #include "stm32l4xx_hal.h"
43
44 /** @addtogroup STM32L4xx_HAL_Driver
45 * @{
46 */
47
48 /** @defgroup PWREx PWREx
49 * @brief PWR Extended HAL module driver
50 * @{
51 */
52
53 #ifdef HAL_PWR_MODULE_ENABLED
54
55 /* Private typedef -----------------------------------------------------------*/
56 /* Private define ------------------------------------------------------------*/
57
58 #if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
59 #define PWR_PORTH_AVAILABLE_PINS ((uint32_t)0x0000000B) /* PH0/PH1/PH3 */
60 #elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
61 #define PWR_PORTH_AVAILABLE_PINS ((uint32_t)0x0000000B) /* PH0/PH1/PH3 */
62 #elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
63 #define PWR_PORTH_AVAILABLE_PINS ((uint32_t)0x00000003) /* PH0/PH1 */
64 #elif defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
65 #define PWR_PORTH_AVAILABLE_PINS ((uint32_t)0x0000FFFF) /* PH0..PH15 */
66 #endif
67
68 #if defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
69 #define PWR_PORTI_AVAILABLE_PINS ((uint32_t)0x00000FFF) /* PI0..PI11 */
70 #endif
71
72 /** @defgroup PWR_Extended_Private_Defines PWR Extended Private Defines
73 * @{
74 */
75
76 /** @defgroup PWREx_PVM_Mode_Mask PWR PVM Mode Mask
77 * @{
78 */
79 #define PVM_MODE_IT ((uint32_t)0x00010000) /*!< Mask for interruption yielded by PVM threshold crossing */
80 #define PVM_MODE_EVT ((uint32_t)0x00020000) /*!< Mask for event yielded by PVM threshold crossing */
81 #define PVM_RISING_EDGE ((uint32_t)0x00000001) /*!< Mask for rising edge set as PVM trigger */
82 #define PVM_FALLING_EDGE ((uint32_t)0x00000002) /*!< Mask for falling edge set as PVM trigger */
83 /**
84 * @}
85 */
86
87 /** @defgroup PWREx_TimeOut_Value PWR Extended Flag Setting Time Out Value
88 * @{
89 */
90 #define PWR_FLAG_SETTING_DELAY_US 50UL /*!< Time out value for REGLPF and VOSF flags setting */
91 /**
92 * @}
93 */
94
95
96
97 /**
98 * @}
99 */
100
101
102
103 /* Private macro -------------------------------------------------------------*/
104 /* Private variables ---------------------------------------------------------*/
105 /* Private function prototypes -----------------------------------------------*/
106 /* Exported functions --------------------------------------------------------*/
107
108 /** @defgroup PWREx_Exported_Functions PWR Extended Exported Functions
109 * @{
110 */
111
112 /** @defgroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions
113 * @brief Extended Peripheral Control functions
114 *
115 @verbatim
116 ===============================================================================
117 ##### Extended Peripheral Initialization and de-initialization functions #####
118 ===============================================================================
119 [..]
120
121 @endverbatim
122 * @{
123 */
124
125
126 /**
127 * @brief Return Voltage Scaling Range.
128 * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_RANGE1 or PWR_REGULATOR_VOLTAGE_RANGE2
129 * or PWR_REGULATOR_VOLTAGE_SCALE1_BOOST when applicable)
130 */
HAL_PWREx_GetVoltageRange(void)131 uint32_t HAL_PWREx_GetVoltageRange(void)
132 {
133 #if defined(PWR_CR5_R1MODE)
134 if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2)
135 {
136 return PWR_REGULATOR_VOLTAGE_SCALE2;
137 }
138 else if (READ_BIT(PWR->CR5, PWR_CR5_R1MODE) == PWR_CR5_R1MODE)
139 {
140 /* PWR_CR5_R1MODE bit set means that Range 1 Boost is disabled */
141 return PWR_REGULATOR_VOLTAGE_SCALE1;
142 }
143 else
144 {
145 return PWR_REGULATOR_VOLTAGE_SCALE1_BOOST;
146 }
147 #else
148 return (PWR->CR1 & PWR_CR1_VOS);
149 #endif
150 }
151
152
153
154 /**
155 * @brief Configure the main internal regulator output voltage.
156 * @param VoltageScaling: specifies the regulator output voltage to achieve
157 * a tradeoff between performance and power consumption.
158 * This parameter can be one of the following values:
159 @if STM32L4S9xx
160 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1_BOOST when available, Regulator voltage output range 1 boost mode,
161 * typical output voltage at 1.2 V,
162 * system frequency up to 120 MHz.
163 @endif
164 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode,
165 * typical output voltage at 1.2 V,
166 * system frequency up to 80 MHz.
167 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode,
168 * typical output voltage at 1.0 V,
169 * system frequency up to 26 MHz.
170 * @note When moving from Range 1 to Range 2, the system frequency must be decreased to
171 * a value below 26 MHz before calling HAL_PWREx_ControlVoltageScaling() API.
172 * When moving from Range 2 to Range 1, the system frequency can be increased to
173 * a value up to 80 MHz after calling HAL_PWREx_ControlVoltageScaling() API. For
174 * some devices, the system frequency can be increased up to 120 MHz.
175 * @note When moving from Range 2 to Range 1, the API waits for VOSF flag to be
176 * cleared before returning the status. If the flag is not cleared within
177 * 50 microseconds, HAL_TIMEOUT status is reported.
178 * @retval HAL Status
179 */
HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)180 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
181 {
182 uint32_t wait_loop_index;
183
184 assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
185
186 #if defined(PWR_CR5_R1MODE)
187 if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1_BOOST)
188 {
189 /* If current range is range 2 */
190 if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2)
191 {
192 /* Make sure Range 1 Boost is enabled */
193 CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE);
194
195 /* Set Range 1 */
196 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
197
198 /* Wait until VOSF is cleared */
199 wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1;
200 while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
201 {
202 wait_loop_index--;
203 }
204 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
205 {
206 return HAL_TIMEOUT;
207 }
208 }
209 /* If current range is range 1 normal or boost mode */
210 else
211 {
212 /* Enable Range 1 Boost (no issue if bit already reset) */
213 CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE);
214 }
215 }
216 else if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1)
217 {
218 /* If current range is range 2 */
219 if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2)
220 {
221 /* Make sure Range 1 Boost is disabled */
222 SET_BIT(PWR->CR5, PWR_CR5_R1MODE);
223
224 /* Set Range 1 */
225 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
226
227 /* Wait until VOSF is cleared */
228 wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1;
229 while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
230 {
231 wait_loop_index--;
232 }
233 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
234 {
235 return HAL_TIMEOUT;
236 }
237 }
238 /* If current range is range 1 normal or boost mode */
239 else
240 {
241 /* Disable Range 1 Boost (no issue if bit already set) */
242 SET_BIT(PWR->CR5, PWR_CR5_R1MODE);
243 }
244 }
245 else
246 {
247 /* Set Range 2 */
248 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2);
249 /* No need to wait for VOSF to be cleared for this transition */
250 /* PWR_CR5_R1MODE bit setting has no effect in Range 2 */
251 }
252
253 #else
254
255 /* If Set Range 1 */
256 if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1)
257 {
258 if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE1)
259 {
260 /* Set Range 1 */
261 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
262
263 /* Wait until VOSF is cleared */
264 wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U;
265 while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
266 {
267 wait_loop_index--;
268 }
269 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
270 {
271 return HAL_TIMEOUT;
272 }
273 }
274 }
275 else
276 {
277 if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE2)
278 {
279 /* Set Range 2 */
280 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2);
281 /* No need to wait for VOSF to be cleared for this transition */
282 }
283 }
284 #endif
285
286 return HAL_OK;
287 }
288
289
290 /**
291 * @brief Enable battery charging.
292 * When VDD is present, charge the external battery on VBAT thru an internal resistor.
293 * @param ResistorSelection: specifies the resistor impedance.
294 * This parameter can be one of the following values:
295 * @arg @ref PWR_BATTERY_CHARGING_RESISTOR_5 5 kOhms resistor
296 * @arg @ref PWR_BATTERY_CHARGING_RESISTOR_1_5 1.5 kOhms resistor
297 * @retval None
298 */
HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection)299 void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection)
300 {
301 assert_param(IS_PWR_BATTERY_RESISTOR_SELECT(ResistorSelection));
302
303 /* Specify resistor selection */
304 MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, ResistorSelection);
305
306 /* Enable battery charging */
307 SET_BIT(PWR->CR4, PWR_CR4_VBE);
308 }
309
310
311 /**
312 * @brief Disable battery charging.
313 * @retval None
314 */
HAL_PWREx_DisableBatteryCharging(void)315 void HAL_PWREx_DisableBatteryCharging(void)
316 {
317 CLEAR_BIT(PWR->CR4, PWR_CR4_VBE);
318 }
319
320
321 #if defined(PWR_CR2_USV)
322 /**
323 * @brief Enable VDDUSB supply.
324 * @note Remove VDDUSB electrical and logical isolation, once VDDUSB supply is present.
325 * @retval None
326 */
HAL_PWREx_EnableVddUSB(void)327 void HAL_PWREx_EnableVddUSB(void)
328 {
329 SET_BIT(PWR->CR2, PWR_CR2_USV);
330 }
331
332
333 /**
334 * @brief Disable VDDUSB supply.
335 * @retval None
336 */
HAL_PWREx_DisableVddUSB(void)337 void HAL_PWREx_DisableVddUSB(void)
338 {
339 CLEAR_BIT(PWR->CR2, PWR_CR2_USV);
340 }
341 #endif /* PWR_CR2_USV */
342
343 #if defined(PWR_CR2_IOSV)
344 /**
345 * @brief Enable VDDIO2 supply.
346 * @note Remove VDDIO2 electrical and logical isolation, once VDDIO2 supply is present.
347 * @retval None
348 */
HAL_PWREx_EnableVddIO2(void)349 void HAL_PWREx_EnableVddIO2(void)
350 {
351 SET_BIT(PWR->CR2, PWR_CR2_IOSV);
352 }
353
354
355 /**
356 * @brief Disable VDDIO2 supply.
357 * @retval None
358 */
HAL_PWREx_DisableVddIO2(void)359 void HAL_PWREx_DisableVddIO2(void)
360 {
361 CLEAR_BIT(PWR->CR2, PWR_CR2_IOSV);
362 }
363 #endif /* PWR_CR2_IOSV */
364
365
366 /**
367 * @brief Enable Internal Wake-up Line.
368 * @retval None
369 */
HAL_PWREx_EnableInternalWakeUpLine(void)370 void HAL_PWREx_EnableInternalWakeUpLine(void)
371 {
372 SET_BIT(PWR->CR3, PWR_CR3_EIWF);
373 }
374
375
376 /**
377 * @brief Disable Internal Wake-up Line.
378 * @retval None
379 */
HAL_PWREx_DisableInternalWakeUpLine(void)380 void HAL_PWREx_DisableInternalWakeUpLine(void)
381 {
382 CLEAR_BIT(PWR->CR3, PWR_CR3_EIWF);
383 }
384
385
386
387 /**
388 * @brief Enable GPIO pull-up state in Standby and Shutdown modes.
389 * @note Set the relevant PUy bits of PWR_PUCRx register to configure the I/O in
390 * pull-up state in Standby and Shutdown modes.
391 * @note This state is effective in Standby and Shutdown modes only if APC bit
392 * is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
393 * @note The configuration is lost when exiting the Shutdown mode due to the
394 * power-on reset, maintained when exiting the Standby mode.
395 * @note To avoid any conflict at Standby and Shutdown modes exits, the corresponding
396 * PDy bit of PWR_PDCRx register is cleared unless it is reserved.
397 * @note Even if a PUy bit to set is reserved, the other PUy bits entered as input
398 * parameter at the same time are set.
399 * @param GPIO: Specify the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H
400 * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.
401 * @param GPIONumber: Specify the I/O pins numbers.
402 * This parameter can be one of the following values:
403 * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less
404 * I/O pins are available) or the logical OR of several of them to set
405 * several bits for a given port in a single API call.
406 * @retval HAL Status
407 */
HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO,uint32_t GPIONumber)408 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
409 {
410 HAL_StatusTypeDef status = HAL_OK;
411
412 assert_param(IS_PWR_GPIO(GPIO));
413 assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
414
415 switch (GPIO)
416 {
417 case PWR_GPIO_A:
418 SET_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));
419 CLEAR_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15))));
420 break;
421 case PWR_GPIO_B:
422 SET_BIT(PWR->PUCRB, GPIONumber);
423 CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));
424 break;
425 case PWR_GPIO_C:
426 SET_BIT(PWR->PUCRC, GPIONumber);
427 CLEAR_BIT(PWR->PDCRC, GPIONumber);
428 break;
429 #if defined(GPIOD)
430 case PWR_GPIO_D:
431 SET_BIT(PWR->PUCRD, GPIONumber);
432 CLEAR_BIT(PWR->PDCRD, GPIONumber);
433 break;
434 #endif
435 #if defined(GPIOE)
436 case PWR_GPIO_E:
437 SET_BIT(PWR->PUCRE, GPIONumber);
438 CLEAR_BIT(PWR->PDCRE, GPIONumber);
439 break;
440 #endif
441 #if defined(GPIOF)
442 case PWR_GPIO_F:
443 SET_BIT(PWR->PUCRF, GPIONumber);
444 CLEAR_BIT(PWR->PDCRF, GPIONumber);
445 break;
446 #endif
447 #if defined(GPIOG)
448 case PWR_GPIO_G:
449 SET_BIT(PWR->PUCRG, GPIONumber);
450 CLEAR_BIT(PWR->PDCRG, GPIONumber);
451 break;
452 #endif
453 case PWR_GPIO_H:
454 SET_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
455 #if defined (STM32L496xx) || defined (STM32L4A6xx)
456 CLEAR_BIT(PWR->PDCRH, ((GPIONumber & PWR_PORTH_AVAILABLE_PINS) & (~(PWR_GPIO_BIT_3))));
457 #else
458 CLEAR_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
459 #endif
460 break;
461 #if defined(GPIOI)
462 case PWR_GPIO_I:
463 SET_BIT(PWR->PUCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS));
464 CLEAR_BIT(PWR->PDCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS));
465 break;
466 #endif
467 default:
468 status = HAL_ERROR;
469 break;
470 }
471
472 return status;
473 }
474
475
476 /**
477 * @brief Disable GPIO pull-up state in Standby mode and Shutdown modes.
478 * @note Reset the relevant PUy bits of PWR_PUCRx register used to configure the I/O
479 * in pull-up state in Standby and Shutdown modes.
480 * @note Even if a PUy bit to reset is reserved, the other PUy bits entered as input
481 * parameter at the same time are reset.
482 * @param GPIO: Specifies the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H
483 * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.
484 * @param GPIONumber: Specify the I/O pins numbers.
485 * This parameter can be one of the following values:
486 * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less
487 * I/O pins are available) or the logical OR of several of them to reset
488 * several bits for a given port in a single API call.
489 * @retval HAL Status
490 */
HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO,uint32_t GPIONumber)491 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
492 {
493 HAL_StatusTypeDef status = HAL_OK;
494
495 assert_param(IS_PWR_GPIO(GPIO));
496 assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
497
498 switch (GPIO)
499 {
500 case PWR_GPIO_A:
501 CLEAR_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));
502 break;
503 case PWR_GPIO_B:
504 CLEAR_BIT(PWR->PUCRB, GPIONumber);
505 break;
506 case PWR_GPIO_C:
507 CLEAR_BIT(PWR->PUCRC, GPIONumber);
508 break;
509 #if defined(GPIOD)
510 case PWR_GPIO_D:
511 CLEAR_BIT(PWR->PUCRD, GPIONumber);
512 break;
513 #endif
514 #if defined(GPIOE)
515 case PWR_GPIO_E:
516 CLEAR_BIT(PWR->PUCRE, GPIONumber);
517 break;
518 #endif
519 #if defined(GPIOF)
520 case PWR_GPIO_F:
521 CLEAR_BIT(PWR->PUCRF, GPIONumber);
522 break;
523 #endif
524 #if defined(GPIOG)
525 case PWR_GPIO_G:
526 CLEAR_BIT(PWR->PUCRG, GPIONumber);
527 break;
528 #endif
529 case PWR_GPIO_H:
530 CLEAR_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
531 break;
532 #if defined(GPIOI)
533 case PWR_GPIO_I:
534 CLEAR_BIT(PWR->PUCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS));
535 break;
536 #endif
537 default:
538 status = HAL_ERROR;
539 break;
540 }
541
542 return status;
543 }
544
545
546
547 /**
548 * @brief Enable GPIO pull-down state in Standby and Shutdown modes.
549 * @note Set the relevant PDy bits of PWR_PDCRx register to configure the I/O in
550 * pull-down state in Standby and Shutdown modes.
551 * @note This state is effective in Standby and Shutdown modes only if APC bit
552 * is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
553 * @note The configuration is lost when exiting the Shutdown mode due to the
554 * power-on reset, maintained when exiting the Standby mode.
555 * @note To avoid any conflict at Standby and Shutdown modes exits, the corresponding
556 * PUy bit of PWR_PUCRx register is cleared unless it is reserved.
557 * @note Even if a PDy bit to set is reserved, the other PDy bits entered as input
558 * parameter at the same time are set.
559 * @param GPIO: Specify the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H
560 * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.
561 * @param GPIONumber: Specify the I/O pins numbers.
562 * This parameter can be one of the following values:
563 * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less
564 * I/O pins are available) or the logical OR of several of them to set
565 * several bits for a given port in a single API call.
566 * @retval HAL Status
567 */
HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO,uint32_t GPIONumber)568 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
569 {
570 HAL_StatusTypeDef status = HAL_OK;
571
572 assert_param(IS_PWR_GPIO(GPIO));
573 assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
574
575 switch (GPIO)
576 {
577 case PWR_GPIO_A:
578 SET_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15))));
579 CLEAR_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));
580 break;
581 case PWR_GPIO_B:
582 SET_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));
583 CLEAR_BIT(PWR->PUCRB, GPIONumber);
584 break;
585 case PWR_GPIO_C:
586 SET_BIT(PWR->PDCRC, GPIONumber);
587 CLEAR_BIT(PWR->PUCRC, GPIONumber);
588 break;
589 #if defined(GPIOD)
590 case PWR_GPIO_D:
591 SET_BIT(PWR->PDCRD, GPIONumber);
592 CLEAR_BIT(PWR->PUCRD, GPIONumber);
593 break;
594 #endif
595 #if defined(GPIOE)
596 case PWR_GPIO_E:
597 SET_BIT(PWR->PDCRE, GPIONumber);
598 CLEAR_BIT(PWR->PUCRE, GPIONumber);
599 break;
600 #endif
601 #if defined(GPIOF)
602 case PWR_GPIO_F:
603 SET_BIT(PWR->PDCRF, GPIONumber);
604 CLEAR_BIT(PWR->PUCRF, GPIONumber);
605 break;
606 #endif
607 #if defined(GPIOG)
608 case PWR_GPIO_G:
609 SET_BIT(PWR->PDCRG, GPIONumber);
610 CLEAR_BIT(PWR->PUCRG, GPIONumber);
611 break;
612 #endif
613 case PWR_GPIO_H:
614 #if defined (STM32L496xx) || defined (STM32L4A6xx)
615 SET_BIT(PWR->PDCRH, ((GPIONumber & PWR_PORTH_AVAILABLE_PINS) & (~(PWR_GPIO_BIT_3))));
616 #else
617 SET_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
618 #endif
619 CLEAR_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
620 break;
621 #if defined(GPIOI)
622 case PWR_GPIO_I:
623 SET_BIT(PWR->PDCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS));
624 CLEAR_BIT(PWR->PUCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS));
625 break;
626 #endif
627 default:
628 status = HAL_ERROR;
629 break;
630 }
631
632 return status;
633 }
634
635
636 /**
637 * @brief Disable GPIO pull-down state in Standby and Shutdown modes.
638 * @note Reset the relevant PDy bits of PWR_PDCRx register used to configure the I/O
639 * in pull-down state in Standby and Shutdown modes.
640 * @note Even if a PDy bit to reset is reserved, the other PDy bits entered as input
641 * parameter at the same time are reset.
642 * @param GPIO: Specifies the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H
643 * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.
644 * @param GPIONumber: Specify the I/O pins numbers.
645 * This parameter can be one of the following values:
646 * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less
647 * I/O pins are available) or the logical OR of several of them to reset
648 * several bits for a given port in a single API call.
649 * @retval HAL Status
650 */
HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO,uint32_t GPIONumber)651 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
652 {
653 HAL_StatusTypeDef status = HAL_OK;
654
655 assert_param(IS_PWR_GPIO(GPIO));
656 assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
657
658 switch (GPIO)
659 {
660 case PWR_GPIO_A:
661 CLEAR_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15))));
662 break;
663 case PWR_GPIO_B:
664 CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));
665 break;
666 case PWR_GPIO_C:
667 CLEAR_BIT(PWR->PDCRC, GPIONumber);
668 break;
669 #if defined(GPIOD)
670 case PWR_GPIO_D:
671 CLEAR_BIT(PWR->PDCRD, GPIONumber);
672 break;
673 #endif
674 #if defined(GPIOE)
675 case PWR_GPIO_E:
676 CLEAR_BIT(PWR->PDCRE, GPIONumber);
677 break;
678 #endif
679 #if defined(GPIOF)
680 case PWR_GPIO_F:
681 CLEAR_BIT(PWR->PDCRF, GPIONumber);
682 break;
683 #endif
684 #if defined(GPIOG)
685 case PWR_GPIO_G:
686 CLEAR_BIT(PWR->PDCRG, GPIONumber);
687 break;
688 #endif
689 case PWR_GPIO_H:
690 #if defined (STM32L496xx) || defined (STM32L4A6xx)
691 CLEAR_BIT(PWR->PDCRH, ((GPIONumber & PWR_PORTH_AVAILABLE_PINS) & (~(PWR_GPIO_BIT_3))));
692 #else
693 CLEAR_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
694 #endif
695 break;
696 #if defined(GPIOI)
697 case PWR_GPIO_I:
698 CLEAR_BIT(PWR->PDCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS));
699 break;
700 #endif
701 default:
702 status = HAL_ERROR;
703 break;
704 }
705
706 return status;
707 }
708
709
710
711 /**
712 * @brief Enable pull-up and pull-down configuration.
713 * @note When APC bit is set, the I/O pull-up and pull-down configurations defined in
714 * PWR_PUCRx and PWR_PDCRx registers are applied in Standby and Shutdown modes.
715 * @note Pull-up set by PUy bit of PWR_PUCRx register is not activated if the corresponding
716 * PDy bit of PWR_PDCRx register is also set (pull-down configuration priority is higher).
717 * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() API's ensure there
718 * is no conflict when setting PUy or PDy bit.
719 * @retval None
720 */
HAL_PWREx_EnablePullUpPullDownConfig(void)721 void HAL_PWREx_EnablePullUpPullDownConfig(void)
722 {
723 SET_BIT(PWR->CR3, PWR_CR3_APC);
724 }
725
726
727 /**
728 * @brief Disable pull-up and pull-down configuration.
729 * @note When APC bit is cleared, the I/O pull-up and pull-down configurations defined in
730 * PWR_PUCRx and PWR_PDCRx registers are not applied in Standby and Shutdown modes.
731 * @retval None
732 */
HAL_PWREx_DisablePullUpPullDownConfig(void)733 void HAL_PWREx_DisablePullUpPullDownConfig(void)
734 {
735 CLEAR_BIT(PWR->CR3, PWR_CR3_APC);
736 }
737
738
739
740 /**
741 * @brief Enable SRAM2 content retention in Standby mode.
742 * @note When RRS bit is set, SRAM2 is powered by the low-power regulator in
743 * Standby mode and its content is kept.
744 * @retval None
745 */
HAL_PWREx_EnableSRAM2ContentRetention(void)746 void HAL_PWREx_EnableSRAM2ContentRetention(void)
747 {
748 SET_BIT(PWR->CR3, PWR_CR3_RRS);
749 }
750
751
752 /**
753 * @brief Disable SRAM2 content retention in Standby mode.
754 * @note When RRS bit is reset, SRAM2 is powered off in Standby mode
755 * and its content is lost.
756 * @retval None
757 */
HAL_PWREx_DisableSRAM2ContentRetention(void)758 void HAL_PWREx_DisableSRAM2ContentRetention(void)
759 {
760 CLEAR_BIT(PWR->CR3, PWR_CR3_RRS);
761 }
762
763
764 #if defined(PWR_CR3_EN_ULP)
765 /**
766 * @brief Enable Ultra Low Power BORL, BORH and PVD for STOP2 and Standby modes.
767 * @note All the other modes are not affected by this bit.
768 * @retval None
769 */
HAL_PWREx_EnableBORPVD_ULP(void)770 void HAL_PWREx_EnableBORPVD_ULP(void)
771 {
772 SET_BIT(PWR->CR3, PWR_CR3_EN_ULP);
773 }
774
775
776 /**
777 * @brief Disable Ultra Low Power BORL, BORH and PVD for STOP2 and Standby modes.
778 * @note All the other modes are not affected by this bit
779 * @retval None
780 */
HAL_PWREx_DisableBORPVD_ULP(void)781 void HAL_PWREx_DisableBORPVD_ULP(void)
782 {
783 CLEAR_BIT(PWR->CR3, PWR_CR3_EN_ULP);
784 }
785 #endif /* PWR_CR3_EN_ULP */
786
787
788 #if defined(PWR_CR4_EXT_SMPS_ON)
789 /**
790 * @brief Enable the CFLDO working @ 0.95V.
791 * @note When external SMPS is used & CFLDO operating in Range 2, the regulated voltage of the
792 * internal CFLDO can be reduced to 0.95V.
793 * @retval None
794 */
HAL_PWREx_EnableExtSMPS_0V95(void)795 void HAL_PWREx_EnableExtSMPS_0V95(void)
796 {
797 SET_BIT(PWR->CR4, PWR_CR4_EXT_SMPS_ON);
798 }
799
800 /**
801 * @brief Disable the CFLDO working @ 0.95V
802 * @note Before SMPS is switched off, the regulated voltage of the
803 * internal CFLDO shall be set to 1.00V.
804 * 1.00V. is also default operating Range 2 voltage.
805 * @retval None
806 */
HAL_PWREx_DisableExtSMPS_0V95(void)807 void HAL_PWREx_DisableExtSMPS_0V95(void)
808 {
809 CLEAR_BIT(PWR->CR4, PWR_CR4_EXT_SMPS_ON);
810 }
811 #endif /* PWR_CR4_EXT_SMPS_ON */
812
813
814 #if defined(PWR_CR1_RRSTP)
815 /**
816 * @brief Enable SRAM3 content retention in Stop 2 mode.
817 * @note When RRSTP bit is set, SRAM3 is powered by the low-power regulator in
818 * Stop 2 mode and its content is kept.
819 * @retval None
820 */
HAL_PWREx_EnableSRAM3ContentRetention(void)821 void HAL_PWREx_EnableSRAM3ContentRetention(void)
822 {
823 SET_BIT(PWR->CR1, PWR_CR1_RRSTP);
824 }
825
826
827 /**
828 * @brief Disable SRAM3 content retention in Stop 2 mode.
829 * @note When RRSTP bit is reset, SRAM3 is powered off in Stop 2 mode
830 * and its content is lost.
831 * @retval None
832 */
HAL_PWREx_DisableSRAM3ContentRetention(void)833 void HAL_PWREx_DisableSRAM3ContentRetention(void)
834 {
835 CLEAR_BIT(PWR->CR1, PWR_CR1_RRSTP);
836 }
837 #endif /* PWR_CR1_RRSTP */
838
839 #if defined(PWR_CR3_DSIPDEN)
840 /**
841 * @brief Enable pull-down activation on DSI pins.
842 * @retval None
843 */
HAL_PWREx_EnableDSIPinsPDActivation(void)844 void HAL_PWREx_EnableDSIPinsPDActivation(void)
845 {
846 SET_BIT(PWR->CR3, PWR_CR3_DSIPDEN);
847 }
848
849
850 /**
851 * @brief Disable pull-down activation on DSI pins.
852 * @retval None
853 */
HAL_PWREx_DisableDSIPinsPDActivation(void)854 void HAL_PWREx_DisableDSIPinsPDActivation(void)
855 {
856 CLEAR_BIT(PWR->CR3, PWR_CR3_DSIPDEN);
857 }
858 #endif /* PWR_CR3_DSIPDEN */
859
860 #if defined(PWR_CR2_PVME1)
861 /**
862 * @brief Enable the Power Voltage Monitoring 1: VDDUSB versus 1.2V.
863 * @retval None
864 */
HAL_PWREx_EnablePVM1(void)865 void HAL_PWREx_EnablePVM1(void)
866 {
867 SET_BIT(PWR->CR2, PWR_PVM_1);
868 }
869
870 /**
871 * @brief Disable the Power Voltage Monitoring 1: VDDUSB versus 1.2V.
872 * @retval None
873 */
HAL_PWREx_DisablePVM1(void)874 void HAL_PWREx_DisablePVM1(void)
875 {
876 CLEAR_BIT(PWR->CR2, PWR_PVM_1);
877 }
878 #endif /* PWR_CR2_PVME1 */
879
880
881 #if defined(PWR_CR2_PVME2)
882 /**
883 * @brief Enable the Power Voltage Monitoring 2: VDDIO2 versus 0.9V.
884 * @retval None
885 */
HAL_PWREx_EnablePVM2(void)886 void HAL_PWREx_EnablePVM2(void)
887 {
888 SET_BIT(PWR->CR2, PWR_PVM_2);
889 }
890
891 /**
892 * @brief Disable the Power Voltage Monitoring 2: VDDIO2 versus 0.9V.
893 * @retval None
894 */
HAL_PWREx_DisablePVM2(void)895 void HAL_PWREx_DisablePVM2(void)
896 {
897 CLEAR_BIT(PWR->CR2, PWR_PVM_2);
898 }
899 #endif /* PWR_CR2_PVME2 */
900
901
902 /**
903 * @brief Enable the Power Voltage Monitoring 3: VDDA versus 1.62V.
904 * @retval None
905 */
HAL_PWREx_EnablePVM3(void)906 void HAL_PWREx_EnablePVM3(void)
907 {
908 SET_BIT(PWR->CR2, PWR_PVM_3);
909 }
910
911 /**
912 * @brief Disable the Power Voltage Monitoring 3: VDDA versus 1.62V.
913 * @retval None
914 */
HAL_PWREx_DisablePVM3(void)915 void HAL_PWREx_DisablePVM3(void)
916 {
917 CLEAR_BIT(PWR->CR2, PWR_PVM_3);
918 }
919
920
921 /**
922 * @brief Enable the Power Voltage Monitoring 4: VDDA versus 2.2V.
923 * @retval None
924 */
HAL_PWREx_EnablePVM4(void)925 void HAL_PWREx_EnablePVM4(void)
926 {
927 SET_BIT(PWR->CR2, PWR_PVM_4);
928 }
929
930 /**
931 * @brief Disable the Power Voltage Monitoring 4: VDDA versus 2.2V.
932 * @retval None
933 */
HAL_PWREx_DisablePVM4(void)934 void HAL_PWREx_DisablePVM4(void)
935 {
936 CLEAR_BIT(PWR->CR2, PWR_PVM_4);
937 }
938
939
940
941
942 /**
943 * @brief Configure the Peripheral Voltage Monitoring (PVM).
944 * @param sConfigPVM: pointer to a PWR_PVMTypeDef structure that contains the
945 * PVM configuration information.
946 * @note The API configures a single PVM according to the information contained
947 * in the input structure. To configure several PVMs, the API must be singly
948 * called for each PVM used.
949 * @note Refer to the electrical characteristics of your device datasheet for
950 * more details about the voltage thresholds corresponding to each
951 * detection level and to each monitored supply.
952 * @retval HAL status
953 */
HAL_PWREx_ConfigPVM(PWR_PVMTypeDef * sConfigPVM)954 HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM)
955 {
956 HAL_StatusTypeDef status = HAL_OK;
957
958 /* Check the parameters */
959 assert_param(IS_PWR_PVM_TYPE(sConfigPVM->PVMType));
960 assert_param(IS_PWR_PVM_MODE(sConfigPVM->Mode));
961
962
963 /* Configure EXTI 35 to 38 interrupts if so required:
964 scan thru PVMType to detect which PVMx is set and
965 configure the corresponding EXTI line accordingly. */
966 switch (sConfigPVM->PVMType)
967 {
968 #if defined(PWR_CR2_PVME1)
969 case PWR_PVM_1:
970 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
971 __HAL_PWR_PVM1_EXTI_DISABLE_EVENT();
972 __HAL_PWR_PVM1_EXTI_DISABLE_IT();
973 __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE();
974 __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE();
975
976 /* Configure interrupt mode */
977 if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
978 {
979 __HAL_PWR_PVM1_EXTI_ENABLE_IT();
980 }
981
982 /* Configure event mode */
983 if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
984 {
985 __HAL_PWR_PVM1_EXTI_ENABLE_EVENT();
986 }
987
988 /* Configure the edge */
989 if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
990 {
991 __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE();
992 }
993
994 if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
995 {
996 __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE();
997 }
998 break;
999 #endif /* PWR_CR2_PVME1 */
1000
1001 #if defined(PWR_CR2_PVME2)
1002 case PWR_PVM_2:
1003 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
1004 __HAL_PWR_PVM2_EXTI_DISABLE_EVENT();
1005 __HAL_PWR_PVM2_EXTI_DISABLE_IT();
1006 __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE();
1007 __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE();
1008
1009 /* Configure interrupt mode */
1010 if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
1011 {
1012 __HAL_PWR_PVM2_EXTI_ENABLE_IT();
1013 }
1014
1015 /* Configure event mode */
1016 if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
1017 {
1018 __HAL_PWR_PVM2_EXTI_ENABLE_EVENT();
1019 }
1020
1021 /* Configure the edge */
1022 if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
1023 {
1024 __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE();
1025 }
1026
1027 if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
1028 {
1029 __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE();
1030 }
1031 break;
1032 #endif /* PWR_CR2_PVME2 */
1033
1034 case PWR_PVM_3:
1035 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
1036 __HAL_PWR_PVM3_EXTI_DISABLE_EVENT();
1037 __HAL_PWR_PVM3_EXTI_DISABLE_IT();
1038 __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE();
1039 __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE();
1040
1041 /* Configure interrupt mode */
1042 if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
1043 {
1044 __HAL_PWR_PVM3_EXTI_ENABLE_IT();
1045 }
1046
1047 /* Configure event mode */
1048 if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
1049 {
1050 __HAL_PWR_PVM3_EXTI_ENABLE_EVENT();
1051 }
1052
1053 /* Configure the edge */
1054 if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
1055 {
1056 __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE();
1057 }
1058
1059 if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
1060 {
1061 __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE();
1062 }
1063 break;
1064
1065 case PWR_PVM_4:
1066 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
1067 __HAL_PWR_PVM4_EXTI_DISABLE_EVENT();
1068 __HAL_PWR_PVM4_EXTI_DISABLE_IT();
1069 __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE();
1070 __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE();
1071
1072 /* Configure interrupt mode */
1073 if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
1074 {
1075 __HAL_PWR_PVM4_EXTI_ENABLE_IT();
1076 }
1077
1078 /* Configure event mode */
1079 if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
1080 {
1081 __HAL_PWR_PVM4_EXTI_ENABLE_EVENT();
1082 }
1083
1084 /* Configure the edge */
1085 if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
1086 {
1087 __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE();
1088 }
1089
1090 if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
1091 {
1092 __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE();
1093 }
1094 break;
1095
1096 default:
1097 status = HAL_ERROR;
1098 break;
1099 }
1100
1101 return status;
1102 }
1103
1104
1105
1106 /**
1107 * @brief Enter Low-power Run mode
1108 * @note In Low-power Run mode, all I/O pins keep the same state as in Run mode.
1109 * @note When Regulator is set to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the
1110 * Flash in power-down monde in setting the RUN_PD bit in FLASH_ACR register.
1111 * Additionally, the clock frequency must be reduced below 2 MHz.
1112 * Setting RUN_PD in FLASH_ACR then appropriately reducing the clock frequency must
1113 * be done before calling HAL_PWREx_EnableLowPowerRunMode() API.
1114 * @retval None
1115 */
HAL_PWREx_EnableLowPowerRunMode(void)1116 void HAL_PWREx_EnableLowPowerRunMode(void)
1117 {
1118 /* Set Regulator parameter */
1119 SET_BIT(PWR->CR1, PWR_CR1_LPR);
1120 }
1121
1122
1123 /**
1124 * @brief Exit Low-power Run mode.
1125 * @note Before HAL_PWREx_DisableLowPowerRunMode() completion, the function checks that
1126 * REGLPF has been properly reset (otherwise, HAL_PWREx_DisableLowPowerRunMode
1127 * returns HAL_TIMEOUT status). The system clock frequency can then be
1128 * increased above 2 MHz.
1129 * @retval HAL Status
1130 */
HAL_PWREx_DisableLowPowerRunMode(void)1131 HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void)
1132 {
1133 uint32_t wait_loop_index;
1134
1135 /* Clear LPR bit */
1136 CLEAR_BIT(PWR->CR1, PWR_CR1_LPR);
1137
1138 /* Wait until REGLPF is reset */
1139 wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U;
1140 while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) && (wait_loop_index != 0U))
1141 {
1142 wait_loop_index--;
1143 }
1144 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF))
1145 {
1146 return HAL_TIMEOUT;
1147 }
1148
1149 return HAL_OK;
1150 }
1151
1152
1153 /**
1154 * @brief Enter Stop 0 mode.
1155 * @note In Stop 0 mode, main and low voltage regulators are ON.
1156 * @note In Stop 0 mode, all I/O pins keep the same state as in Run mode.
1157 * @note All clocks in the VCORE domain are stopped; the PLL, the MSI,
1158 * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability
1159 * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI
1160 * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated
1161 * only to the peripheral requesting it.
1162 * SRAM1, SRAM2 and register contents are preserved.
1163 * The BOR is available.
1164 * @note When exiting Stop 0 mode by issuing an interrupt or a wakeup event,
1165 * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
1166 * is set; the MSI oscillator is selected if STOPWUCK is cleared.
1167 * @note By keeping the internal regulator ON during Stop 0 mode, the consumption
1168 * is higher although the startup time is reduced.
1169 * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction.
1170 * This parameter can be one of the following values:
1171 * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction
1172 * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction
1173 * @retval None
1174 */
HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry)1175 void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry)
1176 {
1177 /* Check the parameters */
1178 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
1179
1180 /* Stop 0 mode with Main Regulator */
1181 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP0);
1182
1183 /* Set SLEEPDEEP bit of Cortex System Control Register */
1184 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
1185
1186 /* Select Stop mode entry --------------------------------------------------*/
1187 if(STOPEntry == PWR_STOPENTRY_WFI)
1188 {
1189 /* Request Wait For Interrupt */
1190 __WFI();
1191 }
1192 else
1193 {
1194 /* Request Wait For Event */
1195 __SEV();
1196 __WFE();
1197 __WFE();
1198 }
1199
1200 /* Reset SLEEPDEEP bit of Cortex System Control Register */
1201 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
1202 }
1203
1204
1205 /**
1206 * @brief Enter Stop 1 mode.
1207 * @note In Stop 1 mode, only low power voltage regulator is ON.
1208 * @note In Stop 1 mode, all I/O pins keep the same state as in Run mode.
1209 * @note All clocks in the VCORE domain are stopped; the PLL, the MSI,
1210 * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability
1211 * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI
1212 * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated
1213 * only to the peripheral requesting it.
1214 * SRAM1, SRAM2 and register contents are preserved.
1215 * The BOR is available.
1216 * @note When exiting Stop 1 mode by issuing an interrupt or a wakeup event,
1217 * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
1218 * is set; the MSI oscillator is selected if STOPWUCK is cleared.
1219 * @note Due to low power mode, an additional startup delay is incurred when waking up from Stop 1 mode.
1220 * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction.
1221 * This parameter can be one of the following values:
1222 * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction
1223 * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction
1224 * @retval None
1225 */
HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry)1226 void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry)
1227 {
1228 /* Check the parameters */
1229 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
1230
1231 /* Stop 1 mode with Low-Power Regulator */
1232 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP1);
1233
1234 /* Set SLEEPDEEP bit of Cortex System Control Register */
1235 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
1236
1237 /* Select Stop mode entry --------------------------------------------------*/
1238 if(STOPEntry == PWR_STOPENTRY_WFI)
1239 {
1240 /* Request Wait For Interrupt */
1241 __WFI();
1242 }
1243 else
1244 {
1245 /* Request Wait For Event */
1246 __SEV();
1247 __WFE();
1248 __WFE();
1249 }
1250
1251 /* Reset SLEEPDEEP bit of Cortex System Control Register */
1252 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
1253 }
1254
1255
1256 /**
1257 * @brief Enter Stop 2 mode.
1258 * @note In Stop 2 mode, only low power voltage regulator is ON.
1259 * @note In Stop 2 mode, all I/O pins keep the same state as in Run mode.
1260 * @note All clocks in the VCORE domain are stopped, the PLL, the MSI,
1261 * the HSI and the HSE oscillators are disabled. Some peripherals with wakeup capability
1262 * (LCD, LPTIM1, I2C3 and LPUART) can switch on the HSI to receive a frame, and switch off the HSI after
1263 * receiving the frame if it is not a wakeup frame. In this case the HSI clock is propagated only
1264 * to the peripheral requesting it.
1265 * SRAM1, SRAM2 and register contents are preserved.
1266 * The BOR is available.
1267 * The voltage regulator is set in low-power mode but LPR bit must be cleared to enter stop 2 mode.
1268 * Otherwise, Stop 1 mode is entered.
1269 * @note When exiting Stop 2 mode by issuing an interrupt or a wakeup event,
1270 * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
1271 * is set; the MSI oscillator is selected if STOPWUCK is cleared.
1272 * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction.
1273 * This parameter can be one of the following values:
1274 * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction
1275 * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction
1276 * @retval None
1277 */
HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry)1278 void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry)
1279 {
1280 /* Check the parameter */
1281 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
1282
1283 /* Set Stop mode 2 */
1284 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP2);
1285
1286 /* Set SLEEPDEEP bit of Cortex System Control Register */
1287 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
1288
1289 /* Select Stop mode entry --------------------------------------------------*/
1290 if(STOPEntry == PWR_STOPENTRY_WFI)
1291 {
1292 /* Request Wait For Interrupt */
1293 __WFI();
1294 }
1295 else
1296 {
1297 /* Request Wait For Event */
1298 __SEV();
1299 __WFE();
1300 __WFE();
1301 }
1302
1303 /* Reset SLEEPDEEP bit of Cortex System Control Register */
1304 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
1305 }
1306
1307
1308
1309
1310
1311 /**
1312 * @brief Enter Shutdown mode.
1313 * @note In Shutdown mode, the PLL, the HSI, the MSI, the LSI and the HSE oscillators are switched
1314 * off. The voltage regulator is disabled and Vcore domain is powered off.
1315 * SRAM1, SRAM2 and registers contents are lost except for registers in the Backup domain.
1316 * The BOR is not available.
1317 * @note The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state.
1318 * @retval None
1319 */
HAL_PWREx_EnterSHUTDOWNMode(void)1320 void HAL_PWREx_EnterSHUTDOWNMode(void)
1321 {
1322
1323 /* Set Shutdown mode */
1324 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_SHUTDOWN);
1325
1326 /* Set SLEEPDEEP bit of Cortex System Control Register */
1327 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
1328
1329 /* This option is used to ensure that store operations are completed */
1330 #if defined ( __CC_ARM)
1331 __force_stores();
1332 #endif
1333 /* Request Wait For Interrupt */
1334 __WFI();
1335 }
1336
1337
1338
1339
1340 /**
1341 * @brief This function handles the PWR PVD/PVMx interrupt request.
1342 * @note This API should be called under the PVD_PVM_IRQHandler().
1343 * @retval None
1344 */
HAL_PWREx_PVD_PVM_IRQHandler(void)1345 void HAL_PWREx_PVD_PVM_IRQHandler(void)
1346 {
1347 /* Check PWR exti flag */
1348 if(__HAL_PWR_PVD_EXTI_GET_FLAG() != 0x0U)
1349 {
1350 /* PWR PVD interrupt user callback */
1351 HAL_PWR_PVDCallback();
1352
1353 /* Clear PVD exti pending bit */
1354 __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
1355 }
1356 /* Next, successively check PVMx exti flags */
1357 #if defined(PWR_CR2_PVME1)
1358 if(__HAL_PWR_PVM1_EXTI_GET_FLAG() != 0x0U)
1359 {
1360 /* PWR PVM1 interrupt user callback */
1361 HAL_PWREx_PVM1Callback();
1362
1363 /* Clear PVM1 exti pending bit */
1364 __HAL_PWR_PVM1_EXTI_CLEAR_FLAG();
1365 }
1366 #endif /* PWR_CR2_PVME1 */
1367 #if defined(PWR_CR2_PVME2)
1368 if(__HAL_PWR_PVM2_EXTI_GET_FLAG() != 0x0U)
1369 {
1370 /* PWR PVM2 interrupt user callback */
1371 HAL_PWREx_PVM2Callback();
1372
1373 /* Clear PVM2 exti pending bit */
1374 __HAL_PWR_PVM2_EXTI_CLEAR_FLAG();
1375 }
1376 #endif /* PWR_CR2_PVME2 */
1377 if(__HAL_PWR_PVM3_EXTI_GET_FLAG() != 0x0U)
1378 {
1379 /* PWR PVM3 interrupt user callback */
1380 HAL_PWREx_PVM3Callback();
1381
1382 /* Clear PVM3 exti pending bit */
1383 __HAL_PWR_PVM3_EXTI_CLEAR_FLAG();
1384 }
1385 if(__HAL_PWR_PVM4_EXTI_GET_FLAG() != 0x0U)
1386 {
1387 /* PWR PVM4 interrupt user callback */
1388 HAL_PWREx_PVM4Callback();
1389
1390 /* Clear PVM4 exti pending bit */
1391 __HAL_PWR_PVM4_EXTI_CLEAR_FLAG();
1392 }
1393 }
1394
1395
1396 #if defined(PWR_CR2_PVME1)
1397 /**
1398 * @brief PWR PVM1 interrupt callback
1399 * @retval None
1400 */
HAL_PWREx_PVM1Callback(void)1401 __weak void HAL_PWREx_PVM1Callback(void)
1402 {
1403 /* NOTE : This function should not be modified; when the callback is needed,
1404 HAL_PWREx_PVM1Callback() API can be implemented in the user file
1405 */
1406 }
1407 #endif /* PWR_CR2_PVME1 */
1408
1409 #if defined(PWR_CR2_PVME2)
1410 /**
1411 * @brief PWR PVM2 interrupt callback
1412 * @retval None
1413 */
HAL_PWREx_PVM2Callback(void)1414 __weak void HAL_PWREx_PVM2Callback(void)
1415 {
1416 /* NOTE : This function should not be modified; when the callback is needed,
1417 HAL_PWREx_PVM2Callback() API can be implemented in the user file
1418 */
1419 }
1420 #endif /* PWR_CR2_PVME2 */
1421
1422 /**
1423 * @brief PWR PVM3 interrupt callback
1424 * @retval None
1425 */
HAL_PWREx_PVM3Callback(void)1426 __weak void HAL_PWREx_PVM3Callback(void)
1427 {
1428 /* NOTE : This function should not be modified; when the callback is needed,
1429 HAL_PWREx_PVM3Callback() API can be implemented in the user file
1430 */
1431 }
1432
1433 /**
1434 * @brief PWR PVM4 interrupt callback
1435 * @retval None
1436 */
HAL_PWREx_PVM4Callback(void)1437 __weak void HAL_PWREx_PVM4Callback(void)
1438 {
1439 /* NOTE : This function should not be modified; when the callback is needed,
1440 HAL_PWREx_PVM4Callback() API can be implemented in the user file
1441 */
1442 }
1443
1444
1445 /**
1446 * @}
1447 */
1448
1449 /**
1450 * @}
1451 */
1452
1453 #endif /* HAL_PWR_MODULE_ENABLED */
1454 /**
1455 * @}
1456 */
1457
1458 /**
1459 * @}
1460 */
1461
1462 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1463
