1 /**
2 ******************************************************************************
3 * @file stm32l4xx_hal_dma.c
4 * @author MCD Application Team
5 * @brief DMA HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Direct Memory Access (DMA) peripheral:
8 * + Initialization and de-initialization functions
9 * + IO operation functions
10 * + Peripheral State and errors functions
11 @verbatim
12 ==============================================================================
13 ##### How to use this driver #####
14 ==============================================================================
15 [..]
16 (#) Enable and configure the peripheral to be connected to the DMA Channel
17 (except for internal SRAM / FLASH memories: no initialization is
18 necessary). Please refer to the Reference manual for connection between peripherals
19 and DMA requests.
20
21 (#) For a given Channel, program the required configuration through the following parameters:
22 Channel request, Transfer Direction, Source and Destination data formats,
23 Circular or Normal mode, Channel Priority level, Source and Destination Increment mode
24 using HAL_DMA_Init() function.
25
26 Prior to HAL_DMA_Init the peripheral clock shall be enabled for both DMA & DMAMUX
27 thanks to:
28 (##) DMA1 or DMA2: __HAL_RCC_DMA1_CLK_ENABLE() or __HAL_RCC_DMA2_CLK_ENABLE() ;
29 (##) DMAMUX1: __HAL_RCC_DMAMUX1_CLK_ENABLE();
30
31 (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
32 detection.
33
34 (#) Use HAL_DMA_Abort() function to abort the current transfer
35
36 -@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
37
38 *** Polling mode IO operation ***
39 =================================
40 [..]
41 (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
42 address and destination address and the Length of data to be transferred
43 (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
44 case a fixed Timeout can be configured by User depending from his application.
45
46 *** Interrupt mode IO operation ***
47 ===================================
48 [..]
49 (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
50 (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
51 (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
52 Source address and destination address and the Length of data to be transferred.
53 In this case the DMA interrupt is configured
54 (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
55 (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
56 add his own function to register callbacks with HAL_DMA_RegisterCallback().
57
58 *** DMA HAL driver macros list ***
59 =============================================
60 [..]
61 Below the list of macros in DMA HAL driver.
62
63 (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel.
64 (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel.
65 (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags.
66 (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags.
67 (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts.
68 (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts.
69 (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not.
70
71 [..]
72 (@) You can refer to the DMA HAL driver header file for more useful macros
73
74 @endverbatim
75 ******************************************************************************
76 * @attention
77 *
78 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
79 *
80 * Redistribution and use in source and binary forms, with or without modification,
81 * are permitted provided that the following conditions are met:
82 * 1. Redistributions of source code must retain the above copyright notice,
83 * this list of conditions and the following disclaimer.
84 * 2. Redistributions in binary form must reproduce the above copyright notice,
85 * this list of conditions and the following disclaimer in the documentation
86 * and/or other materials provided with the distribution.
87 * 3. Neither the name of STMicroelectronics nor the names of its contributors
88 * may be used to endorse or promote products derived from this software
89 * without specific prior written permission.
90 *
91 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
92 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
93 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
94 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
95 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
96 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
97 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
98 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
99 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
100 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
101 *
102 ******************************************************************************
103 */
104
105 /* Includes ------------------------------------------------------------------*/
106 #include "stm32l4xx_hal.h"
107
108 /** @addtogroup STM32L4xx_HAL_Driver
109 * @{
110 */
111
112 /** @defgroup DMA DMA
113 * @brief DMA HAL module driver
114 * @{
115 */
116
117 #ifdef HAL_DMA_MODULE_ENABLED
118
119 /* Private typedef -----------------------------------------------------------*/
120 /* Private define ------------------------------------------------------------*/
121 /* Private macro -------------------------------------------------------------*/
122 /* Private variables ---------------------------------------------------------*/
123 /* Private function prototypes -----------------------------------------------*/
124 /** @defgroup DMA_Private_Functions DMA Private Functions
125 * @{
126 */
127 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
128 #if defined(DMAMUX1)
129 static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma);
130 static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma);
131 #endif /* DMAMUX1 */
132
133 /**
134 * @}
135 */
136
137 /* Exported functions ---------------------------------------------------------*/
138
139 /** @defgroup DMA_Exported_Functions DMA Exported Functions
140 * @{
141 */
142
143 /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
144 * @brief Initialization and de-initialization functions
145 *
146 @verbatim
147 ===============================================================================
148 ##### Initialization and de-initialization functions #####
149 ===============================================================================
150 [..]
151 This section provides functions allowing to initialize the DMA Channel source
152 and destination addresses, incrementation and data sizes, transfer direction,
153 circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
154 [..]
155 The HAL_DMA_Init() function follows the DMA configuration procedures as described in
156 reference manual.
157
158 @endverbatim
159 * @{
160 */
161
162 /**
163 * @brief Initialize the DMA according to the specified
164 * parameters in the DMA_InitTypeDef and initialize the associated handle.
165 * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
166 * the configuration information for the specified DMA Channel.
167 * @retval HAL status
168 */
HAL_DMA_Init(DMA_HandleTypeDef * hdma)169 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
170 {
171 uint32_t tmp;
172
173 /* Check the DMA handle allocation */
174 if(hdma == NULL)
175 {
176 return HAL_ERROR;
177 }
178
179 /* Check the parameters */
180 assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
181 assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
182 assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
183 assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
184 assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
185 assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
186 assert_param(IS_DMA_MODE(hdma->Init.Mode));
187 assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
188
189 assert_param(IS_DMA_ALL_REQUEST(hdma->Init.Request));
190
191 /* Compute the channel index */
192 if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
193 {
194 /* DMA1 */
195 hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
196 hdma->DmaBaseAddress = DMA1;
197 }
198 else
199 {
200 /* DMA2 */
201 hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2;
202 hdma->DmaBaseAddress = DMA2;
203 }
204
205 /* Change DMA peripheral state */
206 hdma->State = HAL_DMA_STATE_BUSY;
207
208 /* Get the CR register value */
209 tmp = hdma->Instance->CCR;
210
211 /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and MEM2MEM bits */
212 tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE |
213 DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC |
214 DMA_CCR_DIR | DMA_CCR_MEM2MEM));
215
216 /* Prepare the DMA Channel configuration */
217 tmp |= hdma->Init.Direction |
218 hdma->Init.PeriphInc | hdma->Init.MemInc |
219 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
220 hdma->Init.Mode | hdma->Init.Priority;
221
222 /* Write to DMA Channel CR register */
223 hdma->Instance->CCR = tmp;
224
225
226 #if defined(DMAMUX1)
227 /* Initialize parameters for DMAMUX channel :
228 DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask
229 */
230 DMA_CalcDMAMUXChannelBaseAndMask(hdma);
231
232 if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
233 {
234 /* if memory to memory force the request to 0*/
235 hdma->Init.Request = DMA_REQUEST_MEM2MEM;
236 }
237
238 /* Set peripheral request to DMAMUX channel */
239 hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID);
240
241 /* Clear the DMAMUX synchro overrun flag */
242 hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
243
244 if(((hdma->Init.Request > 0U) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3)))
245 {
246 /* Initialize parameters for DMAMUX request generator :
247 DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask
248 */
249 DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);
250
251 /* Reset the DMAMUX request generator register*/
252 hdma->DMAmuxRequestGen->RGCR = 0U;
253
254 /* Clear the DMAMUX request generator overrun flag */
255 hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
256 }
257 else
258 {
259 hdma->DMAmuxRequestGen = 0U;
260 hdma->DMAmuxRequestGenStatus = 0U;
261 hdma->DMAmuxRequestGenStatusMask = 0U;
262 }
263 #endif /* DMAMUX1 */
264
265 #if !defined (DMAMUX1)
266
267 /* Set request selection */
268 if(hdma->Init.Direction != DMA_MEMORY_TO_MEMORY)
269 {
270 /* Write to DMA channel selection register */
271 if (DMA1 == hdma->DmaBaseAddress)
272 {
273 /* Reset request selection for DMA1 Channelx */
274 DMA1_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex & 0x1cU));
275
276 /* Configure request selection for DMA1 Channelx */
277 DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << (hdma->ChannelIndex & 0x1cU));
278 }
279 else /* DMA2 */
280 {
281 /* Reset request selection for DMA2 Channelx */
282 DMA2_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex & 0x1cU));
283
284 /* Configure request selection for DMA2 Channelx */
285 DMA2_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << (hdma->ChannelIndex & 0x1cU));
286 }
287 }
288
289 #endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx */
290 /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L442xx || STM32L486xx */
291 /* STM32L496xx || STM32L4A6xx */
292
293 /* Initialise the error code */
294 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
295
296 /* Initialize the DMA state*/
297 hdma->State = HAL_DMA_STATE_READY;
298
299 /* Allocate lock resource and initialize it */
300 hdma->Lock = HAL_UNLOCKED;
301
302 return HAL_OK;
303 }
304
305 /**
306 * @brief DeInitialize the DMA peripheral.
307 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
308 * the configuration information for the specified DMA Channel.
309 * @retval HAL status
310 */
HAL_DMA_DeInit(DMA_HandleTypeDef * hdma)311 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
312 {
313
314 /* Check the DMA handle allocation */
315 if (NULL == hdma )
316 {
317 return HAL_ERROR;
318 }
319
320 /* Check the parameters */
321 assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
322
323 /* Disable the selected DMA Channelx */
324 __HAL_DMA_DISABLE(hdma);
325
326 /* Compute the channel index */
327 if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
328 {
329 /* DMA1 */
330 hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
331 hdma->DmaBaseAddress = DMA1;
332 }
333 else
334 {
335 /* DMA2 */
336 hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2;
337 hdma->DmaBaseAddress = DMA2;
338 }
339
340 /* Reset DMA Channel control register */
341 hdma->Instance->CCR = 0;
342
343 /* Clear all flags */
344 hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU));
345
346 #if !defined (DMAMUX1)
347
348 /* Reset DMA channel selection register */
349 if (DMA1 == hdma->DmaBaseAddress)
350 {
351 /* DMA1 */
352 DMA1_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex & 0x1cU));
353 }
354 else
355 {
356 /* DMA2 */
357 DMA2_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex & 0x1cU));
358 }
359 #endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx */
360 /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L442xx || STM32L486xx */
361 /* STM32L496xx || STM32L4A6xx */
362
363 #if defined(DMAMUX1)
364
365 /* Initialize parameters for DMAMUX channel :
366 DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */
367
368 DMA_CalcDMAMUXChannelBaseAndMask(hdma);
369
370 /* Reset the DMAMUX channel that corresponds to the DMA channel */
371 hdma->DMAmuxChannel->CCR = 0;
372
373 /* Clear the DMAMUX synchro overrun flag */
374 hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
375
376 /* Reset Request generator parameters if any */
377 if(((hdma->Init.Request > 0U) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3)))
378 {
379 /* Initialize parameters for DMAMUX request generator :
380 DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask
381 */
382 DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);
383
384 /* Reset the DMAMUX request generator register*/
385 hdma->DMAmuxRequestGen->RGCR = 0U;
386
387 /* Clear the DMAMUX request generator overrun flag */
388 hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
389 }
390
391 hdma->DMAmuxRequestGen = 0U;
392 hdma->DMAmuxRequestGenStatus = 0U;
393 hdma->DMAmuxRequestGenStatusMask = 0U;
394
395 #endif /* DMAMUX1 */
396
397 /* Clean callbacks */
398 hdma->XferCpltCallback = NULL;
399 hdma->XferHalfCpltCallback = NULL;
400 hdma->XferErrorCallback = NULL;
401 hdma->XferAbortCallback = NULL;
402
403 /* Initialise the error code */
404 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
405
406 /* Initialize the DMA state */
407 hdma->State = HAL_DMA_STATE_RESET;
408
409 /* Release Lock */
410 __HAL_UNLOCK(hdma);
411
412 return HAL_OK;
413 }
414
415 /**
416 * @}
417 */
418
419 /** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
420 * @brief Input and Output operation functions
421 *
422 @verbatim
423 ===============================================================================
424 ##### IO operation functions #####
425 ===============================================================================
426 [..] This section provides functions allowing to:
427 (+) Configure the source, destination address and data length and Start DMA transfer
428 (+) Configure the source, destination address and data length and
429 Start DMA transfer with interrupt
430 (+) Abort DMA transfer
431 (+) Poll for transfer complete
432 (+) Handle DMA interrupt request
433
434 @endverbatim
435 * @{
436 */
437
438 /**
439 * @brief Start the DMA Transfer.
440 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
441 * the configuration information for the specified DMA Channel.
442 * @param SrcAddress The source memory Buffer address
443 * @param DstAddress The destination memory Buffer address
444 * @param DataLength The length of data to be transferred from source to destination
445 * @retval HAL status
446 */
HAL_DMA_Start(DMA_HandleTypeDef * hdma,uint32_t SrcAddress,uint32_t DstAddress,uint32_t DataLength)447 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
448 {
449 HAL_StatusTypeDef status = HAL_OK;
450
451 /* Check the parameters */
452 assert_param(IS_DMA_BUFFER_SIZE(DataLength));
453
454 /* Process locked */
455 __HAL_LOCK(hdma);
456
457 if(HAL_DMA_STATE_READY == hdma->State)
458 {
459 /* Change DMA peripheral state */
460 hdma->State = HAL_DMA_STATE_BUSY;
461 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
462
463 /* Disable the peripheral */
464 __HAL_DMA_DISABLE(hdma);
465
466 /* Configure the source, destination address and the data length & clear flags*/
467 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
468
469 /* Enable the Peripheral */
470 __HAL_DMA_ENABLE(hdma);
471 }
472 else
473 {
474 /* Process Unlocked */
475 __HAL_UNLOCK(hdma);
476 status = HAL_BUSY;
477 }
478 return status;
479 }
480
481 /**
482 * @brief Start the DMA Transfer with interrupt enabled.
483 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
484 * the configuration information for the specified DMA Channel.
485 * @param SrcAddress The source memory Buffer address
486 * @param DstAddress The destination memory Buffer address
487 * @param DataLength The length of data to be transferred from source to destination
488 * @retval HAL status
489 */
HAL_DMA_Start_IT(DMA_HandleTypeDef * hdma,uint32_t SrcAddress,uint32_t DstAddress,uint32_t DataLength)490 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
491 {
492 HAL_StatusTypeDef status = HAL_OK;
493
494 /* Check the parameters */
495 assert_param(IS_DMA_BUFFER_SIZE(DataLength));
496
497 /* Process locked */
498 __HAL_LOCK(hdma);
499
500 if(HAL_DMA_STATE_READY == hdma->State)
501 {
502 /* Change DMA peripheral state */
503 hdma->State = HAL_DMA_STATE_BUSY;
504 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
505
506 /* Disable the peripheral */
507 __HAL_DMA_DISABLE(hdma);
508
509 /* Configure the source, destination address and the data length & clear flags*/
510 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
511
512 /* Enable the transfer complete interrupt */
513 /* Enable the transfer Error interrupt */
514 if(NULL != hdma->XferHalfCpltCallback )
515 {
516 /* Enable the Half transfer complete interrupt as well */
517 __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
518 }
519 else
520 {
521 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
522 __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
523 }
524
525 #ifdef DMAMUX1
526
527 /* Check if DMAMUX Synchronization is enabled*/
528 if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U)
529 {
530 /* Enable DMAMUX sync overrun IT*/
531 hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;
532 }
533
534 if(hdma->DMAmuxRequestGen != 0U)
535 {
536 /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/
537 /* enable the request gen overrun IT*/
538 hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
539 }
540
541 #endif /* DMAMUX1 */
542
543 /* Enable the Peripheral */
544 __HAL_DMA_ENABLE(hdma);
545 }
546 else
547 {
548 /* Process Unlocked */
549 __HAL_UNLOCK(hdma);
550
551 /* Remain BUSY */
552 status = HAL_BUSY;
553 }
554 return status;
555 }
556
557 /**
558 * @brief Abort the DMA Transfer.
559 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
560 * the configuration information for the specified DMA Channel.
561 * @retval HAL status
562 */
HAL_DMA_Abort(DMA_HandleTypeDef * hdma)563 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
564 {
565 HAL_StatusTypeDef status = HAL_OK;
566
567 /* Check the DMA peripheral handle */
568 if(NULL == hdma)
569 {
570 return HAL_ERROR;
571 }
572
573 /* Disable DMA IT */
574 __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
575
576 #if defined(DMAMUX1)
577 /* disable the DMAMUX sync overrun IT*/
578 hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
579 #endif /* DMAMUX1 */
580
581 /* Disable the channel */
582 __HAL_DMA_DISABLE(hdma);
583
584 /* Clear all flags */
585 hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU));
586
587 #if defined(DMAMUX1)
588 /* Clear the DMAMUX synchro overrun flag */
589 hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
590
591 if(hdma->DMAmuxRequestGen != 0U)
592 {
593 /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
594 /* disable the request gen overrun IT*/
595 hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
596
597 /* Clear the DMAMUX request generator overrun flag */
598 hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
599 }
600
601 #endif /* DMAMUX1 */
602
603 /* Change the DMA state */
604 hdma->State = HAL_DMA_STATE_READY;
605
606 /* Process Unlocked */
607 __HAL_UNLOCK(hdma);
608
609 return status;
610 }
611
612 /**
613 * @brief Aborts the DMA Transfer in Interrupt mode.
614 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
615 * the configuration information for the specified DMA Channel.
616 * @retval HAL status
617 */
HAL_DMA_Abort_IT(DMA_HandleTypeDef * hdma)618 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
619 {
620 HAL_StatusTypeDef status = HAL_OK;
621
622 if(HAL_DMA_STATE_BUSY != hdma->State)
623 {
624 /* no transfer ongoing */
625 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
626
627 status = HAL_ERROR;
628 }
629 else
630 {
631 /* Disable DMA IT */
632 __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
633
634 /* Disable the channel */
635 __HAL_DMA_DISABLE(hdma);
636
637 #if defined(DMAMUX1)
638 /* disable the DMAMUX sync overrun IT*/
639 hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
640
641 /* Clear all flags */
642 hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU));
643
644 /* Clear the DMAMUX synchro overrun flag */
645 hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
646
647 if(hdma->DMAmuxRequestGen != 0U)
648 {
649 /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
650 /* disable the request gen overrun IT*/
651 hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
652
653 /* Clear the DMAMUX request generator overrun flag */
654 hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
655 }
656
657 #else
658 /* Clear all flags */
659 hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU));
660 #endif /* DMAMUX1 */
661
662 /* Change the DMA state */
663 hdma->State = HAL_DMA_STATE_READY;
664
665 /* Process Unlocked */
666 __HAL_UNLOCK(hdma);
667
668 /* Call User Abort callback */
669 if(hdma->XferAbortCallback != NULL)
670 {
671 hdma->XferAbortCallback(hdma);
672 }
673 }
674 return status;
675 }
676
677 /**
678 * @brief Polling for transfer complete.
679 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
680 * the configuration information for the specified DMA Channel.
681 * @param CompleteLevel Specifies the DMA level complete.
682 * @param Timeout Timeout duration.
683 * @retval HAL status
684 */
HAL_DMA_PollForTransfer(DMA_HandleTypeDef * hdma,HAL_DMA_LevelCompleteTypeDef CompleteLevel,uint32_t Timeout)685 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
686 {
687 uint32_t temp;
688 uint32_t tickstart;
689
690 if(HAL_DMA_STATE_BUSY != hdma->State)
691 {
692 /* no transfer ongoing */
693 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
694 __HAL_UNLOCK(hdma);
695 return HAL_ERROR;
696 }
697
698 /* Polling mode not supported in circular mode */
699 if (0U != (hdma->Instance->CCR & DMA_CCR_CIRC))
700 {
701 hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
702 return HAL_ERROR;
703 }
704
705 /* Get the level transfer complete flag */
706 if (HAL_DMA_FULL_TRANSFER == CompleteLevel)
707 {
708 /* Transfer Complete flag */
709 temp = DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1cU);
710 }
711 else
712 {
713 /* Half Transfer Complete flag */
714 temp = DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1cU);
715 }
716
717 /* Get tick */
718 tickstart = HAL_GetTick();
719
720 while(0U == (hdma->DmaBaseAddress->ISR & temp))
721 {
722 if((0U != (hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << (hdma->ChannelIndex& 0x1cU)))))
723 {
724 /* When a DMA transfer error occurs */
725 /* A hardware clear of its EN bits is performed */
726 /* Clear all flags */
727 hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU));
728
729 /* Update error code */
730 hdma->ErrorCode = HAL_DMA_ERROR_TE;
731
732 /* Change the DMA state */
733 hdma->State= HAL_DMA_STATE_READY;
734
735 /* Process Unlocked */
736 __HAL_UNLOCK(hdma);
737
738 return HAL_ERROR;
739 }
740 /* Check for the Timeout */
741 if(Timeout != HAL_MAX_DELAY)
742 {
743 if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
744 {
745 /* Update error code */
746 hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
747
748 /* Change the DMA state */
749 hdma->State = HAL_DMA_STATE_READY;
750
751 /* Process Unlocked */
752 __HAL_UNLOCK(hdma);
753
754 return HAL_ERROR;
755 }
756 }
757 }
758
759 #if defined(DMAMUX1)
760 /*Check for DMAMUX Request generator (if used) overrun status */
761 if(hdma->DMAmuxRequestGen != 0U)
762 {
763 /* if using DMAMUX request generator Check for DMAMUX request generator overrun */
764 if((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)
765 {
766 /* Disable the request gen overrun interrupt */
767 hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
768
769 /* Clear the DMAMUX request generator overrun flag */
770 hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
771
772 /* Update error code */
773 hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN;
774 }
775 }
776
777 /* Check for DMAMUX Synchronization overrun */
778 if((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)
779 {
780 /* Clear the DMAMUX synchro overrun flag */
781 hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
782
783 /* Update error code */
784 hdma->ErrorCode |= HAL_DMA_ERROR_SYNC;
785 }
786 #endif /* DMAMUX1 */
787
788 if(HAL_DMA_FULL_TRANSFER == CompleteLevel)
789 {
790 /* Clear the transfer complete flag */
791 hdma->DmaBaseAddress->IFCR = (DMA_FLAG_TC1 << (hdma->ChannelIndex& 0x1cU));
792
793 /* The selected Channelx EN bit is cleared (DMA is disabled and
794 all transfers are complete) */
795 hdma->State = HAL_DMA_STATE_READY;
796 }
797 else
798 {
799 /* Clear the half transfer complete flag */
800 hdma->DmaBaseAddress->IFCR = (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1cU));
801 }
802
803 /* Process unlocked */
804 __HAL_UNLOCK(hdma);
805
806 return HAL_OK;
807 }
808
809 /**
810 * @brief Handle DMA interrupt request.
811 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
812 * the configuration information for the specified DMA Channel.
813 * @retval None
814 */
HAL_DMA_IRQHandler(DMA_HandleTypeDef * hdma)815 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
816 {
817 uint32_t flag_it = hdma->DmaBaseAddress->ISR;
818 uint32_t source_it = hdma->Instance->CCR;
819
820 /* Half Transfer Complete Interrupt management ******************************/
821 if ((0U != (flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1cU)))) && (0U != (source_it & DMA_IT_HT)))
822 {
823 /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
824 if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
825 {
826 /* Disable the half transfer interrupt */
827 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
828 }
829 /* Clear the half transfer complete flag */
830 hdma->DmaBaseAddress->IFCR = DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1cU);
831
832 /* DMA peripheral state is not updated in Half Transfer */
833 /* but in Transfer Complete case */
834
835 if(hdma->XferHalfCpltCallback != NULL)
836 {
837 /* Half transfer callback */
838 hdma->XferHalfCpltCallback(hdma);
839 }
840 }
841
842 /* Transfer Complete Interrupt management ***********************************/
843 else if ((0U != (flag_it & (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1cU)))) && (0U != (source_it & DMA_IT_TC)))
844 {
845 if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
846 {
847 /* Disable the transfer complete and error interrupt */
848 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
849
850 /* Change the DMA state */
851 hdma->State = HAL_DMA_STATE_READY;
852 }
853 /* Clear the transfer complete flag */
854 hdma->DmaBaseAddress->IFCR = (DMA_ISR_TCIF1 << (hdma->ChannelIndex & 0x1cU));
855
856 /* Process Unlocked */
857 __HAL_UNLOCK(hdma);
858
859 if(hdma->XferCpltCallback != NULL)
860 {
861 /* Transfer complete callback */
862 hdma->XferCpltCallback(hdma);
863 }
864 }
865
866 /* Transfer Error Interrupt management **************************************/
867 else if ((0U != (flag_it & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1cU)))) && (0U != (source_it & DMA_IT_TE)))
868 {
869 /* When a DMA transfer error occurs */
870 /* A hardware clear of its EN bits is performed */
871 /* Disable ALL DMA IT */
872 __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
873
874 /* Clear all flags */
875 hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU));
876
877 /* Update error code */
878 hdma->ErrorCode = HAL_DMA_ERROR_TE;
879
880 /* Change the DMA state */
881 hdma->State = HAL_DMA_STATE_READY;
882
883 /* Process Unlocked */
884 __HAL_UNLOCK(hdma);
885
886 if (hdma->XferErrorCallback != NULL)
887 {
888 /* Transfer error callback */
889 hdma->XferErrorCallback(hdma);
890 }
891 }
892 else
893 {
894 /* Nothing To Do */
895 }
896 return;
897 }
898
899 /**
900 * @brief Register callbacks
901 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
902 * the configuration information for the specified DMA Channel.
903 * @param CallbackID User Callback identifer
904 * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
905 * @param pCallback pointer to private callbacsk function which has pointer to
906 * a DMA_HandleTypeDef structure as parameter.
907 * @retval HAL status
908 */
HAL_DMA_RegisterCallback(DMA_HandleTypeDef * hdma,HAL_DMA_CallbackIDTypeDef CallbackID,void (* pCallback)(DMA_HandleTypeDef * _hdma))909 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma))
910 {
911 HAL_StatusTypeDef status = HAL_OK;
912
913 /* Process locked */
914 __HAL_LOCK(hdma);
915
916 if(HAL_DMA_STATE_READY == hdma->State)
917 {
918 switch (CallbackID)
919 {
920 case HAL_DMA_XFER_CPLT_CB_ID:
921 hdma->XferCpltCallback = pCallback;
922 break;
923
924 case HAL_DMA_XFER_HALFCPLT_CB_ID:
925 hdma->XferHalfCpltCallback = pCallback;
926 break;
927
928 case HAL_DMA_XFER_ERROR_CB_ID:
929 hdma->XferErrorCallback = pCallback;
930 break;
931
932 case HAL_DMA_XFER_ABORT_CB_ID:
933 hdma->XferAbortCallback = pCallback;
934 break;
935
936 default:
937 status = HAL_ERROR;
938 break;
939 }
940 }
941 else
942 {
943 status = HAL_ERROR;
944 }
945
946 /* Release Lock */
947 __HAL_UNLOCK(hdma);
948
949 return status;
950 }
951
952 /**
953 * @brief UnRegister callbacks
954 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
955 * the configuration information for the specified DMA Channel.
956 * @param CallbackID User Callback identifer
957 * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
958 * @retval HAL status
959 */
HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef * hdma,HAL_DMA_CallbackIDTypeDef CallbackID)960 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
961 {
962 HAL_StatusTypeDef status = HAL_OK;
963
964 /* Process locked */
965 __HAL_LOCK(hdma);
966
967 if(HAL_DMA_STATE_READY == hdma->State)
968 {
969 switch (CallbackID)
970 {
971 case HAL_DMA_XFER_CPLT_CB_ID:
972 hdma->XferCpltCallback = NULL;
973 break;
974
975 case HAL_DMA_XFER_HALFCPLT_CB_ID:
976 hdma->XferHalfCpltCallback = NULL;
977 break;
978
979 case HAL_DMA_XFER_ERROR_CB_ID:
980 hdma->XferErrorCallback = NULL;
981 break;
982
983 case HAL_DMA_XFER_ABORT_CB_ID:
984 hdma->XferAbortCallback = NULL;
985 break;
986
987 case HAL_DMA_XFER_ALL_CB_ID:
988 hdma->XferCpltCallback = NULL;
989 hdma->XferHalfCpltCallback = NULL;
990 hdma->XferErrorCallback = NULL;
991 hdma->XferAbortCallback = NULL;
992 break;
993
994 default:
995 status = HAL_ERROR;
996 break;
997 }
998 }
999 else
1000 {
1001 status = HAL_ERROR;
1002 }
1003
1004 /* Release Lock */
1005 __HAL_UNLOCK(hdma);
1006
1007 return status;
1008 }
1009
1010 /**
1011 * @}
1012 */
1013
1014
1015
1016 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions
1017 * @brief Peripheral State and Errors functions
1018 *
1019 @verbatim
1020 ===============================================================================
1021 ##### Peripheral State and Errors functions #####
1022 ===============================================================================
1023 [..]
1024 This subsection provides functions allowing to
1025 (+) Check the DMA state
1026 (+) Get error code
1027
1028 @endverbatim
1029 * @{
1030 */
1031
1032 /**
1033 * @brief Return the DMA hande state.
1034 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
1035 * the configuration information for the specified DMA Channel.
1036 * @retval HAL state
1037 */
HAL_DMA_GetState(DMA_HandleTypeDef * hdma)1038 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
1039 {
1040 /* Return DMA handle state */
1041 return hdma->State;
1042 }
1043
1044 /**
1045 * @brief Return the DMA error code.
1046 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
1047 * the configuration information for the specified DMA Channel.
1048 * @retval DMA Error Code
1049 */
HAL_DMA_GetError(DMA_HandleTypeDef * hdma)1050 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
1051 {
1052 return hdma->ErrorCode;
1053 }
1054
1055 /**
1056 * @}
1057 */
1058
1059 /**
1060 * @}
1061 */
1062
1063 /** @addtogroup DMA_Private_Functions
1064 * @{
1065 */
1066
1067 /**
1068 * @brief Sets the DMA Transfer parameter.
1069 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
1070 * the configuration information for the specified DMA Channel.
1071 * @param SrcAddress The source memory Buffer address
1072 * @param DstAddress The destination memory Buffer address
1073 * @param DataLength The length of data to be transferred from source to destination
1074 * @retval HAL status
1075 */
DMA_SetConfig(DMA_HandleTypeDef * hdma,uint32_t SrcAddress,uint32_t DstAddress,uint32_t DataLength)1076 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
1077 {
1078 #if defined(DMAMUX1)
1079 /* Clear the DMAMUX synchro overrun flag */
1080 hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
1081
1082 if(hdma->DMAmuxRequestGen != 0U)
1083 {
1084 /* Clear the DMAMUX request generator overrun flag */
1085 hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
1086 }
1087 #endif
1088
1089 /* Clear all flags */
1090 hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU));
1091
1092 /* Configure DMA Channel data length */
1093 hdma->Instance->CNDTR = DataLength;
1094
1095 /* Memory to Peripheral */
1096 if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
1097 {
1098 /* Configure DMA Channel destination address */
1099 hdma->Instance->CPAR = DstAddress;
1100
1101 /* Configure DMA Channel source address */
1102 hdma->Instance->CMAR = SrcAddress;
1103 }
1104 /* Peripheral to Memory */
1105 else
1106 {
1107 /* Configure DMA Channel source address */
1108 hdma->Instance->CPAR = SrcAddress;
1109
1110 /* Configure DMA Channel destination address */
1111 hdma->Instance->CMAR = DstAddress;
1112 }
1113 }
1114
1115 #if defined(DMAMUX1)
1116
1117 /**
1118 * @brief Updates the DMA handle with the DMAMUX channel and status mask depending on channel number
1119 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
1120 * the configuration information for the specified DMA Channel.
1121 * @retval None
1122 */
DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef * hdma)1123 static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma)
1124 {
1125 uint32_t channel_number;
1126 DMAMUX_Channel_TypeDef *DMAMUX1_ChannelBase;
1127
1128 /* check if instance is not outside the DMA channel range */
1129 if ((uint32_t)hdma->Instance < (uint32_t)DMA2_Channel1)
1130 {
1131 /* DMA1 */
1132 DMAMUX1_ChannelBase = DMAMUX1_Channel0;
1133 }
1134 else
1135 {
1136 /* DMA2 */
1137 DMAMUX1_ChannelBase = DMAMUX1_Channel7;
1138 }
1139 channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U;
1140 hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX1_ChannelBase + ((hdma->ChannelIndex >> 2U) * ((uint32_t)DMAMUX1_Channel1 - (uint32_t)DMAMUX1_Channel0)));
1141 hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus;
1142 hdma->DMAmuxChannelStatusMask = 1UL << (channel_number & 0x1cU);
1143 }
1144
1145 /**
1146 * @brief Updates the DMA handle with the DMAMUX request generator params
1147 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
1148 * the configuration information for the specified DMA Channel.
1149 * @retval None
1150 */
1151
DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef * hdma)1152 static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma)
1153 {
1154 uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID;
1155
1156 /* DMA Channels are connected to DMAMUX1 request generator blocks*/
1157 hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U)));
1158
1159 hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus;
1160
1161 /* here "Request" is either DMA_REQUEST_GENERATOR0 to 4, i.e. <= 4*/
1162 hdma->DMAmuxRequestGenStatusMask = 1UL << ((request - 1U) & 0x3U);
1163 }
1164
1165 #endif /* DMAMUX1 */
1166
1167 /**
1168 * @}
1169 */
1170
1171 /**
1172 * @}
1173 */
1174
1175 #endif /* HAL_DMA_MODULE_ENABLED */
1176 /**
1177 * @}
1178 */
1179
1180 /**
1181 * @}
1182 */
1183
1184 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1185
