1 /**
2 ******************************************************************************
3 * @file stm32l4xx_hal_cortex.c
4 * @author MCD Application Team
5 * @brief CORTEX HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the CORTEX:
8 * + Initialization and Configuration functions
9 * + Peripheral Control functions
10 *
11 @verbatim
12 ==============================================================================
13 ##### How to use this driver #####
14 ==============================================================================
15
16 [..]
17 *** How to configure Interrupts using CORTEX HAL driver ***
18 ===========================================================
19 [..]
20 This section provides functions allowing to configure the NVIC interrupts (IRQ).
21 The Cortex-M4 exceptions are managed by CMSIS functions.
22
23 (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function.
24 (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
25 (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
26
27 -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible.
28 The pending IRQ priority will be managed only by the sub priority.
29
30 -@- IRQ priority order (sorted by highest to lowest priority):
31 (+@) Lowest pre-emption priority
32 (+@) Lowest sub priority
33 (+@) Lowest hardware priority (IRQ number)
34
35 [..]
36 *** How to configure SysTick using CORTEX HAL driver ***
37 ========================================================
38 [..]
39 Setup SysTick Timer for time base.
40
41 (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
42 is a CMSIS function that:
43 (++) Configures the SysTick Reload register with value passed as function parameter.
44 (++) Configures the SysTick IRQ priority to the lowest value (0x0F).
45 (++) Resets the SysTick Counter register.
46 (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
47 (++) Enables the SysTick Interrupt.
48 (++) Starts the SysTick Counter.
49
50 (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
51 __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
52 HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
53 inside the stm32l4xx_hal_cortex.h file.
54
55 (+) You can change the SysTick IRQ priority by calling the
56 HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
57 call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
58
59 (+) To adjust the SysTick time base, use the following formula:
60
61 Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
62 (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
63 (++) Reload Value should not exceed 0xFFFFFF
64
65 @endverbatim
66 ******************************************************************************
67
68 The table below gives the allowed values of the pre-emption priority and subpriority according
69 to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function.
70
71 ==========================================================================================================================
72 NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
73 ==========================================================================================================================
74 NVIC_PRIORITYGROUP_0 | 0 | 0-15 | 0 bit for pre-emption priority
75 | | | 4 bits for subpriority
76 --------------------------------------------------------------------------------------------------------------------------
77 NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bit for pre-emption priority
78 | | | 3 bits for subpriority
79 --------------------------------------------------------------------------------------------------------------------------
80 NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
81 | | | 2 bits for subpriority
82 --------------------------------------------------------------------------------------------------------------------------
83 NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
84 | | | 1 bit for subpriority
85 --------------------------------------------------------------------------------------------------------------------------
86 NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bits for pre-emption priority
87 | | | 0 bit for subpriority
88 ==========================================================================================================================
89
90 ******************************************************************************
91 * @attention
92 *
93 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
94 *
95 * Redistribution and use in source and binary forms, with or without modification,
96 * are permitted provided that the following conditions are met:
97 * 1. Redistributions of source code must retain the above copyright notice,
98 * this list of conditions and the following disclaimer.
99 * 2. Redistributions in binary form must reproduce the above copyright notice,
100 * this list of conditions and the following disclaimer in the documentation
101 * and/or other materials provided with the distribution.
102 * 3. Neither the name of STMicroelectronics nor the names of its contributors
103 * may be used to endorse or promote products derived from this software
104 * without specific prior written permission.
105 *
106 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
107 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
108 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
109 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
110 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
111 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
112 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
113 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
114 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
115 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
116 *
117 ******************************************************************************
118 */
119
120 /* Includes ------------------------------------------------------------------*/
121 #include "stm32l4xx_hal.h"
122
123 /** @addtogroup STM32L4xx_HAL_Driver
124 * @{
125 */
126
127 /** @addtogroup CORTEX
128 * @{
129 */
130
131 #ifdef HAL_CORTEX_MODULE_ENABLED
132
133 /* Private types -------------------------------------------------------------*/
134 /* Private variables ---------------------------------------------------------*/
135 /* Private constants ---------------------------------------------------------*/
136 /* Private macros ------------------------------------------------------------*/
137 /* Private functions ---------------------------------------------------------*/
138 /* Exported functions --------------------------------------------------------*/
139
140 /** @addtogroup CORTEX_Exported_Functions
141 * @{
142 */
143
144
145 /** @addtogroup CORTEX_Exported_Functions_Group1
146 * @brief Initialization and Configuration functions
147 *
148 @verbatim
149 ==============================================================================
150 ##### Initialization and Configuration functions #####
151 ==============================================================================
152 [..]
153 This section provides the CORTEX HAL driver functions allowing to configure Interrupts
154 SysTick functionalities
155
156 @endverbatim
157 * @{
158 */
159
160
161 /**
162 * @brief Set the priority grouping field (pre-emption priority and subpriority)
163 * using the required unlock sequence.
164 * @param PriorityGroup: The priority grouping bits length.
165 * This parameter can be one of the following values:
166 * @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority,
167 * 4 bits for subpriority
168 * @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority,
169 * 3 bits for subpriority
170 * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority,
171 * 2 bits for subpriority
172 * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority,
173 * 1 bit for subpriority
174 * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority,
175 * 0 bit for subpriority
176 * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
177 * The pending IRQ priority will be managed only by the subpriority.
178 * @retval None
179 */
HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)180 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
181 {
182 /* Check the parameters */
183 assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
184
185 /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
186 NVIC_SetPriorityGrouping(PriorityGroup);
187 }
188
189 /**
190 * @brief Set the priority of an interrupt.
191 * @param IRQn: External interrupt number.
192 * This parameter can be an enumerator of IRQn_Type enumeration
193 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
194 * @param PreemptPriority: The pre-emption priority for the IRQn channel.
195 * This parameter can be a value between 0 and 15
196 * A lower priority value indicates a higher priority
197 * @param SubPriority: the subpriority level for the IRQ channel.
198 * This parameter can be a value between 0 and 15
199 * A lower priority value indicates a higher priority.
200 * @retval None
201 */
HAL_NVIC_SetPriority(IRQn_Type IRQn,uint32_t PreemptPriority,uint32_t SubPriority)202 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
203 {
204 uint32_t prioritygroup = 0x00;
205
206 /* Check the parameters */
207 assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
208 assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
209
210 prioritygroup = NVIC_GetPriorityGrouping();
211
212 NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
213 }
214
215 /**
216 * @brief Enable a device specific interrupt in the NVIC interrupt controller.
217 * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
218 * function should be called before.
219 * @param IRQn External interrupt number.
220 * This parameter can be an enumerator of IRQn_Type enumeration
221 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
222 * @retval None
223 */
HAL_NVIC_EnableIRQ(IRQn_Type IRQn)224 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
225 {
226 /* Check the parameters */
227 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
228
229 /* Enable interrupt */
230 NVIC_EnableIRQ(IRQn);
231 }
232
233 /**
234 * @brief Disable a device specific interrupt in the NVIC interrupt controller.
235 * @param IRQn External interrupt number.
236 * This parameter can be an enumerator of IRQn_Type enumeration
237 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
238 * @retval None
239 */
HAL_NVIC_DisableIRQ(IRQn_Type IRQn)240 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
241 {
242 /* Check the parameters */
243 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
244
245 /* Disable interrupt */
246 NVIC_DisableIRQ(IRQn);
247 }
248
249 /**
250 * @brief Initiate a system reset request to reset the MCU.
251 * @retval None
252 */
HAL_NVIC_SystemReset(void)253 void HAL_NVIC_SystemReset(void)
254 {
255 /* System Reset */
256 NVIC_SystemReset();
257 }
258
259 /**
260 * @brief Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick):
261 * Counter is in free running mode to generate periodic interrupts.
262 * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
263 * @retval status: - 0 Function succeeded.
264 * - 1 Function failed.
265 */
HAL_SYSTICK_Config(uint32_t TicksNumb)266 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
267 {
268 return SysTick_Config(TicksNumb);
269 }
270 /**
271 * @}
272 */
273
274 /** @addtogroup CORTEX_Exported_Functions_Group2
275 * @brief Cortex control functions
276 *
277 @verbatim
278 ==============================================================================
279 ##### Peripheral Control functions #####
280 ==============================================================================
281 [..]
282 This subsection provides a set of functions allowing to control the CORTEX
283 (NVIC, SYSTICK, MPU) functionalities.
284
285
286 @endverbatim
287 * @{
288 */
289
290 /**
291 * @brief Get the priority grouping field from the NVIC Interrupt Controller.
292 * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
293 */
HAL_NVIC_GetPriorityGrouping(void)294 uint32_t HAL_NVIC_GetPriorityGrouping(void)
295 {
296 /* Get the PRIGROUP[10:8] field value */
297 return NVIC_GetPriorityGrouping();
298 }
299
300 /**
301 * @brief Get the priority of an interrupt.
302 * @param IRQn: External interrupt number.
303 * This parameter can be an enumerator of IRQn_Type enumeration
304 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
305 * @param PriorityGroup: the priority grouping bits length.
306 * This parameter can be one of the following values:
307 * @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority,
308 * 4 bits for subpriority
309 * @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority,
310 * 3 bits for subpriority
311 * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority,
312 * 2 bits for subpriority
313 * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority,
314 * 1 bit for subpriority
315 * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority,
316 * 0 bit for subpriority
317 * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
318 * @param pSubPriority: Pointer on the Subpriority value (starting from 0).
319 * @retval None
320 */
HAL_NVIC_GetPriority(IRQn_Type IRQn,uint32_t PriorityGroup,uint32_t * pPreemptPriority,uint32_t * pSubPriority)321 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
322 {
323 /* Check the parameters */
324 assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
325 /* Get priority for Cortex-M system or device specific interrupts */
326 NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
327 }
328
329 /**
330 * @brief Set Pending bit of an external interrupt.
331 * @param IRQn External interrupt number
332 * This parameter can be an enumerator of IRQn_Type enumeration
333 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
334 * @retval None
335 */
HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)336 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
337 {
338 /* Check the parameters */
339 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
340
341 /* Set interrupt pending */
342 NVIC_SetPendingIRQ(IRQn);
343 }
344
345 /**
346 * @brief Get Pending Interrupt (read the pending register in the NVIC
347 * and return the pending bit for the specified interrupt).
348 * @param IRQn External interrupt number.
349 * This parameter can be an enumerator of IRQn_Type enumeration
350 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
351 * @retval status: - 0 Interrupt status is not pending.
352 * - 1 Interrupt status is pending.
353 */
HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)354 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
355 {
356 /* Check the parameters */
357 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
358
359 /* Return 1 if pending else 0 */
360 return NVIC_GetPendingIRQ(IRQn);
361 }
362
363 /**
364 * @brief Clear the pending bit of an external interrupt.
365 * @param IRQn External interrupt number.
366 * This parameter can be an enumerator of IRQn_Type enumeration
367 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
368 * @retval None
369 */
HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)370 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
371 {
372 /* Check the parameters */
373 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
374
375 /* Clear pending interrupt */
376 NVIC_ClearPendingIRQ(IRQn);
377 }
378
379 /**
380 * @brief Get active interrupt (read the active register in NVIC and return the active bit).
381 * @param IRQn External interrupt number
382 * This parameter can be an enumerator of IRQn_Type enumeration
383 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
384 * @retval status: - 0 Interrupt status is not pending.
385 * - 1 Interrupt status is pending.
386 */
HAL_NVIC_GetActive(IRQn_Type IRQn)387 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
388 {
389 /* Return 1 if active else 0 */
390 return NVIC_GetActive(IRQn);
391 }
392
393 /**
394 * @brief Configure the SysTick clock source.
395 * @param CLKSource: specifies the SysTick clock source.
396 * This parameter can be one of the following values:
397 * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
398 * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
399 * @retval None
400 */
HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)401 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
402 {
403 /* Check the parameters */
404 assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
405 if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
406 {
407 SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
408 }
409 else
410 {
411 SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
412 }
413 }
414
415 /**
416 * @brief Handle SYSTICK interrupt request.
417 * @retval None
418 */
HAL_SYSTICK_IRQHandler(void)419 void HAL_SYSTICK_IRQHandler(void)
420 {
421 HAL_SYSTICK_Callback();
422 }
423
424 /**
425 * @brief SYSTICK callback.
426 * @retval None
427 */
HAL_SYSTICK_Callback(void)428 __weak void HAL_SYSTICK_Callback(void)
429 {
430 /* NOTE : This function should not be modified, when the callback is needed,
431 the HAL_SYSTICK_Callback could be implemented in the user file
432 */
433 }
434
435 #if (__MPU_PRESENT == 1)
436 /**
437 * @brief Disable the MPU.
438 * @retval None
439 */
HAL_MPU_Disable(void)440 void HAL_MPU_Disable(void)
441 {
442 /* Make sure outstanding transfers are done */
443 __DMB();
444
445 /* Disable fault exceptions */
446 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
447
448 /* Disable the MPU and clear the control register*/
449 MPU->CTRL = 0U;
450 }
451
452 /**
453 * @brief Enable the MPU.
454 * @param MPU_Control: Specifies the control mode of the MPU during hard fault,
455 * NMI, FAULTMASK and privileged accessto the default memory
456 * This parameter can be one of the following values:
457 * @arg MPU_HFNMI_PRIVDEF_NONE
458 * @arg MPU_HARDFAULT_NMI
459 * @arg MPU_PRIVILEGED_DEFAULT
460 * @arg MPU_HFNMI_PRIVDEF
461 * @retval None
462 */
HAL_MPU_Enable(uint32_t MPU_Control)463 void HAL_MPU_Enable(uint32_t MPU_Control)
464 {
465 /* Enable the MPU */
466 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
467
468 /* Enable fault exceptions */
469 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
470
471 /* Ensure MPU settings take effects */
472 __DSB();
473 __ISB();
474 }
475
476 /**
477 * @brief Initialize and configure the Region and the memory to be protected.
478 * @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains
479 * the initialization and configuration information.
480 * @retval None
481 */
HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef * MPU_Init)482 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
483 {
484 /* Check the parameters */
485 assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
486 assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
487
488 /* Set the Region number */
489 MPU->RNR = MPU_Init->Number;
490
491 if ((MPU_Init->Enable) != RESET)
492 {
493 /* Check the parameters */
494 assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
495 assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
496 assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
497 assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
498 assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
499 assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
500 assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
501 assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
502
503 MPU->RBAR = MPU_Init->BaseAddress;
504 MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
505 ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
506 ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
507 ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
508 ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
509 ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
510 ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
511 ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
512 ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
513 }
514 else
515 {
516 MPU->RBAR = 0x00;
517 MPU->RASR = 0x00;
518 }
519 }
520 #endif /* __MPU_PRESENT */
521
522 /**
523 * @}
524 */
525
526 /**
527 * @}
528 */
529
530 #endif /* HAL_CORTEX_MODULE_ENABLED */
531 /**
532 * @}
533 */
534
535 /**
536 * @}
537 */
538
539 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
540
