1 /**
2 ******************************************************************************
3 * @file stm32l4xx_hal_adc.c
4 * @author MCD Application Team
5 * @brief This file provides firmware functions to manage the following
6 * functionalities of the Analog to Digital Convertor (ADC)
7 * peripheral:
8 * + Initialization and de-initialization functions
9 * ++ Initialization and Configuration of ADC
10 * + Operation functions
11 * ++ Start, stop, get result of conversions of regular
12 * group, using 3 possible modes: polling, interruption or DMA.
13 * + Control functions
14 * ++ Channels configuration on regular group
15 * ++ Analog Watchdog configuration
16 * + State functions
17 * ++ ADC state machine management
18 * ++ Interrupts and flags management
19 * Other functions (extended functions) are available in file
20 * "stm32l4xx_hal_adc_ex.c".
21 *
22 @verbatim
23 ==============================================================================
24 ##### ADC peripheral features #####
25 ==============================================================================
26 [..]
27 (+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution.
28
29 (+) Interrupt generation at the end of regular conversion and in case of
30 analog watchdog or overrun events.
31
32 (+) Single and continuous conversion modes.
33
34 (+) Scan mode for conversion of several channels sequentially.
35
36 (+) Data alignment with in-built data coherency.
37
38 (+) Programmable sampling time (channel wise)
39
40 (+) External trigger (timer or EXTI) with configurable polarity
41
42 (+) DMA request generation for transfer of conversions data of regular group.
43
44 (+) Configurable delay between conversions in Dual interleaved mode.
45
46 (+) ADC channels selectable single/differential input.
47
48 (+) ADC offset shared on 4 offset instances.
49 (+) ADC calibration
50
51 (+) ADC conversion of regular group.
52
53 (+) ADC supply requirements: 1.62 V to 3.6 V.
54
55 (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to
56 Vdda or to an external voltage reference).
57
58
59 ##### How to use this driver #####
60 ==============================================================================
61 [..]
62
63 *** Configuration of top level parameters related to ADC ***
64 ============================================================
65 [..]
66
67 (#) Enable the ADC interface
68 (++) As prerequisite, ADC clock must be configured at RCC top level.
69
70 (++) Two clock settings are mandatory:
71 (+++) ADC clock (core clock, also possibly conversion clock).
72
73 (+++) ADC clock (conversions clock).
74 Two possible clock sources: synchronous clock derived from APB clock
75 or asynchronous clock derived from system clock, PLLSAI1 or the PLLSAI2
76 running up to 80MHz.
77
78 (+++) Example:
79 Into HAL_ADC_MspInit() (recommended code location) or with
80 other device clock parameters configuration:
81 (+++) __HAL_RCC_ADC_CLK_ENABLE(); (mandatory)
82
83 RCC_ADCCLKSOURCE_PLL enable: (optional: if asynchronous clock selected)
84 (+++) RCC_PeriphClkInitTypeDef RCC_PeriphClkInit;
85 (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
86 (+++) PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_PLL;
87 (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
88
89 (++) ADC clock source and clock prescaler are configured at ADC level with
90 parameter "ClockPrescaler" using function HAL_ADC_Init().
91
92 (#) ADC pins configuration
93 (++) Enable the clock for the ADC GPIOs
94 using macro __HAL_RCC_GPIOx_CLK_ENABLE()
95 (++) Configure these ADC pins in analog mode
96 using function HAL_GPIO_Init()
97
98 (#) Optionally, in case of usage of ADC with interruptions:
99 (++) Configure the NVIC for ADC
100 using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
101 (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
102 into the function of corresponding ADC interruption vector
103 ADCx_IRQHandler().
104
105 (#) Optionally, in case of usage of DMA:
106 (++) Configure the DMA (DMA channel, mode normal or circular, ...)
107 using function HAL_DMA_Init().
108 (++) Configure the NVIC for DMA
109 using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
110 (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
111 into the function of corresponding DMA interruption vector
112 DMAx_Channelx_IRQHandler().
113
114 *** Configuration of ADC, group regular, channels parameters ***
115 ================================================================
116 [..]
117
118 (#) Configure the ADC parameters (resolution, data alignment, ...)
119 and regular group parameters (conversion trigger, sequencer, ...)
120 using function HAL_ADC_Init().
121
122 (#) Configure the channels for regular group parameters (channel number,
123 channel rank into sequencer, ..., into regular group)
124 using function HAL_ADC_ConfigChannel().
125
126 (#) Optionally, configure the analog watchdog parameters (channels
127 monitored, thresholds, ...)
128 using function HAL_ADC_AnalogWDGConfig().
129
130 *** Execution of ADC conversions ***
131 ====================================
132 [..]
133
134 (#) Optionally, perform an automatic ADC calibration to improve the
135 conversion accuracy
136 using function HAL_ADCEx_Calibration_Start().
137
138 (#) ADC driver can be used among three modes: polling, interruption,
139 transfer by DMA.
140
141 (++) ADC conversion by polling:
142 (+++) Activate the ADC peripheral and start conversions
143 using function HAL_ADC_Start()
144 (+++) Wait for ADC conversion completion
145 using function HAL_ADC_PollForConversion()
146 (+++) Retrieve conversion results
147 using function HAL_ADC_GetValue()
148 (+++) Stop conversion and disable the ADC peripheral
149 using function HAL_ADC_Stop()
150
151 (++) ADC conversion by interruption:
152 (+++) Activate the ADC peripheral and start conversions
153 using function HAL_ADC_Start_IT()
154 (+++) Wait for ADC conversion completion by call of function
155 HAL_ADC_ConvCpltCallback()
156 (this function must be implemented in user program)
157 (+++) Retrieve conversion results
158 using function HAL_ADC_GetValue()
159 (+++) Stop conversion and disable the ADC peripheral
160 using function HAL_ADC_Stop_IT()
161
162 (++) ADC conversion with transfer by DMA:
163 (+++) Activate the ADC peripheral and start conversions
164 using function HAL_ADC_Start_DMA()
165 (+++) Wait for ADC conversion completion by call of function
166 HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
167 (these functions must be implemented in user program)
168 (+++) Conversion results are automatically transferred by DMA into
169 destination variable address.
170 (+++) Stop conversion and disable the ADC peripheral
171 using function HAL_ADC_Stop_DMA()
172
173 [..]
174
175 (@) Callback functions must be implemented in user program:
176 (+@) HAL_ADC_ErrorCallback()
177 (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
178 (+@) HAL_ADC_ConvCpltCallback()
179 (+@) HAL_ADC_ConvHalfCpltCallback
180
181 *** Deinitialization of ADC ***
182 ============================================================
183 [..]
184
185 (#) Disable the ADC interface
186 (++) ADC clock can be hard reset and disabled at RCC top level.
187 (++) Hard reset of ADC peripherals
188 using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET().
189 (++) ADC clock disable
190 using the equivalent macro/functions as configuration step.
191 (+++) Example:
192 Into HAL_ADC_MspDeInit() (recommended code location) or with
193 other device clock parameters configuration:
194 (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI14;
195 (+++) RCC_OscInitStructure.HSI14State = RCC_HSI14_OFF; (if not used for system clock)
196 (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);
197
198 (#) ADC pins configuration
199 (++) Disable the clock for the ADC GPIOs
200 using macro __HAL_RCC_GPIOx_CLK_DISABLE()
201
202 (#) Optionally, in case of usage of ADC with interruptions:
203 (++) Disable the NVIC for ADC
204 using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
205
206 (#) Optionally, in case of usage of DMA:
207 (++) Deinitialize the DMA
208 using function HAL_DMA_Init().
209 (++) Disable the NVIC for DMA
210 using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
211
212 [..]
213
214 *** Callback registration ***
215 =============================================
216 [..]
217
218 The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1,
219 allows the user to configure dynamically the driver callbacks.
220 Use Functions @ref HAL_ADC_RegisterCallback()
221 to register an interrupt callback.
222 [..]
223
224 Function @ref HAL_ADC_RegisterCallback() allows to register following callbacks:
225 (+) ConvCpltCallback : ADC conversion complete callback
226 (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback
227 (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback
228 (+) ErrorCallback : ADC error callback
229 (+) InjectedConvCpltCallback : ADC group injected conversion complete callback
230 (+) InjectedQueueOverflowCallback : ADC group injected context queue overflow callback
231 (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback
232 (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback
233 (+) EndOfSamplingCallback : ADC end of sampling callback
234 (+) MspInitCallback : ADC Msp Init callback
235 (+) MspDeInitCallback : ADC Msp DeInit callback
236 This function takes as parameters the HAL peripheral handle, the Callback ID
237 and a pointer to the user callback function.
238 [..]
239
240 Use function @ref HAL_ADC_UnRegisterCallback to reset a callback to the default
241 weak function.
242 [..]
243
244 @ref HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle,
245 and the Callback ID.
246 This function allows to reset following callbacks:
247 (+) ConvCpltCallback : ADC conversion complete callback
248 (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback
249 (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback
250 (+) ErrorCallback : ADC error callback
251 (+) InjectedConvCpltCallback : ADC group injected conversion complete callback
252 (+) InjectedQueueOverflowCallback : ADC group injected context queue overflow callback
253 (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback
254 (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback
255 (+) EndOfSamplingCallback : ADC end of sampling callback
256 (+) MspInitCallback : ADC Msp Init callback
257 (+) MspDeInitCallback : ADC Msp DeInit callback
258 [..]
259
260 By default, after the @ref HAL_ADC_Init() and when the state is @ref HAL_ADC_STATE_RESET
261 all callbacks are set to the corresponding weak functions:
262 examples @ref HAL_ADC_ConvCpltCallback(), @ref HAL_ADC_ErrorCallback().
263 Exception done for MspInit and MspDeInit functions that are
264 reset to the legacy weak functions in the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() only when
265 these callbacks are null (not registered beforehand).
266 [..]
267
268 If MspInit or MspDeInit are not null, the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit()
269 keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
270 [..]
271
272 Callbacks can be registered/unregistered in @ref HAL_ADC_STATE_READY state only.
273 Exception done MspInit/MspDeInit functions that can be registered/unregistered
274 in @ref HAL_ADC_STATE_READY or @ref HAL_ADC_STATE_RESET state,
275 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
276 [..]
277
278 Then, the user first registers the MspInit/MspDeInit user callbacks
279 using @ref HAL_ADC_RegisterCallback() before calling @ref HAL_ADC_DeInit()
280 or @ref HAL_ADC_Init() function.
281 [..]
282
283 When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or
284 not defined, the callback registration feature is not available and all callbacks
285 are set to the corresponding weak functions.
286
287 @endverbatim
288 ******************************************************************************
289 * @attention
290 *
291 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
292 *
293 * Redistribution and use in source and binary forms, with or without modification,
294 * are permitted provided that the following conditions are met:
295 * 1. Redistributions of source code must retain the above copyright notice,
296 * this list of conditions and the following disclaimer.
297 * 2. Redistributions in binary form must reproduce the above copyright notice,
298 * this list of conditions and the following disclaimer in the documentation
299 * and/or other materials provided with the distribution.
300 * 3. Neither the name of STMicroelectronics nor the names of its contributors
301 * may be used to endorse or promote products derived from this software
302 * without specific prior written permission.
303 *
304 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
305 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
306 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
307 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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309 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
310 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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312 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
313 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
314 *
315 ******************************************************************************
316 */
317
318 /* Includes ------------------------------------------------------------------*/
319 #include "stm32l4xx_hal.h"
320
321 /** @addtogroup STM32L4xx_HAL_Driver
322 * @{
323 */
324
325 /** @defgroup ADC ADC
326 * @brief ADC HAL module driver
327 * @{
328 */
329
330 #ifdef HAL_ADC_MODULE_ENABLED
331
332 /* Private typedef -----------------------------------------------------------*/
333 /* Private define ------------------------------------------------------------*/
334
335 /** @defgroup ADC_Private_Constants ADC Private Constants
336 * @{
337 */
338
339 #define ADC_CFGR_FIELDS_1 ((ADC_CFGR_RES | ADC_CFGR_ALIGN |\
340 ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\
341 ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM |\
342 ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL)) /*!< ADC_CFGR fields of parameters that can be updated
343 when no regular conversion is on-going */
344
345 /* Timeout values for ADC operations (enable settling time, */
346 /* disable settling time, ...). */
347 /* Values defined to be higher than worst cases: low clock frequency, */
348 /* maximum prescalers. */
349 #define ADC_ENABLE_TIMEOUT (2UL) /*!< ADC enable time-out value */
350 #define ADC_DISABLE_TIMEOUT (2UL) /*!< ADC disable time-out value */
351
352 /* Timeout to wait for current conversion on going to be completed. */
353 /* Timeout fixed to longest ADC conversion possible, for 1 channel: */
354 /* - maximum sampling time (640.5 adc_clk) */
355 /* - ADC resolution (Tsar 12 bits= 12.5 adc_clk) */
356 /* - System clock / ADC clock <= 4096 (hypothesis of maximum clock ratio) */
357 /* - ADC oversampling ratio 256 */
358 /* Calculation: 653 * 4096 * 256 CPU clock cycles max */
359 /* Unit: cycles of CPU clock. */
360 #define ADC_CONVERSION_TIME_MAX_CPU_CYCLES (653UL * 4096UL * 256UL) /*!< ADC conversion completion time-out value */
361
362
363 /**
364 * @}
365 */
366
367 /* Private macro -------------------------------------------------------------*/
368 /* Private variables ---------------------------------------------------------*/
369 /* Private function prototypes -----------------------------------------------*/
370 /* Exported functions --------------------------------------------------------*/
371
372 /** @defgroup ADC_Exported_Functions ADC Exported Functions
373 * @{
374 */
375
376 /** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
377 * @brief ADC Initialization and Configuration functions
378 *
379 @verbatim
380 ===============================================================================
381 ##### Initialization and de-initialization functions #####
382 ===============================================================================
383 [..] This section provides functions allowing to:
384 (+) Initialize and configure the ADC.
385 (+) De-initialize the ADC.
386 @endverbatim
387 * @{
388 */
389
390 /**
391 * @brief Initialize the ADC peripheral and regular group according to
392 * parameters specified in structure "ADC_InitTypeDef".
393 * @note As prerequisite, ADC clock must be configured at RCC top level
394 * (refer to description of RCC configuration for ADC
395 * in header of this file).
396 * @note Possibility to update parameters on the fly:
397 * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
398 * coming from ADC state reset. Following calls to this function can
399 * be used to reconfigure some parameters of ADC_InitTypeDef
400 * structure on the fly, without modifying MSP configuration. If ADC
401 * MSP has to be modified again, HAL_ADC_DeInit() must be called
402 * before HAL_ADC_Init().
403 * The setting of these parameters is conditioned to ADC state.
404 * For parameters constraints, see comments of structure
405 * "ADC_InitTypeDef".
406 * @note This function configures the ADC within 2 scopes: scope of entire
407 * ADC and scope of regular group. For parameters details, see comments
408 * of structure "ADC_InitTypeDef".
409 * @note Parameters related to common ADC registers (ADC clock mode) are set
410 * only if all ADCs are disabled.
411 * If this is not the case, these common parameters setting are
412 * bypassed without error reporting: it can be the intended behaviour in
413 * case of update of a parameter of ADC_InitTypeDef on the fly,
414 * without disabling the other ADCs.
415 * @param hadc ADC handle
416 * @retval HAL status
417 */
HAL_ADC_Init(ADC_HandleTypeDef * hadc)418 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
419 {
420 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
421 uint32_t tmpCFGR;
422 uint32_t tmp_adc_reg_is_conversion_on_going;
423 __IO uint32_t wait_loop_index = 0;
424 uint32_t tmp_adc_is_conversion_on_going_regular;
425 uint32_t tmp_adc_is_conversion_on_going_injected;
426
427 /* Check ADC handle */
428 if(hadc == NULL)
429 {
430 return HAL_ERROR;
431 }
432
433 /* Check the parameters */
434 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
435 assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
436 assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
437 #if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0)
438 assert_param(IS_ADC_DFSDMCFG_MODE(hadc));
439 #endif
440 assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
441 assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
442 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
443 assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
444 assert_param(IS_ADC_EXTTRIG(hadc, hadc->Init.ExternalTrigConv));
445 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
446 assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
447 assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
448 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
449 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode));
450
451 if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
452 {
453 assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
454 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
455
456 if(hadc->Init.DiscontinuousConvMode == ENABLE)
457 {
458 assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion));
459 }
460 }
461
462 /* DISCEN and CONT bits cannot be set at the same time */
463 assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE)));
464
465 /* Actions performed only if ADC is coming from state reset: */
466 /* - Initialization of ADC MSP */
467 if(hadc->State == HAL_ADC_STATE_RESET)
468 {
469 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
470 /* Init the ADC Callback settings */
471 hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; /* Legacy weak callback */
472 hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; /* Legacy weak callback */
473 hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; /* Legacy weak callback */
474 hadc->ErrorCallback = HAL_ADC_ErrorCallback; /* Legacy weak callback */
475 hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; /* Legacy weak callback */
476 hadc->InjectedQueueOverflowCallback = HAL_ADCEx_InjectedQueueOverflowCallback; /* Legacy weak callback */
477 hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback; /* Legacy weak callback */
478 hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback; /* Legacy weak callback */
479 hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback; /* Legacy weak callback */
480
481 if (hadc->MspInitCallback == NULL)
482 {
483 hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
484 }
485
486 /* Init the low level hardware */
487 hadc->MspInitCallback(hadc);
488 #else
489 /* Init the low level hardware */
490 HAL_ADC_MspInit(hadc);
491 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
492
493 /* Set ADC error code to none */
494 ADC_CLEAR_ERRORCODE(hadc);
495
496 /* Initialize Lock */
497 hadc->Lock = HAL_UNLOCKED;
498 }
499
500 /* - Exit from deep-power-down mode and ADC voltage regulator enable */
501 if(LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL)
502 {
503 /* Disable ADC deep power down mode */
504 LL_ADC_DisableDeepPowerDown(hadc->Instance);
505
506 /* System was in deep power down mode, calibration must
507 be relaunched or a previously saved calibration factor
508 re-applied once the ADC voltage regulator is enabled */
509 }
510
511 if(LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
512 {
513 /* Enable ADC internal voltage regulator */
514 LL_ADC_EnableInternalRegulator(hadc->Instance);
515
516 /* Note: Variable divided by 2 to compensate partially */
517 /* CPU processing cycles, scaling in us split to not */
518 /* exceed 32 bits register capacity and handle low frequency. */
519 wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL)));
520 while(wait_loop_index != 0UL)
521 {
522 wait_loop_index--;
523 }
524 }
525
526 /* Verification that ADC voltage regulator is correctly enabled, whether */
527 /* or not ADC is coming from state reset (if any potential problem of */
528 /* clocking, voltage regulator would not be enabled). */
529 if(LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
530 {
531 /* Update ADC state machine to error */
532 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
533
534 /* Set ADC error code to ADC IP internal error */
535 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
536
537 tmp_hal_status = HAL_ERROR;
538 }
539
540 /* Configuration of ADC parameters if previous preliminary actions are */
541 /* correctly completed and if there is no conversion on going on regular */
542 /* group (ADC may already be enabled at this point if HAL_ADC_Init() is */
543 /* called to update a parameter on the fly). */
544 tmp_adc_reg_is_conversion_on_going = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
545
546 if( ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
547 && (tmp_adc_reg_is_conversion_on_going == 0UL)
548 )
549 {
550 /* Set ADC state */
551 ADC_STATE_CLR_SET(hadc->State,
552 HAL_ADC_STATE_REG_BUSY,
553 HAL_ADC_STATE_BUSY_INTERNAL);
554
555 /* Configuration of common ADC parameters */
556
557 /* Parameters update conditioned to ADC state: */
558 /* Parameters that can be updated only when ADC is disabled: */
559 /* - clock configuration */
560 if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
561 {
562 if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
563 {
564 /* Reset configuration of ADC common register CCR: */
565 /* */
566 /* - ADC clock mode and ACC prescaler (CKMODE and PRESC bits)are set */
567 /* according to adc->Init.ClockPrescaler. It selects the clock */
568 /* source and sets the clock division factor. */
569 /* */
570 /* Some parameters of this register are not reset, since they are set */
571 /* by other functions and must be kept in case of usage of this */
572 /* function on the fly (update of a parameter of ADC_InitTypeDef */
573 /* without needing to reconfigure all other ADC groups/channels */
574 /* parameters): */
575 /* - when multimode feature is available, multimode-related */
576 /* parameters: MDMA, DMACFG, DELAY, DUAL (set by API */
577 /* HAL_ADCEx_MultiModeConfigChannel() ) */
578 /* - internal measurement paths: Vbat, temperature sensor, Vref */
579 /* (set into HAL_ADC_ConfigChannel() or */
580 /* HAL_ADCEx_InjectedConfigChannel() ) */
581 LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance), hadc->Init.ClockPrescaler);
582 }
583 }
584
585 /* Configuration of ADC: */
586 /* - resolution Init.Resolution */
587 /* - data alignment Init.DataAlign */
588 /* - external trigger to start conversion Init.ExternalTrigConv */
589 /* - external trigger polarity Init.ExternalTrigConvEdge */
590 /* - continuous conversion mode Init.ContinuousConvMode */
591 /* - overrun Init.Overrun */
592 /* - discontinuous mode Init.DiscontinuousConvMode */
593 /* - discontinuous mode channel count Init.NbrOfDiscConversion */
594 tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
595 hadc->Init.Overrun |
596 hadc->Init.DataAlign |
597 hadc->Init.Resolution |
598 ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode) );
599
600 if (hadc->Init.DiscontinuousConvMode == ENABLE)
601 {
602 tmpCFGR |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion);
603 }
604
605 /* Enable external trigger if trigger selection is different of software */
606 /* start. */
607 /* Note: This configuration keeps the hardware feature of parameter */
608 /* ExternalTrigConvEdge "trigger edge none" equivalent to */
609 /* software start. */
610 if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
611 {
612 tmpCFGR |= ( (hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL)
613 | hadc->Init.ExternalTrigConvEdge
614 );
615 }
616
617 /* Update Configuration Register CFGR */
618 MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR);
619
620 /* Parameters update conditioned to ADC state: */
621 /* Parameters that can be updated when ADC is disabled or enabled without */
622 /* conversion on going on regular and injected groups: */
623 /* - DMA continuous request Init.DMAContinuousRequests */
624 /* - LowPowerAutoWait feature Init.LowPowerAutoWait */
625 /* - Oversampling parameters Init.Oversampling */
626 tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
627 tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
628 if ( (tmp_adc_is_conversion_on_going_regular == 0UL)
629 && (tmp_adc_is_conversion_on_going_injected == 0UL)
630 )
631 {
632 tmpCFGR = ( ADC_CFGR_DFSDM(hadc) |
633 ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) |
634 ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests) );
635
636 MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmpCFGR);
637
638 if (hadc->Init.OversamplingMode == ENABLE)
639 {
640 assert_param(IS_ADC_OVERSAMPLING_RATIO(hadc->Init.Oversampling.Ratio));
641 assert_param(IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversampling.RightBitShift));
642 assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversampling.TriggeredMode));
643 assert_param(IS_ADC_REGOVERSAMPLING_MODE(hadc->Init.Oversampling.OversamplingStopReset));
644
645 /* Configuration of Oversampler: */
646 /* - Oversampling Ratio */
647 /* - Right bit shift */
648 /* - Triggered mode */
649 /* - Oversampling mode (continued/resumed) */
650 MODIFY_REG(hadc->Instance->CFGR2,
651 ADC_CFGR2_OVSR |
652 ADC_CFGR2_OVSS |
653 ADC_CFGR2_TROVS |
654 ADC_CFGR2_ROVSM,
655 ADC_CFGR2_ROVSE |
656 hadc->Init.Oversampling.Ratio |
657 hadc->Init.Oversampling.RightBitShift |
658 hadc->Init.Oversampling.TriggeredMode |
659 hadc->Init.Oversampling.OversamplingStopReset
660 );
661 }
662 else
663 {
664 /* Disable ADC oversampling scope on ADC group regular */
665 CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE);
666 }
667
668 }
669
670 /* Configuration of regular group sequencer: */
671 /* - if scan mode is disabled, regular channels sequence length is set to */
672 /* 0x00: 1 channel converted (channel on regular rank 1) */
673 /* Parameter "NbrOfConversion" is discarded. */
674 /* Note: Scan mode is not present by hardware on this device, but */
675 /* emulated by software for alignment over all STM32 devices. */
676 /* - if scan mode is enabled, regular channels sequence length is set to */
677 /* parameter "NbrOfConversion". */
678
679 if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
680 {
681 /* Set number of ranks in regular group sequencer */
682 MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1));
683 }
684 else
685 {
686 CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L);
687 }
688
689 /* Initialize the ADC state */
690 /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */
691 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY);
692 }
693 else
694 {
695 /* Update ADC state machine to error */
696 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
697
698 tmp_hal_status = HAL_ERROR;
699 }
700
701 /* Return function status */
702 return tmp_hal_status;
703 }
704
705 /**
706 * @brief Deinitialize the ADC peripheral registers to their default reset
707 * values, with deinitialization of the ADC MSP.
708 * @note For devices with several ADCs: reset of ADC common registers is done
709 * only if all ADCs sharing the same common group are disabled.
710 * (function "HAL_ADC_MspDeInit()" is also called under the same conditions:
711 * all ADC instances use the same core clock at RCC level, disabling
712 * the core clock reset all ADC instances).
713 * If this is not the case, reset of these common parameters reset is
714 * bypassed without error reporting: it can be the intended behavior in
715 * case of reset of a single ADC while the other ADCs sharing the same
716 * common group is still running.
717 * @note By default, HAL_ADC_DeInit() set ADC in mode deep power-down:
718 * this saves more power by reducing leakage currents
719 * and is particularly interesting before entering MCU low-power modes.
720 * @param hadc ADC handle
721 * @retval HAL status
722 */
HAL_ADC_DeInit(ADC_HandleTypeDef * hadc)723 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
724 {
725 HAL_StatusTypeDef tmp_hal_status;
726
727 /* Check ADC handle */
728 if(hadc == NULL)
729 {
730 return HAL_ERROR;
731 }
732
733 /* Check the parameters */
734 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
735
736 /* Set ADC state */
737 SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
738
739 /* Stop potential conversion on going */
740 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
741
742 /* Disable ADC peripheral if conversions are effectively stopped */
743 /* Flush register JSQR: reset the queue sequencer when injected */
744 /* queue sequencer is enabled and ADC disabled. */
745 /* The software and hardware triggers of the injected sequence are both */
746 /* internally disabled just after the completion of the last valid */
747 /* injected sequence. */
748 SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQM);
749
750 /* Disable ADC peripheral if conversions are effectively stopped */
751 if (tmp_hal_status == HAL_OK)
752 {
753 /* Disable the ADC peripheral */
754 tmp_hal_status = ADC_Disable(hadc);
755
756 /* Check if ADC is effectively disabled */
757 if (tmp_hal_status == HAL_OK)
758 {
759 /* Change ADC state */
760 hadc->State = HAL_ADC_STATE_READY;
761 }
762 }
763
764 /* Note: HAL ADC deInit is done independently of ADC conversion stop */
765 /* and disable return status. In case of status fail, attempt to */
766 /* perform deinitialization anyway and it is up user code in */
767 /* in HAL_ADC_MspDeInit() to reset the ADC peripheral using */
768 /* system RCC hard reset. */
769
770 /* ========== Reset ADC registers ========== */
771 /* Reset register IER */
772 __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3 | ADC_IT_AWD2 | ADC_IT_AWD1 |
773 ADC_IT_JQOVF | ADC_IT_OVR |
774 ADC_IT_JEOS | ADC_IT_JEOC |
775 ADC_IT_EOS | ADC_IT_EOC |
776 ADC_IT_EOSMP | ADC_IT_RDY ) );
777
778 /* Reset register ISR */
779 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3 | ADC_FLAG_AWD2 | ADC_FLAG_AWD1 |
780 ADC_FLAG_JQOVF | ADC_FLAG_OVR |
781 ADC_FLAG_JEOS | ADC_FLAG_JEOC |
782 ADC_FLAG_EOS | ADC_FLAG_EOC |
783 ADC_FLAG_EOSMP | ADC_FLAG_RDY ) );
784
785 /* Reset register CR */
786 /* Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART,
787 ADC_CR_ADCAL, ADC_CR_ADDIS and ADC_CR_ADEN are in access mode "read-set":
788 no direct reset applicable.
789 Update CR register to reset value where doable by software */
790 CLEAR_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF);
791 SET_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD);
792
793 /* Reset register CFGR */
794 CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_FIELDS);
795 SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
796
797 /* Reset register CFGR2 */
798 CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSM | ADC_CFGR2_TROVS | ADC_CFGR2_OVSS |
799 ADC_CFGR2_OVSR | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE );
800
801 /* Reset register SMPR1 */
802 CLEAR_BIT(hadc->Instance->SMPR1, ADC_SMPR1_FIELDS);
803
804 /* Reset register SMPR2 */
805 CLEAR_BIT(hadc->Instance->SMPR2, ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16 |
806 ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13 |
807 ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10 );
808
809 /* Reset register TR1 */
810 CLEAR_BIT(hadc->Instance->TR1, ADC_TR1_HT1 | ADC_TR1_LT1);
811
812 /* Reset register TR2 */
813 CLEAR_BIT(hadc->Instance->TR2, ADC_TR2_HT2 | ADC_TR2_LT2);
814
815 /* Reset register TR3 */
816 CLEAR_BIT(hadc->Instance->TR3, ADC_TR3_HT3 | ADC_TR3_LT3);
817
818 /* Reset register SQR1 */
819 CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2 |
820 ADC_SQR1_SQ1 | ADC_SQR1_L);
821
822 /* Reset register SQR2 */
823 CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 |
824 ADC_SQR2_SQ6 | ADC_SQR2_SQ5);
825
826 /* Reset register SQR3 */
827 CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12 |
828 ADC_SQR3_SQ11 | ADC_SQR3_SQ10);
829
830 /* Reset register SQR4 */
831 CLEAR_BIT(hadc->Instance->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15);
832
833 /* Register JSQR was reset when the ADC was disabled */
834
835 /* Reset register DR */
836 /* bits in access mode read only, no direct reset applicable*/
837
838 /* Reset register OFR1 */
839 CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1);
840 /* Reset register OFR2 */
841 CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2);
842 /* Reset register OFR3 */
843 CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3);
844 /* Reset register OFR4 */
845 CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4);
846
847 /* Reset registers JDR1, JDR2, JDR3, JDR4 */
848 /* bits in access mode read only, no direct reset applicable*/
849
850 /* Reset register AWD2CR */
851 CLEAR_BIT(hadc->Instance->AWD2CR, ADC_AWD2CR_AWD2CH);
852
853 /* Reset register AWD3CR */
854 CLEAR_BIT(hadc->Instance->AWD3CR, ADC_AWD3CR_AWD3CH);
855
856 /* Reset register DIFSEL */
857 CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_DIFSEL);
858
859 /* Reset register CALFACT */
860 CLEAR_BIT(hadc->Instance->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
861
862
863 /* ========== Reset common ADC registers ========== */
864
865 /* Software is allowed to change common parameters only when all the other
866 ADCs are disabled. */
867 if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
868 {
869 /* Reset configuration of ADC common register CCR:
870 - clock mode: CKMODE, PRESCEN
871 - multimode related parameters (when this feature is available): MDMA,
872 DMACFG, DELAY, DUAL (set by HAL_ADCEx_MultiModeConfigChannel() API)
873 - internal measurement paths: Vbat, temperature sensor, Vref (set into
874 HAL_ADC_ConfigChannel() or HAL_ADCEx_InjectedConfigChannel() )
875 */
876 ADC_CLEAR_COMMON_CONTROL_REGISTER(hadc);
877 }
878
879 /* DeInit the low level hardware.
880
881 For example:
882 __HAL_RCC_ADC_FORCE_RESET();
883 __HAL_RCC_ADC_RELEASE_RESET();
884 __HAL_RCC_ADC_CLK_DISABLE();
885
886 Keep in mind that all ADCs use the same clock: disabling
887 the clock will reset all ADCs.
888
889 */
890 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
891 if (hadc->MspDeInitCallback == NULL)
892 {
893 hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
894 }
895
896 /* DeInit the low level hardware: RCC clock, NVIC */
897 hadc->MspDeInitCallback(hadc);
898 #else
899 /* DeInit the low level hardware: RCC clock, NVIC */
900 HAL_ADC_MspDeInit(hadc);
901 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
902
903 /* Set ADC error code to none */
904 ADC_CLEAR_ERRORCODE(hadc);
905
906 /* Reset injected channel configuration parameters */
907 hadc->InjectionConfig.ContextQueue = 0;
908 hadc->InjectionConfig.ChannelCount = 0;
909
910 /* Set ADC state */
911 hadc->State = HAL_ADC_STATE_RESET;
912
913 /* Process unlocked */
914 __HAL_UNLOCK(hadc);
915
916 /* Return function status */
917 return tmp_hal_status;
918 }
919
920 /**
921 * @brief Initialize the ADC MSP.
922 * @param hadc ADC handle
923 * @retval None
924 */
HAL_ADC_MspInit(ADC_HandleTypeDef * hadc)925 __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
926 {
927 /* Prevent unused argument(s) compilation warning */
928 UNUSED(hadc);
929
930 /* NOTE : This function should not be modified. When the callback is needed,
931 function HAL_ADC_MspInit must be implemented in the user file.
932 */
933 }
934
935 /**
936 * @brief DeInitialize the ADC MSP.
937 * @param hadc ADC handle
938 * @note All ADC instances use the same core clock at RCC level, disabling
939 * the core clock reset all ADC instances).
940 * @retval None
941 */
HAL_ADC_MspDeInit(ADC_HandleTypeDef * hadc)942 __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
943 {
944 /* Prevent unused argument(s) compilation warning */
945 UNUSED(hadc);
946
947 /* NOTE : This function should not be modified. When the callback is needed,
948 function HAL_ADC_MspDeInit must be implemented in the user file.
949 */
950 }
951
952 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
953 /**
954 * @brief Register a User ADC Callback
955 * To be used instead of the weak predefined callback
956 * @param hadc Pointer to a ADC_HandleTypeDef structure that contains
957 * the configuration information for the specified ADC.
958 * @param CallbackID ID of the callback to be registered
959 * This parameter can be one of the following values:
960 * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID
961 * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion complete callback ID
962 * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID
963 * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID
964 * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID
965 * @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID ADC group injected context queue overflow callback ID
966 * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog 2 callback ID
967 * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID ADC analog watchdog 3 callback ID
968 * @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID ADC end of sampling callback ID
969 * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID
970 * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID
971 * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID
972 * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID
973 * @param pCallback pointer to the Callback function
974 * @retval HAL status
975 */
HAL_ADC_RegisterCallback(ADC_HandleTypeDef * hadc,HAL_ADC_CallbackIDTypeDef CallbackID,pADC_CallbackTypeDef pCallback)976 HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback)
977 {
978 HAL_StatusTypeDef status = HAL_OK;
979
980 if (pCallback == NULL)
981 {
982 /* Update the error code */
983 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
984
985 return HAL_ERROR;
986 }
987
988 if ((hadc->State & HAL_ADC_STATE_READY) != 0UL)
989 {
990 switch (CallbackID)
991 {
992 case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
993 hadc->ConvCpltCallback = pCallback;
994 break;
995
996 case HAL_ADC_CONVERSION_HALF_CB_ID :
997 hadc->ConvHalfCpltCallback = pCallback;
998 break;
999
1000 case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
1001 hadc->LevelOutOfWindowCallback = pCallback;
1002 break;
1003
1004 case HAL_ADC_ERROR_CB_ID :
1005 hadc->ErrorCallback = pCallback;
1006 break;
1007
1008 case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
1009 hadc->InjectedConvCpltCallback = pCallback;
1010 break;
1011
1012 case HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID :
1013 hadc->InjectedQueueOverflowCallback = pCallback;
1014 break;
1015
1016 case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID :
1017 hadc->LevelOutOfWindow2Callback = pCallback;
1018 break;
1019
1020 case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID :
1021 hadc->LevelOutOfWindow3Callback = pCallback;
1022 break;
1023
1024 case HAL_ADC_END_OF_SAMPLING_CB_ID :
1025 hadc->EndOfSamplingCallback = pCallback;
1026 break;
1027
1028 case HAL_ADC_MSPINIT_CB_ID :
1029 hadc->MspInitCallback = pCallback;
1030 break;
1031
1032 case HAL_ADC_MSPDEINIT_CB_ID :
1033 hadc->MspDeInitCallback = pCallback;
1034 break;
1035
1036 default :
1037 /* Update the error code */
1038 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
1039
1040 /* Return error status */
1041 status = HAL_ERROR;
1042 break;
1043 }
1044 }
1045 else if (HAL_ADC_STATE_RESET == hadc->State)
1046 {
1047 switch (CallbackID)
1048 {
1049 case HAL_ADC_MSPINIT_CB_ID :
1050 hadc->MspInitCallback = pCallback;
1051 break;
1052
1053 case HAL_ADC_MSPDEINIT_CB_ID :
1054 hadc->MspDeInitCallback = pCallback;
1055 break;
1056
1057 default :
1058 /* Update the error code */
1059 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
1060
1061 /* Return error status */
1062 status = HAL_ERROR;
1063 break;
1064 }
1065 }
1066 else
1067 {
1068 /* Update the error code */
1069 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
1070
1071 /* Return error status */
1072 status = HAL_ERROR;
1073 }
1074
1075 return status;
1076 }
1077
1078 /**
1079 * @brief Unregister a ADC Callback
1080 * ADC callback is redirected to the weak predefined callback
1081 * @param hadc Pointer to a ADC_HandleTypeDef structure that contains
1082 * the configuration information for the specified ADC.
1083 * @param CallbackID ID of the callback to be unregistered
1084 * This parameter can be one of the following values:
1085 * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID
1086 * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion complete callback ID
1087 * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID
1088 * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID
1089 * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID
1090 * @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID ADC group injected context queue overflow callback ID
1091 * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog 2 callback ID
1092 * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID ADC analog watchdog 3 callback ID
1093 * @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID ADC end of sampling callback ID
1094 * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID
1095 * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID
1096 * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID
1097 * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID
1098 * @retval HAL status
1099 */
HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef * hadc,HAL_ADC_CallbackIDTypeDef CallbackID)1100 HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID)
1101 {
1102 HAL_StatusTypeDef status = HAL_OK;
1103
1104 if ((hadc->State & HAL_ADC_STATE_READY) != 0UL)
1105 {
1106 switch (CallbackID)
1107 {
1108 case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
1109 hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback;
1110 break;
1111
1112 case HAL_ADC_CONVERSION_HALF_CB_ID :
1113 hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback;
1114 break;
1115
1116 case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
1117 hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback;
1118 break;
1119
1120 case HAL_ADC_ERROR_CB_ID :
1121 hadc->ErrorCallback = HAL_ADC_ErrorCallback;
1122 break;
1123
1124 case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
1125 hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback;
1126 break;
1127
1128 case HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID :
1129 hadc->InjectedQueueOverflowCallback = HAL_ADCEx_InjectedQueueOverflowCallback;
1130 break;
1131
1132 case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID :
1133 hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback;
1134 break;
1135
1136 case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID :
1137 hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback;
1138 break;
1139
1140 case HAL_ADC_END_OF_SAMPLING_CB_ID :
1141 hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback;
1142 break;
1143
1144 case HAL_ADC_MSPINIT_CB_ID :
1145 hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
1146 break;
1147
1148 case HAL_ADC_MSPDEINIT_CB_ID :
1149 hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
1150 break;
1151
1152 default :
1153 /* Update the error code */
1154 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
1155
1156 /* Return error status */
1157 status = HAL_ERROR;
1158 break;
1159 }
1160 }
1161 else if (HAL_ADC_STATE_RESET == hadc->State)
1162 {
1163 switch (CallbackID)
1164 {
1165 case HAL_ADC_MSPINIT_CB_ID :
1166 hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
1167 break;
1168
1169 case HAL_ADC_MSPDEINIT_CB_ID :
1170 hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
1171 break;
1172
1173 default :
1174 /* Update the error code */
1175 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
1176
1177 /* Return error status */
1178 status = HAL_ERROR;
1179 break;
1180 }
1181 }
1182 else
1183 {
1184 /* Update the error code */
1185 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
1186
1187 /* Return error status */
1188 status = HAL_ERROR;
1189 }
1190
1191 return status;
1192 }
1193
1194 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
1195
1196 /**
1197 * @}
1198 */
1199
1200 /** @defgroup ADC_Exported_Functions_Group2 ADC Input and Output operation functions
1201 * @brief ADC IO operation functions
1202 *
1203 @verbatim
1204 ===============================================================================
1205 ##### IO operation functions #####
1206 ===============================================================================
1207 [..] This section provides functions allowing to:
1208 (+) Start conversion of regular group.
1209 (+) Stop conversion of regular group.
1210 (+) Poll for conversion complete on regular group.
1211 (+) Poll for conversion event.
1212 (+) Get result of regular channel conversion.
1213 (+) Start conversion of regular group and enable interruptions.
1214 (+) Stop conversion of regular group and disable interruptions.
1215 (+) Handle ADC interrupt request
1216 (+) Start conversion of regular group and enable DMA transfer.
1217 (+) Stop conversion of regular group and disable ADC DMA transfer.
1218 @endverbatim
1219 * @{
1220 */
1221
1222 /**
1223 * @brief Enable ADC, start conversion of regular group.
1224 * @note Interruptions enabled in this function: None.
1225 * @note Case of multimode enabled (when multimode feature is available):
1226 * if ADC is Slave, ADC is enabled but conversion is not started,
1227 * if ADC is master, ADC is enabled and multimode conversion is started.
1228 * @param hadc ADC handle
1229 * @retval HAL status
1230 */
HAL_ADC_Start(ADC_HandleTypeDef * hadc)1231 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
1232 {
1233 HAL_StatusTypeDef tmp_hal_status;
1234 #if defined(ADC_MULTIMODE_SUPPORT)
1235 const ADC_TypeDef *tmpADC_Master;
1236 uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
1237 #endif
1238
1239 /* Check the parameters */
1240 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1241
1242 /* Perform ADC enable and conversion start if no conversion is on going */
1243 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
1244 {
1245 /* Process locked */
1246 __HAL_LOCK(hadc);
1247
1248 /* Enable the ADC peripheral */
1249 tmp_hal_status = ADC_Enable(hadc);
1250
1251 /* Start conversion if ADC is effectively enabled */
1252 if (tmp_hal_status == HAL_OK)
1253 {
1254 /* Set ADC state */
1255 /* - Clear state bitfield related to regular group conversion results */
1256 /* - Set state bitfield related to regular operation */
1257 ADC_STATE_CLR_SET(hadc->State,
1258 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
1259 HAL_ADC_STATE_REG_BUSY);
1260
1261 #if defined(ADC_MULTIMODE_SUPPORT)
1262 /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
1263 - if ADC instance is master or if multimode feature is not available
1264 - if multimode setting is disabled (ADC instance slave in independent mode) */
1265 if ( (__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
1266 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
1267 )
1268 {
1269 CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
1270 }
1271 #endif
1272
1273 /* Set ADC error code */
1274 /* Check if a conversion is on going on ADC group injected */
1275 if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
1276 {
1277 /* Reset ADC error code fields related to regular conversions only */
1278 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
1279 }
1280 else
1281 {
1282 /* Reset all ADC error code fields */
1283 ADC_CLEAR_ERRORCODE(hadc);
1284 }
1285
1286 /* Clear ADC group regular conversion flag and overrun flag */
1287 /* (To ensure of no unknown state from potential previous ADC operations) */
1288 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
1289
1290 /* Process unlocked */
1291 /* Unlock before starting ADC conversions: in case of potential */
1292 /* interruption, to let the process to ADC IRQ Handler. */
1293 __HAL_UNLOCK(hadc);
1294
1295 /* Enable conversion of regular group. */
1296 /* If software start has been selected, conversion starts immediately. */
1297 /* If external trigger has been selected, conversion will start at next */
1298 /* trigger event. */
1299 /* Case of multimode enabled (when multimode feature is available): */
1300 /* - if ADC is slave and dual regular conversions are enabled, ADC is */
1301 /* enabled only (conversion is not started), */
1302 /* - if ADC is master, ADC is enabled and conversion is started. */
1303 #if defined(ADC_MULTIMODE_SUPPORT)
1304 if ( (__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
1305 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
1306 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
1307 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
1308 )
1309 {
1310 /* ADC instance is not a multimode slave instance with multimode regular conversions enabled */
1311 if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL)
1312 {
1313 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
1314 }
1315
1316 /* Start ADC group regular conversion */
1317 LL_ADC_REG_StartConversion(hadc->Instance);
1318 }
1319 else
1320 {
1321 /* ADC instance is a multimode slave instance with multimode regular conversions enabled */
1322 SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
1323 /* if Master ADC JAUTO bit is set, update Slave State in setting
1324 HAL_ADC_STATE_INJ_BUSY bit and in resetting HAL_ADC_STATE_INJ_EOC bit */
1325 tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
1326 if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != 0UL)
1327 {
1328 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
1329 }
1330
1331 }
1332 #else
1333 if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL)
1334 {
1335 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
1336 }
1337
1338 /* Start ADC group regular conversion */
1339 LL_ADC_REG_StartConversion(hadc->Instance);
1340 #endif
1341 }
1342 else
1343 {
1344 /* Process unlocked */
1345 __HAL_UNLOCK(hadc);
1346 }
1347 }
1348 else
1349 {
1350 tmp_hal_status = HAL_BUSY;
1351 }
1352
1353 /* Return function status */
1354 return tmp_hal_status;
1355 }
1356
1357 /**
1358 * @brief Stop ADC conversion of regular group (and injected channels in
1359 * case of auto_injection mode), disable ADC peripheral.
1360 * @note: ADC peripheral disable is forcing stop of potential
1361 * conversion on injected group. If injected group is under use, it
1362 * should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
1363 * @param hadc ADC handle
1364 * @retval HAL status.
1365 */
HAL_ADC_Stop(ADC_HandleTypeDef * hadc)1366 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
1367 {
1368 HAL_StatusTypeDef tmp_hal_status;
1369
1370 /* Check the parameters */
1371 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1372
1373 /* Process locked */
1374 __HAL_LOCK(hadc);
1375
1376 /* 1. Stop potential conversion on going, on ADC groups regular and injected */
1377 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
1378
1379 /* Disable ADC peripheral if conversions are effectively stopped */
1380 if (tmp_hal_status == HAL_OK)
1381 {
1382 /* 2. Disable the ADC peripheral */
1383 tmp_hal_status = ADC_Disable(hadc);
1384
1385 /* Check if ADC is effectively disabled */
1386 if (tmp_hal_status == HAL_OK)
1387 {
1388 /* Set ADC state */
1389 ADC_STATE_CLR_SET(hadc->State,
1390 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
1391 HAL_ADC_STATE_READY);
1392 }
1393 }
1394
1395 /* Process unlocked */
1396 __HAL_UNLOCK(hadc);
1397
1398 /* Return function status */
1399 return tmp_hal_status;
1400 }
1401
1402 /**
1403 * @brief Wait for regular group conversion to be completed.
1404 * @note ADC conversion flags EOS (end of sequence) and EOC (end of
1405 * conversion) are cleared by this function, with an exception:
1406 * if low power feature "LowPowerAutoWait" is enabled, flags are
1407 * not cleared to not interfere with this feature until data register
1408 * is read using function HAL_ADC_GetValue().
1409 * @note This function cannot be used in a particular setup: ADC configured
1410 * in DMA mode and polling for end of each conversion (ADC init
1411 * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV).
1412 * In this case, DMA resets the flag EOC and polling cannot be
1413 * performed on each conversion. Nevertheless, polling can still
1414 * be performed on the complete sequence (ADC init
1415 * parameter "EOCSelection" set to ADC_EOC_SEQ_CONV).
1416 * @param hadc ADC handle
1417 * @param Timeout Timeout value in millisecond.
1418 * @retval HAL status
1419 */
HAL_ADC_PollForConversion(ADC_HandleTypeDef * hadc,uint32_t Timeout)1420 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
1421 {
1422 uint32_t tickstart;
1423 uint32_t tmp_Flag_End;
1424 uint32_t tmp_cfgr;
1425 #if defined(ADC_MULTIMODE_SUPPORT)
1426 const ADC_TypeDef *tmpADC_Master;
1427 uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
1428 #endif
1429
1430 /* Check the parameters */
1431 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1432
1433 /* If end of conversion selected to end of sequence conversions */
1434 if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
1435 {
1436 tmp_Flag_End = ADC_FLAG_EOS;
1437 }
1438 /* If end of conversion selected to end of unitary conversion */
1439 else /* ADC_EOC_SINGLE_CONV */
1440 {
1441 /* Verification that ADC configuration is compliant with polling for */
1442 /* each conversion: */
1443 /* Particular case is ADC configured in DMA mode and ADC sequencer with */
1444 /* several ranks and polling for end of each conversion. */
1445 /* For code simplicity sake, this particular case is generalized to */
1446 /* ADC configured in DMA mode and and polling for end of each conversion. */
1447 #if defined(ADC_MULTIMODE_SUPPORT)
1448 if ( (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
1449 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
1450 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
1451 )
1452 {
1453 /* Check ADC DMA mode in independent mode on ADC group regular */
1454 if(READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN) != 0UL)
1455 {
1456 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
1457 return HAL_ERROR;
1458 }
1459 else
1460 {
1461 tmp_Flag_End = (ADC_FLAG_EOC);
1462 }
1463 }
1464 else
1465 {
1466 /* Check ADC DMA mode in multimode on ADC group regular */
1467 if (LL_ADC_GetMultiDMATransfer(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) != LL_ADC_MULTI_REG_DMA_EACH_ADC)
1468 {
1469 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
1470 return HAL_ERROR;
1471 }
1472 else
1473 {
1474 tmp_Flag_End = (ADC_FLAG_EOC);
1475 }
1476 }
1477 #else
1478 /* Check ADC DMA mode */
1479 if(READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN) != 0UL)
1480 {
1481 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
1482 return HAL_ERROR;
1483 }
1484 else
1485 {
1486 tmp_Flag_End = (ADC_FLAG_EOC);
1487 }
1488 #endif
1489 }
1490
1491 /* Get tick count */
1492 tickstart = HAL_GetTick();
1493
1494 /* Wait until End of unitary conversion or sequence conversions flag is raised */
1495 while((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
1496 {
1497 /* Check if timeout is disabled (set to infinite wait) */
1498 if(Timeout != HAL_MAX_DELAY)
1499 {
1500 if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
1501 {
1502 /* Update ADC state machine to timeout */
1503 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
1504
1505 /* Process unlocked */
1506 __HAL_UNLOCK(hadc);
1507
1508 return HAL_TIMEOUT;
1509 }
1510 }
1511 }
1512
1513 /* Update ADC state machine */
1514 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
1515
1516 /* Determine whether any further conversion upcoming on group regular */
1517 /* by external trigger, continuous mode or scan sequence on going. */
1518 if( (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
1519 && (hadc->Init.ContinuousConvMode == DISABLE)
1520 )
1521 {
1522 /* Check whether end of sequence is reached */
1523 if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) )
1524 {
1525 /* Set ADC state */
1526 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
1527
1528 if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
1529 {
1530 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
1531 }
1532 }
1533 }
1534
1535 /* Get relevant register CFGR in ADC instance of ADC master or slave */
1536 /* in function of multimode state (for devices with multimode */
1537 /* available). */
1538 #if defined(ADC_MULTIMODE_SUPPORT)
1539 if ( (__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
1540 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
1541 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
1542 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
1543 )
1544 {
1545 /* Retrieve handle ADC CFGR register */
1546 tmp_cfgr = READ_REG(hadc->Instance->CFGR);
1547 }
1548 else
1549 {
1550 /* Retrieve Master ADC CFGR register */
1551 tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
1552 tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
1553 }
1554 #else
1555 /* Retrieve handle ADC CFGR register */
1556 tmp_cfgr = READ_REG(hadc->Instance->CFGR);
1557 #endif
1558
1559 /* Clear polled flag */
1560 if (tmp_Flag_End == ADC_FLAG_EOS)
1561 {
1562 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOS);
1563 }
1564 else
1565 {
1566 /* Clear end of conversion EOC flag of regular group if low power feature */
1567 /* "LowPowerAutoWait " is disabled, to not interfere with this feature */
1568 /* until data register is read using function HAL_ADC_GetValue(). */
1569 if (READ_BIT(tmp_cfgr, ADC_CFGR_AUTDLY) == 0UL)
1570 {
1571 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
1572 }
1573 }
1574
1575 /* Return function status */
1576 return HAL_OK;
1577 }
1578
1579 /**
1580 * @brief Poll for ADC event.
1581 * @param hadc ADC handle
1582 * @param EventType the ADC event type.
1583 * This parameter can be one of the following values:
1584 * @arg @ref ADC_EOSMP_EVENT ADC End of Sampling event
1585 * @arg @ref ADC_AWD1_EVENT ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 devices)
1586 * @arg @ref ADC_AWD2_EVENT ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 families)
1587 * @arg @ref ADC_AWD3_EVENT ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 families)
1588 * @arg @ref ADC_OVR_EVENT ADC Overrun event
1589 * @arg @ref ADC_JQOVF_EVENT ADC Injected context queue overflow event
1590 * @param Timeout Timeout value in millisecond.
1591 * @note The relevant flag is cleared if found to be set, except for ADC_FLAG_OVR.
1592 * Indeed, the latter is reset only if hadc->Init.Overrun field is set
1593 * to ADC_OVR_DATA_OVERWRITTEN. Otherwise, data register may be potentially overwritten
1594 * by a new converted data as soon as OVR is cleared.
1595 * To reset OVR flag once the preserved data is retrieved, the user can resort
1596 * to macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
1597 * @retval HAL status
1598 */
HAL_ADC_PollForEvent(ADC_HandleTypeDef * hadc,uint32_t EventType,uint32_t Timeout)1599 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
1600 {
1601 uint32_t tickstart;
1602
1603 /* Check the parameters */
1604 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1605 assert_param(IS_ADC_EVENT_TYPE(EventType));
1606
1607 /* Get tick count */
1608 tickstart = HAL_GetTick();
1609
1610 /* Check selected event flag */
1611 while(__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL)
1612 {
1613 /* Check if timeout is disabled (set to infinite wait) */
1614 if(Timeout != HAL_MAX_DELAY)
1615 {
1616 if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
1617 {
1618 /* Update ADC state machine to timeout */
1619 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
1620
1621 /* Process unlocked */
1622 __HAL_UNLOCK(hadc);
1623
1624 return HAL_TIMEOUT;
1625 }
1626 }
1627 }
1628
1629 switch(EventType)
1630 {
1631 /* End Of Sampling event */
1632 case ADC_EOSMP_EVENT:
1633 /* Set ADC state */
1634 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
1635
1636 /* Clear the End Of Sampling flag */
1637 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP);
1638
1639 break;
1640
1641 /* Analog watchdog (level out of window) event */
1642 /* Note: In case of several analog watchdog enabled, if needed to know */
1643 /* which one triggered and on which ADCx, test ADC state of analog watchdog */
1644 /* flags HAL_ADC_STATE_AWD1/2/3 using function "HAL_ADC_GetState()". */
1645 /* For example: */
1646 /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " */
1647 /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD2) != 0UL) " */
1648 /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD3) != 0UL) " */
1649
1650 /* Check analog watchdog 1 flag */
1651 case ADC_AWD_EVENT:
1652 /* Set ADC state */
1653 SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
1654
1655 /* Clear ADC analog watchdog flag */
1656 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
1657
1658 break;
1659
1660 /* Check analog watchdog 2 flag */
1661 case ADC_AWD2_EVENT:
1662 /* Set ADC state */
1663 SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
1664
1665 /* Clear ADC analog watchdog flag */
1666 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
1667
1668 break;
1669
1670 /* Check analog watchdog 3 flag */
1671 case ADC_AWD3_EVENT:
1672 /* Set ADC state */
1673 SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
1674
1675 /* Clear ADC analog watchdog flag */
1676 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
1677
1678 break;
1679
1680 /* Injected context queue overflow event */
1681 case ADC_JQOVF_EVENT:
1682 /* Set ADC state */
1683 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
1684
1685 /* Set ADC error code to Injected context queue overflow */
1686 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
1687
1688 /* Clear ADC Injected context queue overflow flag */
1689 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
1690
1691 break;
1692
1693 /* Overrun event */
1694 default: /* Case ADC_OVR_EVENT */
1695 /* If overrun is set to overwrite previous data, overrun event is not */
1696 /* considered as an error. */
1697 /* (cf ref manual "Managing conversions without using the DMA and without */
1698 /* overrun ") */
1699 if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
1700 {
1701 /* Set ADC state */
1702 SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
1703
1704 /* Set ADC error code to overrun */
1705 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
1706 }
1707 else
1708 {
1709 /* Clear ADC Overrun flag only if Overrun is set to ADC_OVR_DATA_OVERWRITTEN
1710 otherwise, data register is potentially overwritten by new converted data as soon
1711 as OVR is cleared. */
1712 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
1713 }
1714 break;
1715 }
1716
1717 /* Return function status */
1718 return HAL_OK;
1719 }
1720
1721 /**
1722 * @brief Enable ADC, start conversion of regular group with interruption.
1723 * @note Interruptions enabled in this function according to initialization
1724 * setting : EOC (end of conversion), EOS (end of sequence),
1725 * OVR overrun.
1726 * Each of these interruptions has its dedicated callback function.
1727 * @note Case of multimode enabled (when multimode feature is available):
1728 * HAL_ADC_Start_IT() must be called for ADC Slave first, then for
1729 * ADC Master.
1730 * For ADC Slave, ADC is enabled only (conversion is not started).
1731 * For ADC Master, ADC is enabled and multimode conversion is started.
1732 * @note To guarantee a proper reset of all interruptions once all the needed
1733 * conversions are obtained, HAL_ADC_Stop_IT() must be called to ensure
1734 * a correct stop of the IT-based conversions.
1735 * @note By default, HAL_ADC_Start_IT() does not enable the End Of Sampling
1736 * interruption. If required (e.g. in case of oversampling with trigger
1737 * mode), the user must:
1738 * 1. first clear the EOSMP flag if set with macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP)
1739 * 2. then enable the EOSMP interrupt with macro __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOSMP)
1740 * before calling HAL_ADC_Start_IT().
1741 * @param hadc ADC handle
1742 * @retval HAL status
1743 */
HAL_ADC_Start_IT(ADC_HandleTypeDef * hadc)1744 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
1745 {
1746 HAL_StatusTypeDef tmp_hal_status;
1747 #if defined(ADC_MULTIMODE_SUPPORT)
1748 const ADC_TypeDef *tmpADC_Master;
1749 uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
1750 #endif
1751
1752 /* Check the parameters */
1753 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1754
1755 /* Perform ADC enable and conversion start if no conversion is on going */
1756 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
1757 {
1758 /* Process locked */
1759 __HAL_LOCK(hadc);
1760
1761 /* Enable the ADC peripheral */
1762 tmp_hal_status = ADC_Enable(hadc);
1763
1764 /* Start conversion if ADC is effectively enabled */
1765 if (tmp_hal_status == HAL_OK)
1766 {
1767 /* Set ADC state */
1768 /* - Clear state bitfield related to regular group conversion results */
1769 /* - Set state bitfield related to regular operation */
1770 ADC_STATE_CLR_SET(hadc->State,
1771 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
1772 HAL_ADC_STATE_REG_BUSY);
1773
1774 #if defined(ADC_MULTIMODE_SUPPORT)
1775 /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
1776 - if ADC instance is master or if multimode feature is not available
1777 - if multimode setting is disabled (ADC instance slave in independent mode) */
1778 if ( (__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
1779 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
1780 )
1781 {
1782 CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
1783 }
1784 #endif
1785
1786 /* Set ADC error code */
1787 /* Check if a conversion is on going on ADC group injected */
1788 if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL)
1789 {
1790 /* Reset ADC error code fields related to regular conversions only */
1791 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR|HAL_ADC_ERROR_DMA));
1792 }
1793 else
1794 {
1795 /* Reset all ADC error code fields */
1796 ADC_CLEAR_ERRORCODE(hadc);
1797 }
1798
1799 /* Clear ADC group regular conversion flag and overrun flag */
1800 /* (To ensure of no unknown state from potential previous ADC operations) */
1801 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
1802
1803 /* Process unlocked */
1804 /* Unlock before starting ADC conversions: in case of potential */
1805 /* interruption, to let the process to ADC IRQ Handler. */
1806 __HAL_UNLOCK(hadc);
1807
1808 /* Disable all interruptions before enabling the desired ones */
1809 __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
1810
1811 /* Enable ADC end of conversion interrupt */
1812 switch(hadc->Init.EOCSelection)
1813 {
1814 case ADC_EOC_SEQ_CONV:
1815 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOS);
1816 break;
1817 /* case ADC_EOC_SINGLE_CONV */
1818 default:
1819 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC);
1820 break;
1821 }
1822
1823 /* Enable ADC overrun interrupt */
1824 /* If hadc->Init.Overrun is set to ADC_OVR_DATA_PRESERVED, only then is
1825 ADC_IT_OVR enabled; otherwise data overwrite is considered as normal
1826 behavior and no CPU time is lost for a non-processed interruption */
1827 if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
1828 {
1829 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
1830 }
1831
1832 /* Enable conversion of regular group. */
1833 /* If software start has been selected, conversion starts immediately. */
1834 /* If external trigger has been selected, conversion will start at next */
1835 /* trigger event. */
1836 /* Case of multimode enabled (when multimode feature is available): */
1837 /* - if ADC is slave and dual regular conversions are enabled, ADC is */
1838 /* enabled only (conversion is not started), */
1839 /* - if ADC is master, ADC is enabled and conversion is started. */
1840 #if defined(ADC_MULTIMODE_SUPPORT)
1841 if ( (__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
1842 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
1843 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
1844 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
1845 )
1846 {
1847 /* ADC instance is not a multimode slave instance with multimode regular conversions enabled */
1848 if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL)
1849 {
1850 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
1851
1852 /* Enable as well injected interruptions in case
1853 HAL_ADCEx_InjectedStart_IT() has not been called beforehand. This
1854 allows to start regular and injected conversions when JAUTO is
1855 set with a single call to HAL_ADC_Start_IT() */
1856 switch(hadc->Init.EOCSelection)
1857 {
1858 case ADC_EOC_SEQ_CONV:
1859 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
1860 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
1861 break;
1862 /* case ADC_EOC_SINGLE_CONV */
1863 default:
1864 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
1865 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
1866 break;
1867 }
1868 }
1869
1870 /* Start ADC group regular conversion */
1871 LL_ADC_REG_StartConversion(hadc->Instance);
1872 }
1873 else
1874 {
1875 /* ADC instance is a multimode slave instance with multimode regular conversions enabled */
1876 SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
1877 /* if Master ADC JAUTO bit is set, Slave injected interruptions
1878 are enabled nevertheless (for same reason as above) */
1879 tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
1880 if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != 0UL)
1881 {
1882 /* First, update Slave State in setting HAL_ADC_STATE_INJ_BUSY bit
1883 and in resetting HAL_ADC_STATE_INJ_EOC bit */
1884 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
1885 /* Next, set Slave injected interruptions */
1886 switch(hadc->Init.EOCSelection)
1887 {
1888 case ADC_EOC_SEQ_CONV:
1889 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
1890 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
1891 break;
1892 /* case ADC_EOC_SINGLE_CONV */
1893 default:
1894 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
1895 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
1896 break;
1897 }
1898 }
1899 }
1900 #else
1901 /* ADC instance is not a multimode slave instance with multimode regular conversions enabled */
1902 if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL)
1903 {
1904 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
1905
1906 /* Enable as well injected interruptions in case
1907 HAL_ADCEx_InjectedStart_IT() has not been called beforehand. This
1908 allows to start regular and injected conversions when JAUTO is
1909 set with a single call to HAL_ADC_Start_IT() */
1910 switch(hadc->Init.EOCSelection)
1911 {
1912 case ADC_EOC_SEQ_CONV:
1913 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
1914 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
1915 break;
1916 /* case ADC_EOC_SINGLE_CONV */
1917 default:
1918 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
1919 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
1920 break;
1921 }
1922 }
1923
1924 /* Start ADC group regular conversion */
1925 LL_ADC_REG_StartConversion(hadc->Instance);
1926 #endif
1927 }
1928 else
1929 {
1930 /* Process unlocked */
1931 __HAL_UNLOCK(hadc);
1932 }
1933
1934 }
1935 else
1936 {
1937 tmp_hal_status = HAL_BUSY;
1938 }
1939
1940 /* Return function status */
1941 return tmp_hal_status;
1942 }
1943
1944 /**
1945 * @brief Stop ADC conversion of regular group (and injected group in
1946 * case of auto_injection mode), disable interrution of
1947 * end-of-conversion, disable ADC peripheral.
1948 * @param hadc ADC handle
1949 * @retval HAL status.
1950 */
HAL_ADC_Stop_IT(ADC_HandleTypeDef * hadc)1951 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
1952 {
1953 HAL_StatusTypeDef tmp_hal_status;
1954
1955 /* Check the parameters */
1956 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1957
1958 /* Process locked */
1959 __HAL_LOCK(hadc);
1960
1961 /* 1. Stop potential conversion on going, on ADC groups regular and injected */
1962 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
1963
1964 /* Disable ADC peripheral if conversions are effectively stopped */
1965 if (tmp_hal_status == HAL_OK)
1966 {
1967 /* Disable ADC end of conversion interrupt for regular group */
1968 /* Disable ADC overrun interrupt */
1969 __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
1970
1971 /* 2. Disable the ADC peripheral */
1972 tmp_hal_status = ADC_Disable(hadc);
1973
1974 /* Check if ADC is effectively disabled */
1975 if (tmp_hal_status == HAL_OK)
1976 {
1977 /* Set ADC state */
1978 ADC_STATE_CLR_SET(hadc->State,
1979 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
1980 HAL_ADC_STATE_READY);
1981 }
1982 }
1983
1984 /* Process unlocked */
1985 __HAL_UNLOCK(hadc);
1986
1987 /* Return function status */
1988 return tmp_hal_status;
1989 }
1990
1991 /**
1992 * @brief Enable ADC, start conversion of regular group and transfer result through DMA.
1993 * @note Interruptions enabled in this function:
1994 * overrun (if applicable), DMA half transfer, DMA transfer complete.
1995 * Each of these interruptions has its dedicated callback function.
1996 * @note Case of multimode enabled (when multimode feature is available): HAL_ADC_Start_DMA()
1997 * is designed for single-ADC mode only. For multimode, the dedicated
1998 * HAL_ADCEx_MultiModeStart_DMA() function must be used.
1999 * @param hadc ADC handle
2000 * @param pData Destination Buffer address.
2001 * @param Length Number of data to be transferred from ADC peripheral to memory
2002 * @retval HAL status.
2003 */
HAL_ADC_Start_DMA(ADC_HandleTypeDef * hadc,uint32_t * pData,uint32_t Length)2004 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
2005 {
2006 HAL_StatusTypeDef tmp_hal_status;
2007 #if defined(ADC_MULTIMODE_SUPPORT)
2008 uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
2009 #endif
2010
2011 /* Check the parameters */
2012 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2013
2014 /* Perform ADC enable and conversion start if no conversion is on going */
2015 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
2016 {
2017 /* Process locked */
2018 __HAL_LOCK(hadc);
2019
2020 #if defined(ADC_MULTIMODE_SUPPORT)
2021 /* Ensure that multimode regular conversions are not enabled. */
2022 /* Otherwise, dedicated API HAL_ADCEx_MultiModeStart_DMA() must be used. */
2023 if ( (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
2024 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
2025 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
2026 )
2027 #endif
2028 {
2029 /* Enable the ADC peripheral */
2030 tmp_hal_status = ADC_Enable(hadc);
2031
2032 /* Start conversion if ADC is effectively enabled */
2033 if (tmp_hal_status == HAL_OK)
2034 {
2035 /* Set ADC state */
2036 /* - Clear state bitfield related to regular group conversion results */
2037 /* - Set state bitfield related to regular operation */
2038 ADC_STATE_CLR_SET(hadc->State,
2039 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
2040 HAL_ADC_STATE_REG_BUSY);
2041
2042 #if defined(ADC_MULTIMODE_SUPPORT)
2043 /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
2044 - if ADC instance is master or if multimode feature is not available
2045 - if multimode setting is disabled (ADC instance slave in independent mode) */
2046 if ( (__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
2047 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
2048 )
2049 {
2050 CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
2051 }
2052 #endif
2053
2054 /* Check if a conversion is on going on ADC group injected */
2055 if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL)
2056 {
2057 /* Reset ADC error code fields related to regular conversions only */
2058 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
2059 }
2060 else
2061 {
2062 /* Reset all ADC error code fields */
2063 ADC_CLEAR_ERRORCODE(hadc);
2064 }
2065
2066 /* Set the DMA transfer complete callback */
2067 hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
2068
2069 /* Set the DMA half transfer complete callback */
2070 hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
2071
2072 /* Set the DMA error callback */
2073 hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
2074
2075
2076 /* Manage ADC and DMA start: ADC overrun interruption, DMA start, */
2077 /* ADC start (in case of SW start): */
2078
2079 /* Clear regular group conversion flag and overrun flag */
2080 /* (To ensure of no unknown state from potential previous ADC */
2081 /* operations) */
2082 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
2083
2084 /* Process unlocked */
2085 /* Unlock before starting ADC conversions: in case of potential */
2086 /* interruption, to let the process to ADC IRQ Handler. */
2087 __HAL_UNLOCK(hadc);
2088
2089 /* With DMA, overrun event is always considered as an error even if
2090 hadc->Init.Overrun is set to ADC_OVR_DATA_OVERWRITTEN. Therefore,
2091 ADC_IT_OVR is enabled. */
2092 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
2093
2094 /* Enable ADC DMA mode */
2095 SET_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
2096
2097 /* Start the DMA channel */
2098 tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
2099
2100 /* Enable conversion of regular group. */
2101 /* If software start has been selected, conversion starts immediately. */
2102 /* If external trigger has been selected, conversion will start at next */
2103 /* trigger event. */
2104 /* Start ADC group regular conversion */
2105 LL_ADC_REG_StartConversion(hadc->Instance);
2106 }
2107 else
2108 {
2109 /* Process unlocked */
2110 __HAL_UNLOCK(hadc);
2111 }
2112
2113 }
2114 #if defined(ADC_MULTIMODE_SUPPORT)
2115 else
2116 {
2117 tmp_hal_status = HAL_ERROR;
2118 /* Process unlocked */
2119 __HAL_UNLOCK(hadc);
2120 }
2121 #endif
2122 }
2123 else
2124 {
2125 tmp_hal_status = HAL_BUSY;
2126 }
2127
2128 /* Return function status */
2129 return tmp_hal_status;
2130 }
2131
2132 /**
2133 * @brief Stop ADC conversion of regular group (and injected group in
2134 * case of auto_injection mode), disable ADC DMA transfer, disable
2135 * ADC peripheral.
2136 * @note: ADC peripheral disable is forcing stop of potential
2137 * conversion on ADC group injected. If ADC group injected is under use, it
2138 * should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
2139 * @note Case of multimode enabled (when multimode feature is available):
2140 * HAL_ADC_Stop_DMA() function is dedicated to single-ADC mode only.
2141 * For multimode, the dedicated HAL_ADCEx_MultiModeStop_DMA() API must be used.
2142 * @param hadc ADC handle
2143 * @retval HAL status.
2144 */
HAL_ADC_Stop_DMA(ADC_HandleTypeDef * hadc)2145 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
2146 {
2147 HAL_StatusTypeDef tmp_hal_status;
2148
2149 /* Check the parameters */
2150 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2151
2152 /* Process locked */
2153 __HAL_LOCK(hadc);
2154
2155 /* 1. Stop potential ADC group regular conversion on going */
2156 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
2157
2158 /* Disable ADC peripheral if conversions are effectively stopped */
2159 if (tmp_hal_status == HAL_OK)
2160 {
2161 /* Disable ADC DMA (ADC DMA configuration of continous requests is kept) */
2162 CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
2163
2164 /* Disable the DMA channel (in case of DMA in circular mode or stop */
2165 /* while DMA transfer is on going) */
2166 if(hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY)
2167 {
2168 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
2169
2170 /* Check if DMA channel effectively disabled */
2171 if (tmp_hal_status != HAL_OK)
2172 {
2173 /* Update ADC state machine to error */
2174 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
2175 }
2176 }
2177
2178 /* Disable ADC overrun interrupt */
2179 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
2180
2181 /* 2. Disable the ADC peripheral */
2182 /* Update "tmp_hal_status" only if DMA channel disabling passed, */
2183 /* to keep in memory a potential failing status. */
2184 if (tmp_hal_status == HAL_OK)
2185 {
2186 tmp_hal_status = ADC_Disable(hadc);
2187 }
2188 else
2189 {
2190 (void)ADC_Disable(hadc);
2191 }
2192
2193 /* Check if ADC is effectively disabled */
2194 if (tmp_hal_status == HAL_OK)
2195 {
2196 /* Set ADC state */
2197 ADC_STATE_CLR_SET(hadc->State,
2198 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
2199 HAL_ADC_STATE_READY);
2200 }
2201
2202 }
2203
2204 /* Process unlocked */
2205 __HAL_UNLOCK(hadc);
2206
2207 /* Return function status */
2208 return tmp_hal_status;
2209 }
2210
2211 /**
2212 * @brief Get ADC regular group conversion result.
2213 * @note Reading register DR automatically clears ADC flag EOC
2214 * (ADC group regular end of unitary conversion).
2215 * @note This function does not clear ADC flag EOS
2216 * (ADC group regular end of sequence conversion).
2217 * Occurrence of flag EOS rising:
2218 * - If sequencer is composed of 1 rank, flag EOS is equivalent
2219 * to flag EOC.
2220 * - If sequencer is composed of several ranks, during the scan
2221 * sequence flag EOC only is raised, at the end of the scan sequence
2222 * both flags EOC and EOS are raised.
2223 * To clear this flag, either use function:
2224 * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
2225 * model polling: @ref HAL_ADC_PollForConversion()
2226 * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
2227 * @param hadc ADC handle
2228 * @retval ADC group regular conversion data
2229 */
HAL_ADC_GetValue(ADC_HandleTypeDef * hadc)2230 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
2231 {
2232 /* Check the parameters */
2233 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2234
2235 /* Note: EOC flag is not cleared here by software because automatically */
2236 /* cleared by hardware when reading register DR. */
2237
2238 /* Return ADC converted value */
2239 return hadc->Instance->DR;
2240 }
2241
2242 /**
2243 * @brief Handle ADC interrupt request.
2244 * @param hadc ADC handle
2245 * @retval None
2246 */
HAL_ADC_IRQHandler(ADC_HandleTypeDef * hadc)2247 void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
2248 {
2249 uint32_t overrun_error = 0UL; /* flag set if overrun occurrence has to be considered as an error */
2250 uint32_t tmp_isr = hadc->Instance->ISR;
2251 uint32_t tmp_ier = hadc->Instance->IER;
2252 uint32_t tmp_adc_inj_is_trigger_source_sw_start;
2253 uint32_t tmp_adc_reg_is_trigger_source_sw_start;
2254 uint32_t tmp_cfgr;
2255 #if defined(ADC_MULTIMODE_SUPPORT)
2256 const ADC_TypeDef *tmpADC_Master;
2257 uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
2258 #endif
2259
2260 /* Check the parameters */
2261 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2262 assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
2263
2264 /* ========== Check End of Sampling flag for ADC group regular ========== */
2265 if(((tmp_isr & ADC_FLAG_EOSMP) == ADC_FLAG_EOSMP) && ((tmp_ier & ADC_IT_EOSMP) == ADC_IT_EOSMP))
2266 {
2267 /* Update state machine on end of sampling status if not in error state */
2268 if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
2269 {
2270 /* Set ADC state */
2271 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
2272 }
2273
2274 /* End Of Sampling callback */
2275 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2276 hadc->EndOfSamplingCallback(hadc);
2277 #else
2278 HAL_ADCEx_EndOfSamplingCallback(hadc);
2279 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2280
2281 /* Clear regular group conversion flag */
2282 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP );
2283 }
2284
2285 /* ====== Check ADC group regular end of unitary conversion sequence conversions ===== */
2286 if((((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) ||
2287 (((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS)) )
2288 {
2289 /* Update state machine on conversion status if not in error state */
2290 if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
2291 {
2292 /* Set ADC state */
2293 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
2294 }
2295
2296 /* Determine whether any further conversion upcoming on group regular */
2297 /* by external trigger, continuous mode or scan sequence on going */
2298 /* to disable interruption. */
2299 if(LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
2300 {
2301 /* Get relevant register CFGR in ADC instance of ADC master or slave */
2302 /* in function of multimode state (for devices with multimode */
2303 /* available). */
2304 #if defined(ADC_MULTIMODE_SUPPORT)
2305 if ( (__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
2306 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
2307 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
2308 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
2309 )
2310 {
2311 /* check CONT bit directly in handle ADC CFGR register */
2312 tmp_cfgr = READ_REG(hadc->Instance->CFGR);
2313 }
2314 else
2315 {
2316 /* else need to check Master ADC CONT bit */
2317 tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
2318 tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
2319 }
2320 #else
2321 tmp_cfgr = READ_REG(hadc->Instance->CFGR);
2322 #endif
2323
2324 /* Carry on if continuous mode is disabled */
2325 if (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) != ADC_CFGR_CONT)
2326 {
2327 /* If End of Sequence is reached, disable interrupts */
2328 if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) )
2329 {
2330 /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
2331 /* ADSTART==0 (no conversion on going) */
2332 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
2333 {
2334 /* Disable ADC end of sequence conversion interrupt */
2335 /* Note: Overrun interrupt was enabled with EOC interrupt in */
2336 /* HAL_Start_IT(), but is not disabled here because can be used */
2337 /* by overrun IRQ process below. */
2338 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
2339
2340 /* Set ADC state */
2341 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
2342
2343 if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
2344 {
2345 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
2346 }
2347 }
2348 else
2349 {
2350 /* Change ADC state to error state */
2351 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
2352
2353 /* Set ADC error code to ADC IP internal error */
2354 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
2355 }
2356 }
2357 }
2358 }
2359
2360 /* Conversion complete callback */
2361 /* Note: Into callback function "HAL_ADC_ConvCpltCallback()", */
2362 /* to determine if conversion has been triggered from EOC or EOS, */
2363 /* possibility to use: */
2364 /* " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */
2365 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2366 hadc->ConvCpltCallback(hadc);
2367 #else
2368 HAL_ADC_ConvCpltCallback(hadc);
2369 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2370
2371 /* Clear regular group conversion flag */
2372 /* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of */
2373 /* conversion flags clear induces the release of the preserved data.*/
2374 /* Therefore, if the preserved data value is needed, it must be */
2375 /* read preliminarily into HAL_ADC_ConvCpltCallback(). */
2376 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS) );
2377 }
2378
2379 /* ====== Check ADC group injected end of unitary conversion sequence conversions ===== */
2380 if( (((tmp_isr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) && ((tmp_ier & ADC_IT_JEOC) == ADC_IT_JEOC)) ||
2381 (((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) && ((tmp_ier & ADC_IT_JEOS) == ADC_IT_JEOS)) )
2382 {
2383 /* Update state machine on conversion status if not in error state */
2384 if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
2385 {
2386 /* Set ADC state */
2387 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
2388 }
2389
2390 /* Retrieve ADC configuration */
2391 tmp_adc_inj_is_trigger_source_sw_start = LL_ADC_INJ_IsTriggerSourceSWStart(hadc->Instance);
2392 tmp_adc_reg_is_trigger_source_sw_start = LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance);
2393 /* Get relevant register CFGR in ADC instance of ADC master or slave */
2394 /* in function of multimode state (for devices with multimode */
2395 /* available). */
2396 #if defined(ADC_MULTIMODE_SUPPORT)
2397 if ( (__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
2398 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
2399 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
2400 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
2401 )
2402 {
2403 tmp_cfgr = READ_REG(hadc->Instance->CFGR);
2404 }
2405 else
2406 {
2407 tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
2408 tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
2409 }
2410 #else
2411 tmp_cfgr = READ_REG(hadc->Instance->CFGR);
2412 #endif
2413
2414 /* Disable interruption if no further conversion upcoming by injected */
2415 /* external trigger or by automatic injected conversion with regular */
2416 /* group having no further conversion upcoming (same conditions as */
2417 /* regular group interruption disabling above), */
2418 /* and if injected scan sequence is completed. */
2419 if((tmp_adc_inj_is_trigger_source_sw_start != 0UL) ||
2420 ((READ_BIT (tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) &&
2421 ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) &&
2422 (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) == 0UL) ) ) )
2423 {
2424 /* If End of Sequence is reached, disable interrupts */
2425 if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
2426 {
2427 /* Particular case if injected contexts queue is enabled: */
2428 /* when the last context has been fully processed, JSQR is reset */
2429 /* by the hardware. Even if no injected conversion is planned to come */
2430 /* (queue empty, triggers are ignored), it can start again */
2431 /* immediately after setting a new context (JADSTART is still set). */
2432 /* Therefore, state of HAL ADC injected group is kept to busy. */
2433 if(READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL)
2434 {
2435 /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */
2436 /* JADSTART==0 (no conversion on going) */
2437 if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
2438 {
2439 /* Disable ADC end of sequence conversion interrupt */
2440 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS);
2441
2442 /* Set ADC state */
2443 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
2444
2445 if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL)
2446 {
2447 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
2448 }
2449 }
2450 else
2451 {
2452 /* Update ADC state machine to error */
2453 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
2454
2455 /* Set ADC error code to ADC IP internal error */
2456 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
2457 }
2458 }
2459 }
2460 }
2461
2462 /* Injected Conversion complete callback */
2463 /* Note: HAL_ADCEx_InjectedConvCpltCallback can resort to
2464 if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOS)) or
2465 if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOC)) to determine whether
2466 interruption has been triggered by end of conversion or end of
2467 sequence. */
2468 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2469 hadc->InjectedConvCpltCallback(hadc);
2470 #else
2471 HAL_ADCEx_InjectedConvCpltCallback(hadc);
2472 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2473
2474 /* Clear injected group conversion flag */
2475 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC | ADC_FLAG_JEOS);
2476 }
2477
2478 /* ========== Check Analog watchdog 1 flag ========== */
2479 if (((tmp_isr & ADC_FLAG_AWD1) == ADC_FLAG_AWD1) && ((tmp_ier & ADC_IT_AWD1) == ADC_IT_AWD1))
2480 {
2481 /* Set ADC state */
2482 SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
2483
2484 /* Level out of window 1 callback */
2485 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2486 hadc->LevelOutOfWindowCallback(hadc);
2487 #else
2488 HAL_ADC_LevelOutOfWindowCallback(hadc);
2489 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2490
2491 /* Clear ADC analog watchdog flag */
2492 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
2493 }
2494
2495 /* ========== Check analog watchdog 2 flag ========== */
2496 if (((tmp_isr & ADC_FLAG_AWD2) == ADC_FLAG_AWD2) && ((tmp_ier & ADC_IT_AWD2) == ADC_IT_AWD2))
2497 {
2498 /* Set ADC state */
2499 SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
2500
2501 /* Level out of window 2 callback */
2502 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2503 hadc->LevelOutOfWindow2Callback(hadc);
2504 #else
2505 HAL_ADCEx_LevelOutOfWindow2Callback(hadc);
2506 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2507
2508 /* Clear ADC analog watchdog flag */
2509 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
2510 }
2511
2512 /* ========== Check analog watchdog 3 flag ========== */
2513 if (((tmp_isr & ADC_FLAG_AWD3) == ADC_FLAG_AWD3) && ((tmp_ier & ADC_IT_AWD3) == ADC_IT_AWD3))
2514 {
2515 /* Set ADC state */
2516 SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
2517
2518 /* Level out of window 3 callback */
2519 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2520 hadc->LevelOutOfWindow3Callback(hadc);
2521 #else
2522 HAL_ADCEx_LevelOutOfWindow3Callback(hadc);
2523 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2524
2525 /* Clear ADC analog watchdog flag */
2526 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
2527 }
2528
2529 /* ========== Check Overrun flag ========== */
2530 if (((tmp_isr & ADC_FLAG_OVR) == ADC_FLAG_OVR) && ((tmp_ier & ADC_IT_OVR) == ADC_IT_OVR))
2531 {
2532 /* If overrun is set to overwrite previous data (default setting), */
2533 /* overrun event is not considered as an error. */
2534 /* (cf ref manual "Managing conversions without using the DMA and without */
2535 /* overrun ") */
2536 /* Exception for usage with DMA overrun event always considered as an */
2537 /* error. */
2538 if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
2539 {
2540 overrun_error = 1UL;
2541 }
2542 else
2543 {
2544 /* Check DMA configuration */
2545 #if defined(ADC_MULTIMODE_SUPPORT)
2546 if (tmp_multimode_config != LL_ADC_MULTI_INDEPENDENT)
2547 {
2548 /* Multimode (when feature is available) is enabled,
2549 Common Control Register MDMA bits must be checked. */
2550 if (LL_ADC_GetMultiDMATransfer(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) != LL_ADC_MULTI_REG_DMA_EACH_ADC)
2551 {
2552 overrun_error = 1UL;
2553 }
2554 }
2555 else
2556 #endif
2557 {
2558 /* Multimode not set or feature not available or ADC independent */
2559 if ((hadc->Instance->CFGR & ADC_CFGR_DMAEN) != 0UL)
2560 {
2561 overrun_error = 1UL;
2562 }
2563 }
2564 }
2565
2566 if (overrun_error == 1UL)
2567 {
2568 /* Change ADC state to error state */
2569 SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
2570
2571 /* Set ADC error code to overrun */
2572 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
2573
2574 /* Error callback */
2575 /* Note: In case of overrun, ADC conversion data is preserved until */
2576 /* flag OVR is reset. */
2577 /* Therefore, old ADC conversion data can be retrieved in */
2578 /* function "HAL_ADC_ErrorCallback()". */
2579 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2580 hadc->ErrorCallback(hadc);
2581 #else
2582 HAL_ADC_ErrorCallback(hadc);
2583 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2584 }
2585
2586 /* Clear ADC overrun flag */
2587 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
2588 }
2589
2590 /* ========== Check Injected context queue overflow flag ========== */
2591 if (((tmp_isr & ADC_FLAG_JQOVF) == ADC_FLAG_JQOVF) && ((tmp_ier & ADC_IT_JQOVF) == ADC_IT_JQOVF))
2592 {
2593 /* Change ADC state to overrun state */
2594 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
2595
2596 /* Set ADC error code to Injected context queue overflow */
2597 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
2598
2599 /* Clear the Injected context queue overflow flag */
2600 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
2601
2602 /* Injected context queue overflow callback */
2603 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2604 hadc->InjectedQueueOverflowCallback(hadc);
2605 #else
2606 HAL_ADCEx_InjectedQueueOverflowCallback(hadc);
2607 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2608 }
2609
2610 }
2611
2612 /**
2613 * @brief Conversion complete callback in non-blocking mode.
2614 * @param hadc ADC handle
2615 * @retval None
2616 */
HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef * hadc)2617 __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
2618 {
2619 /* Prevent unused argument(s) compilation warning */
2620 UNUSED(hadc);
2621
2622 /* NOTE : This function should not be modified. When the callback is needed,
2623 function HAL_ADC_ConvCpltCallback must be implemented in the user file.
2624 */
2625 }
2626
2627 /**
2628 * @brief Conversion DMA half-transfer callback in non-blocking mode.
2629 * @param hadc ADC handle
2630 * @retval None
2631 */
HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef * hadc)2632 __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
2633 {
2634 /* Prevent unused argument(s) compilation warning */
2635 UNUSED(hadc);
2636
2637 /* NOTE : This function should not be modified. When the callback is needed,
2638 function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
2639 */
2640 }
2641
2642 /**
2643 * @brief Analog watchdog 1 callback in non-blocking mode.
2644 * @param hadc ADC handle
2645 * @retval None
2646 */
HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef * hadc)2647 __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
2648 {
2649 /* Prevent unused argument(s) compilation warning */
2650 UNUSED(hadc);
2651
2652 /* NOTE : This function should not be modified. When the callback is needed,
2653 function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file.
2654 */
2655 }
2656
2657 /**
2658 * @brief ADC error callback in non-blocking mode
2659 * (ADC conversion with interruption or transfer by DMA).
2660 * @note In case of error due to overrun when using ADC with DMA transfer
2661 * (HAL ADC handle parameter "ErrorCode" to state "HAL_ADC_ERROR_OVR"):
2662 * - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()".
2663 * - If needed, restart a new ADC conversion using function
2664 * "HAL_ADC_Start_DMA()"
2665 * (this function is also clearing overrun flag)
2666 * @param hadc ADC handle
2667 * @retval None
2668 */
HAL_ADC_ErrorCallback(ADC_HandleTypeDef * hadc)2669 __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
2670 {
2671 /* Prevent unused argument(s) compilation warning */
2672 UNUSED(hadc);
2673
2674 /* NOTE : This function should not be modified. When the callback is needed,
2675 function HAL_ADC_ErrorCallback must be implemented in the user file.
2676 */
2677 }
2678
2679 /**
2680 * @}
2681 */
2682
2683 /** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
2684 * @brief Peripheral Control functions
2685 *
2686 @verbatim
2687 ===============================================================================
2688 ##### Peripheral Control functions #####
2689 ===============================================================================
2690 [..] This section provides functions allowing to:
2691 (+) Configure channels on regular group
2692 (+) Configure the analog watchdog
2693
2694 @endverbatim
2695 * @{
2696 */
2697
2698 /**
2699 * @brief Configure a channel to be assigned to ADC group regular.
2700 * @note In case of usage of internal measurement channels:
2701 * Vbat/VrefInt/TempSensor.
2702 * These internal paths can be disabled using function
2703 * HAL_ADC_DeInit().
2704 * @note Possibility to update parameters on the fly:
2705 * This function initializes channel into ADC group regular,
2706 * following calls to this function can be used to reconfigure
2707 * some parameters of structure "ADC_ChannelConfTypeDef" on the fly,
2708 * without resetting the ADC.
2709 * The setting of these parameters is conditioned to ADC state:
2710 * Refer to comments of structure "ADC_ChannelConfTypeDef".
2711 * @param hadc ADC handle
2712 * @param sConfig Structure of ADC channel assigned to ADC group regular.
2713 * @retval HAL status
2714 */
HAL_ADC_ConfigChannel(ADC_HandleTypeDef * hadc,ADC_ChannelConfTypeDef * sConfig)2715 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
2716 {
2717 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
2718 uint32_t tmpOffsetShifted;
2719 uint32_t tmp_config_internal_channel;
2720 __IO uint32_t wait_loop_index = 0;
2721 uint32_t tmp_adc_is_conversion_on_going_regular;
2722 uint32_t tmp_adc_is_conversion_on_going_injected;
2723
2724 /* Check the parameters */
2725 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2726 assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
2727 assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
2728 assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfig->SingleDiff));
2729 assert_param(IS_ADC_OFFSET_NUMBER(sConfig->OffsetNumber));
2730 assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfig->Offset));
2731
2732 /* if ROVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is
2733 ignored (considered as reset) */
2734 assert_param(!((sConfig->OffsetNumber != ADC_OFFSET_NONE) && (hadc->Init.OversamplingMode == ENABLE)));
2735
2736 /* Verification of channel number */
2737 if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED)
2738 {
2739 assert_param(IS_ADC_CHANNEL(hadc, sConfig->Channel));
2740 }
2741 else
2742 {
2743 assert_param(IS_ADC_DIFF_CHANNEL(hadc, sConfig->Channel));
2744 }
2745
2746 /* Process locked */
2747 __HAL_LOCK(hadc);
2748
2749 /* Parameters update conditioned to ADC state: */
2750 /* Parameters that can be updated when ADC is disabled or enabled without */
2751 /* conversion on going on regular group: */
2752 /* - Channel number */
2753 /* - Channel rank */
2754 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
2755 {
2756 #if !defined (USE_FULL_ASSERT)
2757 /* Correspondence for compatibility with legacy definition of */
2758 /* sequencer ranks in direct number format. This correspondence can */
2759 /* be done only on ranks 1 to 5 due to literal values. */
2760 /* Note: Sequencer ranks in direct number format are no more used */
2761 /* and are detected by activating USE_FULL_ASSERT feature. */
2762 if (sConfig->Rank <= 5U)
2763 {
2764 switch (sConfig->Rank)
2765 {
2766 case 2U: sConfig->Rank = ADC_REGULAR_RANK_2; break;
2767 case 3U: sConfig->Rank = ADC_REGULAR_RANK_3; break;
2768 case 4U: sConfig->Rank = ADC_REGULAR_RANK_4; break;
2769 case 5U: sConfig->Rank = ADC_REGULAR_RANK_5; break;
2770 /* case 1U */
2771 default: sConfig->Rank = ADC_REGULAR_RANK_1; break;
2772 }
2773 }
2774 #endif
2775
2776 /* Set ADC group regular sequence: channel on the selected scan sequence rank */
2777 LL_ADC_REG_SetSequencerRanks(hadc->Instance, sConfig->Rank, sConfig->Channel);
2778
2779 /* Parameters update conditioned to ADC state: */
2780 /* Parameters that can be updated when ADC is disabled or enabled without */
2781 /* conversion on going on regular group: */
2782 /* - Channel sampling time */
2783 /* - Channel offset */
2784 tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
2785 tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
2786 if ( (tmp_adc_is_conversion_on_going_regular == 0UL)
2787 && (tmp_adc_is_conversion_on_going_injected == 0UL)
2788 )
2789 {
2790 #if defined(ADC_SMPR1_SMPPLUS)
2791 /* Manage specific case of sampling time 3.5 cycles replacing 2.5 cyles */
2792 if(sConfig->SamplingTime == ADC_SAMPLETIME_3CYCLES_5)
2793 {
2794 /* Set sampling time of the selected ADC channel */
2795 LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, LL_ADC_SAMPLINGTIME_2CYCLES_5);
2796
2797 /* Set ADC sampling time common configuration */
2798 LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5);
2799 }
2800 else
2801 {
2802 /* Set sampling time of the selected ADC channel */
2803 LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, sConfig->SamplingTime);
2804
2805 /* Set ADC sampling time common configuration */
2806 LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_DEFAULT);
2807 }
2808 #else
2809 /* Set sampling time of the selected ADC channel */
2810 LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, sConfig->SamplingTime);
2811 #endif
2812
2813 /* Configure the offset: offset enable/disable, channel, offset value */
2814
2815 /* Shift the offset with respect to the selected ADC resolution. */
2816 /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
2817 tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfig->Offset);
2818
2819 if(sConfig->OffsetNumber != ADC_OFFSET_NONE)
2820 {
2821 /* Set ADC selected offset number */
2822 LL_ADC_SetOffset(hadc->Instance, sConfig->OffsetNumber, sConfig->Channel, tmpOffsetShifted);
2823
2824 }
2825 else
2826 {
2827 /* Scan each offset register to check if the selected channel is targeted. */
2828 /* If this is the case, the corresponding offset number is disabled. */
2829 if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
2830 {
2831 LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE);
2832 }
2833 if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
2834 {
2835 LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE);
2836 }
2837 if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
2838 {
2839 LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE);
2840 }
2841 if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
2842 {
2843 LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE);
2844 }
2845 }
2846 }
2847
2848 /* Parameters update conditioned to ADC state: */
2849 /* Parameters that can be updated only when ADC is disabled: */
2850 /* - Single or differential mode */
2851 if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
2852 {
2853 /* Set mode single-ended or differential input of the selected ADC channel */
2854 LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfig->Channel, sConfig->SingleDiff);
2855
2856 /* Configuration of differential mode */
2857 if (sConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED)
2858 {
2859 /* Set sampling time of the selected ADC channel */
2860 /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */
2861 LL_ADC_SetChannelSamplingTime(hadc->Instance, __LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel) + 1UL) & 0x1FUL), sConfig->SamplingTime);
2862 }
2863
2864 }
2865
2866 /* Management of internal measurement channels: Vbat/VrefInt/TempSensor. */
2867 /* If internal channel selected, enable dedicated internal buffers and */
2868 /* paths. */
2869 /* Note: these internal measurement paths can be disabled using */
2870 /* HAL_ADC_DeInit(). */
2871
2872 if(__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))
2873 {
2874 tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
2875
2876 /* If the requested internal measurement path has already been enabled, */
2877 /* bypass the configuration processing. */
2878 if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
2879 {
2880 if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
2881 {
2882 LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel);
2883
2884 /* Delay for temperature sensor stabilization time */
2885 /* Wait loop initialization and execution */
2886 /* Note: Variable divided by 2 to compensate partially */
2887 /* CPU processing cycles, scaling in us split to not */
2888 /* exceed 32 bits register capacity and handle low frequency. */
2889 wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL)));
2890 while(wait_loop_index != 0UL)
2891 {
2892 wait_loop_index--;
2893 }
2894 }
2895 }
2896 else if ((sConfig->Channel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
2897 {
2898 if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
2899 {
2900 LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel);
2901 }
2902 }
2903 else if ((sConfig->Channel == ADC_CHANNEL_VREFINT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
2904 {
2905 if (ADC_VREFINT_INSTANCE(hadc))
2906 {
2907 LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel);
2908 }
2909 }
2910 else
2911 {
2912 /* nothing to do */
2913 }
2914 }
2915 }
2916
2917 /* If a conversion is on going on regular group, no update on regular */
2918 /* channel could be done on neither of the channel configuration structure */
2919 /* parameters. */
2920 else
2921 {
2922 /* Update ADC state machine to error */
2923 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
2924
2925 tmp_hal_status = HAL_ERROR;
2926 }
2927
2928 /* Process unlocked */
2929 __HAL_UNLOCK(hadc);
2930
2931 /* Return function status */
2932 return tmp_hal_status;
2933 }
2934
2935 /**
2936 * @brief Configure the analog watchdog.
2937 * @note Possibility to update parameters on the fly:
2938 * This function initializes the selected analog watchdog, successive
2939 * calls to this function can be used to reconfigure some parameters
2940 * of structure "ADC_AnalogWDGConfTypeDef" on the fly, without resetting
2941 * the ADC.
2942 * The setting of these parameters is conditioned to ADC state.
2943 * For parameters constraints, see comments of structure
2944 * "ADC_AnalogWDGConfTypeDef".
2945 * @note On this STM32 serie, analog watchdog thresholds cannot be modified
2946 * while ADC conversion is on going.
2947 * @param hadc ADC handle
2948 * @param AnalogWDGConfig Structure of ADC analog watchdog configuration
2949 * @retval HAL status
2950 */
HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef * hadc,ADC_AnalogWDGConfTypeDef * AnalogWDGConfig)2951 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
2952 {
2953 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
2954 uint32_t tmpAWDHighThresholdShifted;
2955 uint32_t tmpAWDLowThresholdShifted;
2956 uint32_t tmp_adc_is_conversion_on_going_regular;
2957 uint32_t tmp_adc_is_conversion_on_going_injected;
2958
2959 /* Check the parameters */
2960 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2961 assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(AnalogWDGConfig->WatchdogNumber));
2962 assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
2963 assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
2964
2965 if((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) ||
2966 (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) ||
2967 (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) )
2968 {
2969 assert_param(IS_ADC_CHANNEL(hadc, AnalogWDGConfig->Channel));
2970 }
2971
2972 /* Verify thresholds range */
2973 if (hadc->Init.OversamplingMode == ENABLE)
2974 {
2975 /* Case of oversampling enabled: depending on ratio and shift configuration,
2976 analog watchdog thresholds can be higher than ADC resolution.
2977 Verify if thresholds are within maximum thresholds range. */
2978 assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, AnalogWDGConfig->HighThreshold));
2979 assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, AnalogWDGConfig->LowThreshold));
2980 }
2981 else
2982 {
2983 /* Verify if thresholds are within the selected ADC resolution */
2984 assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold));
2985 assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold));
2986 }
2987
2988 /* Process locked */
2989 __HAL_LOCK(hadc);
2990
2991 /* Parameters update conditioned to ADC state: */
2992 /* Parameters that can be updated when ADC is disabled or enabled without */
2993 /* conversion on going on ADC groups regular and injected: */
2994 /* - Analog watchdog channels */
2995 /* - Analog watchdog thresholds */
2996 tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
2997 tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
2998 if ( (tmp_adc_is_conversion_on_going_regular == 0UL)
2999 && (tmp_adc_is_conversion_on_going_injected == 0UL)
3000 )
3001 {
3002 /* Analog watchdog configuration */
3003 if(AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1)
3004 {
3005 /* Configuration of analog watchdog: */
3006 /* - Set the analog watchdog enable mode: one or overall group of */
3007 /* channels, on groups regular and-or injected. */
3008 switch(AnalogWDGConfig->WatchdogMode)
3009 {
3010 case ADC_ANALOGWATCHDOG_SINGLE_REG:
3011 LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel, LL_ADC_GROUP_REGULAR));
3012 break;
3013
3014 case ADC_ANALOGWATCHDOG_SINGLE_INJEC:
3015 LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel, LL_ADC_GROUP_INJECTED));
3016 break;
3017
3018 case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC:
3019 LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel, LL_ADC_GROUP_REGULAR_INJECTED));
3020 break;
3021
3022 case ADC_ANALOGWATCHDOG_ALL_REG:
3023 LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG);
3024 break;
3025
3026 case ADC_ANALOGWATCHDOG_ALL_INJEC:
3027 LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_INJ);
3028 break;
3029
3030 case ADC_ANALOGWATCHDOG_ALL_REGINJEC:
3031 LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG_INJ);
3032 break;
3033
3034 default: /* ADC_ANALOGWATCHDOG_NONE */
3035 LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_DISABLE);
3036 break;
3037 }
3038
3039 /* Shift the offset in function of the selected ADC resolution: */
3040 /* Thresholds have to be left-aligned on bit 11, the LSB (right bits) */
3041 /* are set to 0 */
3042 tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
3043 tmpAWDLowThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
3044
3045 /* Set ADC analog watchdog thresholds value of both thresholds high and low */
3046 LL_ADC_ConfigAnalogWDThresholds(hadc->Instance, AnalogWDGConfig->WatchdogNumber, tmpAWDHighThresholdShifted, tmpAWDLowThresholdShifted);
3047
3048 /* Update state, clear previous result related to AWD1 */
3049 CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD1);
3050
3051 /* Clear flag ADC analog watchdog */
3052 /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */
3053 /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */
3054 /* (in case left enabled by previous ADC operations). */
3055 LL_ADC_ClearFlag_AWD1(hadc->Instance);
3056
3057 /* Configure ADC analog watchdog interrupt */
3058 if(AnalogWDGConfig->ITMode == ENABLE)
3059 {
3060 LL_ADC_EnableIT_AWD1(hadc->Instance);
3061 }
3062 else
3063 {
3064 LL_ADC_DisableIT_AWD1(hadc->Instance);
3065 }
3066 }
3067 /* Case of ADC_ANALOGWATCHDOG_2 or ADC_ANALOGWATCHDOG_3 */
3068 else
3069 {
3070 switch(AnalogWDGConfig->WatchdogMode)
3071 {
3072 case ADC_ANALOGWATCHDOG_SINGLE_REG:
3073 case ADC_ANALOGWATCHDOG_SINGLE_INJEC:
3074 case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC:
3075 /* Update AWD by bitfield to keep the possibility to monitor */
3076 /* several channels by successive calls of this function. */
3077 if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
3078 {
3079 SET_BIT(hadc->Instance->AWD2CR, (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel) & 0x1FUL)));
3080 }
3081 else
3082 {
3083 SET_BIT(hadc->Instance->AWD3CR, (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel) & 0x1FUL)));
3084 }
3085 break;
3086
3087 case ADC_ANALOGWATCHDOG_ALL_REG:
3088 case ADC_ANALOGWATCHDOG_ALL_INJEC:
3089 case ADC_ANALOGWATCHDOG_ALL_REGINJEC:
3090 LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, AnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_ALL_CHANNELS_REG_INJ);
3091 break;
3092
3093 default: /* ADC_ANALOGWATCHDOG_NONE */
3094 LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, AnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_DISABLE);
3095 break;
3096 }
3097
3098 /* Shift the thresholds in function of the selected ADC resolution */
3099 /* have to be left-aligned on bit 7, the LSB (right bits) are set to 0 */
3100 tmpAWDHighThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
3101 tmpAWDLowThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
3102
3103 /* Set ADC analog watchdog thresholds value of both thresholds high and low */
3104 LL_ADC_ConfigAnalogWDThresholds(hadc->Instance, AnalogWDGConfig->WatchdogNumber, tmpAWDHighThresholdShifted, tmpAWDLowThresholdShifted);
3105
3106 if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
3107 {
3108 /* Update state, clear previous result related to AWD2 */
3109 CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD2);
3110
3111 /* Clear flag ADC analog watchdog */
3112 /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */
3113 /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */
3114 /* (in case left enabled by previous ADC operations). */
3115 LL_ADC_ClearFlag_AWD2(hadc->Instance);
3116
3117 /* Configure ADC analog watchdog interrupt */
3118 if(AnalogWDGConfig->ITMode == ENABLE)
3119 {
3120 LL_ADC_EnableIT_AWD2(hadc->Instance);
3121 }
3122 else
3123 {
3124 LL_ADC_DisableIT_AWD2(hadc->Instance);
3125 }
3126 }
3127 /* (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */
3128 else
3129 {
3130 /* Update state, clear previous result related to AWD3 */
3131 CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD3);
3132
3133 /* Clear flag ADC analog watchdog */
3134 /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */
3135 /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */
3136 /* (in case left enabled by previous ADC operations). */
3137 LL_ADC_ClearFlag_AWD3(hadc->Instance);
3138
3139 /* Configure ADC analog watchdog interrupt */
3140 if(AnalogWDGConfig->ITMode == ENABLE)
3141 {
3142 LL_ADC_EnableIT_AWD3(hadc->Instance);
3143 }
3144 else
3145 {
3146 LL_ADC_DisableIT_AWD3(hadc->Instance);
3147 }
3148 }
3149 }
3150
3151 }
3152 /* If a conversion is on going on ADC group regular or injected, no update */
3153 /* could be done on neither of the AWD configuration structure parameters. */
3154 else
3155 {
3156 /* Update ADC state machine to error */
3157 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
3158
3159 tmp_hal_status = HAL_ERROR;
3160 }
3161 /* Process unlocked */
3162 __HAL_UNLOCK(hadc);
3163
3164 /* Return function status */
3165 return tmp_hal_status;
3166 }
3167
3168
3169 /**
3170 * @}
3171 */
3172
3173 /** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
3174 * @brief ADC Peripheral State functions
3175 *
3176 @verbatim
3177 ===============================================================================
3178 ##### Peripheral state and errors functions #####
3179 ===============================================================================
3180 [..]
3181 This subsection provides functions to get in run-time the status of the
3182 peripheral.
3183 (+) Check the ADC state
3184 (+) Check the ADC error code
3185
3186 @endverbatim
3187 * @{
3188 */
3189
3190 /**
3191 * @brief Return the ADC handle state.
3192 * @note ADC state machine is managed by bitfields, ADC status must be
3193 * compared with states bits.
3194 * For example:
3195 * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) "
3196 * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) "
3197 * @param hadc ADC handle
3198 * @retval ADC handle state (bitfield on 32 bits)
3199 */
HAL_ADC_GetState(ADC_HandleTypeDef * hadc)3200 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
3201 {
3202 /* Check the parameters */
3203 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
3204
3205 /* Return ADC handle state */
3206 return hadc->State;
3207 }
3208
3209 /**
3210 * @brief Return the ADC error code.
3211 * @param hadc ADC handle
3212 * @retval ADC error code (bitfield on 32 bits)
3213 */
HAL_ADC_GetError(ADC_HandleTypeDef * hadc)3214 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
3215 {
3216 /* Check the parameters */
3217 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
3218
3219 return hadc->ErrorCode;
3220 }
3221
3222 /**
3223 * @}
3224 */
3225
3226 /**
3227 * @}
3228 */
3229
3230 /** @defgroup ADC_Private_Functions ADC Private Functions
3231 * @{
3232 */
3233
3234 /**
3235 * @brief Stop ADC conversion.
3236 * @param hadc ADC handle
3237 * @param ConversionGroup ADC group regular and/or injected.
3238 * This parameter can be one of the following values:
3239 * @arg @ref ADC_REGULAR_GROUP ADC regular conversion type.
3240 * @arg @ref ADC_INJECTED_GROUP ADC injected conversion type.
3241 * @arg @ref ADC_REGULAR_INJECTED_GROUP ADC regular and injected conversion type.
3242 * @retval HAL status.
3243 */
ADC_ConversionStop(ADC_HandleTypeDef * hadc,uint32_t ConversionGroup)3244 HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t ConversionGroup)
3245 {
3246 uint32_t tickstart;
3247 uint32_t Conversion_Timeout_CPU_cycles = 0UL;
3248 uint32_t conversion_group_reassigned = ConversionGroup;
3249 uint32_t tmp_ADC_CR_ADSTART_JADSTART;
3250 uint32_t tmp_adc_is_conversion_on_going_regular;
3251 uint32_t tmp_adc_is_conversion_on_going_injected;
3252
3253 /* Check the parameters */
3254 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
3255 assert_param(IS_ADC_CONVERSION_GROUP(ConversionGroup));
3256
3257 /* Verification if ADC is not already stopped (on regular and injected */
3258 /* groups) to bypass this function if not needed. */
3259 tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
3260 tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
3261 if ( (tmp_adc_is_conversion_on_going_regular != 0UL)
3262 || (tmp_adc_is_conversion_on_going_injected != 0UL)
3263 )
3264 {
3265 /* Particular case of continuous auto-injection mode combined with */
3266 /* auto-delay mode. */
3267 /* In auto-injection mode, regular group stop ADC_CR_ADSTP is used (not */
3268 /* injected group stop ADC_CR_JADSTP). */
3269 /* Procedure to be followed: Wait until JEOS=1, clear JEOS, set ADSTP=1 */
3270 /* (see reference manual). */
3271 if ( ((hadc->Instance->CFGR & ADC_CFGR_JAUTO) != 0UL)
3272 && (hadc->Init.ContinuousConvMode == ENABLE)
3273 && (hadc->Init.LowPowerAutoWait == ENABLE)
3274 )
3275 {
3276 /* Use stop of regular group */
3277 conversion_group_reassigned = ADC_REGULAR_GROUP;
3278
3279 /* Wait until JEOS=1 (maximum Timeout: 4 injected conversions) */
3280 while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) == 0UL)
3281 {
3282 if (Conversion_Timeout_CPU_cycles >= (ADC_CONVERSION_TIME_MAX_CPU_CYCLES * 4UL))
3283 {
3284 /* Update ADC state machine to error */
3285 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
3286
3287 /* Set ADC error code to ADC IP internal error */
3288 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
3289
3290 return HAL_ERROR;
3291 }
3292 Conversion_Timeout_CPU_cycles ++;
3293 }
3294
3295 /* Clear JEOS */
3296 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOS);
3297 }
3298
3299 /* Stop potential conversion on going on ADC group regular */
3300 if (conversion_group_reassigned != ADC_INJECTED_GROUP)
3301 {
3302 /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */
3303 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
3304 {
3305 if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL)
3306 {
3307 /* Stop ADC group regular conversion */
3308 LL_ADC_REG_StopConversion(hadc->Instance);
3309 }
3310 }
3311 }
3312
3313 /* Stop potential conversion on going on ADC group injected */
3314 if (conversion_group_reassigned != ADC_REGULAR_GROUP)
3315 {
3316 /* Software is allowed to set JADSTP only when JADSTART=1 and ADDIS=0 */
3317 if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL)
3318 {
3319 if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL)
3320 {
3321 /* Stop ADC group injected conversion */
3322 LL_ADC_INJ_StopConversion(hadc->Instance);
3323 }
3324 }
3325 }
3326
3327 /* Selection of start and stop bits with respect to the regular or injected group */
3328 switch(conversion_group_reassigned)
3329 {
3330 case ADC_REGULAR_INJECTED_GROUP:
3331 tmp_ADC_CR_ADSTART_JADSTART = (ADC_CR_ADSTART | ADC_CR_JADSTART);
3332 break;
3333 case ADC_INJECTED_GROUP:
3334 tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_JADSTART;
3335 break;
3336 /* Case ADC_REGULAR_GROUP only*/
3337 default:
3338 tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_ADSTART;
3339 break;
3340 }
3341
3342 /* Wait for conversion effectively stopped */
3343 tickstart = HAL_GetTick();
3344
3345 while((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL)
3346 {
3347 if((HAL_GetTick()-tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
3348 {
3349 /* Update ADC state machine to error */
3350 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
3351
3352 /* Set ADC error code to ADC IP internal error */
3353 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
3354
3355 return HAL_ERROR;
3356 }
3357 }
3358
3359 }
3360
3361 /* Return HAL status */
3362 return HAL_OK;
3363 }
3364
3365
3366
3367 /**
3368 * @brief Enable the selected ADC.
3369 * @note Prerequisite condition to use this function: ADC must be disabled
3370 * and voltage regulator must be enabled (done into HAL_ADC_Init()).
3371 * @param hadc ADC handle
3372 * @retval HAL status.
3373 */
ADC_Enable(ADC_HandleTypeDef * hadc)3374 HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
3375 {
3376 uint32_t tickstart;
3377
3378 /* ADC enable and wait for ADC ready (in case of ADC is disabled or */
3379 /* enabling phase not yet completed: flag ADC ready not yet set). */
3380 /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */
3381 /* causes: ADC clock not running, ...). */
3382 if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
3383 {
3384 /* Check if conditions to enable the ADC are fulfilled */
3385 if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL)
3386 {
3387 /* Update ADC state machine to error */
3388 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
3389
3390 /* Set ADC error code to ADC IP internal error */
3391 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
3392
3393 return HAL_ERROR;
3394 }
3395
3396 /* Enable the ADC peripheral */
3397 LL_ADC_Enable(hadc->Instance);
3398
3399 /* Wait for ADC effectively enabled */
3400 tickstart = HAL_GetTick();
3401
3402 while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
3403 {
3404 /* If ADEN bit is set less than 4 ADC clock cycles after the ADCAL bit
3405 has been cleared (after a calibration), ADEN bit is reset by the
3406 calibration logic.
3407 The workaround is to continue setting ADEN until ADRDY is becomes 1.
3408 Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this
3409 4 ADC clock cycle duration */
3410 /* Note: Test of ADC enabled required due to hardware constraint to */
3411 /* not enable ADC if already enabled. */
3412 if(LL_ADC_IsEnabled(hadc->Instance) == 0UL)
3413 {
3414 LL_ADC_Enable(hadc->Instance);
3415 }
3416
3417 if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
3418 {
3419 /* Update ADC state machine to error */
3420 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
3421
3422 /* Set ADC error code to ADC IP internal error */
3423 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
3424
3425 return HAL_ERROR;
3426 }
3427 }
3428 }
3429
3430 /* Return HAL status */
3431 return HAL_OK;
3432 }
3433
3434 /**
3435 * @brief Disable the selected ADC.
3436 * @note Prerequisite condition to use this function: ADC conversions must be
3437 * stopped.
3438 * @param hadc ADC handle
3439 * @retval HAL status.
3440 */
ADC_Disable(ADC_HandleTypeDef * hadc)3441 HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc)
3442 {
3443 uint32_t tickstart;
3444 const uint32_t tmp_adc_is_disable_on_going = LL_ADC_IsDisableOngoing(hadc->Instance);
3445
3446 /* Verification if ADC is not already disabled: */
3447 /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */
3448 /* disabled. */
3449 if ( (LL_ADC_IsEnabled(hadc->Instance) != 0UL)
3450 && (tmp_adc_is_disable_on_going == 0UL)
3451 )
3452 {
3453 /* Check if conditions to disable the ADC are fulfilled */
3454 if((hadc->Instance->CR & (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN)
3455 {
3456 /* Disable the ADC peripheral */
3457 LL_ADC_Disable(hadc->Instance);
3458 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOSMP | ADC_FLAG_RDY));
3459 }
3460 else
3461 {
3462 /* Update ADC state machine to error */
3463 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
3464
3465 /* Set ADC error code to ADC IP internal error */
3466 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
3467
3468 return HAL_ERROR;
3469 }
3470
3471 /* Wait for ADC effectively disabled */
3472 /* Get tick count */
3473 tickstart = HAL_GetTick();
3474
3475 while((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
3476 {
3477 if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
3478 {
3479 /* Update ADC state machine to error */
3480 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
3481
3482 /* Set ADC error code to ADC IP internal error */
3483 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
3484
3485 return HAL_ERROR;
3486 }
3487 }
3488 }
3489
3490 /* Return HAL status */
3491 return HAL_OK;
3492 }
3493
3494 /**
3495 * @brief DMA transfer complete callback.
3496 * @param hdma pointer to DMA handle.
3497 * @retval None
3498 */
ADC_DMAConvCplt(DMA_HandleTypeDef * hdma)3499 void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
3500 {
3501 /* Retrieve ADC handle corresponding to current DMA handle */
3502 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
3503
3504 /* Update state machine on conversion status if not in error state */
3505 if((hadc->State & (HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) == 0UL)
3506 {
3507 /* Set ADC state */
3508 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
3509
3510 /* Determine whether any further conversion upcoming on group regular */
3511 /* by external trigger, continuous mode or scan sequence on going */
3512 /* to disable interruption. */
3513 /* Is it the end of the regular sequence ? */
3514 if ((hadc->Instance->ISR & ADC_FLAG_EOS) != 0UL)
3515 {
3516 /* Are conversions software-triggered ? */
3517 if(LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
3518 {
3519 /* Is CONT bit set ? */
3520 if(READ_BIT(hadc->Instance->CFGR, ADC_CFGR_CONT) == 0UL)
3521 {
3522 /* CONT bit is not set, no more conversions expected */
3523 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
3524 if((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
3525 {
3526 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
3527 }
3528 }
3529 }
3530 }
3531 else
3532 {
3533 /* DMA End of Transfer interrupt was triggered but conversions sequence
3534 is not over. If DMACFG is set to 0, conversions are stopped. */
3535 if(READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMACFG) == 0UL)
3536 {
3537 /* DMACFG bit is not set, conversions are stopped. */
3538 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
3539 if((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
3540 {
3541 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
3542 }
3543 }
3544 }
3545
3546 /* Conversion complete callback */
3547 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
3548 hadc->ConvCpltCallback(hadc);
3549 #else
3550 HAL_ADC_ConvCpltCallback(hadc);
3551 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
3552 }
3553 else /* DMA and-or internal error occurred */
3554 {
3555 if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL)
3556 {
3557 /* Call HAL ADC Error Callback function */
3558 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
3559 hadc->ErrorCallback(hadc);
3560 #else
3561 HAL_ADC_ErrorCallback(hadc);
3562 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
3563 }
3564 else
3565 {
3566 /* Call ADC DMA error callback */
3567 hadc->DMA_Handle->XferErrorCallback(hdma);
3568 }
3569 }
3570 }
3571
3572 /**
3573 * @brief DMA half transfer complete callback.
3574 * @param hdma pointer to DMA handle.
3575 * @retval None
3576 */
ADC_DMAHalfConvCplt(DMA_HandleTypeDef * hdma)3577 void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
3578 {
3579 /* Retrieve ADC handle corresponding to current DMA handle */
3580 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
3581
3582 /* Half conversion callback */
3583 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
3584 hadc->ConvHalfCpltCallback(hadc);
3585 #else
3586 HAL_ADC_ConvHalfCpltCallback(hadc);
3587 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
3588 }
3589
3590 /**
3591 * @brief DMA error callback.
3592 * @param hdma pointer to DMA handle.
3593 * @retval None
3594 */
ADC_DMAError(DMA_HandleTypeDef * hdma)3595 void ADC_DMAError(DMA_HandleTypeDef *hdma)
3596 {
3597 /* Retrieve ADC handle corresponding to current DMA handle */
3598 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
3599
3600 /* Set ADC state */
3601 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
3602
3603 /* Set ADC error code to DMA error */
3604 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
3605
3606 /* Error callback */
3607 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
3608 hadc->ErrorCallback(hadc);
3609 #else
3610 HAL_ADC_ErrorCallback(hadc);
3611 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
3612 }
3613
3614 /**
3615 * @}
3616 */
3617
3618 #endif /* HAL_ADC_MODULE_ENABLED */
3619 /**
3620 * @}
3621 */
3622
3623 /**
3624 * @}
3625 */
3626
3627 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
3628
