1 /**
2 ******************************************************************************
3 * @file stm32l1xx_hal_pwr.c
4 * @author MCD Application Team
5 * @brief PWR HAL module driver.
6 *
7 * This file provides firmware functions to manage the following
8 * functionalities of the Power Controller (PWR) peripheral:
9 * + Initialization/de-initialization functions
10 * + Peripheral Control functions
11 *
12 ******************************************************************************
13 * @attention
14 *
15 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
16 *
17 * Redistribution and use in source and binary forms, with or without modification,
18 * are permitted provided that the following conditions are met:
19 * 1. Redistributions of source code must retain the above copyright notice,
20 * this list of conditions and the following disclaimer.
21 * 2. Redistributions in binary form must reproduce the above copyright notice,
22 * this list of conditions and the following disclaimer in the documentation
23 * and/or other materials provided with the distribution.
24 * 3. Neither the name of STMicroelectronics nor the names of its contributors
25 * may be used to endorse or promote products derived from this software
26 * without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
29 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
31 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
34 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 *
39 ******************************************************************************
40 */
41
42 /* Includes ------------------------------------------------------------------*/
43 #include "stm32l1xx_hal.h"
44
45 /** @addtogroup STM32L1xx_HAL_Driver
46 * @{
47 */
48
49 /** @defgroup PWR PWR
50 * @brief PWR HAL module driver
51 * @{
52 */
53
54 #ifdef HAL_PWR_MODULE_ENABLED
55
56 /* Private typedef -----------------------------------------------------------*/
57 /* Private define ------------------------------------------------------------*/
58 #define PVD_MODE_IT (0x00010000U)
59 #define PVD_MODE_EVT (0x00020000U)
60 #define PVD_RISING_EDGE (0x00000001U)
61 #define PVD_FALLING_EDGE (0x00000002U)
62
63 /* Private macro -------------------------------------------------------------*/
64 /* Private variables ---------------------------------------------------------*/
65 /* Private function prototypes -----------------------------------------------*/
66 /* Private functions ---------------------------------------------------------*/
67
68 /** @defgroup PWR_Exported_Functions PWR Exported Functions
69 * @{
70 */
71
72 /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
73 * @brief Initialization and de-initialization functions
74 *
75 @verbatim
76 ===============================================================================
77 ##### Initialization and de-initialization functions #####
78 ===============================================================================
79 [..]
80 After reset, the backup domain (RTC registers, RTC backup data
81 registers) is protected against possible unwanted
82 write accesses.
83 To enable access to the RTC Domain and RTC registers, proceed as follows:
84 (+) Enable the Power Controller (PWR) APB1 interface clock using the
85 __HAL_RCC_PWR_CLK_ENABLE() macro.
86 (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
87
88 @endverbatim
89 * @{
90 */
91
92 /**
93 * @brief Deinitializes the PWR peripheral registers to their default reset values.
94 * @note Before calling this function, the VOS[1:0] bits should be configured
95 * to "10" and the system frequency has to be configured accordingly.
96 * To configure the VOS[1:0] bits, use the PWR_VoltageScalingConfig()
97 * function.
98 * @note ULP and FWU bits are not reset by this function.
99 * @retval None
100 */
HAL_PWR_DeInit(void)101 void HAL_PWR_DeInit(void)
102 {
103 __HAL_RCC_PWR_FORCE_RESET();
104 __HAL_RCC_PWR_RELEASE_RESET();
105 }
106
107 /**
108 * @brief Enables access to the backup domain (RTC registers, RTC
109 * backup data registers ).
110 * @note If the HSE divided by 2, 4, 8 or 16 is used as the RTC clock, the
111 * Backup Domain Access should be kept enabled.
112 * @retval None
113 */
HAL_PWR_EnableBkUpAccess(void)114 void HAL_PWR_EnableBkUpAccess(void)
115 {
116 /* Enable access to RTC and backup registers */
117 *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE;
118 }
119
120 /**
121 * @brief Disables access to the backup domain (RTC registers, RTC
122 * backup data registers).
123 * @note If the HSE divided by 2, 4, 8 or 16 is used as the RTC clock, the
124 * Backup Domain Access should be kept enabled.
125 * @retval None
126 */
HAL_PWR_DisableBkUpAccess(void)127 void HAL_PWR_DisableBkUpAccess(void)
128 {
129 /* Disable access to RTC and backup registers */
130 *(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE;
131 }
132
133 /**
134 * @}
135 */
136
137 /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
138 * @brief Low Power modes configuration functions
139 *
140 @verbatim
141
142 ===============================================================================
143 ##### Peripheral Control functions #####
144 ===============================================================================
145
146 *** PVD configuration ***
147 =========================
148 [..]
149 (+) The PVD is used to monitor the VDD power supply by comparing it to a
150 threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
151 (+) The PVD can use an external input analog voltage (PVD_IN) which is compared
152 internally to VREFINT. The PVD_IN (PB7) has to be configured in Analog mode
153 when PWR_PVDLevel_7 is selected (PLS[2:0] = 111).
154
155 (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
156 than the PVD threshold. This event is internally connected to the EXTI
157 line16 and can generate an interrupt if enabled. This is done through
158 __HAL_PWR_PVD_EXTI_ENABLE_IT() macro.
159 (+) The PVD is stopped in Standby mode.
160
161 *** WakeUp pin configuration ***
162 ================================
163 [..]
164 (+) WakeUp pin is used to wake up the system from Standby mode. This pin is
165 forced in input pull-down configuration and is active on rising edges.
166 (+) There are two or three WakeUp pins:
167 WakeUp Pin 1 on PA.00.
168 WakeUp Pin 2 on PC.13.
169 WakeUp Pin 3 on PE.06. : Only on product with GPIOE available
170
171 [..]
172 *** Main and Backup Regulators configuration ***
173 ================================================
174
175 (+) The main internal regulator can be configured to have a tradeoff between
176 performance and power consumption when the device does not operate at
177 the maximum frequency. This is done through __HAL_PWR_VOLTAGESCALING_CONFIG()
178 macro which configure VOS bit in PWR_CR register:
179 (++) When this bit is set (Regulator voltage output Scale 1 mode selected)
180 the System frequency can go up to 32 MHz.
181 (++) When this bit is reset (Regulator voltage output Scale 2 mode selected)
182 the System frequency can go up to 16 MHz.
183 (++) When this bit is reset (Regulator voltage output Scale 3 mode selected)
184 the System frequency can go up to 4.2 MHz.
185
186 Refer to the datasheets for more details.
187
188 *** Low Power modes configuration ***
189 =====================================
190 [..]
191 The device features 5 low-power modes:
192 (+) Low power run mode: regulator in low power mode, limited clock frequency,
193 limited number of peripherals running.
194 (+) Sleep mode: Cortex-M3 core stopped, peripherals kept running.
195 (+) Low power sleep mode: Cortex-M3 core stopped, limited clock frequency,
196 limited number of peripherals running, regulator in low power mode.
197 (+) Stop mode: All clocks are stopped, regulator running, regulator in low power mode.
198 (+) Standby mode: VCORE domain powered off
199
200 *** Low power run mode ***
201 =========================
202 [..]
203 To further reduce the consumption when the system is in Run mode, the regulator can be
204 configured in low power mode. In this mode, the system frequency should not exceed
205 MSI frequency range1.
206 In Low power run mode, all I/O pins keep the same state as in Run mode.
207
208 (+) Entry:
209 (++) VCORE in range2
210 (++) Decrease the system frequency tonot exceed the frequency of MSI frequency range1.
211 (++) The regulator is forced in low power mode using the HAL_PWREx_EnableLowPowerRunMode()
212 function.
213 (+) Exit:
214 (++) The regulator is forced in Main regulator mode using the HAL_PWREx_DisableLowPowerRunMode()
215 function.
216 (++) Increase the system frequency if needed.
217
218 *** Sleep mode ***
219 ==================
220 [..]
221 (+) Entry:
222 The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx)
223 functions with
224 (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
225 (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
226
227 (+) Exit:
228 (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
229 controller (NVIC) can wake up the device from Sleep mode.
230
231 *** Low power sleep mode ***
232 ============================
233 [..]
234 (+) Entry:
235 The Low power sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_LOWPOWERREGULATOR_ON, PWR_SLEEPENTRY_WFx)
236 functions with
237 (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
238 (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
239 (+) The Flash memory can be switched off by using the control bits (SLEEP_PD in the FLASH_ACR register.
240 This reduces power consumption but increases the wake-up time.
241
242 (+) Exit:
243 (++) If the WFI instruction was used to enter Low power sleep mode, any peripheral interrupt
244 acknowledged by the nested vectored interrupt controller (NVIC) can wake up the device
245 from Low power sleep mode. If the WFE instruction was used to enter Low power sleep mode,
246 the MCU exits Sleep mode as soon as an event occurs.
247
248 *** Stop mode ***
249 =================
250 [..]
251 The Stop mode is based on the Cortex-M3 deepsleep mode combined with peripheral
252 clock gating. The voltage regulator can be configured either in normal or low-power mode.
253 In Stop mode, all clocks in the VCORE domain are stopped, the PLL, the MSI, the HSI and
254 the HSE RC oscillators are disabled. Internal SRAM and register contents are preserved.
255 To get the lowest consumption in Stop mode, the internal Flash memory also enters low
256 power mode. When the Flash memory is in power-down mode, an additional startup delay is
257 incurred when waking up from Stop mode.
258 To minimize the consumption In Stop mode, VREFINT, the BOR, PVD, and temperature
259 sensor can be switched off before entering Stop mode. They can be switched on again by
260 software after exiting Stop mode using the ULP bit in the PWR_CR register.
261 In Stop mode, all I/O pins keep the same state as in Run mode.
262
263 (+) Entry:
264 The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI )
265 function with:
266 (++) Main regulator ON.
267 (++) Low Power regulator ON.
268 (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
269 (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
270 (+) Exit:
271 (++) By issuing an interrupt or a wakeup event, the MSI RC oscillator is selected as system clock.
272
273 *** Standby mode ***
274 ====================
275 [..]
276 The Standby mode allows to achieve the lowest power consumption. It is based on the
277 Cortex-M3 deepsleep mode, with the voltage regulator disabled. The VCORE domain is
278 consequently powered off. The PLL, the MSI, the HSI oscillator and the HSE oscillator are
279 also switched off. SRAM and register contents are lost except for the RTC registers, RTC
280 backup registers and Standby circuitry.
281
282 To minimize the consumption In Standby mode, VREFINT, the BOR, PVD, and temperature
283 sensor can be switched off before entering the Standby mode. They can be switched
284 on again by software after exiting the Standby mode.
285 function.
286
287 (+) Entry:
288 (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
289 (+) Exit:
290 (++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
291 tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
292
293 *** Auto-wakeup (AWU) from low-power mode ***
294 =============================================
295 [..]
296 The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
297 Wakeup event, a tamper event, a time-stamp event, or a comparator event,
298 without depending on an external interrupt (Auto-wakeup mode).
299
300 (+) RTC auto-wakeup (AWU) from the Stop mode
301 (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to:
302 (+++) Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt
303 or Event modes) and Enable the RTC Alarm Interrupt using the HAL_RTC_SetAlarm_IT()
304 function
305 (+++) Configure the RTC to generate the RTC alarm using the HAL_RTC_Init()
306 and HAL_RTC_SetTime() functions.
307 (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
308 is necessary to:
309 (+++) Configure the EXTI Line 19 to be sensitive to rising edges (Interrupt or Event modes) and
310 Enable the RTC Tamper or time stamp Interrupt using the HAL_RTCEx_SetTamper_IT()
311 or HAL_RTCEx_SetTimeStamp_IT() functions.
312 (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to:
313 (+++) Configure the EXTI Line 20 to be sensitive to rising edges (Interrupt or Event modes) and
314 Enable the RTC WakeUp Interrupt using the HAL_RTCEx_SetWakeUpTimer_IT() function.
315 (+++) Configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer()
316 function.
317
318 (+) RTC auto-wakeup (AWU) from the Standby mode
319 (++) To wake up from the Standby mode with an RTC alarm event, it is necessary to:
320 (+++) Enable the RTC Alarm Interrupt using the HAL_RTC_SetAlarm_IT() function.
321 (+++) Configure the RTC to generate the RTC alarm using the HAL_RTC_Init()
322 and HAL_RTC_SetTime() functions.
323 (++) To wake up from the Standby mode with an RTC Tamper or time stamp event, it
324 is necessary to:
325 (+++) Enable the RTC Tamper or time stamp Interrupt and Configure the RTC to
326 detect the tamper or time stamp event using the HAL_RTCEx_SetTimeStamp_IT()
327 or HAL_RTCEx_SetTamper_IT()functions.
328 (++) To wake up from the Standby mode with an RTC WakeUp event, it is necessary to:
329 (+++) Enable the RTC WakeUp Interrupt and Configure the RTC to generate the RTC WakeUp event
330 using the HAL_RTCEx_SetWakeUpTimer_IT() and HAL_RTCEx_SetWakeUpTimer() functions.
331
332 (+) Comparator auto-wakeup (AWU) from the Stop mode
333 (++) To wake up from the Stop mode with an comparator 1 or comparator 2 wakeup
334 event, it is necessary to:
335 (+++) Configure the EXTI Line 21 or EXTI Line 22 for comparator to be sensitive to to the
336 selected edges (falling, rising or falling and rising) (Interrupt or Event modes) using
337 the COMP functions.
338 (+++) Configure the comparator to generate the event.
339
340
341
342 @endverbatim
343 * @{
344 */
345
346 /**
347 * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
348 * @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration
349 * information for the PVD.
350 * @note Refer to the electrical characteristics of your device datasheet for
351 * more details about the voltage threshold corresponding to each
352 * detection level.
353 * @retval None
354 */
HAL_PWR_ConfigPVD(PWR_PVDTypeDef * sConfigPVD)355 void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
356 {
357 /* Check the parameters */
358 assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
359 assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
360
361 /* Set PLS[7:5] bits according to PVDLevel value */
362 MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel);
363
364 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
365 __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
366 __HAL_PWR_PVD_EXTI_DISABLE_IT();
367 __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE();
368
369 /* Configure interrupt mode */
370 if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
371 {
372 __HAL_PWR_PVD_EXTI_ENABLE_IT();
373 }
374
375 /* Configure event mode */
376 if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
377 {
378 __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
379 }
380
381 /* Configure the edge */
382 if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
383 {
384 __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
385 }
386
387 if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
388 {
389 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
390 }
391 }
392
393 /**
394 * @brief Enables the Power Voltage Detector(PVD).
395 * @retval None
396 */
HAL_PWR_EnablePVD(void)397 void HAL_PWR_EnablePVD(void)
398 {
399 /* Enable the power voltage detector */
400 *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)ENABLE;
401 }
402
403 /**
404 * @brief Disables the Power Voltage Detector(PVD).
405 * @retval None
406 */
HAL_PWR_DisablePVD(void)407 void HAL_PWR_DisablePVD(void)
408 {
409 /* Disable the power voltage detector */
410 *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)DISABLE;
411 }
412
413 /**
414 * @brief Enables the WakeUp PINx functionality.
415 * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable.
416 * This parameter can be one of the following values:
417 * @arg PWR_WAKEUP_PIN1
418 * @arg PWR_WAKEUP_PIN2
419 * @arg PWR_WAKEUP_PIN3: Only on product with GPIOE available
420 * @retval None
421 */
HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)422 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
423 {
424 /* Check the parameter */
425 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
426 /* Enable the EWUPx pin */
427 *(__IO uint32_t *) CSR_EWUP_BB(WakeUpPinx) = (uint32_t)ENABLE;
428 }
429
430 /**
431 * @brief Disables the WakeUp PINx functionality.
432 * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
433 * This parameter can be one of the following values:
434 * @arg PWR_WAKEUP_PIN1
435 * @arg PWR_WAKEUP_PIN2
436 * @arg PWR_WAKEUP_PIN3: Only on product with GPIOE available
437 * @retval None
438 */
HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)439 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
440 {
441 /* Check the parameter */
442 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
443 /* Disable the EWUPx pin */
444 *(__IO uint32_t *) CSR_EWUP_BB(WakeUpPinx) = (uint32_t)DISABLE;
445 }
446
447 /**
448 * @brief Enters Sleep mode.
449 * @note In Sleep mode, all I/O pins keep the same state as in Run mode.
450 * @param Regulator: Specifies the regulator state in SLEEP mode.
451 * This parameter can be one of the following values:
452 * @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON
453 * @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON
454 * @param SLEEPEntry: Specifies if SLEEP mode is entered with WFI or WFE instruction.
455 * When WFI entry is used, tick interrupt have to be disabled if not desired as
456 * the interrupt wake up source.
457 * This parameter can be one of the following values:
458 * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
459 * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
460 * @retval None
461 */
HAL_PWR_EnterSLEEPMode(uint32_t Regulator,uint8_t SLEEPEntry)462 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
463 {
464 /* Check the parameters */
465 assert_param(IS_PWR_REGULATOR(Regulator));
466 assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
467
468 /* Select the regulator state in Sleep mode: Set PDDS and LPSDSR bit according to PWR_Regulator value */
469 MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPSDSR), Regulator);
470
471 /* Clear SLEEPDEEP bit of Cortex System Control Register */
472 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
473
474 /* Select SLEEP mode entry -------------------------------------------------*/
475 if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
476 {
477 /* Request Wait For Interrupt */
478 __WFI();
479 }
480 else
481 {
482 /* Request Wait For Event */
483 __SEV();
484 __WFE();
485 __WFE();
486 }
487 }
488
489 /**
490 * @brief Enters Stop mode.
491 * @note In Stop mode, all I/O pins keep the same state as in Run mode.
492 * @note When exiting Stop mode by using an interrupt or a wakeup event,
493 * MSI RC oscillator is selected as system clock.
494 * @note When the voltage regulator operates in low power mode, an additional
495 * startup delay is incurred when waking up from Stop mode.
496 * By keeping the internal regulator ON during Stop mode, the consumption
497 * is higher although the startup time is reduced.
498 * @param Regulator: Specifies the regulator state in Stop mode.
499 * This parameter can be one of the following values:
500 * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON
501 * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
502 * @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction.
503 * This parameter can be one of the following values:
504 * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction
505 * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction
506 * @retval None
507 */
HAL_PWR_EnterSTOPMode(uint32_t Regulator,uint8_t STOPEntry)508 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
509 {
510 /* Check the parameters */
511 assert_param(IS_PWR_REGULATOR(Regulator));
512 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
513
514 /* Select the regulator state in Stop mode: Set PDDS and LPSDSR bit according to PWR_Regulator value */
515 MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPSDSR), Regulator);
516
517 /* Set SLEEPDEEP bit of Cortex System Control Register */
518 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
519
520 /* Select Stop mode entry --------------------------------------------------*/
521 if(STOPEntry == PWR_STOPENTRY_WFI)
522 {
523 /* Request Wait For Interrupt */
524 __WFI();
525 }
526 else
527 {
528 /* Request Wait For Event */
529 __SEV();
530 __WFE();
531 __WFE();
532 }
533 /* Reset SLEEPDEEP bit of Cortex System Control Register */
534 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
535 }
536
537 /**
538 * @brief Enters Standby mode.
539 * @note In Standby mode, all I/O pins are high impedance except for:
540 * - Reset pad (still available)
541 * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC
542 * Alarm out, or RTC clock calibration out.
543 * - WKUP pin 1 (PA0) if enabled.
544 * - WKUP pin 2 (PC13) if enabled.
545 * - WKUP pin 3 (PE6) if enabled.
546 * @retval None
547 */
HAL_PWR_EnterSTANDBYMode(void)548 void HAL_PWR_EnterSTANDBYMode(void)
549 {
550 /* Select Standby mode */
551 SET_BIT(PWR->CR, PWR_CR_PDDS);
552
553 /* Set SLEEPDEEP bit of Cortex System Control Register */
554 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
555
556 /* This option is used to ensure that store operations are completed */
557 #if defined ( __CC_ARM)
558 __force_stores();
559 #endif
560 /* Request Wait For Interrupt */
561 __WFI();
562 }
563
564
565 /**
566 * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
567 * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
568 * re-enters SLEEP mode when an interruption handling is over.
569 * Setting this bit is useful when the processor is expected to run only on
570 * interruptions handling.
571 * @retval None
572 */
HAL_PWR_EnableSleepOnExit(void)573 void HAL_PWR_EnableSleepOnExit(void)
574 {
575 /* Set SLEEPONEXIT bit of Cortex System Control Register */
576 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
577 }
578
579
580 /**
581 * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
582 * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
583 * re-enters SLEEP mode when an interruption handling is over.
584 * @retval None
585 */
HAL_PWR_DisableSleepOnExit(void)586 void HAL_PWR_DisableSleepOnExit(void)
587 {
588 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
589 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
590 }
591
592
593 /**
594 * @brief Enables CORTEX M3 SEVONPEND bit.
595 * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
596 * WFE to wake up when an interrupt moves from inactive to pended.
597 * @retval None
598 */
HAL_PWR_EnableSEVOnPend(void)599 void HAL_PWR_EnableSEVOnPend(void)
600 {
601 /* Set SEVONPEND bit of Cortex System Control Register */
602 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
603 }
604
605
606 /**
607 * @brief Disables CORTEX M3 SEVONPEND bit.
608 * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
609 * WFE to wake up when an interrupt moves from inactive to pended.
610 * @retval None
611 */
HAL_PWR_DisableSEVOnPend(void)612 void HAL_PWR_DisableSEVOnPend(void)
613 {
614 /* Clear SEVONPEND bit of Cortex System Control Register */
615 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
616 }
617
618
619
620 /**
621 * @brief This function handles the PWR PVD interrupt request.
622 * @note This API should be called under the PVD_IRQHandler().
623 * @retval None
624 */
HAL_PWR_PVD_IRQHandler(void)625 void HAL_PWR_PVD_IRQHandler(void)
626 {
627 /* Check PWR exti flag */
628 if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
629 {
630 /* PWR PVD interrupt user callback */
631 HAL_PWR_PVDCallback();
632
633 /* Clear PWR Exti pending bit */
634 __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
635 }
636 }
637
638 /**
639 * @brief PWR PVD interrupt callback
640 * @retval None
641 */
HAL_PWR_PVDCallback(void)642 __weak void HAL_PWR_PVDCallback(void)
643 {
644 /* NOTE : This function Should not be modified, when the callback is needed,
645 the HAL_PWR_PVDCallback could be implemented in the user file
646 */
647 }
648
649 /**
650 * @}
651 */
652
653 /**
654 * @}
655 */
656
657 #endif /* HAL_PWR_MODULE_ENABLED */
658 /**
659 * @}
660 */
661
662 /**
663 * @}
664 */
665
666 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
667
