1 /**
2 ******************************************************************************
3 * @file stm32l1xx_hal_i2c.c
4 * @author MCD Application Team
5 * @brief I2C HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Inter Integrated Circuit (I2C) peripheral:
8 * + Initialization and de-initialization functions
9 * + IO operation functions
10 * + Peripheral State, Mode and Error functions
11 *
12 @verbatim
13 ==============================================================================
14 ##### How to use this driver #####
15 ==============================================================================
16 [..]
17 The I2C HAL driver can be used as follows:
18
19 (#) Declare a I2C_HandleTypeDef handle structure, for example:
20 I2C_HandleTypeDef hi2c;
21
22 (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
23 (##) Enable the I2Cx interface clock
24 (##) I2C pins configuration
25 (+++) Enable the clock for the I2C GPIOs
26 (+++) Configure I2C pins as alternate function open-drain
27 (##) NVIC configuration if you need to use interrupt process
28 (+++) Configure the I2Cx interrupt priority
29 (+++) Enable the NVIC I2C IRQ Channel
30 (##) DMA Configuration if you need to use DMA process
31 (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel
32 (+++) Enable the DMAx interface clock using
33 (+++) Configure the DMA handle parameters
34 (+++) Configure the DMA Tx or Rx channel
35 (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
36 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
37 the DMA Tx or Rx channel
38
39 (#) Configure the Communication Speed, Duty cycle, Addressing mode, Own Address1,
40 Dual Addressing mode, Own Address2, General call and Nostretch mode in the hi2c Init structure.
41
42 (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
43 (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.
44
45 (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
46
47 (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
48
49 *** Polling mode IO operation ***
50 =================================
51 [..]
52 (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
53 (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
54 (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
55 (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
56
57 *** Polling mode IO MEM operation ***
58 =====================================
59 [..]
60 (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
61 (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
62
63
64 *** Interrupt mode IO operation ***
65 ===================================
66 [..]
67 (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT()
68 (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
69 add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
70 (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT()
71 (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
72 add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
73 (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT()
74 (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
75 add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
76 (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT()
77 (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
78 add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
79 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
80 add his own code by customization of function pointer HAL_I2C_ErrorCallback()
81 (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
82 (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
83 add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
84 (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
85 This action will inform Master to generate a Stop condition to discard the communication.
86
87
88 *** Interrupt mode IO sequential operation ***
89 ==============================================
90 [..]
91 (@) These interfaces allow to manage a sequential transfer with a repeated start condition
92 when a direction change during transfer
93 [..]
94 (+) A specific option field manage the different steps of a sequential transfer
95 (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below:
96 (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode
97 (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
98 and data to transfer without a final stop condition
99 (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
100 and with new data to transfer if the direction change or manage only the new data to transfer
101 if no direction change and without a final stop condition in both cases
102 (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
103 and with new data to transfer if the direction change or manage only the new data to transfer
104 if no direction change and with a final stop condition in both cases
105
106 (+) Differents sequential I2C interfaces are listed below:
107 (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Transmit_IT()
108 (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
109 add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
110 (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Receive_IT()
111 (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
112 add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
113 (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
114 (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
115 add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
116 (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT()
117 (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can
118 add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).
119 (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can
120 add his own code by customization of function pointer HAL_I2C_ListenCpltCallback()
121 (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Transmit_IT()
122 (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
123 add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
124 (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Receive_IT()
125 (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
126 add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
127 (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
128 add his own code by customization of function pointer HAL_I2C_ErrorCallback()
129 (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
130 (++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
131 add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
132 (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
133 This action will inform Master to generate a Stop condition to discard the communication.
134
135 *** Interrupt mode IO MEM operation ***
136 =======================================
137 [..]
138 (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
139 HAL_I2C_Mem_Write_IT()
140 (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can
141 add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
142 (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
143 HAL_I2C_Mem_Read_IT()
144 (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can
145 add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
146 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
147 add his own code by customization of function pointer HAL_I2C_ErrorCallback()
148
149 *** DMA mode IO operation ***
150 ==============================
151 [..]
152 (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
153 HAL_I2C_Master_Transmit_DMA()
154 (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
155 add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
156 (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
157 HAL_I2C_Master_Receive_DMA()
158 (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
159 add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
160 (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
161 HAL_I2C_Slave_Transmit_DMA()
162 (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
163 add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
164 (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
165 HAL_I2C_Slave_Receive_DMA()
166 (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
167 add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
168 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
169 add his own code by customization of function pointer HAL_I2C_ErrorCallback()
170 (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
171 (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
172 add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
173 (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
174 This action will inform Master to generate a Stop condition to discard the communication.
175
176 *** DMA mode IO MEM operation ***
177 =================================
178 [..]
179 (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
180 HAL_I2C_Mem_Write_DMA()
181 (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can
182 add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
183 (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
184 HAL_I2C_Mem_Read_DMA()
185 (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can
186 add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
187 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
188 add his own code by customization of function pointer HAL_I2C_ErrorCallback()
189
190
191 *** I2C HAL driver macros list ***
192 ==================================
193 [..]
194 Below the list of most used macros in I2C HAL driver.
195
196 (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
197 (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
198 (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode
199 (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
200 (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
201 (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
202 (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
203
204 [..]
205 (@) You can refer to the I2C HAL driver header file for more useful macros
206
207
208 @endverbatim
209 ******************************************************************************
210 * @attention
211 *
212 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
213 *
214 * Redistribution and use in source and binary forms, with or without modification,
215 * are permitted provided that the following conditions are met:
216 * 1. Redistributions of source code must retain the above copyright notice,
217 * this list of conditions and the following disclaimer.
218 * 2. Redistributions in binary form must reproduce the above copyright notice,
219 * this list of conditions and the following disclaimer in the documentation
220 * and/or other materials provided with the distribution.
221 * 3. Neither the name of STMicroelectronics nor the names of its contributors
222 * may be used to endorse or promote products derived from this software
223 * without specific prior written permission.
224 *
225 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
226 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
227 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
228 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
229 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
230 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
231 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
232 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
233 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
234 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
235 *
236 ******************************************************************************
237 */
238
239 /* Includes ------------------------------------------------------------------*/
240 #include "stm32l1xx_hal.h"
241
242 /** @addtogroup STM32L1xx_HAL_Driver
243 * @{
244 */
245
246 /** @defgroup I2C I2C
247 * @brief I2C HAL module driver
248 * @{
249 */
250
251 #ifdef HAL_I2C_MODULE_ENABLED
252
253 /* Private typedef -----------------------------------------------------------*/
254 /* Private define ------------------------------------------------------------*/
255 /** @defgroup I2C_Private_Define I2C Private Define
256 * @{
257 */
258 #define I2C_TIMEOUT_FLAG (35U) /*!< Timeout 35 ms */
259 #define I2C_TIMEOUT_ADDR_SLAVE (10000U) /*!< Timeout 10 s */
260 #define I2C_TIMEOUT_BUSY_FLAG (25U) /*!< Timeout 25 ms */
261 #define I2C_NO_OPTION_FRAME (0xFFFF0000U) /*!< XferOptions default value */
262
263 #define I2C_MIN_PCLK_FREQ (2000000U) /*!< 2 MHz */
264
265 /* Private define for @ref PreviousState usage */
266 #define I2C_STATE_MSK ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (~(uint32_t)HAL_I2C_STATE_READY))) /*!< Mask State define, keep only RX and TX bits */
267 #define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /*!< Default Value */
268 #define I2C_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */
269 #define I2C_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */
270 #define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */
271 #define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */
272
273 /**
274 * @}
275 */
276
277 /* Private macro -------------------------------------------------------------*/
278 /* Private variables ---------------------------------------------------------*/
279 /* Private function prototypes -----------------------------------------------*/
280 /** @defgroup I2C_Private_Functions I2C Private Functions
281 * @{
282 */
283 /* Private functions to handle DMA transfer */
284 static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma);
285 static void I2C_DMAError(DMA_HandleTypeDef *hdma);
286 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
287
288 static void I2C_ITError(I2C_HandleTypeDef *hi2c);
289
290 static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart);
291 static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart);
292 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
293 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
294 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart);
295 static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart);
296 static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
297 static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
298 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
299 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
300 static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c);
301
302 /* Private functions for I2C transfer IRQ handler */
303 static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c);
304 static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c);
305 static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c);
306 static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c);
307 static HAL_StatusTypeDef I2C_Master_SB(I2C_HandleTypeDef *hi2c);
308 static HAL_StatusTypeDef I2C_Master_ADD10(I2C_HandleTypeDef *hi2c);
309 static HAL_StatusTypeDef I2C_Master_ADDR(I2C_HandleTypeDef *hi2c);
310
311 static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c);
312 static HAL_StatusTypeDef I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c);
313 static HAL_StatusTypeDef I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c);
314 static HAL_StatusTypeDef I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c);
315 static HAL_StatusTypeDef I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c);
316 static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c);
317 static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c);
318 /**
319 * @}
320 */
321
322 /* Exported functions --------------------------------------------------------*/
323 /** @defgroup I2C_Exported_Functions I2C Exported Functions
324 * @{
325 */
326
327 /** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
328 * @brief Initialization and Configuration functions
329 *
330 @verbatim
331 ===============================================================================
332 ##### Initialization and de-initialization functions #####
333 ===============================================================================
334 [..] This subsection provides a set of functions allowing to initialize and
335 deinitialize the I2Cx peripheral:
336
337 (+) User must Implement HAL_I2C_MspInit() function in which he configures
338 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
339
340 (+) Call the function HAL_I2C_Init() to configure the selected device with
341 the selected configuration:
342 (++) Communication Speed
343 (++) Duty cycle
344 (++) Addressing mode
345 (++) Own Address 1
346 (++) Dual Addressing mode
347 (++) Own Address 2
348 (++) General call mode
349 (++) Nostretch mode
350
351 (+) Call the function HAL_I2C_DeInit() to restore the default configuration
352 of the selected I2Cx peripheral.
353
354 @endverbatim
355 * @{
356 */
357
358 /**
359 * @brief Initializes the I2C according to the specified parameters
360 * in the I2C_InitTypeDef and initialize the associated handle.
361 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
362 * the configuration information for the specified I2C.
363 * @retval HAL status
364 */
HAL_I2C_Init(I2C_HandleTypeDef * hi2c)365 HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
366 {
367 uint32_t freqrange = 0U;
368 uint32_t pclk1 = 0U;
369
370 /* Check the I2C handle allocation */
371 if(hi2c == NULL)
372 {
373 return HAL_ERROR;
374 }
375
376 /* Check the parameters */
377 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
378 assert_param(IS_I2C_CLOCK_SPEED(hi2c->Init.ClockSpeed));
379 assert_param(IS_I2C_DUTY_CYCLE(hi2c->Init.DutyCycle));
380 assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
381 assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
382 assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
383 assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
384 assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
385 assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
386
387 if(hi2c->State == HAL_I2C_STATE_RESET)
388 {
389 /* Allocate lock resource and initialize it */
390 hi2c->Lock = HAL_UNLOCKED;
391
392 /* Init the low level hardware : GPIO, CLOCK, NVIC */
393 HAL_I2C_MspInit(hi2c);
394 }
395
396 /* Get PCLK1 frequency */
397 pclk1 = HAL_RCC_GetPCLK1Freq();
398
399 /* The minimum allowed frequency is 2 MHz */
400 if(pclk1 < I2C_MIN_PCLK_FREQ)
401 {
402 return HAL_ERROR;
403 }
404
405 hi2c->State = HAL_I2C_STATE_BUSY;
406
407 /* Disable the selected I2C peripheral */
408 __HAL_I2C_DISABLE(hi2c);
409
410 /* Calculate frequency range */
411 freqrange = I2C_FREQ_RANGE(pclk1);
412
413 /*---------------------------- I2Cx CR2 Configuration ----------------------*/
414 /* Configure I2Cx: Frequency range */
415 MODIFY_REG(hi2c->Instance->CR2, I2C_CR2_FREQ, freqrange);
416
417 /*---------------------------- I2Cx TRISE Configuration --------------------*/
418 /* Configure I2Cx: Rise Time */
419 MODIFY_REG(hi2c->Instance->TRISE, I2C_TRISE_TRISE, I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed));
420
421 /*---------------------------- I2Cx CCR Configuration ----------------------*/
422 /* Configure I2Cx: Speed */
423 MODIFY_REG(hi2c->Instance->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle));
424
425 /*---------------------------- I2Cx CR1 Configuration ----------------------*/
426 /* Configure I2Cx: Generalcall and NoStretch mode */
427 MODIFY_REG(hi2c->Instance->CR1, (I2C_CR1_ENGC | I2C_CR1_NOSTRETCH), (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode));
428
429 /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
430 /* Configure I2Cx: Own Address1 and addressing mode */
431 MODIFY_REG(hi2c->Instance->OAR1, (I2C_OAR1_ADDMODE | I2C_OAR1_ADD8_9 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD0), (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1));
432
433 /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
434 /* Configure I2Cx: Dual mode and Own Address2 */
435 MODIFY_REG(hi2c->Instance->OAR2, (I2C_OAR2_ENDUAL | I2C_OAR2_ADD2), (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2));
436
437 /* Enable the selected I2C peripheral */
438 __HAL_I2C_ENABLE(hi2c);
439
440 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
441 hi2c->State = HAL_I2C_STATE_READY;
442 hi2c->PreviousState = I2C_STATE_NONE;
443 hi2c->Mode = HAL_I2C_MODE_NONE;
444
445 return HAL_OK;
446 }
447
448 /**
449 * @brief DeInitialize the I2C peripheral.
450 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
451 * the configuration information for the specified I2C.
452 * @retval HAL status
453 */
HAL_I2C_DeInit(I2C_HandleTypeDef * hi2c)454 HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
455 {
456 /* Check the I2C handle allocation */
457 if(hi2c == NULL)
458 {
459 return HAL_ERROR;
460 }
461
462 /* Check the parameters */
463 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
464
465 hi2c->State = HAL_I2C_STATE_BUSY;
466
467 /* Disable the I2C Peripheral Clock */
468 __HAL_I2C_DISABLE(hi2c);
469
470 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
471 HAL_I2C_MspDeInit(hi2c);
472
473 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
474 hi2c->State = HAL_I2C_STATE_RESET;
475 hi2c->PreviousState = I2C_STATE_NONE;
476 hi2c->Mode = HAL_I2C_MODE_NONE;
477
478 /* Release Lock */
479 __HAL_UNLOCK(hi2c);
480
481 return HAL_OK;
482 }
483
484 /**
485 * @brief Initialize the I2C MSP.
486 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
487 * the configuration information for the specified I2C.
488 * @retval None
489 */
HAL_I2C_MspInit(I2C_HandleTypeDef * hi2c)490 __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
491 {
492 /* Prevent unused argument(s) compilation warning */
493 UNUSED(hi2c);
494
495 /* NOTE : This function should not be modified, when the callback is needed,
496 the HAL_I2C_MspInit could be implemented in the user file
497 */
498 }
499
500 /**
501 * @brief DeInitialize the I2C MSP.
502 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
503 * the configuration information for the specified I2C.
504 * @retval None
505 */
HAL_I2C_MspDeInit(I2C_HandleTypeDef * hi2c)506 __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
507 {
508 /* Prevent unused argument(s) compilation warning */
509 UNUSED(hi2c);
510
511 /* NOTE : This function should not be modified, when the callback is needed,
512 the HAL_I2C_MspDeInit could be implemented in the user file
513 */
514 }
515
516 /**
517 * @}
518 */
519
520 /** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
521 * @brief Data transfers functions
522 *
523 @verbatim
524 ===============================================================================
525 ##### IO operation functions #####
526 ===============================================================================
527 [..]
528 This subsection provides a set of functions allowing to manage the I2C data
529 transfers.
530
531 (#) There are two modes of transfer:
532 (++) Blocking mode : The communication is performed in the polling mode.
533 The status of all data processing is returned by the same function
534 after finishing transfer.
535 (++) No-Blocking mode : The communication is performed using Interrupts
536 or DMA. These functions return the status of the transfer startup.
537 The end of the data processing will be indicated through the
538 dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
539 using DMA mode.
540
541 (#) Blocking mode functions are :
542 (++) HAL_I2C_Master_Transmit()
543 (++) HAL_I2C_Master_Receive()
544 (++) HAL_I2C_Slave_Transmit()
545 (++) HAL_I2C_Slave_Receive()
546 (++) HAL_I2C_Mem_Write()
547 (++) HAL_I2C_Mem_Read()
548 (++) HAL_I2C_IsDeviceReady()
549
550 (#) No-Blocking mode functions with Interrupt are :
551 (++) HAL_I2C_Master_Transmit_IT()
552 (++) HAL_I2C_Master_Receive_IT()
553 (++) HAL_I2C_Slave_Transmit_IT()
554 (++) HAL_I2C_Slave_Receive_IT()
555 (++) HAL_I2C_Master_Sequential_Transmit_IT()
556 (++) HAL_I2C_Master_Sequential_Receive_IT()
557 (++) HAL_I2C_Slave_Sequential_Transmit_IT()
558 (++) HAL_I2C_Slave_Sequential_Receive_IT()
559 (++) HAL_I2C_Mem_Write_IT()
560 (++) HAL_I2C_Mem_Read_IT()
561
562 (#) No-Blocking mode functions with DMA are :
563 (++) HAL_I2C_Master_Transmit_DMA()
564 (++) HAL_I2C_Master_Receive_DMA()
565 (++) HAL_I2C_Slave_Transmit_DMA()
566 (++) HAL_I2C_Slave_Receive_DMA()
567 (++) HAL_I2C_Mem_Write_DMA()
568 (++) HAL_I2C_Mem_Read_DMA()
569
570 (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
571 (++) HAL_I2C_MemTxCpltCallback()
572 (++) HAL_I2C_MemRxCpltCallback()
573 (++) HAL_I2C_MasterTxCpltCallback()
574 (++) HAL_I2C_MasterRxCpltCallback()
575 (++) HAL_I2C_SlaveTxCpltCallback()
576 (++) HAL_I2C_SlaveRxCpltCallback()
577 (++) HAL_I2C_ErrorCallback()
578 (++) HAL_I2C_AbortCpltCallback()
579
580 @endverbatim
581 * @{
582 */
583
584 /**
585 * @brief Transmits in master mode an amount of data in blocking mode.
586 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
587 * the configuration information for the specified I2C.
588 * @param DevAddress Target device address: The device 7 bits address value
589 * in datasheet must be shift at right before call interface
590 * @param pData Pointer to data buffer
591 * @param Size Amount of data to be sent
592 * @param Timeout Timeout duration
593 * @retval HAL status
594 */
HAL_I2C_Master_Transmit(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t Timeout)595 HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
596 {
597 uint32_t tickstart = 0x00U;
598
599 /* Init tickstart for timeout management*/
600 tickstart = HAL_GetTick();
601
602 if(hi2c->State == HAL_I2C_STATE_READY)
603 {
604 /* Wait until BUSY flag is reset */
605 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
606 {
607 return HAL_BUSY;
608 }
609
610 /* Process Locked */
611 __HAL_LOCK(hi2c);
612
613 /* Check if the I2C is already enabled */
614 if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
615 {
616 /* Enable I2C peripheral */
617 __HAL_I2C_ENABLE(hi2c);
618 }
619
620 /* Disable Pos */
621 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
622
623 hi2c->State = HAL_I2C_STATE_BUSY_TX;
624 hi2c->Mode = HAL_I2C_MODE_MASTER;
625 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
626
627 /* Prepare transfer parameters */
628 hi2c->pBuffPtr = pData;
629 hi2c->XferCount = Size;
630 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
631 hi2c->XferSize = hi2c->XferCount;
632
633 /* Send Slave Address */
634 if(I2C_MasterRequestWrite(hi2c, DevAddress, Timeout, tickstart) != HAL_OK)
635 {
636 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
637 {
638 /* Process Unlocked */
639 __HAL_UNLOCK(hi2c);
640 return HAL_ERROR;
641 }
642 else
643 {
644 /* Process Unlocked */
645 __HAL_UNLOCK(hi2c);
646 return HAL_TIMEOUT;
647 }
648 }
649
650 /* Clear ADDR flag */
651 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
652
653 while(hi2c->XferSize > 0U)
654 {
655 /* Wait until TXE flag is set */
656 if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
657 {
658 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
659 {
660 /* Generate Stop */
661 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
662 return HAL_ERROR;
663 }
664 else
665 {
666 return HAL_TIMEOUT;
667 }
668 }
669
670 /* Write data to DR */
671 hi2c->Instance->DR = (*hi2c->pBuffPtr++);
672 hi2c->XferCount--;
673 hi2c->XferSize--;
674
675 if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0U))
676 {
677 /* Write data to DR */
678 hi2c->Instance->DR = (*hi2c->pBuffPtr++);
679 hi2c->XferCount--;
680 hi2c->XferSize--;
681 }
682
683 /* Wait until BTF flag is set */
684 if(I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
685 {
686 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
687 {
688 /* Generate Stop */
689 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
690 return HAL_ERROR;
691 }
692 else
693 {
694 return HAL_TIMEOUT;
695 }
696 }
697 }
698
699 /* Generate Stop */
700 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
701
702 hi2c->State = HAL_I2C_STATE_READY;
703 hi2c->Mode = HAL_I2C_MODE_NONE;
704
705 /* Process Unlocked */
706 __HAL_UNLOCK(hi2c);
707
708 return HAL_OK;
709 }
710 else
711 {
712 return HAL_BUSY;
713 }
714 }
715
716 /**
717 * @brief Receives in master mode an amount of data in blocking mode.
718 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
719 * the configuration information for the specified I2C.
720 * @param DevAddress Target device address: The device 7 bits address value
721 * in datasheet must be shift at right before call interface
722 * @param pData Pointer to data buffer
723 * @param Size Amount of data to be sent
724 * @param Timeout Timeout duration
725 * @retval HAL status
726 */
HAL_I2C_Master_Receive(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t Timeout)727 HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
728 {
729 uint32_t tickstart = 0x00U;
730
731 /* Init tickstart for timeout management*/
732 tickstart = HAL_GetTick();
733
734 if(hi2c->State == HAL_I2C_STATE_READY)
735 {
736 /* Wait until BUSY flag is reset */
737 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
738 {
739 return HAL_BUSY;
740 }
741
742 /* Process Locked */
743 __HAL_LOCK(hi2c);
744
745 /* Check if the I2C is already enabled */
746 if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
747 {
748 /* Enable I2C peripheral */
749 __HAL_I2C_ENABLE(hi2c);
750 }
751
752 /* Disable Pos */
753 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
754
755 hi2c->State = HAL_I2C_STATE_BUSY_RX;
756 hi2c->Mode = HAL_I2C_MODE_MASTER;
757 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
758
759 /* Prepare transfer parameters */
760 hi2c->pBuffPtr = pData;
761 hi2c->XferCount = Size;
762 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
763 hi2c->XferSize = hi2c->XferCount;
764
765 /* Send Slave Address */
766 if(I2C_MasterRequestRead(hi2c, DevAddress, Timeout, tickstart) != HAL_OK)
767 {
768 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
769 {
770 /* Process Unlocked */
771 __HAL_UNLOCK(hi2c);
772 return HAL_ERROR;
773 }
774 else
775 {
776 /* Process Unlocked */
777 __HAL_UNLOCK(hi2c);
778 return HAL_TIMEOUT;
779 }
780 }
781
782 if(hi2c->XferSize == 0U)
783 {
784 /* Clear ADDR flag */
785 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
786
787 /* Generate Stop */
788 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
789 }
790 else if(hi2c->XferSize == 1U)
791 {
792 /* Disable Acknowledge */
793 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
794
795 /* Clear ADDR flag */
796 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
797
798 /* Generate Stop */
799 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
800 }
801 else if(hi2c->XferSize == 2U)
802 {
803 /* Disable Acknowledge */
804 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
805
806 /* Enable Pos */
807 SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
808
809 /* Clear ADDR flag */
810 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
811 }
812 else
813 {
814 /* Enable Acknowledge */
815 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
816
817 /* Clear ADDR flag */
818 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
819 }
820
821 while(hi2c->XferSize > 0U)
822 {
823 if(hi2c->XferSize <= 3U)
824 {
825 /* One byte */
826 if(hi2c->XferSize == 1U)
827 {
828 /* Wait until RXNE flag is set */
829 if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
830 {
831 if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
832 {
833 return HAL_TIMEOUT;
834 }
835 else
836 {
837 return HAL_ERROR;
838 }
839 }
840
841 /* Read data from DR */
842 (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
843 hi2c->XferSize--;
844 hi2c->XferCount--;
845 }
846 /* Two bytes */
847 else if(hi2c->XferSize == 2U)
848 {
849 /* Wait until BTF flag is set */
850 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
851 {
852 return HAL_TIMEOUT;
853 }
854
855 /* Generate Stop */
856 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
857
858 /* Read data from DR */
859 (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
860 hi2c->XferSize--;
861 hi2c->XferCount--;
862
863 /* Read data from DR */
864 (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
865 hi2c->XferSize--;
866 hi2c->XferCount--;
867 }
868 /* 3 Last bytes */
869 else
870 {
871 /* Wait until BTF flag is set */
872 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
873 {
874 return HAL_TIMEOUT;
875 }
876
877 /* Disable Acknowledge */
878 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
879
880 /* Read data from DR */
881 (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
882 hi2c->XferSize--;
883 hi2c->XferCount--;
884
885 /* Wait until BTF flag is set */
886 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
887 {
888 return HAL_TIMEOUT;
889 }
890
891 /* Generate Stop */
892 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
893
894 /* Read data from DR */
895 (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
896 hi2c->XferSize--;
897 hi2c->XferCount--;
898
899 /* Read data from DR */
900 (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
901 hi2c->XferSize--;
902 hi2c->XferCount--;
903 }
904 }
905 else
906 {
907 /* Wait until RXNE flag is set */
908 if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
909 {
910 if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
911 {
912 return HAL_TIMEOUT;
913 }
914 else
915 {
916 return HAL_ERROR;
917 }
918 }
919
920 /* Read data from DR */
921 (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
922 hi2c->XferSize--;
923 hi2c->XferCount--;
924
925 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
926 {
927 /* Read data from DR */
928 (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
929 hi2c->XferSize--;
930 hi2c->XferCount--;
931 }
932 }
933 }
934
935 hi2c->State = HAL_I2C_STATE_READY;
936 hi2c->Mode = HAL_I2C_MODE_NONE;
937
938 /* Process Unlocked */
939 __HAL_UNLOCK(hi2c);
940
941 return HAL_OK;
942 }
943 else
944 {
945 return HAL_BUSY;
946 }
947 }
948
949 /**
950 * @brief Transmits in slave mode an amount of data in blocking mode.
951 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
952 * the configuration information for the specified I2C.
953 * @param pData Pointer to data buffer
954 * @param Size Amount of data to be sent
955 * @param Timeout Timeout duration
956 * @retval HAL status
957 */
HAL_I2C_Slave_Transmit(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t Timeout)958 HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
959 {
960 uint32_t tickstart = 0x00U;
961
962 /* Init tickstart for timeout management*/
963 tickstart = HAL_GetTick();
964
965 if(hi2c->State == HAL_I2C_STATE_READY)
966 {
967 if((pData == NULL) || (Size == 0U))
968 {
969 return HAL_ERROR;
970 }
971
972 /* Process Locked */
973 __HAL_LOCK(hi2c);
974
975 /* Check if the I2C is already enabled */
976 if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
977 {
978 /* Enable I2C peripheral */
979 __HAL_I2C_ENABLE(hi2c);
980 }
981
982 /* Disable Pos */
983 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
984
985 hi2c->State = HAL_I2C_STATE_BUSY_TX;
986 hi2c->Mode = HAL_I2C_MODE_SLAVE;
987 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
988
989 /* Prepare transfer parameters */
990 hi2c->pBuffPtr = pData;
991 hi2c->XferCount = Size;
992 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
993 hi2c->XferSize = hi2c->XferCount;
994
995 /* Enable Address Acknowledge */
996 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
997
998 /* Wait until ADDR flag is set */
999 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1000 {
1001 return HAL_TIMEOUT;
1002 }
1003
1004 /* Clear ADDR flag */
1005 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1006
1007 /* If 10bit addressing mode is selected */
1008 if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
1009 {
1010 /* Wait until ADDR flag is set */
1011 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1012 {
1013 return HAL_TIMEOUT;
1014 }
1015
1016 /* Clear ADDR flag */
1017 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1018 }
1019
1020 while(hi2c->XferSize > 0U)
1021 {
1022 /* Wait until TXE flag is set */
1023 if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1024 {
1025 /* Disable Address Acknowledge */
1026 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1027 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
1028 {
1029 return HAL_ERROR;
1030 }
1031 else
1032 {
1033 return HAL_TIMEOUT;
1034 }
1035 }
1036
1037 /* Write data to DR */
1038 hi2c->Instance->DR = (*hi2c->pBuffPtr++);
1039 hi2c->XferCount--;
1040 hi2c->XferSize--;
1041
1042 if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0U))
1043 {
1044 /* Write data to DR */
1045 hi2c->Instance->DR = (*hi2c->pBuffPtr++);
1046 hi2c->XferCount--;
1047 hi2c->XferSize--;
1048 }
1049 }
1050
1051 /* Wait until AF flag is set */
1052 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK)
1053 {
1054 return HAL_TIMEOUT;
1055 }
1056
1057 /* Clear AF flag */
1058 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
1059
1060 /* Disable Address Acknowledge */
1061 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1062
1063 hi2c->State = HAL_I2C_STATE_READY;
1064 hi2c->Mode = HAL_I2C_MODE_NONE;
1065
1066 /* Process Unlocked */
1067 __HAL_UNLOCK(hi2c);
1068
1069 return HAL_OK;
1070 }
1071 else
1072 {
1073 return HAL_BUSY;
1074 }
1075 }
1076
1077 /**
1078 * @brief Receive in slave mode an amount of data in blocking mode
1079 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1080 * the configuration information for the specified I2C.
1081 * @param pData Pointer to data buffer
1082 * @param Size Amount of data to be sent
1083 * @param Timeout Timeout duration
1084 * @retval HAL status
1085 */
HAL_I2C_Slave_Receive(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t Timeout)1086 HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
1087 {
1088 uint32_t tickstart = 0x00U;
1089
1090 /* Init tickstart for timeout management*/
1091 tickstart = HAL_GetTick();
1092
1093 if(hi2c->State == HAL_I2C_STATE_READY)
1094 {
1095 if((pData == NULL) || (Size == 0U))
1096 {
1097 return HAL_ERROR;
1098 }
1099
1100 /* Process Locked */
1101 __HAL_LOCK(hi2c);
1102
1103 /* Check if the I2C is already enabled */
1104 if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1105 {
1106 /* Enable I2C peripheral */
1107 __HAL_I2C_ENABLE(hi2c);
1108 }
1109
1110 /* Disable Pos */
1111 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1112
1113 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1114 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1115 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1116
1117 /* Prepare transfer parameters */
1118 hi2c->pBuffPtr = pData;
1119 hi2c->XferCount = Size;
1120 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1121 hi2c->XferSize = hi2c->XferCount;
1122
1123 /* Enable Address Acknowledge */
1124 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1125
1126 /* Wait until ADDR flag is set */
1127 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1128 {
1129 return HAL_TIMEOUT;
1130 }
1131
1132 /* Clear ADDR flag */
1133 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1134
1135 while(hi2c->XferSize > 0U)
1136 {
1137 /* Wait until RXNE flag is set */
1138 if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1139 {
1140 /* Disable Address Acknowledge */
1141 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1142 if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
1143 {
1144 return HAL_TIMEOUT;
1145 }
1146 else
1147 {
1148 return HAL_ERROR;
1149 }
1150 }
1151
1152 /* Read data from DR */
1153 (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
1154 hi2c->XferSize--;
1155 hi2c->XferCount--;
1156
1157 if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0U))
1158 {
1159 /* Read data from DR */
1160 (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
1161 hi2c->XferSize--;
1162 hi2c->XferCount--;
1163 }
1164 }
1165
1166 /* Wait until STOP flag is set */
1167 if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1168 {
1169 /* Disable Address Acknowledge */
1170 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1171
1172 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
1173 {
1174 return HAL_ERROR;
1175 }
1176 else
1177 {
1178 return HAL_TIMEOUT;
1179 }
1180 }
1181
1182 /* Clear STOP flag */
1183 __HAL_I2C_CLEAR_STOPFLAG(hi2c);
1184
1185 /* Disable Address Acknowledge */
1186 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1187
1188 hi2c->State = HAL_I2C_STATE_READY;
1189 hi2c->Mode = HAL_I2C_MODE_NONE;
1190
1191 /* Process Unlocked */
1192 __HAL_UNLOCK(hi2c);
1193
1194 return HAL_OK;
1195 }
1196 else
1197 {
1198 return HAL_BUSY;
1199 }
1200 }
1201
1202 /**
1203 * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt
1204 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1205 * the configuration information for the specified I2C.
1206 * @param DevAddress Target device address: The device 7 bits address value
1207 * in datasheet must be shift at right before call interface
1208 * @param pData Pointer to data buffer
1209 * @param Size Amount of data to be sent
1210 * @retval HAL status
1211 */
HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)1212 HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
1213 {
1214 __IO uint32_t count = 0U;
1215
1216 if(hi2c->State == HAL_I2C_STATE_READY)
1217 {
1218 /* Wait until BUSY flag is reset */
1219 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
1220 do
1221 {
1222 if(count-- == 0U)
1223 {
1224 hi2c->PreviousState = I2C_STATE_NONE;
1225 hi2c->State= HAL_I2C_STATE_READY;
1226
1227 /* Process Unlocked */
1228 __HAL_UNLOCK(hi2c);
1229
1230 return HAL_TIMEOUT;
1231 }
1232 }
1233 while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
1234
1235 /* Process Locked */
1236 __HAL_LOCK(hi2c);
1237
1238 /* Check if the I2C is already enabled */
1239 if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1240 {
1241 /* Enable I2C peripheral */
1242 __HAL_I2C_ENABLE(hi2c);
1243 }
1244
1245 /* Disable Pos */
1246 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1247
1248 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1249 hi2c->Mode = HAL_I2C_MODE_MASTER;
1250 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1251
1252 /* Prepare transfer parameters */
1253 hi2c->pBuffPtr = pData;
1254 hi2c->XferCount = Size;
1255 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1256 hi2c->XferSize = hi2c->XferCount;
1257 hi2c->Devaddress = DevAddress;
1258
1259 /* Generate Start */
1260 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
1261
1262 /* Process Unlocked */
1263 __HAL_UNLOCK(hi2c);
1264
1265 /* Note : The I2C interrupts must be enabled after unlocking current process
1266 to avoid the risk of I2C interrupt handle execution before current
1267 process unlock */
1268 /* Enable EVT, BUF and ERR interrupt */
1269 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
1270
1271 return HAL_OK;
1272 }
1273 else
1274 {
1275 return HAL_BUSY;
1276 }
1277 }
1278
1279 /**
1280 * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt
1281 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1282 * the configuration information for the specified I2C.
1283 * @param DevAddress Target device address: The device 7 bits address value
1284 * in datasheet must be shift at right before call interface
1285 * @param pData Pointer to data buffer
1286 * @param Size Amount of data to be sent
1287 * @retval HAL status
1288 */
HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)1289 HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
1290 {
1291 __IO uint32_t count = 0U;
1292
1293 if(hi2c->State == HAL_I2C_STATE_READY)
1294 {
1295 /* Wait until BUSY flag is reset */
1296 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
1297 do
1298 {
1299 if(count-- == 0U)
1300 {
1301 hi2c->PreviousState = I2C_STATE_NONE;
1302 hi2c->State= HAL_I2C_STATE_READY;
1303
1304 /* Process Unlocked */
1305 __HAL_UNLOCK(hi2c);
1306
1307 return HAL_TIMEOUT;
1308 }
1309 }
1310 while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
1311
1312 /* Process Locked */
1313 __HAL_LOCK(hi2c);
1314
1315 /* Check if the I2C is already enabled */
1316 if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1317 {
1318 /* Enable I2C peripheral */
1319 __HAL_I2C_ENABLE(hi2c);
1320 }
1321
1322 /* Disable Pos */
1323 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1324
1325 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1326 hi2c->Mode = HAL_I2C_MODE_MASTER;
1327 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1328
1329 /* Prepare transfer parameters */
1330 hi2c->pBuffPtr = pData;
1331 hi2c->XferCount = Size;
1332 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1333 hi2c->XferSize = hi2c->XferCount;
1334 hi2c->Devaddress = DevAddress;
1335
1336 /* Enable Acknowledge */
1337 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1338
1339 /* Generate Start */
1340 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
1341
1342 /* Process Unlocked */
1343 __HAL_UNLOCK(hi2c);
1344
1345 /* Note : The I2C interrupts must be enabled after unlocking current process
1346 to avoid the risk of I2C interrupt handle execution before current
1347 process unlock */
1348
1349 /* Enable EVT, BUF and ERR interrupt */
1350 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
1351
1352 return HAL_OK;
1353 }
1354 else
1355 {
1356 return HAL_BUSY;
1357 }
1358 }
1359
1360 /**
1361 * @brief Sequential transmit in master mode an amount of data in non-blocking mode with Interrupt
1362 * @note This interface allow to manage repeated start condition when a direction change during transfer
1363 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1364 * the configuration information for the specified I2C.
1365 * @param DevAddress Target device address: The device 7 bits address value
1366 * in datasheet must be shift at right before call interface
1367 * @param pData Pointer to data buffer
1368 * @param Size Amount of data to be sent
1369 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
1370 * @retval HAL status
1371 */
HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)1372 HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
1373 {
1374 __IO uint32_t count = 0U;
1375
1376 /* Check the parameters */
1377 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
1378
1379 if(hi2c->State == HAL_I2C_STATE_READY)
1380 {
1381 /* Check Busy Flag only if FIRST call of Master interface */
1382 if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
1383 {
1384 /* Wait until BUSY flag is reset */
1385 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
1386 do
1387 {
1388 if(count-- == 0U)
1389 {
1390 hi2c->PreviousState = I2C_STATE_NONE;
1391 hi2c->State= HAL_I2C_STATE_READY;
1392
1393 /* Process Unlocked */
1394 __HAL_UNLOCK(hi2c);
1395
1396 return HAL_TIMEOUT;
1397 }
1398 }
1399 while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
1400 }
1401
1402 /* Process Locked */
1403 __HAL_LOCK(hi2c);
1404
1405 /* Check if the I2C is already enabled */
1406 if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1407 {
1408 /* Enable I2C peripheral */
1409 __HAL_I2C_ENABLE(hi2c);
1410 }
1411
1412 /* Disable Pos */
1413 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1414
1415 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1416 hi2c->Mode = HAL_I2C_MODE_MASTER;
1417 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1418
1419 /* Prepare transfer parameters */
1420 hi2c->pBuffPtr = pData;
1421 hi2c->XferCount = Size;
1422 hi2c->XferOptions = XferOptions;
1423 hi2c->XferSize = hi2c->XferCount;
1424 hi2c->Devaddress = DevAddress;
1425
1426 /* Generate Start */
1427 if((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) || (hi2c->PreviousState == I2C_STATE_NONE))
1428 {
1429 /* Generate Start condition if first transfer */
1430 if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
1431 {
1432 /* Generate Start */
1433 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
1434 }
1435 else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX)
1436 {
1437 /* Generate ReStart */
1438 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
1439 }
1440 }
1441
1442 /* Process Unlocked */
1443 __HAL_UNLOCK(hi2c);
1444
1445 /* Note : The I2C interrupts must be enabled after unlocking current process
1446 to avoid the risk of I2C interrupt handle execution before current
1447 process unlock */
1448
1449 /* Enable EVT, BUF and ERR interrupt */
1450 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
1451
1452 return HAL_OK;
1453 }
1454 else
1455 {
1456 return HAL_BUSY;
1457 }
1458 }
1459
1460 /**
1461 * @brief Sequential receive in master mode an amount of data in non-blocking mode with Interrupt
1462 * @note This interface allow to manage repeated start condition when a direction change during transfer
1463 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1464 * the configuration information for the specified I2C.
1465 * @param DevAddress Target device address: The device 7 bits address value
1466 * in datasheet must be shift at right before call interface
1467 * @param pData Pointer to data buffer
1468 * @param Size Amount of data to be sent
1469 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
1470 * @retval HAL status
1471 */
HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)1472 HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
1473 {
1474 __IO uint32_t count = 0U;
1475
1476 /* Check the parameters */
1477 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
1478
1479 if(hi2c->State == HAL_I2C_STATE_READY)
1480 {
1481 /* Check Busy Flag only if FIRST call of Master interface */
1482 if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
1483 {
1484 /* Wait until BUSY flag is reset */
1485 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
1486 do
1487 {
1488 if(count-- == 0U)
1489 {
1490 hi2c->PreviousState = I2C_STATE_NONE;
1491 hi2c->State= HAL_I2C_STATE_READY;
1492
1493 /* Process Unlocked */
1494 __HAL_UNLOCK(hi2c);
1495
1496 return HAL_TIMEOUT;
1497 }
1498 }
1499 while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
1500 }
1501
1502 /* Process Locked */
1503 __HAL_LOCK(hi2c);
1504
1505 /* Check if the I2C is already enabled */
1506 if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1507 {
1508 /* Enable I2C peripheral */
1509 __HAL_I2C_ENABLE(hi2c);
1510 }
1511
1512 /* Disable Pos */
1513 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1514
1515 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1516 hi2c->Mode = HAL_I2C_MODE_MASTER;
1517 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1518
1519 /* Prepare transfer parameters */
1520 hi2c->pBuffPtr = pData;
1521 hi2c->XferCount = Size;
1522 hi2c->XferOptions = XferOptions;
1523 hi2c->XferSize = hi2c->XferCount;
1524 hi2c->Devaddress = DevAddress;
1525
1526 if((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) || (hi2c->PreviousState == I2C_STATE_NONE))
1527 {
1528 /* Generate Start condition if first transfer */
1529 if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_NO_OPTION_FRAME))
1530 {
1531 /* Enable Acknowledge */
1532 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1533
1534 /* Generate Start */
1535 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
1536 }
1537 else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX)
1538 {
1539 /* Enable Acknowledge */
1540 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1541
1542 /* Generate ReStart */
1543 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
1544 }
1545 }
1546
1547 /* Process Unlocked */
1548 __HAL_UNLOCK(hi2c);
1549
1550 /* Note : The I2C interrupts must be enabled after unlocking current process
1551 to avoid the risk of I2C interrupt handle execution before current
1552 process unlock */
1553
1554 /* Enable EVT, BUF and ERR interrupt */
1555 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
1556
1557 return HAL_OK;
1558 }
1559 else
1560 {
1561 return HAL_BUSY;
1562 }
1563 }
1564
1565 /**
1566 * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt
1567 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1568 * the configuration information for the specified I2C.
1569 * @param pData Pointer to data buffer
1570 * @param Size Amount of data to be sent
1571 * @retval HAL status
1572 */
HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)1573 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
1574 {
1575 if(hi2c->State == HAL_I2C_STATE_READY)
1576 {
1577 if((pData == NULL) || (Size == 0U))
1578 {
1579 return HAL_ERROR;
1580 }
1581
1582 /* Process Locked */
1583 __HAL_LOCK(hi2c);
1584
1585 /* Check if the I2C is already enabled */
1586 if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1587 {
1588 /* Enable I2C peripheral */
1589 __HAL_I2C_ENABLE(hi2c);
1590 }
1591
1592 /* Disable Pos */
1593 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1594
1595 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1596 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1597 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1598
1599 /* Prepare transfer parameters */
1600 hi2c->pBuffPtr = pData;
1601 hi2c->XferCount = Size;
1602 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1603 hi2c->XferSize = hi2c->XferCount;
1604
1605 /* Enable Address Acknowledge */
1606 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1607
1608 /* Process Unlocked */
1609 __HAL_UNLOCK(hi2c);
1610
1611 /* Note : The I2C interrupts must be enabled after unlocking current process
1612 to avoid the risk of I2C interrupt handle execution before current
1613 process unlock */
1614
1615 /* Enable EVT, BUF and ERR interrupt */
1616 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
1617
1618 return HAL_OK;
1619 }
1620 else
1621 {
1622 return HAL_BUSY;
1623 }
1624 }
1625
1626 /**
1627 * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt
1628 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1629 * the configuration information for the specified I2C.
1630 * @param pData Pointer to data buffer
1631 * @param Size Amount of data to be sent
1632 * @retval HAL status
1633 */
HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)1634 HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
1635 {
1636 if(hi2c->State == HAL_I2C_STATE_READY)
1637 {
1638 if((pData == NULL) || (Size == 0U))
1639 {
1640 return HAL_ERROR;
1641 }
1642
1643 /* Process Locked */
1644 __HAL_LOCK(hi2c);
1645
1646 /* Check if the I2C is already enabled */
1647 if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1648 {
1649 /* Enable I2C peripheral */
1650 __HAL_I2C_ENABLE(hi2c);
1651 }
1652
1653 /* Disable Pos */
1654 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1655
1656 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1657 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1658 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1659
1660 /* Prepare transfer parameters */
1661 hi2c->pBuffPtr = pData;
1662 hi2c->XferCount = Size;
1663 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1664 hi2c->XferSize = Size;
1665
1666 /* Enable Address Acknowledge */
1667 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1668
1669 /* Process Unlocked */
1670 __HAL_UNLOCK(hi2c);
1671
1672 /* Note : The I2C interrupts must be enabled after unlocking current process
1673 to avoid the risk of I2C interrupt handle execution before current
1674 process unlock */
1675
1676 /* Enable EVT, BUF and ERR interrupt */
1677 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
1678
1679 return HAL_OK;
1680 }
1681 else
1682 {
1683 return HAL_BUSY;
1684 }
1685 }
1686
1687 /**
1688 * @brief Sequential transmit in slave mode an amount of data in non-blocking mode with Interrupt
1689 * @note This interface allow to manage repeated start condition when a direction change during transfer
1690 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1691 * the configuration information for the specified I2C.
1692 * @param pData Pointer to data buffer
1693 * @param Size Amount of data to be sent
1694 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
1695 * @retval HAL status
1696 */
HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)1697 HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
1698 {
1699 /* Check the parameters */
1700 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
1701
1702 if(hi2c->State == HAL_I2C_STATE_LISTEN)
1703 {
1704 if((pData == NULL) || (Size == 0U))
1705 {
1706 return HAL_ERROR;
1707 }
1708
1709 /* Process Locked */
1710 __HAL_LOCK(hi2c);
1711
1712 /* Check if the I2C is already enabled */
1713 if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1714 {
1715 /* Enable I2C peripheral */
1716 __HAL_I2C_ENABLE(hi2c);
1717 }
1718
1719 /* Disable Pos */
1720 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1721
1722 hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
1723 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1724 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1725
1726 /* Prepare transfer parameters */
1727 hi2c->pBuffPtr = pData;
1728 hi2c->XferCount = Size;
1729 hi2c->XferOptions = XferOptions;
1730 hi2c->XferSize = hi2c->XferCount;
1731
1732 /* Clear ADDR flag */
1733 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1734
1735 /* Process Unlocked */
1736 __HAL_UNLOCK(hi2c);
1737
1738 /* Note : The I2C interrupts must be enabled after unlocking current process
1739 to avoid the risk of I2C interrupt handle execution before current
1740 process unlock */
1741
1742 /* Enable EVT, BUF and ERR interrupt */
1743 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
1744
1745 return HAL_OK;
1746 }
1747 else
1748 {
1749 return HAL_BUSY;
1750 }
1751 }
1752
1753 /**
1754 * @brief Sequential receive in slave mode an amount of data in non-blocking mode with Interrupt
1755 * @note This interface allow to manage repeated start condition when a direction change during transfer
1756 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1757 * the configuration information for the specified I2C.
1758 * @param pData Pointer to data buffer
1759 * @param Size Amount of data to be sent
1760 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
1761 * @retval HAL status
1762 */
HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)1763 HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
1764 {
1765 /* Check the parameters */
1766 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
1767
1768 if(hi2c->State == HAL_I2C_STATE_LISTEN)
1769 {
1770 if((pData == NULL) || (Size == 0U))
1771 {
1772 return HAL_ERROR;
1773 }
1774
1775 /* Process Locked */
1776 __HAL_LOCK(hi2c);
1777
1778 /* Check if the I2C is already enabled */
1779 if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1780 {
1781 /* Enable I2C peripheral */
1782 __HAL_I2C_ENABLE(hi2c);
1783 }
1784
1785 /* Disable Pos */
1786 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1787
1788 hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
1789 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1790 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1791
1792 /* Prepare transfer parameters */
1793 hi2c->pBuffPtr = pData;
1794 hi2c->XferCount = Size;
1795 hi2c->XferOptions = XferOptions;
1796 hi2c->XferSize = hi2c->XferCount;
1797
1798 /* Clear ADDR flag */
1799 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1800
1801 /* Process Unlocked */
1802 __HAL_UNLOCK(hi2c);
1803
1804 /* Note : The I2C interrupts must be enabled after unlocking current process
1805 to avoid the risk of I2C interrupt handle execution before current
1806 process unlock */
1807
1808 /* Enable EVT, BUF and ERR interrupt */
1809 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
1810
1811 return HAL_OK;
1812 }
1813 else
1814 {
1815 return HAL_BUSY;
1816 }
1817 }
1818
1819 /**
1820 * @brief Enable the Address listen mode with Interrupt.
1821 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1822 * the configuration information for the specified I2C.
1823 * @retval HAL status
1824 */
HAL_I2C_EnableListen_IT(I2C_HandleTypeDef * hi2c)1825 HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
1826 {
1827 if(hi2c->State == HAL_I2C_STATE_READY)
1828 {
1829 hi2c->State = HAL_I2C_STATE_LISTEN;
1830
1831 /* Check if the I2C is already enabled */
1832 if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1833 {
1834 /* Enable I2C peripheral */
1835 __HAL_I2C_ENABLE(hi2c);
1836 }
1837
1838 /* Enable Address Acknowledge */
1839 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1840
1841 /* Enable EVT and ERR interrupt */
1842 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
1843
1844 return HAL_OK;
1845 }
1846 else
1847 {
1848 return HAL_BUSY;
1849 }
1850 }
1851
1852 /**
1853 * @brief Disable the Address listen mode with Interrupt.
1854 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1855 * the configuration information for the specified I2C.
1856 * @retval HAL status
1857 */
HAL_I2C_DisableListen_IT(I2C_HandleTypeDef * hi2c)1858 HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
1859 {
1860 /* Declaration of tmp to prevent undefined behavior of volatile usage */
1861 uint32_t tmp;
1862
1863 /* Disable Address listen mode only if a transfer is not ongoing */
1864 if(hi2c->State == HAL_I2C_STATE_LISTEN)
1865 {
1866 tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
1867 hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
1868 hi2c->State = HAL_I2C_STATE_READY;
1869 hi2c->Mode = HAL_I2C_MODE_NONE;
1870
1871 /* Disable Address Acknowledge */
1872 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1873
1874 /* Disable EVT and ERR interrupt */
1875 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
1876
1877 return HAL_OK;
1878 }
1879 else
1880 {
1881 return HAL_BUSY;
1882 }
1883 }
1884
1885 /**
1886 * @brief Transmit in master mode an amount of data in non-blocking mode with DMA
1887 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1888 * the configuration information for the specified I2C.
1889 * @param DevAddress Target device address: The device 7 bits address value
1890 * in datasheet must be shift at right before call interface
1891 * @param pData Pointer to data buffer
1892 * @param Size Amount of data to be sent
1893 * @retval HAL status
1894 */
HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)1895 HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
1896 {
1897 __IO uint32_t count = 0U;
1898
1899 if(hi2c->State == HAL_I2C_STATE_READY)
1900 {
1901 /* Wait until BUSY flag is reset */
1902 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
1903 do
1904 {
1905 if(count-- == 0U)
1906 {
1907 hi2c->PreviousState = I2C_STATE_NONE;
1908 hi2c->State= HAL_I2C_STATE_READY;
1909
1910 /* Process Unlocked */
1911 __HAL_UNLOCK(hi2c);
1912
1913 return HAL_TIMEOUT;
1914 }
1915 }
1916 while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
1917
1918 /* Process Locked */
1919 __HAL_LOCK(hi2c);
1920
1921 /* Check if the I2C is already enabled */
1922 if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1923 {
1924 /* Enable I2C peripheral */
1925 __HAL_I2C_ENABLE(hi2c);
1926 }
1927
1928 /* Disable Pos */
1929 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1930
1931 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1932 hi2c->Mode = HAL_I2C_MODE_MASTER;
1933 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1934
1935 /* Prepare transfer parameters */
1936 hi2c->pBuffPtr = pData;
1937 hi2c->XferCount = Size;
1938 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1939 hi2c->XferSize = hi2c->XferCount;
1940 hi2c->Devaddress = DevAddress;
1941
1942 if(hi2c->XferSize > 0U)
1943 {
1944 /* Set the I2C DMA transfer complete callback */
1945 hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
1946
1947 /* Set the DMA error callback */
1948 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
1949
1950 /* Set the unused DMA callbacks to NULL */
1951 hi2c->hdmatx->XferHalfCpltCallback = NULL;
1952 hi2c->hdmatx->XferAbortCallback = NULL;
1953
1954 /* Enable the DMA Channel */
1955 HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
1956
1957 /* Enable Acknowledge */
1958 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1959
1960 /* Generate Start */
1961 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
1962
1963 /* Process Unlocked */
1964 __HAL_UNLOCK(hi2c);
1965
1966 /* Note : The I2C interrupts must be enabled after unlocking current process
1967 to avoid the risk of I2C interrupt handle execution before current
1968 process unlock */
1969
1970 /* Enable EVT and ERR interrupt */
1971 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
1972
1973 /* Enable DMA Request */
1974 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
1975 }
1976 else
1977 {
1978 /* Enable Acknowledge */
1979 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1980
1981 /* Generate Start */
1982 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
1983
1984 /* Process Unlocked */
1985 __HAL_UNLOCK(hi2c);
1986
1987 /* Note : The I2C interrupts must be enabled after unlocking current process
1988 to avoid the risk of I2C interrupt handle execution before current
1989 process unlock */
1990
1991 /* Enable EVT, BUF and ERR interrupt */
1992 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
1993 }
1994
1995 return HAL_OK;
1996 }
1997 else
1998 {
1999 return HAL_BUSY;
2000 }
2001 }
2002
2003 /**
2004 * @brief Receive in master mode an amount of data in non-blocking mode with DMA
2005 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2006 * the configuration information for the specified I2C.
2007 * @param DevAddress Target device address: The device 7 bits address value
2008 * in datasheet must be shift at right before call interface
2009 * @param pData Pointer to data buffer
2010 * @param Size Amount of data to be sent
2011 * @retval HAL status
2012 */
HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)2013 HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
2014 {
2015 __IO uint32_t count = 0U;
2016
2017 if(hi2c->State == HAL_I2C_STATE_READY)
2018 {
2019 /* Wait until BUSY flag is reset */
2020 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
2021 do
2022 {
2023 if(count-- == 0U)
2024 {
2025 hi2c->PreviousState = I2C_STATE_NONE;
2026 hi2c->State= HAL_I2C_STATE_READY;
2027
2028 /* Process Unlocked */
2029 __HAL_UNLOCK(hi2c);
2030
2031 return HAL_TIMEOUT;
2032 }
2033 }
2034 while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
2035
2036 /* Process Locked */
2037 __HAL_LOCK(hi2c);
2038
2039 /* Check if the I2C is already enabled */
2040 if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2041 {
2042 /* Enable I2C peripheral */
2043 __HAL_I2C_ENABLE(hi2c);
2044 }
2045
2046 /* Disable Pos */
2047 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2048
2049 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2050 hi2c->Mode = HAL_I2C_MODE_MASTER;
2051 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2052
2053 /* Prepare transfer parameters */
2054 hi2c->pBuffPtr = pData;
2055 hi2c->XferCount = Size;
2056 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2057 hi2c->XferSize = hi2c->XferCount;
2058 hi2c->Devaddress = DevAddress;
2059
2060 if(hi2c->XferSize > 0U)
2061 {
2062 /* Set the I2C DMA transfer complete callback */
2063 hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
2064
2065 /* Set the DMA error callback */
2066 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
2067
2068 /* Set the unused DMA callbacks to NULL */
2069 hi2c->hdmarx->XferHalfCpltCallback = NULL;
2070 hi2c->hdmarx->XferAbortCallback = NULL;
2071
2072 /* Enable the DMA Channel */
2073 HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
2074
2075 /* Enable Acknowledge */
2076 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2077
2078 /* Generate Start */
2079 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
2080
2081 /* Process Unlocked */
2082 __HAL_UNLOCK(hi2c);
2083
2084 /* Note : The I2C interrupts must be enabled after unlocking current process
2085 to avoid the risk of I2C interrupt handle execution before current
2086 process unlock */
2087
2088 /* Enable EVT and ERR interrupt */
2089 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
2090
2091 /* Enable DMA Request */
2092 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
2093 }
2094 else
2095 {
2096 /* Enable Acknowledge */
2097 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2098
2099 /* Generate Start */
2100 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
2101
2102 /* Process Unlocked */
2103 __HAL_UNLOCK(hi2c);
2104
2105 /* Note : The I2C interrupts must be enabled after unlocking current process
2106 to avoid the risk of I2C interrupt handle execution before current
2107 process unlock */
2108
2109 /* Enable EVT, BUF and ERR interrupt */
2110 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
2111 }
2112
2113 return HAL_OK;
2114 }
2115 else
2116 {
2117 return HAL_BUSY;
2118 }
2119 }
2120
2121 /**
2122 * @brief Abort a master I2C process communication with Interrupt.
2123 * @note This abort can be called only if state is ready
2124 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2125 * the configuration information for the specified I2C.
2126 * @param DevAddress Target device address: The device 7 bits address value
2127 * in datasheet must be shift at right before call interface
2128 * @retval HAL status
2129 */
HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress)2130 HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
2131 {
2132 /* Abort Master transfer during Receive or Transmit process */
2133 if(hi2c->Mode == HAL_I2C_MODE_MASTER)
2134 {
2135 /* Process Locked */
2136 __HAL_LOCK(hi2c);
2137
2138 hi2c->PreviousState = I2C_STATE_NONE;
2139 hi2c->State = HAL_I2C_STATE_ABORT;
2140
2141 /* Disable Acknowledge */
2142 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2143
2144 /* Generate Stop */
2145 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
2146
2147 hi2c->XferCount = 0U;
2148
2149 /* Disable EVT, BUF and ERR interrupt */
2150 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
2151
2152 /* Process Unlocked */
2153 __HAL_UNLOCK(hi2c);
2154
2155 /* Call the corresponding callback to inform upper layer of End of Transfer */
2156 I2C_ITError(hi2c);
2157
2158 return HAL_OK;
2159 }
2160 else
2161 {
2162 /* Wrong usage of abort function */
2163 /* This function should be used only in case of abort monitored by master device */
2164 return HAL_ERROR;
2165 }
2166 }
2167
2168 /**
2169 * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA
2170 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2171 * the configuration information for the specified I2C.
2172 * @param pData Pointer to data buffer
2173 * @param Size Amount of data to be sent
2174 * @retval HAL status
2175 */
HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)2176 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
2177 {
2178 if(hi2c->State == HAL_I2C_STATE_READY)
2179 {
2180 if((pData == NULL) || (Size == 0U))
2181 {
2182 return HAL_ERROR;
2183 }
2184
2185 /* Process Locked */
2186 __HAL_LOCK(hi2c);
2187
2188 /* Check if the I2C is already enabled */
2189 if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2190 {
2191 /* Enable I2C peripheral */
2192 __HAL_I2C_ENABLE(hi2c);
2193 }
2194
2195 /* Disable Pos */
2196 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2197
2198 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2199 hi2c->Mode = HAL_I2C_MODE_SLAVE;
2200 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2201
2202 /* Prepare transfer parameters */
2203 hi2c->pBuffPtr = pData;
2204 hi2c->XferCount = Size;
2205 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2206 hi2c->XferSize = hi2c->XferCount;
2207
2208 /* Set the I2C DMA transfer complete callback */
2209 hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
2210
2211 /* Set the DMA error callback */
2212 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
2213
2214 /* Set the unused DMA callbacks to NULL */
2215 hi2c->hdmatx->XferHalfCpltCallback = NULL;
2216 hi2c->hdmatx->XferAbortCallback = NULL;
2217
2218 /* Enable the DMA Channel */
2219 HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
2220
2221 /* Enable Address Acknowledge */
2222 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2223
2224 /* Process Unlocked */
2225 __HAL_UNLOCK(hi2c);
2226
2227 /* Note : The I2C interrupts must be enabled after unlocking current process
2228 to avoid the risk of I2C interrupt handle execution before current
2229 process unlock */
2230 /* Enable EVT and ERR interrupt */
2231 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
2232
2233 /* Enable DMA Request */
2234 hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
2235
2236 return HAL_OK;
2237 }
2238 else
2239 {
2240 return HAL_BUSY;
2241 }
2242 }
2243
2244 /**
2245 * @brief Receive in slave mode an amount of data in non-blocking mode with DMA
2246 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2247 * the configuration information for the specified I2C.
2248 * @param pData Pointer to data buffer
2249 * @param Size Amount of data to be sent
2250 * @retval HAL status
2251 */
HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)2252 HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
2253 {
2254 if(hi2c->State == HAL_I2C_STATE_READY)
2255 {
2256 if((pData == NULL) || (Size == 0U))
2257 {
2258 return HAL_ERROR;
2259 }
2260
2261 /* Process Locked */
2262 __HAL_LOCK(hi2c);
2263
2264 /* Check if the I2C is already enabled */
2265 if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2266 {
2267 /* Enable I2C peripheral */
2268 __HAL_I2C_ENABLE(hi2c);
2269 }
2270
2271 /* Disable Pos */
2272 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2273
2274 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2275 hi2c->Mode = HAL_I2C_MODE_SLAVE;
2276 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2277
2278 /* Prepare transfer parameters */
2279 hi2c->pBuffPtr = pData;
2280 hi2c->XferCount = Size;
2281 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2282 hi2c->XferSize = hi2c->XferCount;
2283
2284 /* Set the I2C DMA transfer complete callback */
2285 hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
2286
2287 /* Set the DMA error callback */
2288 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
2289
2290 /* Set the unused DMA callbacks to NULL */
2291 hi2c->hdmarx->XferHalfCpltCallback = NULL;
2292 hi2c->hdmarx->XferAbortCallback = NULL;
2293
2294 /* Enable the DMA Channel */
2295 HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
2296
2297 /* Enable Address Acknowledge */
2298 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2299
2300 /* Process Unlocked */
2301 __HAL_UNLOCK(hi2c);
2302
2303 /* Note : The I2C interrupts must be enabled after unlocking current process
2304 to avoid the risk of I2C interrupt handle execution before current
2305 process unlock */
2306 /* Enable EVT and ERR interrupt */
2307 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
2308
2309 /* Enable DMA Request */
2310 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
2311
2312 return HAL_OK;
2313 }
2314 else
2315 {
2316 return HAL_BUSY;
2317 }
2318 }
2319 /**
2320 * @brief Write an amount of data in blocking mode to a specific memory address
2321 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2322 * the configuration information for the specified I2C.
2323 * @param DevAddress Target device address: The device 7 bits address value
2324 * in datasheet must be shift at right before call interface
2325 * @param MemAddress Internal memory address
2326 * @param MemAddSize Size of internal memory address
2327 * @param pData Pointer to data buffer
2328 * @param Size Amount of data to be sent
2329 * @param Timeout Timeout duration
2330 * @retval HAL status
2331 */
HAL_I2C_Mem_Write(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size,uint32_t Timeout)2332 HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
2333 {
2334 uint32_t tickstart = 0x00U;
2335
2336 /* Init tickstart for timeout management*/
2337 tickstart = HAL_GetTick();
2338
2339 /* Check the parameters */
2340 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2341
2342 if(hi2c->State == HAL_I2C_STATE_READY)
2343 {
2344 if((pData == NULL) || (Size == 0U))
2345 {
2346 return HAL_ERROR;
2347 }
2348
2349 /* Wait until BUSY flag is reset */
2350 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
2351 {
2352 return HAL_BUSY;
2353 }
2354
2355 /* Process Locked */
2356 __HAL_LOCK(hi2c);
2357
2358 /* Check if the I2C is already enabled */
2359 if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2360 {
2361 /* Enable I2C peripheral */
2362 __HAL_I2C_ENABLE(hi2c);
2363 }
2364
2365 /* Disable Pos */
2366 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2367
2368 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2369 hi2c->Mode = HAL_I2C_MODE_MEM;
2370 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2371
2372 /* Prepare transfer parameters */
2373 hi2c->pBuffPtr = pData;
2374 hi2c->XferCount = Size;
2375 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2376 hi2c->XferSize = hi2c->XferCount;
2377
2378 /* Send Slave Address and Memory Address */
2379 if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
2380 {
2381 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
2382 {
2383 /* Process Unlocked */
2384 __HAL_UNLOCK(hi2c);
2385 return HAL_ERROR;
2386 }
2387 else
2388 {
2389 /* Process Unlocked */
2390 __HAL_UNLOCK(hi2c);
2391 return HAL_TIMEOUT;
2392 }
2393 }
2394
2395 while(hi2c->XferSize > 0U)
2396 {
2397 /* Wait until TXE flag is set */
2398 if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2399 {
2400 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
2401 {
2402 /* Generate Stop */
2403 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
2404 return HAL_ERROR;
2405 }
2406 else
2407 {
2408 return HAL_TIMEOUT;
2409 }
2410 }
2411
2412 /* Write data to DR */
2413 hi2c->Instance->DR = (*hi2c->pBuffPtr++);
2414 hi2c->XferSize--;
2415 hi2c->XferCount--;
2416
2417 if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
2418 {
2419 /* Write data to DR */
2420 hi2c->Instance->DR = (*hi2c->pBuffPtr++);
2421 hi2c->XferSize--;
2422 hi2c->XferCount--;
2423 }
2424 }
2425
2426 /* Wait until BTF flag is set */
2427 if(I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2428 {
2429 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
2430 {
2431 /* Generate Stop */
2432 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
2433 return HAL_ERROR;
2434 }
2435 else
2436 {
2437 return HAL_TIMEOUT;
2438 }
2439 }
2440
2441 /* Generate Stop */
2442 SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP);
2443
2444 hi2c->State = HAL_I2C_STATE_READY;
2445 hi2c->Mode = HAL_I2C_MODE_NONE;
2446
2447 /* Process Unlocked */
2448 __HAL_UNLOCK(hi2c);
2449
2450 return HAL_OK;
2451 }
2452 else
2453 {
2454 return HAL_BUSY;
2455 }
2456 }
2457
2458 /**
2459 * @brief Read an amount of data in blocking mode from a specific memory address
2460 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2461 * the configuration information for the specified I2C.
2462 * @param DevAddress Target device address: The device 7 bits address value
2463 * in datasheet must be shift at right before call interface
2464 * @param MemAddress Internal memory address
2465 * @param MemAddSize Size of internal memory address
2466 * @param pData Pointer to data buffer
2467 * @param Size Amount of data to be sent
2468 * @param Timeout Timeout duration
2469 * @retval HAL status
2470 */
HAL_I2C_Mem_Read(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size,uint32_t Timeout)2471 HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
2472 {
2473 uint32_t tickstart = 0x00U;
2474
2475 /* Init tickstart for timeout management*/
2476 tickstart = HAL_GetTick();
2477
2478 /* Check the parameters */
2479 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2480
2481 if(hi2c->State == HAL_I2C_STATE_READY)
2482 {
2483 if((pData == NULL) || (Size == 0U))
2484 {
2485 return HAL_ERROR;
2486 }
2487
2488 /* Wait until BUSY flag is reset */
2489 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
2490 {
2491 return HAL_BUSY;
2492 }
2493
2494 /* Process Locked */
2495 __HAL_LOCK(hi2c);
2496
2497 /* Check if the I2C is already enabled */
2498 if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2499 {
2500 /* Enable I2C peripheral */
2501 __HAL_I2C_ENABLE(hi2c);
2502 }
2503
2504 /* Disable Pos */
2505 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2506
2507 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2508 hi2c->Mode = HAL_I2C_MODE_MEM;
2509 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2510
2511 /* Prepare transfer parameters */
2512 hi2c->pBuffPtr = pData;
2513 hi2c->XferCount = Size;
2514 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2515 hi2c->XferSize = hi2c->XferCount;
2516
2517 /* Send Slave Address and Memory Address */
2518 if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
2519 {
2520 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
2521 {
2522 /* Process Unlocked */
2523 __HAL_UNLOCK(hi2c);
2524 return HAL_ERROR;
2525 }
2526 else
2527 {
2528 /* Process Unlocked */
2529 __HAL_UNLOCK(hi2c);
2530 return HAL_TIMEOUT;
2531 }
2532 }
2533
2534 if(hi2c->XferSize == 1U)
2535 {
2536 /* Disable Acknowledge */
2537 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2538
2539 /* Clear ADDR flag */
2540 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
2541
2542 /* Generate Stop */
2543 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
2544 }
2545 else if(hi2c->XferSize == 2U)
2546 {
2547 /* Disable Acknowledge */
2548 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2549
2550 /* Enable Pos */
2551 SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2552
2553 /* Clear ADDR flag */
2554 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
2555 }
2556 else
2557 {
2558 /* Clear ADDR flag */
2559 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
2560 }
2561
2562 while(hi2c->XferSize > 0U)
2563 {
2564 if(hi2c->XferSize <= 3U)
2565 {
2566 /* One byte */
2567 if(hi2c->XferSize== 1U)
2568 {
2569 /* Wait until RXNE flag is set */
2570 if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2571 {
2572 if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
2573 {
2574 return HAL_TIMEOUT;
2575 }
2576 else
2577 {
2578 return HAL_ERROR;
2579 }
2580 }
2581
2582 /* Read data from DR */
2583 (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
2584 hi2c->XferSize--;
2585 hi2c->XferCount--;
2586 }
2587 /* Two bytes */
2588 else if(Size == 2U)
2589 {
2590 /* Wait until BTF flag is set */
2591 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
2592 {
2593 return HAL_TIMEOUT;
2594 }
2595
2596 /* Generate Stop */
2597 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
2598
2599 /* Read data from DR */
2600 (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
2601 hi2c->XferSize--;
2602 hi2c->XferCount--;
2603
2604 /* Read data from DR */
2605 (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
2606 hi2c->XferSize--;
2607 hi2c->XferCount--;
2608 }
2609 /* 3 Last bytes */
2610 else
2611 {
2612 /* Wait until BTF flag is set */
2613 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
2614 {
2615 return HAL_TIMEOUT;
2616 }
2617
2618 /* Disable Acknowledge */
2619 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2620
2621 /* Read data from DR */
2622 (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
2623 hi2c->XferSize--;
2624 hi2c->XferCount--;
2625
2626 /* Wait until BTF flag is set */
2627 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
2628 {
2629 return HAL_TIMEOUT;
2630 }
2631
2632 /* Generate Stop */
2633 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
2634
2635 /* Read data from DR */
2636 (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
2637 hi2c->XferSize--;
2638 hi2c->XferCount--;
2639
2640 /* Read data from DR */
2641 (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
2642 hi2c->XferSize--;
2643 hi2c->XferCount--;
2644 }
2645 }
2646 else
2647 {
2648 /* Wait until RXNE flag is set */
2649 if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2650 {
2651 if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
2652 {
2653 return HAL_TIMEOUT;
2654 }
2655 else
2656 {
2657 return HAL_ERROR;
2658 }
2659 }
2660
2661 /* Read data from DR */
2662 (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
2663 hi2c->XferSize--;
2664 hi2c->XferCount--;
2665
2666 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
2667 {
2668 /* Read data from DR */
2669 (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
2670 hi2c->XferSize--;
2671 hi2c->XferCount--;
2672 }
2673 }
2674 }
2675
2676 hi2c->State = HAL_I2C_STATE_READY;
2677 hi2c->Mode = HAL_I2C_MODE_NONE;
2678
2679 /* Process Unlocked */
2680 __HAL_UNLOCK(hi2c);
2681
2682 return HAL_OK;
2683 }
2684 else
2685 {
2686 return HAL_BUSY;
2687 }
2688 }
2689
2690 /**
2691 * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address
2692 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2693 * the configuration information for the specified I2C.
2694 * @param DevAddress Target device address: The device 7 bits address value
2695 * in datasheet must be shift at right before call interface
2696 * @param MemAddress Internal memory address
2697 * @param MemAddSize Size of internal memory address
2698 * @param pData Pointer to data buffer
2699 * @param Size Amount of data to be sent
2700 * @retval HAL status
2701 */
HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)2702 HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2703 {
2704 uint32_t tickstart = 0x00U;
2705
2706 /* Init tickstart for timeout management*/
2707 tickstart = HAL_GetTick();
2708
2709 /* Check the parameters */
2710 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2711
2712 if(hi2c->State == HAL_I2C_STATE_READY)
2713 {
2714 if((pData == NULL) || (Size == 0U))
2715 {
2716 return HAL_ERROR;
2717 }
2718
2719 /* Wait until BUSY flag is reset */
2720 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
2721 {
2722 return HAL_BUSY;
2723 }
2724
2725 /* Process Locked */
2726 __HAL_LOCK(hi2c);
2727
2728 /* Check if the I2C is already enabled */
2729 if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2730 {
2731 /* Enable I2C peripheral */
2732 __HAL_I2C_ENABLE(hi2c);
2733 }
2734
2735 /* Disable Pos */
2736 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2737
2738 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2739 hi2c->Mode = HAL_I2C_MODE_MEM;
2740 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2741
2742 /* Prepare transfer parameters */
2743 hi2c->pBuffPtr = pData;
2744 hi2c->XferCount = Size;
2745 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2746 hi2c->XferSize = hi2c->XferCount;
2747
2748 /* Send Slave Address and Memory Address */
2749 if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
2750 {
2751 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
2752 {
2753 /* Process Unlocked */
2754 __HAL_UNLOCK(hi2c);
2755 return HAL_ERROR;
2756 }
2757 else
2758 {
2759 /* Process Unlocked */
2760 __HAL_UNLOCK(hi2c);
2761 return HAL_TIMEOUT;
2762 }
2763 }
2764
2765 /* Process Unlocked */
2766 __HAL_UNLOCK(hi2c);
2767
2768 /* Note : The I2C interrupts must be enabled after unlocking current process
2769 to avoid the risk of I2C interrupt handle execution before current
2770 process unlock */
2771
2772 /* Enable EVT, BUF and ERR interrupt */
2773 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
2774
2775 return HAL_OK;
2776 }
2777 else
2778 {
2779 return HAL_BUSY;
2780 }
2781 }
2782
2783 /**
2784 * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address
2785 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2786 * the configuration information for the specified I2C.
2787 * @param DevAddress Target device address: The device 7 bits address value
2788 * in datasheet must be shift at right before call interface
2789 * @param MemAddress Internal memory address
2790 * @param MemAddSize Size of internal memory address
2791 * @param pData Pointer to data buffer
2792 * @param Size Amount of data to be sent
2793 * @retval HAL status
2794 */
HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)2795 HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2796 {
2797 uint32_t tickstart = 0x00U;
2798
2799 /* Init tickstart for timeout management*/
2800 tickstart = HAL_GetTick();
2801
2802 /* Check the parameters */
2803 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2804
2805 if(hi2c->State == HAL_I2C_STATE_READY)
2806 {
2807 if((pData == NULL) || (Size == 0U))
2808 {
2809 return HAL_ERROR;
2810 }
2811
2812 /* Wait until BUSY flag is reset */
2813 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
2814 {
2815 return HAL_BUSY;
2816 }
2817
2818 /* Process Locked */
2819 __HAL_LOCK(hi2c);
2820
2821 /* Check if the I2C is already enabled */
2822 if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2823 {
2824 /* Enable I2C peripheral */
2825 __HAL_I2C_ENABLE(hi2c);
2826 }
2827
2828 /* Disable Pos */
2829 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2830
2831 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2832 hi2c->Mode = HAL_I2C_MODE_MEM;
2833 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2834
2835 /* Prepare transfer parameters */
2836 hi2c->pBuffPtr = pData;
2837 hi2c->XferCount = Size;
2838 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2839 hi2c->XferSize = hi2c->XferCount;
2840
2841 /* Send Slave Address and Memory Address */
2842 if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
2843 {
2844 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
2845 {
2846 /* Process Unlocked */
2847 __HAL_UNLOCK(hi2c);
2848 return HAL_ERROR;
2849 }
2850 else
2851 {
2852 /* Process Unlocked */
2853 __HAL_UNLOCK(hi2c);
2854 return HAL_TIMEOUT;
2855 }
2856 }
2857
2858 if(hi2c->XferCount == 1U)
2859 {
2860 /* Disable Acknowledge */
2861 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2862
2863 /* Clear ADDR flag */
2864 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
2865
2866 /* Generate Stop */
2867 SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP);
2868 }
2869 else if(hi2c->XferCount == 2U)
2870 {
2871 /* Disable Acknowledge */
2872 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2873
2874 /* Enable Pos */
2875 SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2876
2877 /* Clear ADDR flag */
2878 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
2879 }
2880 else
2881 {
2882 /* Enable Acknowledge */
2883 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2884
2885 /* Clear ADDR flag */
2886 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
2887 }
2888
2889 /* Process Unlocked */
2890 __HAL_UNLOCK(hi2c);
2891
2892 /* Note : The I2C interrupts must be enabled after unlocking current process
2893 to avoid the risk of I2C interrupt handle execution before current
2894 process unlock */
2895
2896 /* Enable EVT, BUF and ERR interrupt */
2897 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
2898
2899 return HAL_OK;
2900 }
2901 else
2902 {
2903 return HAL_BUSY;
2904 }
2905 }
2906
2907 /**
2908 * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address
2909 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2910 * the configuration information for the specified I2C.
2911 * @param DevAddress Target device address: The device 7 bits address value
2912 * in datasheet must be shift at right before call interface
2913 * @param MemAddress Internal memory address
2914 * @param MemAddSize Size of internal memory address
2915 * @param pData Pointer to data buffer
2916 * @param Size Amount of data to be sent
2917 * @retval HAL status
2918 */
HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)2919 HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2920 {
2921 uint32_t tickstart = 0x00U;
2922
2923 /* Init tickstart for timeout management*/
2924 tickstart = HAL_GetTick();
2925
2926 /* Check the parameters */
2927 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2928
2929 if(hi2c->State == HAL_I2C_STATE_READY)
2930 {
2931 if((pData == NULL) || (Size == 0U))
2932 {
2933 return HAL_ERROR;
2934 }
2935
2936 /* Wait until BUSY flag is reset */
2937 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
2938 {
2939 return HAL_BUSY;
2940 }
2941
2942 /* Process Locked */
2943 __HAL_LOCK(hi2c);
2944
2945 /* Check if the I2C is already enabled */
2946 if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2947 {
2948 /* Enable I2C peripheral */
2949 __HAL_I2C_ENABLE(hi2c);
2950 }
2951
2952 /* Disable Pos */
2953 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2954
2955 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2956 hi2c->Mode = HAL_I2C_MODE_MEM;
2957 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2958
2959 /* Prepare transfer parameters */
2960 hi2c->pBuffPtr = pData;
2961 hi2c->XferCount = Size;
2962 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2963 hi2c->XferSize = hi2c->XferCount;
2964
2965 /* Set the I2C DMA transfer complete callback */
2966 hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
2967
2968 /* Set the DMA error callback */
2969 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
2970
2971 /* Set the unused DMA callbacks to NULL */
2972 hi2c->hdmatx->XferHalfCpltCallback = NULL;
2973 hi2c->hdmatx->XferAbortCallback = NULL;
2974
2975 /* Enable the DMA Channel */
2976 HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
2977
2978 /* Send Slave Address and Memory Address */
2979 if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
2980 {
2981 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
2982 {
2983 /* Process Unlocked */
2984 __HAL_UNLOCK(hi2c);
2985 return HAL_ERROR;
2986 }
2987 else
2988 {
2989 /* Process Unlocked */
2990 __HAL_UNLOCK(hi2c);
2991 return HAL_TIMEOUT;
2992 }
2993 }
2994
2995 /* Clear ADDR flag */
2996 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
2997
2998 /* Process Unlocked */
2999 __HAL_UNLOCK(hi2c);
3000
3001 /* Note : The I2C interrupts must be enabled after unlocking current process
3002 to avoid the risk of I2C interrupt handle execution before current
3003 process unlock */
3004 /* Enable ERR interrupt */
3005 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
3006
3007 /* Enable DMA Request */
3008 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
3009
3010 return HAL_OK;
3011 }
3012 else
3013 {
3014 return HAL_BUSY;
3015 }
3016 }
3017
3018 /**
3019 * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address.
3020 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3021 * the configuration information for the specified I2C.
3022 * @param DevAddress Target device address: The device 7 bits address value
3023 * in datasheet must be shift at right before call interface
3024 * @param MemAddress Internal memory address
3025 * @param MemAddSize Size of internal memory address
3026 * @param pData Pointer to data buffer
3027 * @param Size Amount of data to be read
3028 * @retval HAL status
3029 */
HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)3030 HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
3031 {
3032 uint32_t tickstart = 0x00U;
3033
3034 /* Init tickstart for timeout management*/
3035 tickstart = HAL_GetTick();
3036
3037 /* Check the parameters */
3038 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
3039
3040 if(hi2c->State == HAL_I2C_STATE_READY)
3041 {
3042 if((pData == NULL) || (Size == 0U))
3043 {
3044 return HAL_ERROR;
3045 }
3046
3047 /* Wait until BUSY flag is reset */
3048 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
3049 {
3050 return HAL_BUSY;
3051 }
3052
3053 /* Process Locked */
3054 __HAL_LOCK(hi2c);
3055
3056 /* Check if the I2C is already enabled */
3057 if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
3058 {
3059 /* Enable I2C peripheral */
3060 __HAL_I2C_ENABLE(hi2c);
3061 }
3062
3063 /* Disable Pos */
3064 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
3065
3066 hi2c->State = HAL_I2C_STATE_BUSY_RX;
3067 hi2c->Mode = HAL_I2C_MODE_MEM;
3068 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3069
3070 /* Prepare transfer parameters */
3071 hi2c->pBuffPtr = pData;
3072 hi2c->XferCount = Size;
3073 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
3074 hi2c->XferSize = hi2c->XferCount;
3075
3076 /* Set the I2C DMA transfer complete callback */
3077 hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
3078
3079 /* Set the DMA error callback */
3080 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
3081
3082 /* Set the unused DMA callbacks to NULL */
3083 hi2c->hdmarx->XferHalfCpltCallback = NULL;
3084 hi2c->hdmarx->XferAbortCallback = NULL;
3085
3086 /* Enable the DMA Channel */
3087 HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
3088
3089 /* Send Slave Address and Memory Address */
3090 if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
3091 {
3092 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
3093 {
3094 /* Process Unlocked */
3095 __HAL_UNLOCK(hi2c);
3096 return HAL_ERROR;
3097 }
3098 else
3099 {
3100 /* Process Unlocked */
3101 __HAL_UNLOCK(hi2c);
3102 return HAL_TIMEOUT;
3103 }
3104 }
3105
3106 if(Size == 1U)
3107 {
3108 /* Disable Acknowledge */
3109 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3110 }
3111 else
3112 {
3113 /* Enable Last DMA bit */
3114 SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
3115 }
3116
3117 /* Clear ADDR flag */
3118 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
3119
3120 /* Process Unlocked */
3121 __HAL_UNLOCK(hi2c);
3122
3123 /* Note : The I2C interrupts must be enabled after unlocking current process
3124 to avoid the risk of I2C interrupt handle execution before current
3125 process unlock */
3126 /* Enable ERR interrupt */
3127 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
3128
3129 /* Enable DMA Request */
3130 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
3131
3132 return HAL_OK;
3133 }
3134 else
3135 {
3136 return HAL_BUSY;
3137 }
3138 }
3139
3140 /**
3141 * @brief Checks if target device is ready for communication.
3142 * @note This function is used with Memory devices
3143 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3144 * the configuration information for the specified I2C.
3145 * @param DevAddress Target device address: The device 7 bits address value
3146 * in datasheet must be shift at right before call interface
3147 * @param Trials Number of trials
3148 * @param Timeout Timeout duration
3149 * @retval HAL status
3150 */
HAL_I2C_IsDeviceReady(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint32_t Trials,uint32_t Timeout)3151 HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
3152 {
3153 uint32_t tickstart = 0U, I2C_Trials = 1U;
3154
3155 /* Get tick */
3156 tickstart = HAL_GetTick();
3157
3158 if(hi2c->State == HAL_I2C_STATE_READY)
3159 {
3160 /* Wait until BUSY flag is reset */
3161 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
3162 {
3163 return HAL_BUSY;
3164 }
3165
3166 /* Process Locked */
3167 __HAL_LOCK(hi2c);
3168
3169 /* Check if the I2C is already enabled */
3170 if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
3171 {
3172 /* Enable I2C peripheral */
3173 __HAL_I2C_ENABLE(hi2c);
3174 }
3175
3176 /* Disable Pos */
3177 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
3178
3179 hi2c->State = HAL_I2C_STATE_BUSY;
3180 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3181 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
3182
3183 do
3184 {
3185 /* Generate Start */
3186 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
3187
3188 /* Wait until SB flag is set */
3189 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, tickstart) != HAL_OK)
3190 {
3191 return HAL_TIMEOUT;
3192 }
3193
3194 /* Send slave address */
3195 hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
3196
3197 /* Wait until ADDR or AF flag are set */
3198 /* Get tick */
3199 tickstart = HAL_GetTick();
3200
3201 while((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == RESET) && \
3202 (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) && \
3203 (hi2c->State != HAL_I2C_STATE_TIMEOUT))
3204 {
3205 if(Timeout != HAL_MAX_DELAY)
3206 {
3207 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
3208 {
3209 hi2c->State = HAL_I2C_STATE_TIMEOUT;
3210 }
3211 }
3212 }
3213
3214 hi2c->State = HAL_I2C_STATE_READY;
3215
3216 /* Check if the ADDR flag has been set */
3217 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)
3218 {
3219 /* Generate Stop */
3220 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
3221
3222 /* Clear ADDR Flag */
3223 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
3224
3225 /* Wait until BUSY flag is reset */
3226 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
3227 {
3228 return HAL_TIMEOUT;
3229 }
3230
3231 hi2c->State = HAL_I2C_STATE_READY;
3232
3233 /* Process Unlocked */
3234 __HAL_UNLOCK(hi2c);
3235
3236 return HAL_OK;
3237 }
3238 else
3239 {
3240 /* Generate Stop */
3241 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
3242
3243 /* Clear AF Flag */
3244 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
3245
3246 /* Wait until BUSY flag is reset */
3247 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
3248 {
3249 return HAL_TIMEOUT;
3250 }
3251 }
3252 }while(I2C_Trials++ < Trials);
3253
3254 hi2c->State = HAL_I2C_STATE_READY;
3255
3256 /* Process Unlocked */
3257 __HAL_UNLOCK(hi2c);
3258
3259 return HAL_ERROR;
3260 }
3261 else
3262 {
3263 return HAL_BUSY;
3264 }
3265 }
3266
3267 /**
3268 * @brief This function handles I2C event interrupt request.
3269 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3270 * the configuration information for the specified I2C.
3271 * @retval None
3272 */
HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef * hi2c)3273 void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
3274 {
3275 uint32_t sr2itflags = READ_REG(hi2c->Instance->SR2);
3276 uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1);
3277 uint32_t itsources = READ_REG(hi2c->Instance->CR2);
3278
3279 /* Master or Memory mode selected */
3280 if((hi2c->Mode == HAL_I2C_MODE_MASTER) || \
3281 (hi2c->Mode == HAL_I2C_MODE_MEM))
3282 {
3283 /* SB Set ----------------------------------------------------------------*/
3284 if(((sr1itflags & I2C_FLAG_SB) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
3285 {
3286 I2C_Master_SB(hi2c);
3287 }
3288 /* ADD10 Set -------------------------------------------------------------*/
3289 else if(((sr1itflags & I2C_FLAG_ADD10) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
3290 {
3291 I2C_Master_ADD10(hi2c);
3292 }
3293 /* ADDR Set --------------------------------------------------------------*/
3294 else if(((sr1itflags & I2C_FLAG_ADDR) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
3295 {
3296 I2C_Master_ADDR(hi2c);
3297 }
3298
3299 /* I2C in mode Transmitter -----------------------------------------------*/
3300 if((hi2c->EventCount == 0U) && ((sr2itflags & I2C_FLAG_TRA) != RESET))
3301 {
3302 /* TXE set and BTF reset -----------------------------------------------*/
3303 if(((sr1itflags & I2C_FLAG_TXE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET))
3304 {
3305 I2C_MasterTransmit_TXE(hi2c);
3306 }
3307 /* BTF set -------------------------------------------------------------*/
3308 else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
3309 {
3310 I2C_MasterTransmit_BTF(hi2c);
3311 }
3312 }
3313 /* I2C in mode Receiver --------------------------------------------------*/
3314 else
3315 {
3316 /* RXNE set and BTF reset -----------------------------------------------*/
3317 if(((sr1itflags & I2C_FLAG_RXNE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET))
3318 {
3319 I2C_MasterReceive_RXNE(hi2c);
3320 }
3321 /* BTF set -------------------------------------------------------------*/
3322 else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
3323 {
3324 I2C_MasterReceive_BTF(hi2c);
3325 }
3326 }
3327 }
3328 /* Slave mode selected */
3329 else
3330 {
3331 /* ADDR set --------------------------------------------------------------*/
3332 if(((sr1itflags & I2C_FLAG_ADDR) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
3333 {
3334 I2C_Slave_ADDR(hi2c);
3335 }
3336 /* STOPF set --------------------------------------------------------------*/
3337 else if(((sr1itflags & I2C_FLAG_STOPF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
3338 {
3339 I2C_Slave_STOPF(hi2c);
3340 }
3341 /* I2C in mode Transmitter -----------------------------------------------*/
3342 else if((sr2itflags & I2C_FLAG_TRA) != RESET)
3343 {
3344 /* TXE set and BTF reset -----------------------------------------------*/
3345 if(((sr1itflags & I2C_FLAG_TXE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET))
3346 {
3347 I2C_SlaveTransmit_TXE(hi2c);
3348 }
3349 /* BTF set -------------------------------------------------------------*/
3350 else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
3351 {
3352 I2C_SlaveTransmit_BTF(hi2c);
3353 }
3354 }
3355 /* I2C in mode Receiver --------------------------------------------------*/
3356 else
3357 {
3358 /* RXNE set and BTF reset ----------------------------------------------*/
3359 if(((sr1itflags & I2C_FLAG_RXNE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET))
3360 {
3361 I2C_SlaveReceive_RXNE(hi2c);
3362 }
3363 /* BTF set -------------------------------------------------------------*/
3364 else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
3365 {
3366 I2C_SlaveReceive_BTF(hi2c);
3367 }
3368 }
3369 }
3370 }
3371
3372 /**
3373 * @brief This function handles I2C error interrupt request.
3374 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3375 * the configuration information for the specified I2C.
3376 * @retval None
3377 */
HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef * hi2c)3378 void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
3379 {
3380 uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1);
3381 uint32_t itsources = READ_REG(hi2c->Instance->CR2);
3382
3383 /* I2C Bus error interrupt occurred ----------------------------------------*/
3384 if(((sr1itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERR) != RESET))
3385 {
3386 hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
3387
3388 /* Clear BERR flag */
3389 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
3390 }
3391
3392 /* I2C Arbitration Loss error interrupt occurred ---------------------------*/
3393 if(((sr1itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERR) != RESET))
3394 {
3395 hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
3396
3397 /* Clear ARLO flag */
3398 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
3399 }
3400
3401 /* I2C Acknowledge failure error interrupt occurred ------------------------*/
3402 if(((sr1itflags & I2C_FLAG_AF) != RESET) && ((itsources & I2C_IT_ERR) != RESET))
3403 {
3404 if((hi2c->Mode == HAL_I2C_MODE_SLAVE) && \
3405 (hi2c->XferCount == 0U) && \
3406 ((hi2c->State == HAL_I2C_STATE_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) || \
3407 ((hi2c->State == HAL_I2C_STATE_LISTEN) && (hi2c->PreviousState == HAL_I2C_STATE_BUSY_TX))))
3408 {
3409 I2C_Slave_AF(hi2c);
3410 }
3411 else
3412 {
3413 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
3414
3415 /* Do not generate a STOP in case of Slave receive non acknowledge during transfer (mean not at the end of transfer) */
3416 if(hi2c->Mode == HAL_I2C_MODE_MASTER)
3417 {
3418 /* Generate Stop */
3419 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
3420 }
3421
3422 /* Clear AF flag */
3423 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
3424 }
3425 }
3426
3427 /* I2C Over-Run/Under-Run interrupt occurred -------------------------------*/
3428 if(((sr1itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERR) != RESET))
3429 {
3430 hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
3431 /* Clear OVR flag */
3432 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
3433 }
3434
3435 /* Call the Error Callback in case of Error detected -----------------------*/
3436 if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
3437 {
3438 I2C_ITError(hi2c);
3439 }
3440 }
3441
3442 /**
3443 * @brief Master Tx Transfer completed callback.
3444 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3445 * the configuration information for the specified I2C.
3446 * @retval None
3447 */
HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef * hi2c)3448 __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
3449 {
3450 /* Prevent unused argument(s) compilation warning */
3451 UNUSED(hi2c);
3452
3453 /* NOTE : This function should not be modified, when the callback is needed,
3454 the HAL_I2C_MasterTxCpltCallback can be implemented in the user file
3455 */
3456 }
3457
3458 /**
3459 * @brief Master Rx Transfer completed callback.
3460 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3461 * the configuration information for the specified I2C.
3462 * @retval None
3463 */
HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef * hi2c)3464 __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
3465 {
3466 /* Prevent unused argument(s) compilation warning */
3467 UNUSED(hi2c);
3468
3469 /* NOTE : This function should not be modified, when the callback is needed,
3470 the HAL_I2C_MasterRxCpltCallback can be implemented in the user file
3471 */
3472 }
3473
3474 /** @brief Slave Tx Transfer completed callback.
3475 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3476 * the configuration information for the specified I2C.
3477 * @retval None
3478 */
HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef * hi2c)3479 __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
3480 {
3481 /* Prevent unused argument(s) compilation warning */
3482 UNUSED(hi2c);
3483
3484 /* NOTE : This function should not be modified, when the callback is needed,
3485 the HAL_I2C_SlaveTxCpltCallback can be implemented in the user file
3486 */
3487 }
3488
3489 /**
3490 * @brief Slave Rx Transfer completed callback.
3491 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3492 * the configuration information for the specified I2C.
3493 * @retval None
3494 */
HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef * hi2c)3495 __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
3496 {
3497 /* Prevent unused argument(s) compilation warning */
3498 UNUSED(hi2c);
3499
3500 /* NOTE : This function should not be modified, when the callback is needed,
3501 the HAL_I2C_SlaveRxCpltCallback can be implemented in the user file
3502 */
3503 }
3504
3505 /**
3506 * @brief Slave Address Match callback.
3507 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3508 * the configuration information for the specified I2C.
3509 * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XferDirection_definition
3510 * @param AddrMatchCode Address Match Code
3511 * @retval None
3512 */
HAL_I2C_AddrCallback(I2C_HandleTypeDef * hi2c,uint8_t TransferDirection,uint16_t AddrMatchCode)3513 __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
3514 {
3515 /* Prevent unused argument(s) compilation warning */
3516 UNUSED(hi2c);
3517 UNUSED(TransferDirection);
3518 UNUSED(AddrMatchCode);
3519
3520 /* NOTE : This function should not be modified, when the callback is needed,
3521 the HAL_I2C_AddrCallback can be implemented in the user file
3522 */
3523 }
3524
3525 /**
3526 * @brief Listen Complete callback.
3527 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3528 * the configuration information for the specified I2C.
3529 * @retval None
3530 */
HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef * hi2c)3531 __weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
3532 {
3533 /* Prevent unused argument(s) compilation warning */
3534 UNUSED(hi2c);
3535
3536 /* NOTE : This function should not be modified, when the callback is needed,
3537 the HAL_I2C_ListenCpltCallback can be implemented in the user file
3538 */
3539 }
3540
3541 /**
3542 * @brief Memory Tx Transfer completed callback.
3543 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3544 * the configuration information for the specified I2C.
3545 * @retval None
3546 */
HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef * hi2c)3547 __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
3548 {
3549 /* Prevent unused argument(s) compilation warning */
3550 UNUSED(hi2c);
3551
3552 /* NOTE : This function should not be modified, when the callback is needed,
3553 the HAL_I2C_MemTxCpltCallback can be implemented in the user file
3554 */
3555 }
3556
3557 /**
3558 * @brief Memory Rx Transfer completed callback.
3559 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3560 * the configuration information for the specified I2C.
3561 * @retval None
3562 */
HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef * hi2c)3563 __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
3564 {
3565 /* Prevent unused argument(s) compilation warning */
3566 UNUSED(hi2c);
3567
3568 /* NOTE : This function should not be modified, when the callback is needed,
3569 the HAL_I2C_MemRxCpltCallback can be implemented in the user file
3570 */
3571 }
3572
3573 /**
3574 * @brief I2C error callback.
3575 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3576 * the configuration information for the specified I2C.
3577 * @retval None
3578 */
HAL_I2C_ErrorCallback(I2C_HandleTypeDef * hi2c)3579 __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
3580 {
3581 /* Prevent unused argument(s) compilation warning */
3582 UNUSED(hi2c);
3583
3584 /* NOTE : This function should not be modified, when the callback is needed,
3585 the HAL_I2C_ErrorCallback can be implemented in the user file
3586 */
3587 }
3588
3589 /**
3590 * @brief I2C abort callback.
3591 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3592 * the configuration information for the specified I2C.
3593 * @retval None
3594 */
HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef * hi2c)3595 __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
3596 {
3597 /* Prevent unused argument(s) compilation warning */
3598 UNUSED(hi2c);
3599
3600 /* NOTE : This function should not be modified, when the callback is needed,
3601 the HAL_I2C_AbortCpltCallback could be implemented in the user file
3602 */
3603 }
3604
3605 /**
3606 * @}
3607 */
3608
3609 /** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
3610 * @brief Peripheral State and Errors functions
3611 *
3612 @verbatim
3613 ===============================================================================
3614 ##### Peripheral State, Mode and Error functions #####
3615 ===============================================================================
3616 [..]
3617 This subsection permits to get in run-time the status of the peripheral
3618 and the data flow.
3619
3620 @endverbatim
3621 * @{
3622 */
3623
3624 /**
3625 * @brief Return the I2C handle state.
3626 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3627 * the configuration information for the specified I2C.
3628 * @retval HAL state
3629 */
HAL_I2C_GetState(I2C_HandleTypeDef * hi2c)3630 HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
3631 {
3632 /* Return I2C handle state */
3633 return hi2c->State;
3634 }
3635
3636 /**
3637 * @brief Return the I2C Master, Slave, Memory or no mode.
3638 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3639 * the configuration information for I2C module
3640 * @retval HAL mode
3641 */
HAL_I2C_GetMode(I2C_HandleTypeDef * hi2c)3642 HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
3643 {
3644 return hi2c->Mode;
3645 }
3646
3647 /**
3648 * @brief Return the I2C error code.
3649 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3650 * the configuration information for the specified I2C.
3651 * @retval I2C Error Code
3652 */
HAL_I2C_GetError(I2C_HandleTypeDef * hi2c)3653 uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
3654 {
3655 return hi2c->ErrorCode;
3656 }
3657
3658 /**
3659 * @}
3660 */
3661
3662 /**
3663 * @}
3664 */
3665
3666
3667 /** @addtogroup I2C_Private_Functions
3668 * @{
3669 */
3670
3671
3672 /**
3673 * @brief Handle TXE flag for Master
3674 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3675 * the configuration information for I2C module
3676 * @retval HAL status
3677 */
I2C_MasterTransmit_TXE(I2C_HandleTypeDef * hi2c)3678 static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c)
3679 {
3680 if((hi2c->XferSize == 0U) && (hi2c->State == HAL_I2C_STATE_BUSY_TX))
3681 {
3682 /* Call TxCpltCallback() directly if no stop mode is set */
3683 if((hi2c->XferOptions != I2C_FIRST_AND_LAST_FRAME) && (hi2c->XferOptions != I2C_LAST_FRAME) && (hi2c->XferOptions != I2C_NO_OPTION_FRAME))
3684 {
3685 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
3686
3687 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
3688 hi2c->Mode = HAL_I2C_MODE_NONE;
3689 hi2c->State = HAL_I2C_STATE_READY;
3690
3691 HAL_I2C_MasterTxCpltCallback(hi2c);
3692 }
3693 else /* Generate Stop condition then Call TxCpltCallback() */
3694 {
3695 /* Disable EVT, BUF and ERR interrupt */
3696 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
3697
3698 /* Generate Stop */
3699 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
3700
3701 hi2c->PreviousState = I2C_STATE_NONE;
3702 hi2c->State = HAL_I2C_STATE_READY;
3703
3704 if(hi2c->Mode == HAL_I2C_MODE_MEM)
3705 {
3706 hi2c->Mode = HAL_I2C_MODE_NONE;
3707 HAL_I2C_MemTxCpltCallback(hi2c);
3708 }
3709 else
3710 {
3711 hi2c->Mode = HAL_I2C_MODE_NONE;
3712 HAL_I2C_MasterTxCpltCallback(hi2c);
3713 }
3714 }
3715 }
3716 else if((hi2c->State == HAL_I2C_STATE_BUSY_TX) || \
3717 ((hi2c->Mode == HAL_I2C_MODE_MEM) && (hi2c->State == HAL_I2C_STATE_BUSY_RX)))
3718 {
3719 if(hi2c->XferCount == 0U)
3720 {
3721 /* Disable BUF interrupt */
3722 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
3723 }
3724 else
3725 {
3726 /* Write data to DR */
3727 hi2c->Instance->DR = (*hi2c->pBuffPtr++);
3728 hi2c->XferCount--;
3729 }
3730 }
3731 return HAL_OK;
3732 }
3733
3734 /**
3735 * @brief Handle BTF flag for Master transmitter
3736 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3737 * the configuration information for I2C module
3738 * @retval HAL status
3739 */
I2C_MasterTransmit_BTF(I2C_HandleTypeDef * hi2c)3740 static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c)
3741 {
3742 if(hi2c->State == HAL_I2C_STATE_BUSY_TX)
3743 {
3744 if(hi2c->XferCount != 0U)
3745 {
3746 /* Write data to DR */
3747 hi2c->Instance->DR = (*hi2c->pBuffPtr++);
3748 hi2c->XferCount--;
3749 }
3750 else
3751 {
3752 /* Call TxCpltCallback() directly if no stop mode is set */
3753 if((hi2c->XferOptions != I2C_FIRST_AND_LAST_FRAME) && (hi2c->XferOptions != I2C_LAST_FRAME) && (hi2c->XferOptions != I2C_NO_OPTION_FRAME))
3754 {
3755 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
3756
3757 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
3758 hi2c->Mode = HAL_I2C_MODE_NONE;
3759 hi2c->State = HAL_I2C_STATE_READY;
3760
3761 HAL_I2C_MasterTxCpltCallback(hi2c);
3762 }
3763 else /* Generate Stop condition then Call TxCpltCallback() */
3764 {
3765 /* Disable EVT, BUF and ERR interrupt */
3766 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
3767
3768 /* Generate Stop */
3769 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
3770
3771 hi2c->PreviousState = I2C_STATE_NONE;
3772 hi2c->State = HAL_I2C_STATE_READY;
3773
3774 if(hi2c->Mode == HAL_I2C_MODE_MEM)
3775 {
3776 hi2c->Mode = HAL_I2C_MODE_NONE;
3777
3778 HAL_I2C_MemTxCpltCallback(hi2c);
3779 }
3780 else
3781 {
3782 hi2c->Mode = HAL_I2C_MODE_NONE;
3783
3784 HAL_I2C_MasterTxCpltCallback(hi2c);
3785 }
3786 }
3787 }
3788 }
3789 return HAL_OK;
3790 }
3791
3792 /**
3793 * @brief Handle RXNE flag for Master
3794 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3795 * the configuration information for I2C module
3796 * @retval HAL status
3797 */
I2C_MasterReceive_RXNE(I2C_HandleTypeDef * hi2c)3798 static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c)
3799 {
3800 if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
3801 {
3802 if(hi2c->XferCount > 3U)
3803 {
3804 /* Read data from DR */
3805 (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
3806 hi2c->XferCount--;
3807 }
3808 else if((hi2c->XferCount == 2U) || (hi2c->XferCount == 3U))
3809 {
3810 if(hi2c->XferOptions != I2C_NEXT_FRAME)
3811 {
3812 /* Disable Acknowledge */
3813 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3814
3815 /* Enable Pos */
3816 SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
3817 }
3818 else
3819 {
3820 /* Enable Acknowledge */
3821 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3822 }
3823
3824 /* Disable BUF interrupt */
3825 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
3826 }
3827 else
3828 {
3829 if(hi2c->XferOptions != I2C_NEXT_FRAME)
3830 {
3831 /* Disable Acknowledge */
3832 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3833 }
3834 else
3835 {
3836 /* Enable Acknowledge */
3837 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3838 }
3839
3840 /* Disable EVT, BUF and ERR interrupt */
3841 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
3842
3843 /* Read data from DR */
3844 (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
3845 hi2c->XferCount--;
3846
3847 hi2c->State = HAL_I2C_STATE_READY;
3848
3849 if(hi2c->Mode == HAL_I2C_MODE_MEM)
3850 {
3851 hi2c->PreviousState = I2C_STATE_NONE;
3852 hi2c->Mode = HAL_I2C_MODE_NONE;
3853 HAL_I2C_MemRxCpltCallback(hi2c);
3854 }
3855 else
3856 {
3857 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
3858 hi2c->Mode = HAL_I2C_MODE_NONE;
3859 HAL_I2C_MasterRxCpltCallback(hi2c);
3860 }
3861 }
3862 }
3863 return HAL_OK;
3864 }
3865
3866 /**
3867 * @brief Handle BTF flag for Master receiver
3868 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3869 * the configuration information for I2C module
3870 * @retval HAL status
3871 */
I2C_MasterReceive_BTF(I2C_HandleTypeDef * hi2c)3872 static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c)
3873 {
3874 if(hi2c->XferCount == 3U)
3875 {
3876 if((hi2c->XferOptions == I2C_FIRST_AND_LAST_FRAME) || (hi2c->XferOptions == I2C_LAST_FRAME) || (hi2c->XferOptions == I2C_NO_OPTION_FRAME))
3877 {
3878 /* Disable Acknowledge */
3879 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3880 }
3881
3882 /* Read data from DR */
3883 (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
3884 hi2c->XferCount--;
3885 }
3886 else if(hi2c->XferCount == 2U)
3887 {
3888 /* Prepare next transfer or stop current transfer */
3889 if((hi2c->XferOptions != I2C_FIRST_AND_LAST_FRAME) && (hi2c->XferOptions != I2C_LAST_FRAME) && (hi2c->XferOptions != I2C_NO_OPTION_FRAME))
3890 {
3891 if(hi2c->XferOptions != I2C_NEXT_FRAME)
3892 {
3893 /* Disable Acknowledge */
3894 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3895 }
3896 else
3897 {
3898 /* Enable Acknowledge */
3899 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3900 }
3901 }
3902 else
3903 {
3904 /* Generate Stop */
3905 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
3906 }
3907
3908 /* Read data from DR */
3909 (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
3910 hi2c->XferCount--;
3911
3912 /* Read data from DR */
3913 (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
3914 hi2c->XferCount--;
3915
3916 /* Disable EVT and ERR interrupt */
3917 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
3918
3919 hi2c->State = HAL_I2C_STATE_READY;
3920
3921 if(hi2c->Mode == HAL_I2C_MODE_MEM)
3922 {
3923 hi2c->PreviousState = I2C_STATE_NONE;
3924 hi2c->Mode = HAL_I2C_MODE_NONE;
3925 HAL_I2C_MemRxCpltCallback(hi2c);
3926 }
3927 else
3928 {
3929 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
3930 hi2c->Mode = HAL_I2C_MODE_NONE;
3931 HAL_I2C_MasterRxCpltCallback(hi2c);
3932 }
3933 }
3934 else
3935 {
3936 /* Read data from DR */
3937 (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
3938 hi2c->XferCount--;
3939 }
3940 return HAL_OK;
3941 }
3942
3943 /**
3944 * @brief Handle SB flag for Master
3945 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3946 * the configuration information for I2C module
3947 * @retval HAL status
3948 */
I2C_Master_SB(I2C_HandleTypeDef * hi2c)3949 static HAL_StatusTypeDef I2C_Master_SB(I2C_HandleTypeDef *hi2c)
3950 {
3951 if(hi2c->Mode == HAL_I2C_MODE_MEM)
3952 {
3953 if(hi2c->EventCount == 0U)
3954 {
3955 /* Send slave address */
3956 hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress);
3957 }
3958 else
3959 {
3960 hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress);
3961 }
3962 }
3963 else
3964 {
3965 if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
3966 {
3967 /* Send slave 7 Bits address */
3968 if(hi2c->State == HAL_I2C_STATE_BUSY_TX)
3969 {
3970 hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress);
3971 }
3972 else
3973 {
3974 hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress);
3975 }
3976 }
3977 else
3978 {
3979 if(hi2c->EventCount == 0U)
3980 {
3981 /* Send header of slave address */
3982 hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(hi2c->Devaddress);
3983 }
3984 else if(hi2c->EventCount == 1U)
3985 {
3986 /* Send header of slave address */
3987 hi2c->Instance->DR = I2C_10BIT_HEADER_READ(hi2c->Devaddress);
3988 }
3989 }
3990 }
3991
3992 return HAL_OK;
3993 }
3994
3995 /**
3996 * @brief Handle ADD10 flag for Master
3997 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3998 * the configuration information for I2C module
3999 * @retval HAL status
4000 */
I2C_Master_ADD10(I2C_HandleTypeDef * hi2c)4001 static HAL_StatusTypeDef I2C_Master_ADD10(I2C_HandleTypeDef *hi2c)
4002 {
4003 /* Send slave address */
4004 hi2c->Instance->DR = I2C_10BIT_ADDRESS(hi2c->Devaddress);
4005
4006 return HAL_OK;
4007 }
4008
4009 /**
4010 * @brief Handle ADDR flag for Master
4011 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4012 * the configuration information for I2C module
4013 * @retval HAL status
4014 */
I2C_Master_ADDR(I2C_HandleTypeDef * hi2c)4015 static HAL_StatusTypeDef I2C_Master_ADDR(I2C_HandleTypeDef *hi2c)
4016 {
4017 if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
4018 {
4019 if((hi2c->EventCount == 0U) && (hi2c->Mode == HAL_I2C_MODE_MEM))
4020 {
4021 /* Clear ADDR flag */
4022 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
4023 }
4024 else if((hi2c->EventCount == 0U) && (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT))
4025 {
4026 /* Clear ADDR flag */
4027 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
4028
4029 /* Generate Restart */
4030 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
4031
4032 hi2c->EventCount++;
4033 }
4034 else
4035 {
4036 if(hi2c->XferCount == 0U)
4037 {
4038 /* Clear ADDR flag */
4039 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
4040
4041 /* Generate Stop */
4042 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
4043 }
4044 else if(hi2c->XferCount == 1U)
4045 {
4046 if(hi2c->XferOptions == I2C_NO_OPTION_FRAME)
4047 {
4048 /* Disable Acknowledge */
4049 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4050
4051 if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
4052 {
4053 /* Disable Acknowledge */
4054 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4055
4056 /* Clear ADDR flag */
4057 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
4058 }
4059 else
4060 {
4061 /* Clear ADDR flag */
4062 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
4063
4064 /* Generate Stop */
4065 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
4066 }
4067 }
4068 /* Prepare next transfer or stop current transfer */
4069 else if((hi2c->XferOptions != I2C_FIRST_AND_LAST_FRAME) && (hi2c->XferOptions != I2C_LAST_FRAME) \
4070 && (hi2c->PreviousState != I2C_STATE_MASTER_BUSY_RX))
4071 {
4072 if(hi2c->XferOptions != I2C_NEXT_FRAME)
4073 {
4074 /* Disable Acknowledge */
4075 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4076 }
4077 else
4078 {
4079 /* Enable Acknowledge */
4080 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4081 }
4082
4083 /* Clear ADDR flag */
4084 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
4085 }
4086 else
4087 {
4088 /* Disable Acknowledge */
4089 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4090
4091 /* Clear ADDR flag */
4092 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
4093
4094 /* Generate Stop */
4095 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
4096 }
4097 }
4098 else if(hi2c->XferCount == 2U)
4099 {
4100 if(hi2c->XferOptions != I2C_NEXT_FRAME)
4101 {
4102 /* Disable Acknowledge */
4103 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4104
4105 /* Enable Pos */
4106 SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
4107 }
4108 else
4109 {
4110 /* Enable Acknowledge */
4111 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4112 }
4113
4114 if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
4115 {
4116 /* Enable Last DMA bit */
4117 SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
4118 }
4119
4120 /* Clear ADDR flag */
4121 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
4122 }
4123 else
4124 {
4125 /* Enable Acknowledge */
4126 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4127
4128 if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
4129 {
4130 /* Enable Last DMA bit */
4131 SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
4132 }
4133
4134 /* Clear ADDR flag */
4135 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
4136 }
4137
4138 /* Reset Event counter */
4139 hi2c->EventCount = 0U;
4140 }
4141 }
4142 else
4143 {
4144 /* Clear ADDR flag */
4145 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
4146 }
4147
4148 return HAL_OK;
4149 }
4150
4151 /**
4152 * @brief Handle TXE flag for Slave
4153 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4154 * the configuration information for I2C module
4155 * @retval HAL status
4156 */
I2C_SlaveTransmit_TXE(I2C_HandleTypeDef * hi2c)4157 static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c)
4158 {
4159 if(hi2c->XferCount != 0U)
4160 {
4161 /* Write data to DR */
4162 hi2c->Instance->DR = (*hi2c->pBuffPtr++);
4163 hi2c->XferCount--;
4164
4165 if((hi2c->XferCount == 0U) && (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN))
4166 {
4167 /* Last Byte is received, disable Interrupt */
4168 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
4169
4170 /* Set state at HAL_I2C_STATE_LISTEN */
4171 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
4172 hi2c->State = HAL_I2C_STATE_LISTEN;
4173
4174 /* Call the Tx complete callback to inform upper layer of the end of receive process */
4175 HAL_I2C_SlaveTxCpltCallback(hi2c);
4176 }
4177 }
4178 return HAL_OK;
4179 }
4180
4181 /**
4182 * @brief Handle BTF flag for Slave transmitter
4183 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4184 * the configuration information for I2C module
4185 * @retval HAL status
4186 */
I2C_SlaveTransmit_BTF(I2C_HandleTypeDef * hi2c)4187 static HAL_StatusTypeDef I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c)
4188 {
4189 if(hi2c->XferCount != 0U)
4190 {
4191 /* Write data to DR */
4192 hi2c->Instance->DR = (*hi2c->pBuffPtr++);
4193 hi2c->XferCount--;
4194 }
4195 return HAL_OK;
4196 }
4197
4198 /**
4199 * @brief Handle RXNE flag for Slave
4200 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4201 * the configuration information for I2C module
4202 * @retval HAL status
4203 */
I2C_SlaveReceive_RXNE(I2C_HandleTypeDef * hi2c)4204 static HAL_StatusTypeDef I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c)
4205 {
4206 if(hi2c->XferCount != 0U)
4207 {
4208 /* Read data from DR */
4209 (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
4210 hi2c->XferCount--;
4211
4212 if((hi2c->XferCount == 0U) && (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN))
4213 {
4214 /* Last Byte is received, disable Interrupt */
4215 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
4216
4217 /* Set state at HAL_I2C_STATE_LISTEN */
4218 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
4219 hi2c->State = HAL_I2C_STATE_LISTEN;
4220
4221 /* Call the Rx complete callback to inform upper layer of the end of receive process */
4222 HAL_I2C_SlaveRxCpltCallback(hi2c);
4223 }
4224 }
4225 return HAL_OK;
4226 }
4227
4228 /**
4229 * @brief Handle BTF flag for Slave receiver
4230 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4231 * the configuration information for I2C module
4232 * @retval HAL status
4233 */
I2C_SlaveReceive_BTF(I2C_HandleTypeDef * hi2c)4234 static HAL_StatusTypeDef I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c)
4235 {
4236 if(hi2c->XferCount != 0U)
4237 {
4238 /* Read data from DR */
4239 (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
4240 hi2c->XferCount--;
4241 }
4242 return HAL_OK;
4243 }
4244
4245 /**
4246 * @brief Handle ADD flag for Slave
4247 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4248 * the configuration information for I2C module
4249 * @retval HAL status
4250 */
I2C_Slave_ADDR(I2C_HandleTypeDef * hi2c)4251 static HAL_StatusTypeDef I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c)
4252 {
4253 uint8_t TransferDirection = I2C_DIRECTION_RECEIVE;
4254 uint16_t SlaveAddrCode = 0U;
4255
4256 /* Transfer Direction requested by Master */
4257 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TRA) == RESET)
4258 {
4259 TransferDirection = I2C_DIRECTION_TRANSMIT;
4260 }
4261
4262 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_DUALF) == RESET)
4263 {
4264 SlaveAddrCode = hi2c->Init.OwnAddress1;
4265 }
4266 else
4267 {
4268 SlaveAddrCode = hi2c->Init.OwnAddress2;
4269 }
4270
4271 /* Call Slave Addr callback */
4272 HAL_I2C_AddrCallback(hi2c, TransferDirection, SlaveAddrCode);
4273
4274 return HAL_OK;
4275 }
4276
4277 /**
4278 * @brief Handle STOPF flag for Slave
4279 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4280 * the configuration information for I2C module
4281 * @retval HAL status
4282 */
I2C_Slave_STOPF(I2C_HandleTypeDef * hi2c)4283 static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c)
4284 {
4285 /* Disable EVT, BUF and ERR interrupt */
4286 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
4287
4288 /* Clear STOPF flag */
4289 __HAL_I2C_CLEAR_STOPFLAG(hi2c);
4290
4291 /* Disable Acknowledge */
4292 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4293
4294 /* If a DMA is ongoing, Update handle size context */
4295 if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
4296 {
4297 if((hi2c->State == HAL_I2C_STATE_BUSY_RX) || (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN))
4298 {
4299 hi2c->XferCount = __HAL_DMA_GET_COUNTER(hi2c->hdmarx);
4300 }
4301 else
4302 {
4303 hi2c->XferCount = __HAL_DMA_GET_COUNTER(hi2c->hdmatx);
4304 }
4305 }
4306
4307 /* All data are not transferred, so set error code accordingly */
4308 if(hi2c->XferCount != 0U)
4309 {
4310 /* Store Last receive data if any */
4311 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
4312 {
4313 /* Read data from DR */
4314 (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
4315 hi2c->XferCount--;
4316 }
4317
4318 /* Store Last receive data if any */
4319 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
4320 {
4321 /* Read data from DR */
4322 (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
4323 hi2c->XferCount--;
4324 }
4325
4326 /* Set ErrorCode corresponding to a Non-Acknowledge */
4327 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
4328 }
4329
4330 if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
4331 {
4332 /* Call the corresponding callback to inform upper layer of End of Transfer */
4333 I2C_ITError(hi2c);
4334 }
4335 else
4336 {
4337 if((hi2c->State == HAL_I2C_STATE_LISTEN ) || (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) || \
4338 (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN))
4339 {
4340 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
4341 hi2c->PreviousState = I2C_STATE_NONE;
4342 hi2c->State = HAL_I2C_STATE_READY;
4343 hi2c->Mode = HAL_I2C_MODE_NONE;
4344
4345 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
4346 HAL_I2C_ListenCpltCallback(hi2c);
4347 }
4348 else
4349 {
4350 if((hi2c->PreviousState == I2C_STATE_SLAVE_BUSY_RX) || (hi2c->State == HAL_I2C_STATE_BUSY_RX))
4351 {
4352 hi2c->PreviousState = I2C_STATE_NONE;
4353 hi2c->State = HAL_I2C_STATE_READY;
4354 hi2c->Mode = HAL_I2C_MODE_NONE;
4355
4356 HAL_I2C_SlaveRxCpltCallback(hi2c);
4357 }
4358 }
4359 }
4360 return HAL_OK;
4361 }
4362
4363 /**
4364 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4365 * the configuration information for I2C module
4366 * @retval HAL status
4367 */
I2C_Slave_AF(I2C_HandleTypeDef * hi2c)4368 static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c)
4369 {
4370 if(((hi2c->XferOptions == I2C_FIRST_AND_LAST_FRAME) || (hi2c->XferOptions == I2C_LAST_FRAME)) && \
4371 (hi2c->State == HAL_I2C_STATE_LISTEN))
4372 {
4373 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
4374
4375 /* Disable EVT, BUF and ERR interrupt */
4376 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
4377
4378 /* Clear AF flag */
4379 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
4380
4381 /* Disable Acknowledge */
4382 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4383
4384 hi2c->PreviousState = I2C_STATE_NONE;
4385 hi2c->State = HAL_I2C_STATE_READY;
4386 hi2c->Mode = HAL_I2C_MODE_NONE;
4387
4388 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
4389 HAL_I2C_ListenCpltCallback(hi2c);
4390 }
4391 else if(hi2c->State == HAL_I2C_STATE_BUSY_TX)
4392 {
4393 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
4394 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
4395 hi2c->State = HAL_I2C_STATE_READY;
4396 hi2c->Mode = HAL_I2C_MODE_NONE;
4397
4398 /* Disable EVT, BUF and ERR interrupt */
4399 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
4400
4401 /* Clear AF flag */
4402 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
4403
4404 /* Disable Acknowledge */
4405 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4406
4407 HAL_I2C_SlaveTxCpltCallback(hi2c);
4408 }
4409 else
4410 {
4411 /* Clear AF flag only */
4412 /* State Listen, but XferOptions == FIRST or NEXT */
4413 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
4414 }
4415
4416 return HAL_OK;
4417 }
4418
4419 /**
4420 * @brief I2C interrupts error process
4421 * @param hi2c I2C handle.
4422 * @retval None
4423 */
I2C_ITError(I2C_HandleTypeDef * hi2c)4424 static void I2C_ITError(I2C_HandleTypeDef *hi2c)
4425 {
4426 /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
4427 uint32_t CurrentState = hi2c->State;
4428
4429 if((CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN) || (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN))
4430 {
4431 /* keep HAL_I2C_STATE_LISTEN */
4432 hi2c->PreviousState = I2C_STATE_NONE;
4433 hi2c->State = HAL_I2C_STATE_LISTEN;
4434 }
4435 else
4436 {
4437 /* If state is an abort treatment on going, don't change state */
4438 /* This change will be do later */
4439 if((hi2c->State != HAL_I2C_STATE_ABORT) && ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) != I2C_CR2_DMAEN))
4440 {
4441 hi2c->State = HAL_I2C_STATE_READY;
4442 }
4443 hi2c->PreviousState = I2C_STATE_NONE;
4444 hi2c->Mode = HAL_I2C_MODE_NONE;
4445 }
4446
4447 /* Disable Pos bit in I2C CR1 when error occurred in Master/Mem Receive IT Process */
4448 hi2c->Instance->CR1 &= ~I2C_CR1_POS;
4449
4450 /* Abort DMA transfer */
4451 if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
4452 {
4453 hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
4454
4455 if(hi2c->hdmatx->State != HAL_DMA_STATE_READY)
4456 {
4457 /* Set the DMA Abort callback :
4458 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4459 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
4460
4461 if(HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
4462 {
4463 /* Disable I2C peripheral to prevent dummy data in buffer */
4464 __HAL_I2C_DISABLE(hi2c);
4465
4466 hi2c->State = HAL_I2C_STATE_READY;
4467
4468 /* Call Directly XferAbortCallback function in case of error */
4469 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
4470 }
4471 }
4472 else
4473 {
4474 /* Set the DMA Abort callback :
4475 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4476 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
4477
4478 if(HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
4479 {
4480 /* Store Last receive data if any */
4481 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
4482 {
4483 /* Read data from DR */
4484 (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
4485 }
4486
4487 /* Disable I2C peripheral to prevent dummy data in buffer */
4488 __HAL_I2C_DISABLE(hi2c);
4489
4490 hi2c->State = HAL_I2C_STATE_READY;
4491
4492 /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
4493 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
4494 }
4495 }
4496 }
4497 else if(hi2c->State == HAL_I2C_STATE_ABORT)
4498 {
4499 hi2c->State = HAL_I2C_STATE_READY;
4500 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4501
4502 /* Store Last receive data if any */
4503 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
4504 {
4505 /* Read data from DR */
4506 (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
4507 }
4508
4509 /* Disable I2C peripheral to prevent dummy data in buffer */
4510 __HAL_I2C_DISABLE(hi2c);
4511
4512 /* Call the corresponding callback to inform upper layer of End of Transfer */
4513 HAL_I2C_AbortCpltCallback(hi2c);
4514 }
4515 else
4516 {
4517 /* Store Last receive data if any */
4518 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
4519 {
4520 /* Read data from DR */
4521 (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
4522 }
4523
4524 /* Call user error callback */
4525 HAL_I2C_ErrorCallback(hi2c);
4526 }
4527 /* STOP Flag is not set after a NACK reception */
4528 /* So may inform upper layer that listen phase is stopped */
4529 /* during NACK error treatment */
4530 if((hi2c->State == HAL_I2C_STATE_LISTEN) && ((hi2c->ErrorCode & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF))
4531 {
4532 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
4533 hi2c->PreviousState = I2C_STATE_NONE;
4534 hi2c->State = HAL_I2C_STATE_READY;
4535 hi2c->Mode = HAL_I2C_MODE_NONE;
4536
4537 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
4538 HAL_I2C_ListenCpltCallback(hi2c);
4539 }
4540 }
4541
4542 /**
4543 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4544 * the configuration information for I2C module
4545 * @param DevAddress Target device address: The device 7 bits address value
4546 * in datasheet must be shift at right before call interface
4547 * @param Timeout Timeout duration
4548 * @param Tickstart Tick start value
4549 * @retval HAL status
4550 */
I2C_MasterRequestWrite(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint32_t Timeout,uint32_t Tickstart)4551 static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart)
4552 {
4553 /* Generate Start condition if first transfer */
4554 if((hi2c->XferOptions == I2C_FIRST_AND_LAST_FRAME) || (hi2c->XferOptions == I2C_FIRST_FRAME) || (hi2c->XferOptions == I2C_NO_OPTION_FRAME))
4555 {
4556 /* Generate Start */
4557 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
4558 }
4559 else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX)
4560 {
4561 /* Generate ReStart */
4562 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
4563 }
4564
4565 /* Wait until SB flag is set */
4566 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
4567 {
4568 return HAL_TIMEOUT;
4569 }
4570
4571 if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
4572 {
4573 /* Send slave address */
4574 hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
4575 }
4576 else
4577 {
4578 /* Send header of slave address */
4579 hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
4580
4581 /* Wait until ADD10 flag is set */
4582 if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK)
4583 {
4584 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
4585 {
4586 return HAL_ERROR;
4587 }
4588 else
4589 {
4590 return HAL_TIMEOUT;
4591 }
4592 }
4593
4594 /* Send slave address */
4595 hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);
4596 }
4597
4598 /* Wait until ADDR flag is set */
4599 if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
4600 {
4601 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
4602 {
4603 return HAL_ERROR;
4604 }
4605 else
4606 {
4607 return HAL_TIMEOUT;
4608 }
4609 }
4610
4611 return HAL_OK;
4612 }
4613
4614 /**
4615 * @brief Master sends target device address for read request.
4616 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4617 * the configuration information for I2C module
4618 * @param DevAddress Target device address: The device 7 bits address value
4619 * in datasheet must be shift at right before call interface
4620 * @param Timeout Timeout duration
4621 * @param Tickstart Tick start value
4622 * @retval HAL status
4623 */
I2C_MasterRequestRead(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint32_t Timeout,uint32_t Tickstart)4624 static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart)
4625 {
4626 /* Enable Acknowledge */
4627 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4628
4629 /* Generate Start condition if first transfer */
4630 if((hi2c->XferOptions == I2C_FIRST_AND_LAST_FRAME) || (hi2c->XferOptions == I2C_FIRST_FRAME) || (hi2c->XferOptions == I2C_NO_OPTION_FRAME))
4631 {
4632 /* Generate Start */
4633 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
4634 }
4635 else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX)
4636 {
4637 /* Generate ReStart */
4638 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
4639 }
4640
4641 /* Wait until SB flag is set */
4642 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
4643 {
4644 return HAL_TIMEOUT;
4645 }
4646
4647 if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
4648 {
4649 /* Send slave address */
4650 hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress);
4651 }
4652 else
4653 {
4654 /* Send header of slave address */
4655 hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
4656
4657 /* Wait until ADD10 flag is set */
4658 if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK)
4659 {
4660 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
4661 {
4662 return HAL_ERROR;
4663 }
4664 else
4665 {
4666 return HAL_TIMEOUT;
4667 }
4668 }
4669
4670 /* Send slave address */
4671 hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);
4672
4673 /* Wait until ADDR flag is set */
4674 if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
4675 {
4676 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
4677 {
4678 return HAL_ERROR;
4679 }
4680 else
4681 {
4682 return HAL_TIMEOUT;
4683 }
4684 }
4685
4686 /* Clear ADDR flag */
4687 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
4688
4689 /* Generate Restart */
4690 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
4691
4692 /* Wait until SB flag is set */
4693 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
4694 {
4695 return HAL_TIMEOUT;
4696 }
4697
4698 /* Send header of slave address */
4699 hi2c->Instance->DR = I2C_10BIT_HEADER_READ(DevAddress);
4700 }
4701
4702 /* Wait until ADDR flag is set */
4703 if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
4704 {
4705 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
4706 {
4707 return HAL_ERROR;
4708 }
4709 else
4710 {
4711 return HAL_TIMEOUT;
4712 }
4713 }
4714
4715 return HAL_OK;
4716 }
4717
4718 /**
4719 * @brief Master sends target device address followed by internal memory address for write request.
4720 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4721 * the configuration information for I2C module
4722 * @param DevAddress Target device address: The device 7 bits address value
4723 * in datasheet must be shift at right before call interface
4724 * @param MemAddress Internal memory address
4725 * @param MemAddSize Size of internal memory address
4726 * @param Timeout Timeout duration
4727 * @param Tickstart Tick start value
4728 * @retval HAL status
4729 */
I2C_RequestMemoryWrite(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint32_t Timeout,uint32_t Tickstart)4730 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
4731 {
4732 /* Generate Start */
4733 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
4734
4735 /* Wait until SB flag is set */
4736 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
4737 {
4738 return HAL_TIMEOUT;
4739 }
4740
4741 /* Send slave address */
4742 hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
4743
4744 /* Wait until ADDR flag is set */
4745 if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
4746 {
4747 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
4748 {
4749 return HAL_ERROR;
4750 }
4751 else
4752 {
4753 return HAL_TIMEOUT;
4754 }
4755 }
4756
4757 /* Clear ADDR flag */
4758 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
4759
4760 /* Wait until TXE flag is set */
4761 if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
4762 {
4763 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
4764 {
4765 /* Generate Stop */
4766 SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP);
4767 return HAL_ERROR;
4768 }
4769 else
4770 {
4771 return HAL_TIMEOUT;
4772 }
4773 }
4774
4775 /* If Memory address size is 8Bit */
4776 if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
4777 {
4778 /* Send Memory Address */
4779 hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
4780 }
4781 /* If Memory address size is 16Bit */
4782 else
4783 {
4784 /* Send MSB of Memory Address */
4785 hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress);
4786
4787 /* Wait until TXE flag is set */
4788 if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
4789 {
4790 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
4791 {
4792 /* Generate Stop */
4793 SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP);
4794 return HAL_ERROR;
4795 }
4796 else
4797 {
4798 return HAL_TIMEOUT;
4799 }
4800 }
4801
4802 /* Send LSB of Memory Address */
4803 hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
4804 }
4805
4806 return HAL_OK;
4807 }
4808
4809 /**
4810 * @brief Master sends target device address followed by internal memory address for read request.
4811 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4812 * the configuration information for I2C module
4813 * @param DevAddress Target device address: The device 7 bits address value
4814 * in datasheet must be shift at right before call interface
4815 * @param MemAddress Internal memory address
4816 * @param MemAddSize Size of internal memory address
4817 * @param Timeout Timeout duration
4818 * @param Tickstart Tick start value
4819 * @retval HAL status
4820 */
I2C_RequestMemoryRead(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint32_t Timeout,uint32_t Tickstart)4821 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
4822 {
4823 /* Enable Acknowledge */
4824 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4825
4826 /* Generate Start */
4827 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
4828
4829 /* Wait until SB flag is set */
4830 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
4831 {
4832 return HAL_TIMEOUT;
4833 }
4834
4835 /* Send slave address */
4836 hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
4837
4838 /* Wait until ADDR flag is set */
4839 if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
4840 {
4841 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
4842 {
4843 return HAL_ERROR;
4844 }
4845 else
4846 {
4847 return HAL_TIMEOUT;
4848 }
4849 }
4850
4851 /* Clear ADDR flag */
4852 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
4853
4854 /* Wait until TXE flag is set */
4855 if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
4856 {
4857 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
4858 {
4859 /* Generate Stop */
4860 SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP);
4861 return HAL_ERROR;
4862 }
4863 else
4864 {
4865 return HAL_TIMEOUT;
4866 }
4867 }
4868
4869 /* If Memory address size is 8Bit */
4870 if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
4871 {
4872 /* Send Memory Address */
4873 hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
4874 }
4875 /* If Memory address size is 16Bit */
4876 else
4877 {
4878 /* Send MSB of Memory Address */
4879 hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress);
4880
4881 /* Wait until TXE flag is set */
4882 if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
4883 {
4884 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
4885 {
4886 /* Generate Stop */
4887 SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP);
4888 return HAL_ERROR;
4889 }
4890 else
4891 {
4892 return HAL_TIMEOUT;
4893 }
4894 }
4895
4896 /* Send LSB of Memory Address */
4897 hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
4898 }
4899
4900 /* Wait until TXE flag is set */
4901 if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
4902 {
4903 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
4904 {
4905 /* Generate Stop */
4906 SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP);
4907 return HAL_ERROR;
4908 }
4909 else
4910 {
4911 return HAL_TIMEOUT;
4912 }
4913 }
4914
4915 /* Generate Restart */
4916 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
4917
4918 /* Wait until SB flag is set */
4919 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
4920 {
4921 return HAL_TIMEOUT;
4922 }
4923
4924 /* Send slave address */
4925 hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress);
4926
4927 /* Wait until ADDR flag is set */
4928 if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
4929 {
4930 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
4931 {
4932 return HAL_ERROR;
4933 }
4934 else
4935 {
4936 return HAL_TIMEOUT;
4937 }
4938 }
4939
4940 return HAL_OK;
4941 }
4942
4943 /**
4944 * @brief DMA I2C process complete callback.
4945 * @param hdma DMA handle
4946 * @retval None
4947 */
I2C_DMAXferCplt(DMA_HandleTypeDef * hdma)4948 static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma)
4949 {
4950 I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
4951
4952 if((hi2c->State == HAL_I2C_STATE_BUSY_TX) || ((hi2c->State == HAL_I2C_STATE_BUSY_RX) && (hi2c->Mode == HAL_I2C_MODE_SLAVE)))
4953 {
4954 /* Disable DMA Request */
4955 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
4956
4957 hi2c->XferCount = 0U;
4958
4959 /* Enable EVT and ERR interrupt */
4960 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
4961 }
4962 else
4963 {
4964 /* Disable Acknowledge */
4965 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4966
4967 /* Generate Stop */
4968 SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP);
4969
4970 /* Disable Last DMA */
4971 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
4972
4973 /* Disable DMA Request */
4974 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
4975
4976 hi2c->XferCount = 0U;
4977
4978 /* Check if Errors has been detected during transfer */
4979 if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
4980 {
4981 HAL_I2C_ErrorCallback(hi2c);
4982 }
4983 else
4984 {
4985 hi2c->State = HAL_I2C_STATE_READY;
4986
4987 if(hi2c->Mode == HAL_I2C_MODE_MEM)
4988 {
4989 hi2c->Mode = HAL_I2C_MODE_NONE;
4990
4991 HAL_I2C_MemRxCpltCallback(hi2c);
4992 }
4993 else
4994 {
4995 hi2c->Mode = HAL_I2C_MODE_NONE;
4996
4997 HAL_I2C_MasterRxCpltCallback(hi2c);
4998 }
4999 }
5000 }
5001 }
5002
5003 /**
5004 * @brief DMA I2C communication error callback.
5005 * @param hdma DMA handle
5006 * @retval None
5007 */
I2C_DMAError(DMA_HandleTypeDef * hdma)5008 static void I2C_DMAError(DMA_HandleTypeDef *hdma)
5009 {
5010 I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
5011
5012 /* Disable Acknowledge */
5013 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5014
5015 hi2c->XferCount = 0U;
5016
5017 hi2c->State = HAL_I2C_STATE_READY;
5018 hi2c->Mode = HAL_I2C_MODE_NONE;
5019
5020 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
5021
5022 HAL_I2C_ErrorCallback(hi2c);
5023 }
5024
5025 /**
5026 * @brief DMA I2C communication abort callback
5027 * (To be called at end of DMA Abort procedure).
5028 * @param hdma: DMA handle.
5029 * @retval None
5030 */
I2C_DMAAbort(DMA_HandleTypeDef * hdma)5031 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
5032 {
5033 I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
5034
5035 /* Disable Acknowledge */
5036 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5037
5038 hi2c->XferCount = 0U;
5039
5040 /* Reset XferAbortCallback */
5041 hi2c->hdmatx->XferAbortCallback = NULL;
5042 hi2c->hdmarx->XferAbortCallback = NULL;
5043
5044 /* Check if come from abort from user */
5045 if(hi2c->State == HAL_I2C_STATE_ABORT)
5046 {
5047 hi2c->State = HAL_I2C_STATE_READY;
5048 hi2c->Mode = HAL_I2C_MODE_NONE;
5049 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
5050
5051 /* Disable I2C peripheral to prevent dummy data in buffer */
5052 __HAL_I2C_DISABLE(hi2c);
5053
5054 /* Call the corresponding callback to inform upper layer of End of Transfer */
5055 HAL_I2C_AbortCpltCallback(hi2c);
5056 }
5057 else
5058 {
5059 hi2c->State = HAL_I2C_STATE_READY;
5060 hi2c->Mode = HAL_I2C_MODE_NONE;
5061
5062 /* Disable I2C peripheral to prevent dummy data in buffer */
5063 __HAL_I2C_DISABLE(hi2c);
5064
5065 /* Call the corresponding callback to inform upper layer of End of Transfer */
5066 HAL_I2C_ErrorCallback(hi2c);
5067 }
5068 }
5069
5070 /**
5071 * @brief This function handles I2C Communication Timeout.
5072 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5073 * the configuration information for I2C module
5074 * @param Flag specifies the I2C flag to check.
5075 * @param Status The new Flag status (SET or RESET).
5076 * @param Timeout Timeout duration
5077 * @param Tickstart Tick start value
5078 * @retval HAL status
5079 */
I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Flag,FlagStatus Status,uint32_t Timeout,uint32_t Tickstart)5080 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
5081 {
5082 while(__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
5083 {
5084 /* Check for the Timeout */
5085 if(Timeout != HAL_MAX_DELAY)
5086 {
5087 if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))
5088 {
5089 hi2c->PreviousState = I2C_STATE_NONE;
5090 hi2c->State= HAL_I2C_STATE_READY;
5091 hi2c->Mode = HAL_I2C_MODE_NONE;
5092
5093 /* Process Unlocked */
5094 __HAL_UNLOCK(hi2c);
5095 return HAL_TIMEOUT;
5096 }
5097 }
5098 }
5099 return HAL_OK;
5100 }
5101
5102 /**
5103 * @brief This function handles I2C Communication Timeout for Master addressing phase.
5104 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5105 * the configuration information for I2C module
5106 * @param Flag specifies the I2C flag to check.
5107 * @param Timeout Timeout duration
5108 * @param Tickstart Tick start value
5109 * @retval HAL status
5110 */
I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Flag,uint32_t Timeout,uint32_t Tickstart)5111 static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart)
5112 {
5113 while(__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)
5114 {
5115 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
5116 {
5117 /* Generate Stop */
5118 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
5119
5120 /* Clear AF Flag */
5121 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5122
5123 hi2c->ErrorCode = HAL_I2C_ERROR_AF;
5124 hi2c->PreviousState = I2C_STATE_NONE;
5125 hi2c->State= HAL_I2C_STATE_READY;
5126
5127 /* Process Unlocked */
5128 __HAL_UNLOCK(hi2c);
5129
5130 return HAL_ERROR;
5131 }
5132
5133 /* Check for the Timeout */
5134 if(Timeout != HAL_MAX_DELAY)
5135 {
5136 if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))
5137 {
5138 hi2c->PreviousState = I2C_STATE_NONE;
5139 hi2c->State= HAL_I2C_STATE_READY;
5140
5141 /* Process Unlocked */
5142 __HAL_UNLOCK(hi2c);
5143
5144 return HAL_TIMEOUT;
5145 }
5146 }
5147 }
5148 return HAL_OK;
5149 }
5150
5151 /**
5152 * @brief This function handles I2C Communication Timeout for specific usage of TXE flag.
5153 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5154 * the configuration information for the specified I2C.
5155 * @param Timeout Timeout duration
5156 * @param Tickstart Tick start value
5157 * @retval HAL status
5158 */
I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)5159 static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
5160 {
5161 while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
5162 {
5163 /* Check if a NACK is detected */
5164 if(I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
5165 {
5166 return HAL_ERROR;
5167 }
5168
5169 /* Check for the Timeout */
5170 if(Timeout != HAL_MAX_DELAY)
5171 {
5172 if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout))
5173 {
5174 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
5175 hi2c->PreviousState = I2C_STATE_NONE;
5176 hi2c->State= HAL_I2C_STATE_READY;
5177
5178 /* Process Unlocked */
5179 __HAL_UNLOCK(hi2c);
5180
5181 return HAL_TIMEOUT;
5182 }
5183 }
5184 }
5185 return HAL_OK;
5186 }
5187
5188 /**
5189 * @brief This function handles I2C Communication Timeout for specific usage of BTF flag.
5190 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5191 * the configuration information for the specified I2C.
5192 * @param Timeout Timeout duration
5193 * @param Tickstart Tick start value
5194 * @retval HAL status
5195 */
I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)5196 static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
5197 {
5198 while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET)
5199 {
5200 /* Check if a NACK is detected */
5201 if(I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
5202 {
5203 return HAL_ERROR;
5204 }
5205
5206 /* Check for the Timeout */
5207 if(Timeout != HAL_MAX_DELAY)
5208 {
5209 if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout))
5210 {
5211 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
5212 hi2c->PreviousState = I2C_STATE_NONE;
5213 hi2c->State= HAL_I2C_STATE_READY;
5214
5215 /* Process Unlocked */
5216 __HAL_UNLOCK(hi2c);
5217
5218 return HAL_TIMEOUT;
5219 }
5220 }
5221 }
5222 return HAL_OK;
5223 }
5224
5225 /**
5226 * @brief This function handles I2C Communication Timeout for specific usage of STOP flag.
5227 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5228 * the configuration information for the specified I2C.
5229 * @param Timeout Timeout duration
5230 * @param Tickstart Tick start value
5231 * @retval HAL status
5232 */
I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)5233 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
5234 {
5235 while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
5236 {
5237 /* Check if a NACK is detected */
5238 if(I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
5239 {
5240 return HAL_ERROR;
5241 }
5242
5243 /* Check for the Timeout */
5244 if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout))
5245 {
5246 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
5247 hi2c->PreviousState = I2C_STATE_NONE;
5248 hi2c->State= HAL_I2C_STATE_READY;
5249
5250 /* Process Unlocked */
5251 __HAL_UNLOCK(hi2c);
5252
5253 return HAL_TIMEOUT;
5254 }
5255 }
5256 return HAL_OK;
5257 }
5258
5259 /**
5260 * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag.
5261 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5262 * the configuration information for the specified I2C.
5263 * @param Timeout Timeout duration
5264 * @param Tickstart Tick start value
5265 * @retval HAL status
5266 */
I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)5267 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
5268 {
5269
5270 while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
5271 {
5272 /* Check if a STOPF is detected */
5273 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
5274 {
5275 /* Clear STOP Flag */
5276 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
5277
5278 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
5279 hi2c->PreviousState = I2C_STATE_NONE;
5280 hi2c->State= HAL_I2C_STATE_READY;
5281
5282 /* Process Unlocked */
5283 __HAL_UNLOCK(hi2c);
5284
5285 return HAL_ERROR;
5286 }
5287
5288 /* Check for the Timeout */
5289 if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout))
5290 {
5291 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
5292 hi2c->State= HAL_I2C_STATE_READY;
5293
5294 /* Process Unlocked */
5295 __HAL_UNLOCK(hi2c);
5296
5297 return HAL_TIMEOUT;
5298 }
5299 }
5300 return HAL_OK;
5301 }
5302
5303 /**
5304 * @brief This function handles Acknowledge failed detection during an I2C Communication.
5305 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5306 * the configuration information for the specified I2C.
5307 * @retval HAL status
5308 */
I2C_IsAcknowledgeFailed(I2C_HandleTypeDef * hi2c)5309 static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c)
5310 {
5311 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
5312 {
5313 /* Clear NACKF Flag */
5314 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5315
5316 hi2c->ErrorCode = HAL_I2C_ERROR_AF;
5317 hi2c->PreviousState = I2C_STATE_NONE;
5318 hi2c->State= HAL_I2C_STATE_READY;
5319
5320 /* Process Unlocked */
5321 __HAL_UNLOCK(hi2c);
5322
5323 return HAL_ERROR;
5324 }
5325 return HAL_OK;
5326 }
5327 /**
5328 * @}
5329 */
5330
5331 #endif /* HAL_I2C_MODULE_ENABLED */
5332
5333 /**
5334 * @}
5335 */
5336
5337 /**
5338 * @}
5339 */
5340
5341 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
5342
