1 /**
2 ******************************************************************************
3 * @file stm32l1xx_hal_cortex.c
4 * @author MCD Application Team
5 * @brief CORTEX HAL module driver.
6 *
7 * This file provides firmware functions to manage the following
8 * functionalities of the CORTEX:
9 * + Initialization and de-initialization functions
10 * + Peripheral Control functions
11 *
12 * @verbatim
13 ==============================================================================
14 ##### How to use this driver #####
15 ==============================================================================
16
17 [..]
18 *** How to configure Interrupts using Cortex HAL driver ***
19 ===========================================================
20 [..]
21 This section provide functions allowing to configure the NVIC interrupts (IRQ).
22 The Cortex-M3 exceptions are managed by CMSIS functions.
23
24 (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function
25
26 (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority()
27
28 (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ()
29
30
31 -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible.
32 The pending IRQ priority will be managed only by the sub priority.
33
34 -@- IRQ priority order (sorted by highest to lowest priority):
35 (+@) Lowest pre-emption priority
36 (+@) Lowest sub priority
37 (+@) Lowest hardware priority (IRQ number)
38
39 [..]
40 *** How to configure Systick using Cortex HAL driver ***
41 ========================================================
42 [..]
43 Setup SysTick Timer for 1 msec interrupts.
44
45 (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which
46 is a CMSIS function that:
47 (++) Configures the SysTick Reload register with value passed as function parameter.
48 (++) Configures the SysTick IRQ priority to the lowest value (0x0F).
49 (++) Resets the SysTick Counter register.
50 (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
51 (++) Enables the SysTick Interrupt.
52 (++) Starts the SysTick Counter.
53
54 (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
55 __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
56 HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
57 inside the stm32l1xx_hal_cortex.h file.
58
59 (+) You can change the SysTick IRQ priority by calling the
60 HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
61 call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
62
63 (+) To adjust the SysTick time base, use the following formula:
64
65 Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
66 (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
67 (++) Reload Value should not exceed 0xFFFFFF
68
69 @endverbatim
70 ******************************************************************************
71 * @attention
72 *
73 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
74 *
75 * Redistribution and use in source and binary forms, with or without modification,
76 * are permitted provided that the following conditions are met:
77 * 1. Redistributions of source code must retain the above copyright notice,
78 * this list of conditions and the following disclaimer.
79 * 2. Redistributions in binary form must reproduce the above copyright notice,
80 * this list of conditions and the following disclaimer in the documentation
81 * and/or other materials provided with the distribution.
82 * 3. Neither the name of STMicroelectronics nor the names of its contributors
83 * may be used to endorse or promote products derived from this software
84 * without specific prior written permission.
85 *
86 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
87 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
88 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
89 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
90 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
91 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
92 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
93 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
94 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
95 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
96 *
97 ******************************************************************************
98 */
99
100 /*
101 Additional Tables: CORTEX_NVIC_Priority_Table
102 The table below gives the allowed values of the pre-emption priority and subpriority according
103 to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function.
104 ==========================================================================================================================
105 NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
106 ==========================================================================================================================
107 NVIC_PRIORITYGROUP_0 | 0 | 0-15 | 0 bits for pre-emption priority
108 | | | 4 bits for subpriority
109 --------------------------------------------------------------------------------------------------------------------------
110 NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bits for pre-emption priority
111 | | | 3 bits for subpriority
112 --------------------------------------------------------------------------------------------------------------------------
113 NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
114 | | | 2 bits for subpriority
115 --------------------------------------------------------------------------------------------------------------------------
116 NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
117 | | | 1 bits for subpriority
118 --------------------------------------------------------------------------------------------------------------------------
119 NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bits for pre-emption priority
120 | | | 0 bits for subpriority
121 ==========================================================================================================================
122 */
123
124 /* Includes ------------------------------------------------------------------*/
125 #include "stm32l1xx_hal.h"
126
127 /** @addtogroup STM32L1xx_HAL_Driver
128 * @{
129 */
130
131 /** @defgroup CORTEX CORTEX
132 * @brief CORTEX HAL module driver
133 * @{
134 */
135
136 #ifdef HAL_CORTEX_MODULE_ENABLED
137
138 /* Private typedef -----------------------------------------------------------*/
139 /* Private define ------------------------------------------------------------*/
140 /* Private macro -------------------------------------------------------------*/
141 /* Private variables ---------------------------------------------------------*/
142 /* Private function prototypes -----------------------------------------------*/
143 /* Private functions ---------------------------------------------------------*/
144
145 /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
146 * @{
147 */
148
149
150 /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
151 * @brief Initialization and Configuration functions
152 *
153 @verbatim
154 ==============================================================================
155 ##### Initialization and de-initialization functions #####
156 ==============================================================================
157 [..]
158 This section provide the Cortex HAL driver functions allowing to configure Interrupts
159 Systick functionalities
160
161 @endverbatim
162 * @{
163 */
164
165
166 /**
167 * @brief Sets the priority grouping field (pre-emption priority and subpriority)
168 * using the required unlock sequence.
169 * @param PriorityGroup: The priority grouping bits length.
170 * This parameter can be one of the following values:
171 * @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority
172 * 4 bits for subpriority
173 * @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority
174 * 3 bits for subpriority
175 * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority
176 * 2 bits for subpriority
177 * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority
178 * 1 bits for subpriority
179 * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority
180 * 0 bits for subpriority
181 * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
182 * The pending IRQ priority will be managed only by the subpriority.
183 * @retval None
184 */
HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)185 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
186 {
187 /* Check the parameters */
188 assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
189
190 /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
191 NVIC_SetPriorityGrouping(PriorityGroup);
192 }
193
194 /**
195 * @brief Sets the priority of an interrupt.
196 * @param IRQn: External interrupt number
197 * This parameter can be an enumerator of IRQn_Type enumeration
198 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xx.h))
199 * @param PreemptPriority: The pre-emption priority for the IRQn channel.
200 * This parameter can be a value between 0 and 15
201 * A lower priority value indicates a higher priority
202 * @param SubPriority: the subpriority level for the IRQ channel.
203 * This parameter can be a value between 0 and 15
204 * A lower priority value indicates a higher priority.
205 * @retval None
206 */
HAL_NVIC_SetPriority(IRQn_Type IRQn,uint32_t PreemptPriority,uint32_t SubPriority)207 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
208 {
209 uint32_t prioritygroup = 0x00;
210
211 /* Check the parameters */
212 assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
213 assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
214
215 prioritygroup = NVIC_GetPriorityGrouping();
216
217 NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
218 }
219
220 /**
221 * @brief Enables a device specific interrupt in the NVIC interrupt controller.
222 * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
223 * function should be called before.
224 * @param IRQn External interrupt number
225 * This parameter can be an enumerator of IRQn_Type enumeration
226 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xx.h))
227 * @retval None
228 */
HAL_NVIC_EnableIRQ(IRQn_Type IRQn)229 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
230 {
231 /* Check the parameters */
232 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
233
234 /* Enable interrupt */
235 NVIC_EnableIRQ(IRQn);
236 }
237
238 /**
239 * @brief Disables a device specific interrupt in the NVIC interrupt controller.
240 * @param IRQn External interrupt number
241 * This parameter can be an enumerator of IRQn_Type enumeration
242 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h))
243 * @retval None
244 */
HAL_NVIC_DisableIRQ(IRQn_Type IRQn)245 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
246 {
247 /* Check the parameters */
248 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
249
250 /* Disable interrupt */
251 NVIC_DisableIRQ(IRQn);
252 }
253
254 /**
255 * @brief Initiates a system reset request to reset the MCU.
256 * @retval None
257 */
HAL_NVIC_SystemReset(void)258 void HAL_NVIC_SystemReset(void)
259 {
260 /* System Reset */
261 NVIC_SystemReset();
262 }
263
264 /**
265 * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer.
266 * Counter is in free running mode to generate periodic interrupts.
267 * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
268 * @retval status: - 0 Function succeeded.
269 * - 1 Function failed.
270 */
HAL_SYSTICK_Config(uint32_t TicksNumb)271 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
272 {
273 return SysTick_Config(TicksNumb);
274 }
275 /**
276 * @}
277 */
278
279 /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
280 * @brief Cortex control functions
281 *
282 @verbatim
283 ==============================================================================
284 ##### Peripheral Control functions #####
285 ==============================================================================
286 [..]
287 This subsection provides a set of functions allowing to control the CORTEX
288 (NVIC, SYSTICK, MPU) functionalities.
289
290
291 @endverbatim
292 * @{
293 */
294
295 #if (__MPU_PRESENT == 1)
296 /**
297 * @brief Enable the MPU.
298 * @param MPU_Control: Specifies the control mode of the MPU during hard fault,
299 * NMI, FAULTMASK and privileged accessto the default memory
300 * This parameter can be one of the following values:
301 * @arg MPU_HFNMI_PRIVDEF_NONE
302 * @arg MPU_HARDFAULT_NMI
303 * @arg MPU_PRIVILEGED_DEFAULT
304 * @arg MPU_HFNMI_PRIVDEF
305 * @retval None
306 */
HAL_MPU_Enable(uint32_t MPU_Control)307 void HAL_MPU_Enable(uint32_t MPU_Control)
308 {
309 /* Enable the MPU */
310 MPU->CTRL = (MPU_Control | MPU_CTRL_ENABLE_Msk);
311
312 /* Ensure MPU setting take effects */
313 __DSB();
314 __ISB();
315 }
316
317 /**
318 * @brief Disable the MPU.
319 * @retval None
320 */
HAL_MPU_Disable(void)321 void HAL_MPU_Disable(void)
322 {
323 /* Make sure outstanding transfers are done */
324 __DMB();
325
326 /* Disable the MPU and clear the control register*/
327 MPU->CTRL = 0;
328 }
329
330 /**
331 * @brief Initializes and configures the Region and the memory to be protected.
332 * @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains
333 * the initialization and configuration information.
334 * @retval None
335 */
HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef * MPU_Init)336 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
337 {
338 /* Check the parameters */
339 assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
340 assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
341
342 /* Set the Region number */
343 MPU->RNR = MPU_Init->Number;
344
345 if ((MPU_Init->Enable) != RESET)
346 {
347 /* Check the parameters */
348 assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
349 assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
350 assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
351 assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
352 assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
353 assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
354 assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
355 assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
356
357 MPU->RBAR = MPU_Init->BaseAddress;
358 MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
359 ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
360 ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
361 ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
362 ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
363 ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
364 ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
365 ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
366 ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
367 }
368 else
369 {
370 MPU->RBAR = 0x00;
371 MPU->RASR = 0x00;
372 }
373 }
374 #endif /* __MPU_PRESENT */
375
376 /**
377 * @brief Gets the priority grouping field from the NVIC Interrupt Controller.
378 * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
379 */
HAL_NVIC_GetPriorityGrouping(void)380 uint32_t HAL_NVIC_GetPriorityGrouping(void)
381 {
382 /* Get the PRIGROUP[10:8] field value */
383 return NVIC_GetPriorityGrouping();
384 }
385
386 /**
387 * @brief Gets the priority of an interrupt.
388 * @param IRQn: External interrupt number
389 * This parameter can be an enumerator of IRQn_Type enumeration
390 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h))
391 * @param PriorityGroup: the priority grouping bits length.
392 * This parameter can be one of the following values:
393 * @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority
394 * 4 bits for subpriority
395 * @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority
396 * 3 bits for subpriority
397 * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority
398 * 2 bits for subpriority
399 * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority
400 * 1 bits for subpriority
401 * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority
402 * 0 bits for subpriority
403 * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
404 * @param pSubPriority: Pointer on the Subpriority value (starting from 0).
405 * @retval None
406 */
HAL_NVIC_GetPriority(IRQn_Type IRQn,uint32_t PriorityGroup,uint32_t * pPreemptPriority,uint32_t * pSubPriority)407 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
408 {
409 /* Check the parameters */
410 assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
411 /* Get priority for Cortex-M system or device specific interrupts */
412 NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
413 }
414
415 /**
416 * @brief Sets Pending bit of an external interrupt.
417 * @param IRQn External interrupt number
418 * This parameter can be an enumerator of IRQn_Type enumeration
419 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h))
420 * @retval None
421 */
HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)422 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
423 {
424 /* Set interrupt pending */
425 NVIC_SetPendingIRQ(IRQn);
426 }
427
428 /**
429 * @brief Gets Pending Interrupt (reads the pending register in the NVIC
430 * and returns the pending bit for the specified interrupt).
431 * @param IRQn External interrupt number
432 * This parameter can be an enumerator of IRQn_Type enumeration
433 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h))
434 * @retval status: - 0 Interrupt status is not pending.
435 * - 1 Interrupt status is pending.
436 */
HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)437 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
438 {
439 /* Return 1 if pending else 0 */
440 return NVIC_GetPendingIRQ(IRQn);
441 }
442
443 /**
444 * @brief Clears the pending bit of an external interrupt.
445 * @param IRQn External interrupt number
446 * This parameter can be an enumerator of IRQn_Type enumeration
447 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h))
448 * @retval None
449 */
HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)450 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
451 {
452 /* Clear pending interrupt */
453 NVIC_ClearPendingIRQ(IRQn);
454 }
455
456 /**
457 * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
458 * @param IRQn External interrupt number
459 * This parameter can be an enumerator of IRQn_Type enumeration
460 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h))
461 * @retval status: - 0 Interrupt status is not pending.
462 * - 1 Interrupt status is pending.
463 */
HAL_NVIC_GetActive(IRQn_Type IRQn)464 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
465 {
466 /* Return 1 if active else 0 */
467 return NVIC_GetActive(IRQn);
468 }
469
470 /**
471 * @brief Configures the SysTick clock source.
472 * @param CLKSource: specifies the SysTick clock source.
473 * This parameter can be one of the following values:
474 * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
475 * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
476 * @retval None
477 */
HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)478 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
479 {
480 /* Check the parameters */
481 assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
482 if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
483 {
484 SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
485 }
486 else
487 {
488 SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
489 }
490 }
491
492 /**
493 * @brief This function handles SYSTICK interrupt request.
494 * @retval None
495 */
HAL_SYSTICK_IRQHandler(void)496 void HAL_SYSTICK_IRQHandler(void)
497 {
498 HAL_SYSTICK_Callback();
499 }
500
501 /**
502 * @brief SYSTICK callback.
503 * @retval None
504 */
HAL_SYSTICK_Callback(void)505 __weak void HAL_SYSTICK_Callback(void)
506 {
507 /* NOTE : This function Should not be modified, when the callback is needed,
508 the HAL_SYSTICK_Callback could be implemented in the user file
509 */
510 }
511
512 /**
513 * @}
514 */
515
516 /**
517 * @}
518 */
519
520 #endif /* HAL_CORTEX_MODULE_ENABLED */
521 /**
522 * @}
523 */
524
525 /**
526 * @}
527 */
528
529 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
530
