1 /**
2 ******************************************************************************
3 * @file stm32l1xx_hal_adc.c
4 * @author MCD Application Team
5 * @brief This file provides firmware functions to manage the following
6 * functionalities of the Analog to Digital Convertor (ADC)
7 * peripheral:
8 * + Initialization and de-initialization functions
9 * ++ Initialization and Configuration of ADC
10 * + Operation functions
11 * ++ Start, stop, get result of conversions of regular
12 * group, using 3 possible modes: polling, interruption or DMA.
13 * + Control functions
14 * ++ Channels configuration on regular group
15 * ++ Channels configuration on injected group
16 * ++ Analog Watchdog configuration
17 * + State functions
18 * ++ ADC state machine management
19 * ++ Interrupts and flags management
20 * Other functions (extended functions) are available in file
21 * "stm32l1xx_hal_adc_ex.c".
22 *
23 @verbatim
24 ==============================================================================
25 ##### ADC peripheral features #####
26 ==============================================================================
27 [..]
28 (+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution
29
30 (+) Interrupt generation at the end of regular conversion, end of injected
31 conversion, and in case of analog watchdog or overrun events.
32
33 (+) Single and continuous conversion modes.
34
35 (+) Scan mode for conversion of several channels sequentially.
36
37 (+) Data alignment with in-built data coherency.
38
39 (+) Programmable sampling time (channel wise)
40
41 (+) ADC conversion of regular group and injected group.
42
43 (+) External trigger (timer or EXTI) with configurable polarity
44 for both regular and injected groups.
45
46 (+) DMA request generation for transfer of conversions data of regular group.
47
48 (+) ADC offset on injected channels
49
50 (+) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at
51 slower speed.
52
53 (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to
54 Vdda or to an external voltage reference).
55
56
57 ##### How to use this driver #####
58 ==============================================================================
59 [..]
60
61 *** Configuration of top level parameters related to ADC ***
62 ============================================================
63 [..]
64
65 (#) Enable the ADC interface
66 (++) As prerequisite, ADC clock must be configured at RCC top level.
67 Caution: On STM32L1, ADC clock frequency max is 16MHz (refer
68 to device datasheet).
69 Therefore, ADC clock prescaler must be configured in
70 function of ADC clock source frequency to remain below
71 this maximum frequency.
72
73 (++) Two clock settings are mandatory:
74 (+++) ADC clock (core clock).
75 (+++) ADC clock (conversions clock).
76 Only one possible clock source: derived from HSI RC 16MHz oscillator
77 (HSI).
78 ADC is connected directly to HSI RC 16MHz oscillator.
79 Therefore, RCC PLL setting has no impact on ADC.
80 PLL can be disabled (".PLL.PLLState = RCC_PLL_NONE") or
81 enabled with HSI16 as clock source
82 (".PLL.PLLSource = RCC_PLLSOURCE_HSI") to be used as device
83 main clock source SYSCLK.
84 The only mandatory setting is ".HSIState = RCC_HSI_ON"
85
86 (+++) Example:
87 Into HAL_ADC_MspInit() (recommended code location) or with
88 other device clock parameters configuration:
89 (+++) __HAL_RCC_ADC1_CLK_ENABLE();
90
91 (+++) HAL_RCC_GetOscConfig(&RCC_OscInitStructure);
92 (+++) RCC_OscInitStructure.OscillatorType = (... | RCC_OSCILLATORTYPE_HSI);
93 (+++) RCC_OscInitStructure.HSIState = RCC_HSI_ON;
94 (+++) RCC_OscInitStructure.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
95 (+++) RCC_OscInitStructure.PLL.PLLState = RCC_PLL_NONE;
96 (+++) RCC_OscInitStructure.PLL.PLLSource = ...
97 (+++) RCC_OscInitStructure.PLL...
98 (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);
99
100 (++) ADC clock prescaler is configured at ADC level with
101 parameter "ClockPrescaler" using function HAL_ADC_Init().
102
103 (#) ADC pins configuration
104 (++) Enable the clock for the ADC GPIOs
105 using macro __HAL_RCC_GPIOx_CLK_ENABLE()
106 (++) Configure these ADC pins in analog mode
107 using function HAL_GPIO_Init()
108
109 (#) Optionally, in case of usage of ADC with interruptions:
110 (++) Configure the NVIC for ADC
111 using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
112 (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
113 into the function of corresponding ADC interruption vector
114 ADCx_IRQHandler().
115
116 (#) Optionally, in case of usage of DMA:
117 (++) Configure the DMA (DMA channel, mode normal or circular, ...)
118 using function HAL_DMA_Init().
119 (++) Configure the NVIC for DMA
120 using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
121 (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
122 into the function of corresponding DMA interruption vector
123 DMAx_Channelx_IRQHandler().
124
125 *** Configuration of ADC, groups regular/injected, channels parameters ***
126 ==========================================================================
127 [..]
128
129 (#) Configure the ADC parameters (resolution, data alignment, ...)
130 and regular group parameters (conversion trigger, sequencer, ...)
131 using function HAL_ADC_Init().
132
133 (#) Configure the channels for regular group parameters (channel number,
134 channel rank into sequencer, ..., into regular group)
135 using function HAL_ADC_ConfigChannel().
136
137 (#) Optionally, configure the injected group parameters (conversion trigger,
138 sequencer, ..., of injected group)
139 and the channels for injected group parameters (channel number,
140 channel rank into sequencer, ..., into injected group)
141 using function HAL_ADCEx_InjectedConfigChannel().
142
143 (#) Optionally, configure the analog watchdog parameters (channels
144 monitored, thresholds, ...)
145 using function HAL_ADC_AnalogWDGConfig().
146
147 (#) Optionally, for devices with several ADC instances: configure the
148 multimode parameters
149 using function HAL_ADCEx_MultiModeConfigChannel().
150
151 *** Execution of ADC conversions ***
152 ====================================
153 [..]
154
155 (#) ADC driver can be used among three modes: polling, interruption,
156 transfer by DMA.
157
158 (++) ADC conversion by polling:
159 (+++) Activate the ADC peripheral and start conversions
160 using function HAL_ADC_Start()
161 (+++) Wait for ADC conversion completion
162 using function HAL_ADC_PollForConversion()
163 (or for injected group: HAL_ADCEx_InjectedPollForConversion() )
164 (+++) Retrieve conversion results
165 using function HAL_ADC_GetValue()
166 (or for injected group: HAL_ADCEx_InjectedGetValue() )
167 (+++) Stop conversion and disable the ADC peripheral
168 using function HAL_ADC_Stop()
169
170 (++) ADC conversion by interruption:
171 (+++) Activate the ADC peripheral and start conversions
172 using function HAL_ADC_Start_IT()
173 (+++) Wait for ADC conversion completion by call of function
174 HAL_ADC_ConvCpltCallback()
175 (this function must be implemented in user program)
176 (or for injected group: HAL_ADCEx_InjectedConvCpltCallback() )
177 (+++) Retrieve conversion results
178 using function HAL_ADC_GetValue()
179 (or for injected group: HAL_ADCEx_InjectedGetValue() )
180 (+++) Stop conversion and disable the ADC peripheral
181 using function HAL_ADC_Stop_IT()
182
183 (++) ADC conversion with transfer by DMA:
184 (+++) Activate the ADC peripheral and start conversions
185 using function HAL_ADC_Start_DMA()
186 (+++) Wait for ADC conversion completion by call of function
187 HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
188 (these functions must be implemented in user program)
189 (+++) Conversion results are automatically transferred by DMA into
190 destination variable address.
191 (+++) Stop conversion and disable the ADC peripheral
192 using function HAL_ADC_Stop_DMA()
193
194 (++) For devices with several ADCs: ADC multimode conversion
195 with transfer by DMA:
196 (+++) Activate the ADC peripheral (slave) and start conversions
197 using function HAL_ADC_Start()
198 (+++) Activate the ADC peripheral (master) and start conversions
199 using function HAL_ADCEx_MultiModeStart_DMA()
200 (+++) Wait for ADC conversion completion by call of function
201 HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
202 (these functions must be implemented in user program)
203 (+++) Conversion results are automatically transferred by DMA into
204 destination variable address.
205 (+++) Stop conversion and disable the ADC peripheral (master)
206 using function HAL_ADCEx_MultiModeStop_DMA()
207 (+++) Stop conversion and disable the ADC peripheral (slave)
208 using function HAL_ADC_Stop_IT()
209
210 [..]
211
212 (@) Callback functions must be implemented in user program:
213 (+@) HAL_ADC_ErrorCallback()
214 (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
215 (+@) HAL_ADC_ConvCpltCallback()
216 (+@) HAL_ADC_ConvHalfCpltCallback
217 (+@) HAL_ADCEx_InjectedConvCpltCallback()
218
219 *** Deinitialization of ADC ***
220 ============================================================
221 [..]
222
223 (#) Disable the ADC interface
224 (++) ADC clock can be hard reset and disabled at RCC top level.
225 (++) Hard reset of ADC peripherals
226 using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET().
227 (++) ADC clock disable
228 using the equivalent macro/functions as configuration step.
229 (+++) Example:
230 Into HAL_ADC_MspDeInit() (recommended code location) or with
231 other device clock parameters configuration:
232 (+++) HAL_RCC_GetOscConfig(&RCC_OscInitStructure);
233 (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI;
234 (+++) RCC_OscInitStructure.HSIState = RCC_HSI_OFF; (if not used for system clock)
235 (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);
236
237 (#) ADC pins configuration
238 (++) Disable the clock for the ADC GPIOs
239 using macro __HAL_RCC_GPIOx_CLK_DISABLE()
240
241 (#) Optionally, in case of usage of ADC with interruptions:
242 (++) Disable the NVIC for ADC
243 using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
244
245 (#) Optionally, in case of usage of DMA:
246 (++) Deinitialize the DMA
247 using function HAL_DMA_Init().
248 (++) Disable the NVIC for DMA
249 using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
250
251 [..]
252
253 @endverbatim
254 ******************************************************************************
255 * @attention
256 *
257 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
258 *
259 * Redistribution and use in source and binary forms, with or without modification,
260 * are permitted provided that the following conditions are met:
261 * 1. Redistributions of source code must retain the above copyright notice,
262 * this list of conditions and the following disclaimer.
263 * 2. Redistributions in binary form must reproduce the above copyright notice,
264 * this list of conditions and the following disclaimer in the documentation
265 * and/or other materials provided with the distribution.
266 * 3. Neither the name of STMicroelectronics nor the names of its contributors
267 * may be used to endorse or promote products derived from this software
268 * without specific prior written permission.
269 *
270 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
271 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
272 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
273 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
274 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
275 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
276 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
277 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
278 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
279 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
280 *
281 ******************************************************************************
282 */
283
284 /* Includes ------------------------------------------------------------------*/
285 #include "stm32l1xx_hal.h"
286
287 /** @addtogroup STM32L1xx_HAL_Driver
288 * @{
289 */
290
291 /** @defgroup ADC ADC
292 * @brief ADC HAL module driver
293 * @{
294 */
295
296 #ifdef HAL_ADC_MODULE_ENABLED
297
298 /* Private typedef -----------------------------------------------------------*/
299 /* Private define ------------------------------------------------------------*/
300 /** @defgroup ADC_Private_Constants ADC Private Constants
301 * @{
302 */
303
304 /* Timeout values for ADC enable and disable settling time. */
305 /* Values defined to be higher than worst cases: low clocks freq, */
306 /* maximum prescaler. */
307 /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */
308 /* prescaler 4, sampling time 7.5 ADC clock cycles, resolution 12 bits. */
309 /* Unit: ms */
310 #define ADC_ENABLE_TIMEOUT (2U)
311 #define ADC_DISABLE_TIMEOUT (2U)
312
313 /* Delay for ADC stabilization time. */
314 /* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */
315 /* Unit: us */
316 #define ADC_STAB_DELAY_US (3U)
317
318 /* Delay for temperature sensor stabilization time. */
319 /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */
320 /* Unit: us */
321 #define ADC_TEMPSENSOR_DELAY_US (10U)
322
323 /**
324 * @}
325 */
326
327 /* Private macro -------------------------------------------------------------*/
328 /* Private variables ---------------------------------------------------------*/
329 /* Private function prototypes -----------------------------------------------*/
330 /** @defgroup ADC_Private_Functions ADC Private Functions
331 * @{
332 */
333 static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
334 static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
335 static void ADC_DMAError(DMA_HandleTypeDef *hdma);
336 /**
337 * @}
338 */
339
340 /* Exported functions --------------------------------------------------------*/
341
342 /** @defgroup ADC_Exported_Functions ADC Exported Functions
343 * @{
344 */
345
346 /** @defgroup ADC_Exported_Functions_Group1 ADC Initialization/de-initialization functions
347 * @brief ADC Initialization and Configuration functions
348 *
349 @verbatim
350 ===============================================================================
351 ##### Initialization and de-initialization functions #####
352 ===============================================================================
353 [..] This section provides functions allowing to:
354 (+) Initialize and configure the ADC.
355 (+) De-initialize the ADC.
356 @endverbatim
357 * @{
358 */
359
360 /**
361 * @brief Initializes the ADC peripheral and regular group according to
362 * parameters specified in structure "ADC_InitTypeDef".
363 * @note As prerequisite, ADC clock must be configured at RCC top level
364 * (clock source APB2).
365 * See commented example code below that can be copied and uncommented
366 * into HAL_ADC_MspInit().
367 * @note Possibility to update parameters on the fly:
368 * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
369 * coming from ADC state reset. Following calls to this function can
370 * be used to reconfigure some parameters of ADC_InitTypeDef
371 * structure on the fly, without modifying MSP configuration. If ADC
372 * MSP has to be modified again, HAL_ADC_DeInit() must be called
373 * before HAL_ADC_Init().
374 * The setting of these parameters is conditioned to ADC state.
375 * For parameters constraints, see comments of structure
376 * "ADC_InitTypeDef".
377 * @note This function configures the ADC within 2 scopes: scope of entire
378 * ADC and scope of regular group. For parameters details, see comments
379 * of structure "ADC_InitTypeDef".
380 * @param hadc: ADC handle
381 * @retval HAL status
382 */
HAL_ADC_Init(ADC_HandleTypeDef * hadc)383 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
384 {
385 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
386 uint32_t tmp_cr1 = 0;
387 uint32_t tmp_cr2 = 0;
388
389 /* Check ADC handle */
390 if(hadc == NULL)
391 {
392 return HAL_ERROR;
393 }
394
395 /* Check the parameters */
396 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
397 assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
398 assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
399 assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
400 assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
401 assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
402 assert_param(IS_ADC_AUTOWAIT(hadc->Init.LowPowerAutoWait));
403 assert_param(IS_ADC_AUTOPOWEROFF(hadc->Init.LowPowerAutoPowerOff));
404 assert_param(IS_ADC_CHANNELSBANK(hadc->Init.ChannelsBank));
405 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
406 assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
407 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
408
409 if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
410 {
411 assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
412 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
413 if(hadc->Init.DiscontinuousConvMode != DISABLE)
414 {
415 assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion));
416 }
417 }
418
419 if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
420 {
421 assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
422 }
423
424
425 /* As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured */
426 /* at RCC top level. */
427 /* Refer to header of this file for more details on clock enabling */
428 /* procedure. */
429
430 /* Actions performed only if ADC is coming from state reset: */
431 /* - Initialization of ADC MSP */
432 if (hadc->State == HAL_ADC_STATE_RESET)
433 {
434 /* Initialize ADC error code */
435 ADC_CLEAR_ERRORCODE(hadc);
436
437 /* Allocate lock resource and initialize it */
438 hadc->Lock = HAL_UNLOCKED;
439
440 /* Enable SYSCFG clock to control the routing Interface (RI) */
441 __HAL_RCC_SYSCFG_CLK_ENABLE();
442
443 /* Init the low level hardware */
444 HAL_ADC_MspInit(hadc);
445 }
446
447 /* Configuration of ADC parameters if previous preliminary actions are */
448 /* correctly completed. */
449 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
450 {
451 /* Set ADC state */
452 ADC_STATE_CLR_SET(hadc->State,
453 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
454 HAL_ADC_STATE_BUSY_INTERNAL);
455
456 /* Set ADC parameters */
457
458 /* Configuration of common ADC clock: clock source HSI with selectable */
459 /* prescaler */
460 MODIFY_REG(ADC->CCR ,
461 ADC_CCR_ADCPRE ,
462 hadc->Init.ClockPrescaler );
463
464 /* Configuration of ADC: */
465 /* - external trigger polarity */
466 /* - End of conversion selection */
467 /* - DMA continuous request */
468 /* - Channels bank (Banks availability depends on devices categories) */
469 /* - continuous conversion mode */
470 tmp_cr2 |= (hadc->Init.DataAlign |
471 hadc->Init.EOCSelection |
472 ADC_CR2_DMACONTREQ(hadc->Init.DMAContinuousRequests) |
473 hadc->Init.ChannelsBank |
474 ADC_CR2_CONTINUOUS(hadc->Init.ContinuousConvMode) );
475
476 /* Enable external trigger if trigger selection is different of software */
477 /* start. */
478 /* Note: This configuration keeps the hardware feature of parameter */
479 /* ExternalTrigConvEdge "trigger edge none" equivalent to */
480 /* software start. */
481 if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
482 {
483 tmp_cr2 |= ( hadc->Init.ExternalTrigConv |
484 hadc->Init.ExternalTrigConvEdge );
485 }
486
487 /* Parameters update conditioned to ADC state: */
488 /* Parameters that can be updated only when ADC is disabled: */
489 /* - delay selection (LowPowerAutoWait mode) */
490 /* - resolution */
491 /* - auto power off (LowPowerAutoPowerOff mode) */
492 /* - scan mode */
493 /* - discontinuous mode disable/enable */
494 /* - discontinuous mode number of conversions */
495 if ((ADC_IS_ENABLE(hadc) == RESET))
496 {
497 tmp_cr2 |= hadc->Init.LowPowerAutoWait;
498
499 tmp_cr1 |= (hadc->Init.Resolution |
500 hadc->Init.LowPowerAutoPowerOff |
501 ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) );
502
503 /* Enable discontinuous mode only if continuous mode is disabled */
504 /* Note: If parameter "Init.ScanConvMode" is set to disable, parameter */
505 /* discontinuous is set anyway, but has no effect on ADC HW. */
506 if (hadc->Init.DiscontinuousConvMode == ENABLE)
507 {
508 if (hadc->Init.ContinuousConvMode == DISABLE)
509 {
510 /* Enable the selected ADC regular discontinuous mode */
511 /* Set the number of channels to be converted in discontinuous mode */
512 SET_BIT(tmp_cr1, ADC_CR1_DISCEN |
513 ADC_CR1_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion) );
514 }
515 else
516 {
517 /* ADC regular group settings continuous and sequencer discontinuous*/
518 /* cannot be enabled simultaneously. */
519
520 /* Update ADC state machine to error */
521 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
522
523 /* Set ADC error code to ADC IP internal error */
524 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
525 }
526 }
527
528 /* Update ADC configuration register CR1 with previous settings */
529 MODIFY_REG(hadc->Instance->CR1,
530 ADC_CR1_RES |
531 ADC_CR1_PDI |
532 ADC_CR1_PDD |
533 ADC_CR1_DISCNUM |
534 ADC_CR1_DISCEN |
535 ADC_CR1_SCAN ,
536 tmp_cr1 );
537 }
538
539 /* Update ADC configuration register CR2 with previous settings */
540 MODIFY_REG(hadc->Instance->CR2 ,
541 ADC_CR2_MASK_ADCINIT() ,
542 tmp_cr2 );
543
544 /* Configuration of regular group sequencer: */
545 /* - if scan mode is disabled, regular channels sequence length is set to */
546 /* 0x00: 1 channel converted (channel on regular rank 1) */
547 /* Parameter "NbrOfConversion" is discarded. */
548 /* Note: Scan mode is present by hardware on this device and, if */
549 /* disabled, discards automatically nb of conversions. Anyway, nb of */
550 /* conversions is forced to 0x00 for alignment over all STM32 devices. */
551 /* - if scan mode is enabled, regular channels sequence length is set to */
552 /* parameter "NbrOfConversion" */
553 if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE)
554 {
555 MODIFY_REG(hadc->Instance->SQR1 ,
556 ADC_SQR1_L ,
557 ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion) );
558 }
559 else
560 {
561 MODIFY_REG(hadc->Instance->SQR1,
562 ADC_SQR1_L ,
563 0x00000000 );
564 }
565
566 /* Check back that ADC registers have effectively been configured to */
567 /* ensure of no potential problem of ADC core IP clocking. */
568 /* Check through register CR2 (excluding execution control bits ADON, */
569 /* JSWSTART, SWSTART and injected trigger bits JEXTEN and JEXTSEL). */
570 if ((READ_REG(hadc->Instance->CR2) & ~(ADC_CR2_ADON |
571 ADC_CR2_SWSTART | ADC_CR2_JSWSTART |
572 ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL ))
573 == tmp_cr2)
574 {
575 /* Set ADC error code to none */
576 ADC_CLEAR_ERRORCODE(hadc);
577
578 /* Set the ADC state */
579 ADC_STATE_CLR_SET(hadc->State,
580 HAL_ADC_STATE_BUSY_INTERNAL,
581 HAL_ADC_STATE_READY);
582 }
583 else
584 {
585 /* Update ADC state machine to error */
586 ADC_STATE_CLR_SET(hadc->State,
587 HAL_ADC_STATE_BUSY_INTERNAL,
588 HAL_ADC_STATE_ERROR_INTERNAL);
589
590 /* Set ADC error code to ADC IP internal error */
591 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
592
593 tmp_hal_status = HAL_ERROR;
594 }
595
596 }
597 else
598 {
599 tmp_hal_status = HAL_ERROR;
600 }
601
602 /* Return function status */
603 return tmp_hal_status;
604 }
605
606 /**
607 * @brief Deinitialize the ADC peripheral registers to its default reset values.
608 * @note To not impact other ADCs, reset of common ADC registers have been
609 * left commented below.
610 * If needed, the example code can be copied and uncommented into
611 * function HAL_ADC_MspDeInit().
612 * @param hadc: ADC handle
613 * @retval HAL status
614 */
HAL_ADC_DeInit(ADC_HandleTypeDef * hadc)615 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
616 {
617 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
618
619 /* Check ADC handle */
620 if(hadc == NULL)
621 {
622 return HAL_ERROR;
623 }
624
625 /* Check the parameters */
626 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
627
628 /* Set ADC state */
629 SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
630
631 /* Stop potential conversion on going, on regular and injected groups */
632 /* Disable ADC peripheral */
633 tmp_hal_status = ADC_ConversionStop_Disable(hadc);
634
635
636 /* Configuration of ADC parameters if previous preliminary actions are */
637 /* correctly completed. */
638 if (tmp_hal_status == HAL_OK)
639 {
640 /* ========== Reset ADC registers ========== */
641 /* Reset register SR */
642 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD | ADC_FLAG_JEOC | ADC_FLAG_EOC |
643 ADC_FLAG_JSTRT | ADC_FLAG_STRT));
644
645 /* Reset register CR1 */
646 CLEAR_BIT(hadc->Instance->CR1, (ADC_CR1_OVRIE | ADC_CR1_RES | ADC_CR1_AWDEN |
647 ADC_CR1_JAWDEN | ADC_CR1_PDI | ADC_CR1_PDD |
648 ADC_CR1_DISCNUM | ADC_CR1_JDISCEN | ADC_CR1_DISCEN |
649 ADC_CR1_JAUTO | ADC_CR1_AWDSGL | ADC_CR1_SCAN |
650 ADC_CR1_JEOCIE | ADC_CR1_AWDIE | ADC_CR1_EOCIE |
651 ADC_CR1_AWDCH ));
652
653 /* Reset register CR2 */
654 ADC_CR2_CLEAR(hadc);
655
656 /* Reset register SMPR0 */
657 ADC_SMPR0_CLEAR(hadc);
658
659 /* Reset register SMPR1 */
660 ADC_SMPR1_CLEAR(hadc);
661
662 /* Reset register SMPR2 */
663 CLEAR_BIT(hadc->Instance->SMPR2, (ADC_SMPR2_SMP19 | ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 |
664 ADC_SMPR2_SMP16 | ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 |
665 ADC_SMPR2_SMP13 | ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 |
666 ADC_SMPR2_SMP10 ));
667
668 /* Reset register SMPR3 */
669 CLEAR_BIT(hadc->Instance->SMPR3, (ADC_SMPR3_SMP9 | ADC_SMPR3_SMP8 | ADC_SMPR3_SMP7 |
670 ADC_SMPR3_SMP6 | ADC_SMPR3_SMP5 | ADC_SMPR3_SMP4 |
671 ADC_SMPR3_SMP3 | ADC_SMPR3_SMP2 | ADC_SMPR3_SMP1 |
672 ADC_SMPR3_SMP0 ));
673
674 /* Reset register JOFR1 */
675 CLEAR_BIT(hadc->Instance->JOFR1, ADC_JOFR1_JOFFSET1);
676 /* Reset register JOFR2 */
677 CLEAR_BIT(hadc->Instance->JOFR2, ADC_JOFR2_JOFFSET2);
678 /* Reset register JOFR3 */
679 CLEAR_BIT(hadc->Instance->JOFR3, ADC_JOFR3_JOFFSET3);
680 /* Reset register JOFR4 */
681 CLEAR_BIT(hadc->Instance->JOFR4, ADC_JOFR4_JOFFSET4);
682
683 /* Reset register HTR */
684 CLEAR_BIT(hadc->Instance->HTR, ADC_HTR_HT);
685 /* Reset register LTR */
686 CLEAR_BIT(hadc->Instance->LTR, ADC_LTR_LT);
687
688 /* Reset register SQR1 */
689 CLEAR_BIT(hadc->Instance->SQR1, (ADC_SQR1_L | __ADC_SQR1_SQXX));
690
691 /* Reset register SQR2 */
692 CLEAR_BIT(hadc->Instance->SQR2, (ADC_SQR2_SQ24 | ADC_SQR2_SQ23 | ADC_SQR2_SQ22 |
693 ADC_SQR2_SQ21 | ADC_SQR2_SQ20 | ADC_SQR2_SQ19 ));
694
695 /* Reset register SQR3 */
696 CLEAR_BIT(hadc->Instance->SQR3, (ADC_SQR3_SQ18 | ADC_SQR3_SQ17 | ADC_SQR3_SQ16 |
697 ADC_SQR3_SQ15 | ADC_SQR3_SQ14 | ADC_SQR3_SQ13 ));
698
699 /* Reset register SQR4 */
700 CLEAR_BIT(hadc->Instance->SQR4, (ADC_SQR4_SQ12 | ADC_SQR4_SQ11 | ADC_SQR4_SQ10 |
701 ADC_SQR4_SQ9 | ADC_SQR4_SQ8 | ADC_SQR4_SQ7 ));
702
703 /* Reset register SQR5 */
704 CLEAR_BIT(hadc->Instance->SQR5, (ADC_SQR5_SQ6 | ADC_SQR5_SQ5 | ADC_SQR5_SQ4 |
705 ADC_SQR5_SQ3 | ADC_SQR5_SQ2 | ADC_SQR5_SQ1 ));
706
707
708 /* Reset register JSQR */
709 CLEAR_BIT(hadc->Instance->JSQR, (ADC_JSQR_JL |
710 ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 |
711 ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 ));
712
713 /* Reset register DR */
714 /* bits in access mode read only, no direct reset applicable*/
715
716 /* Reset registers JDR1, JDR2, JDR3, JDR4 */
717 /* bits in access mode read only, no direct reset applicable*/
718
719 /* Reset register CCR */
720 CLEAR_BIT(ADC->CCR, ADC_CCR_TSVREFE);
721
722 /* ========== Hard reset ADC peripheral ========== */
723 /* Performs a global reset of the entire ADC peripheral: ADC state is */
724 /* forced to a similar state after device power-on. */
725 /* If needed, copy-paste and uncomment the following reset code into */
726 /* function "void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)": */
727 /* */
728 /* __HAL_RCC_ADC1_FORCE_RESET() */
729 /* __HAL_RCC_ADC1_RELEASE_RESET() */
730
731 /* DeInit the low level hardware */
732 HAL_ADC_MspDeInit(hadc);
733
734 /* Set ADC error code to none */
735 ADC_CLEAR_ERRORCODE(hadc);
736
737 /* Set ADC state */
738 hadc->State = HAL_ADC_STATE_RESET;
739
740 }
741
742 /* Process unlocked */
743 __HAL_UNLOCK(hadc);
744
745 /* Return function status */
746 return tmp_hal_status;
747 }
748
749 /**
750 * @brief Initializes the ADC MSP.
751 * @param hadc: ADC handle
752 * @retval None
753 */
HAL_ADC_MspInit(ADC_HandleTypeDef * hadc)754 __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
755 {
756 /* Prevent unused argument(s) compilation warning */
757 UNUSED(hadc);
758
759 /* NOTE : This function should not be modified. When the callback is needed,
760 function HAL_ADC_MspInit must be implemented in the user file.
761 */
762 }
763
764 /**
765 * @brief DeInitializes the ADC MSP.
766 * @param hadc: ADC handle
767 * @retval None
768 */
HAL_ADC_MspDeInit(ADC_HandleTypeDef * hadc)769 __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
770 {
771 /* Prevent unused argument(s) compilation warning */
772 UNUSED(hadc);
773
774 /* NOTE : This function should not be modified. When the callback is needed,
775 function HAL_ADC_MspDeInit must be implemented in the user file.
776 */
777 }
778
779 /**
780 * @}
781 */
782
783 /** @defgroup ADC_Exported_Functions_Group2 ADC Input and Output operation functions
784 * @brief ADC IO operation functions
785 *
786 @verbatim
787 ===============================================================================
788 ##### IO operation functions #####
789 ===============================================================================
790 [..] This section provides functions allowing to:
791 (+) Start conversion of regular group.
792 (+) Stop conversion of regular group.
793 (+) Poll for conversion complete on regular group.
794 (+) Poll for conversion event.
795 (+) Get result of regular channel conversion.
796 (+) Start conversion of regular group and enable interruptions.
797 (+) Stop conversion of regular group and disable interruptions.
798 (+) Handle ADC interrupt request
799 (+) Start conversion of regular group and enable DMA transfer.
800 (+) Stop conversion of regular group and disable ADC DMA transfer.
801 @endverbatim
802 * @{
803 */
804
805 /**
806 * @brief Enables ADC, starts conversion of regular group.
807 * Interruptions enabled in this function: None.
808 * @param hadc: ADC handle
809 * @retval HAL status
810 */
HAL_ADC_Start(ADC_HandleTypeDef * hadc)811 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
812 {
813 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
814
815 /* Check the parameters */
816 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
817
818 /* Process locked */
819 __HAL_LOCK(hadc);
820
821 /* Enable the ADC peripheral */
822 tmp_hal_status = ADC_Enable(hadc);
823
824 /* Start conversion if ADC is effectively enabled */
825 if (tmp_hal_status == HAL_OK)
826 {
827 /* Set ADC state */
828 /* - Clear state bitfield related to regular group conversion results */
829 /* - Set state bitfield related to regular group operation */
830 ADC_STATE_CLR_SET(hadc->State,
831 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
832 HAL_ADC_STATE_REG_BUSY);
833
834 /* If conversions on group regular are also triggering group injected, */
835 /* update ADC state. */
836 if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
837 {
838 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
839 }
840
841 /* State machine update: Check if an injected conversion is ongoing */
842 if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
843 {
844 /* Reset ADC error code fields related to conversions on group regular */
845 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
846 }
847 else
848 {
849 /* Reset ADC all error code fields */
850 ADC_CLEAR_ERRORCODE(hadc);
851 }
852
853 /* Process unlocked */
854 /* Unlock before starting ADC conversions: in case of potential */
855 /* interruption, to let the process to ADC IRQ Handler. */
856 __HAL_UNLOCK(hadc);
857
858 /* Clear regular group conversion flag and overrun flag */
859 /* (To ensure of no unknown state from potential previous ADC operations) */
860 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
861
862 /* Enable conversion of regular group. */
863 /* If software start has been selected, conversion starts immediately. */
864 /* If external trigger has been selected, conversion will start at next */
865 /* trigger event. */
866 if (ADC_IS_SOFTWARE_START_REGULAR(hadc))
867 {
868 /* Start ADC conversion on regular group */
869 SET_BIT(hadc->Instance->CR2, ADC_CR2_SWSTART);
870 }
871 }
872
873 /* Return function status */
874 return tmp_hal_status;
875 }
876
877 /**
878 * @brief Stop ADC conversion of regular group (and injected channels in
879 * case of auto_injection mode), disable ADC peripheral.
880 * @note: ADC peripheral disable is forcing stop of potential
881 * conversion on injected group. If injected group is under use, it
882 * should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
883 * @param hadc: ADC handle
884 * @retval HAL status.
885 */
HAL_ADC_Stop(ADC_HandleTypeDef * hadc)886 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
887 {
888 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
889
890 /* Check the parameters */
891 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
892
893 /* Process locked */
894 __HAL_LOCK(hadc);
895
896 /* Stop potential conversion on going, on regular and injected groups */
897 /* Disable ADC peripheral */
898 tmp_hal_status = ADC_ConversionStop_Disable(hadc);
899
900 /* Check if ADC is effectively disabled */
901 if (tmp_hal_status == HAL_OK)
902 {
903 /* Set ADC state */
904 ADC_STATE_CLR_SET(hadc->State,
905 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
906 HAL_ADC_STATE_READY);
907 }
908
909 /* Process unlocked */
910 __HAL_UNLOCK(hadc);
911
912 /* Return function status */
913 return tmp_hal_status;
914 }
915
916 /**
917 * @brief Wait for regular group conversion to be completed.
918 * @note ADC conversion flags EOS (end of sequence) and EOC (end of
919 * conversion) are cleared by this function, with an exception:
920 * if low power feature "LowPowerAutoWait" is enabled, flags are
921 * not cleared to not interfere with this feature until data register
922 * is read using function HAL_ADC_GetValue().
923 * @note This function cannot be used in a particular setup: ADC configured
924 * in DMA mode and polling for end of each conversion (ADC init
925 * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV).
926 * In this case, DMA resets the flag EOC and polling cannot be
927 * performed on each conversion. Nevertheless, polling can still
928 * be performed on the complete sequence (ADC init
929 * parameter "EOCSelection" set to ADC_EOC_SEQ_CONV).
930 * @param hadc: ADC handle
931 * @param Timeout: Timeout value in millisecond.
932 * @retval HAL status
933 */
HAL_ADC_PollForConversion(ADC_HandleTypeDef * hadc,uint32_t Timeout)934 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
935 {
936 uint32_t tickstart = 0;
937
938 /* Check the parameters */
939 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
940
941 /* Verification that ADC configuration is compliant with polling for */
942 /* each conversion: */
943 /* Particular case is ADC configured in DMA mode and ADC sequencer with */
944 /* several ranks and polling for end of each conversion. */
945 /* For code simplicity sake, this particular case is generalized to */
946 /* ADC configured in DMA mode and and polling for end of each conversion. */
947 if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_EOCS) &&
948 HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA) )
949 {
950 /* Update ADC state machine to error */
951 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
952
953 /* Process unlocked */
954 __HAL_UNLOCK(hadc);
955
956 return HAL_ERROR;
957 }
958
959 /* Get tick count */
960 tickstart = HAL_GetTick();
961
962 /* Wait until End of Conversion flag is raised */
963 while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC))
964 {
965 /* Check if timeout is disabled (set to infinite wait) */
966 if(Timeout != HAL_MAX_DELAY)
967 {
968 if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
969 {
970 /* Update ADC state machine to timeout */
971 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
972
973 /* Process unlocked */
974 __HAL_UNLOCK(hadc);
975
976 return HAL_TIMEOUT;
977 }
978 }
979 }
980
981 /* Clear end of conversion flag of regular group if low power feature */
982 /* "Auto Wait" is disabled, to not interfere with this feature until data */
983 /* register is read using function HAL_ADC_GetValue(). */
984 if (hadc->Init.LowPowerAutoWait == DISABLE)
985 {
986 /* Clear regular group conversion flag */
987 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
988 }
989
990 /* Update ADC state machine */
991 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
992
993 /* Determine whether any further conversion upcoming on group regular */
994 /* by external trigger, continuous mode or scan sequence on going. */
995 /* Note: On STM32L1, there is no independent flag of end of sequence. */
996 /* The test of scan sequence on going is done either with scan */
997 /* sequence disabled or with end of conversion flag set to */
998 /* of end of sequence. */
999 if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
1000 (hadc->Init.ContinuousConvMode == DISABLE) &&
1001 (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
1002 HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) )
1003 {
1004 /* Set ADC state */
1005 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
1006
1007 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
1008 {
1009 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
1010 }
1011 }
1012
1013 /* Return ADC state */
1014 return HAL_OK;
1015 }
1016
1017 /**
1018 * @brief Poll for conversion event.
1019 * @param hadc: ADC handle
1020 * @param EventType: the ADC event type.
1021 * This parameter can be one of the following values:
1022 * @arg ADC_AWD_EVENT: ADC Analog watchdog event.
1023 * @arg ADC_OVR_EVENT: ADC Overrun event.
1024 * @param Timeout: Timeout value in millisecond.
1025 * @retval HAL status
1026 */
HAL_ADC_PollForEvent(ADC_HandleTypeDef * hadc,uint32_t EventType,uint32_t Timeout)1027 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
1028 {
1029 uint32_t tickstart = 0;
1030
1031 /* Check the parameters */
1032 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1033 assert_param(IS_ADC_EVENT_TYPE(EventType));
1034
1035 /* Get tick count */
1036 tickstart = HAL_GetTick();
1037
1038 /* Check selected event flag */
1039 while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET)
1040 {
1041 /* Check if timeout is disabled (set to infinite wait) */
1042 if(Timeout != HAL_MAX_DELAY)
1043 {
1044 if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
1045 {
1046 /* Update ADC state machine to timeout */
1047 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
1048
1049 /* Process unlocked */
1050 __HAL_UNLOCK(hadc);
1051
1052 return HAL_TIMEOUT;
1053 }
1054 }
1055 }
1056
1057 switch(EventType)
1058 {
1059 /* Analog watchdog (level out of window) event */
1060 case ADC_AWD_EVENT:
1061 /* Set ADC state */
1062 SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
1063
1064 /* Clear ADC analog watchdog flag */
1065 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
1066 break;
1067
1068 /* Overrun event */
1069 default: /* Case ADC_OVR_EVENT */
1070 /* Note: On STM32L1, ADC overrun can be set through other parameters */
1071 /* refer to description of parameter "EOCSelection" for more */
1072 /* details. */
1073
1074 /* Set ADC state */
1075 SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
1076 /* Set ADC error code to overrun */
1077 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
1078
1079 /* Clear ADC overrun flag */
1080 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
1081 break;
1082 }
1083
1084 /* Return ADC state */
1085 return HAL_OK;
1086 }
1087
1088 /**
1089 * @brief Enables ADC, starts conversion of regular group with interruption.
1090 * Interruptions enabled in this function:
1091 * - EOC (end of conversion of regular group)
1092 * - overrun
1093 * Each of these interruptions has its dedicated callback function.
1094 * @param hadc: ADC handle
1095 * @retval HAL status
1096 */
HAL_ADC_Start_IT(ADC_HandleTypeDef * hadc)1097 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
1098 {
1099 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
1100
1101 /* Check the parameters */
1102 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1103
1104 /* Process locked */
1105 __HAL_LOCK(hadc);
1106
1107 /* Enable the ADC peripheral */
1108 tmp_hal_status = ADC_Enable(hadc);
1109
1110 /* Start conversion if ADC is effectively enabled */
1111 if (tmp_hal_status == HAL_OK)
1112 {
1113 /* Set ADC state */
1114 /* - Clear state bitfield related to regular group conversion results */
1115 /* - Set state bitfield related to regular group operation */
1116 ADC_STATE_CLR_SET(hadc->State,
1117 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
1118 HAL_ADC_STATE_REG_BUSY);
1119
1120 /* If conversions on group regular are also triggering group injected, */
1121 /* update ADC state. */
1122 if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
1123 {
1124 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
1125 }
1126
1127 /* State machine update: Check if an injected conversion is ongoing */
1128 if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
1129 {
1130 /* Reset ADC error code fields related to conversions on group regular */
1131 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
1132 }
1133 else
1134 {
1135 /* Reset ADC all error code fields */
1136 ADC_CLEAR_ERRORCODE(hadc);
1137 }
1138
1139 /* Process unlocked */
1140 /* Unlock before starting ADC conversions: in case of potential */
1141 /* interruption, to let the process to ADC IRQ Handler. */
1142 __HAL_UNLOCK(hadc);
1143
1144 /* Clear regular group conversion flag and overrun flag */
1145 /* (To ensure of no unknown state from potential previous ADC operations) */
1146 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
1147
1148 /* Enable end of conversion interrupt for regular group */
1149 __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR));
1150
1151 /* Enable conversion of regular group. */
1152 /* If software start has been selected, conversion starts immediately. */
1153 /* If external trigger has been selected, conversion will start at next */
1154 /* trigger event. */
1155 if (ADC_IS_SOFTWARE_START_REGULAR(hadc))
1156 {
1157 /* Start ADC conversion on regular group */
1158 SET_BIT(hadc->Instance->CR2, ADC_CR2_SWSTART);
1159 }
1160 }
1161
1162 /* Return function status */
1163 return tmp_hal_status;
1164 }
1165
1166 /**
1167 * @brief Stop ADC conversion of regular group (and injected group in
1168 * case of auto_injection mode), disable interrution of
1169 * end-of-conversion, disable ADC peripheral.
1170 * @param hadc: ADC handle
1171 * @retval None
1172 */
HAL_ADC_Stop_IT(ADC_HandleTypeDef * hadc)1173 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
1174 {
1175 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
1176
1177 /* Check the parameters */
1178 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1179
1180 /* Process locked */
1181 __HAL_LOCK(hadc);
1182
1183 /* Stop potential conversion on going, on regular and injected groups */
1184 /* Disable ADC peripheral */
1185 tmp_hal_status = ADC_ConversionStop_Disable(hadc);
1186
1187 /* Check if ADC is effectively disabled */
1188 if (tmp_hal_status == HAL_OK)
1189 {
1190 /* Disable ADC end of conversion interrupt for regular group */
1191 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
1192
1193 /* Set ADC state */
1194 ADC_STATE_CLR_SET(hadc->State,
1195 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
1196 HAL_ADC_STATE_READY);
1197 }
1198
1199 /* Process unlocked */
1200 __HAL_UNLOCK(hadc);
1201
1202 /* Return function status */
1203 return tmp_hal_status;
1204 }
1205
1206 /**
1207 * @brief Enables ADC, starts conversion of regular group and transfers result
1208 * through DMA.
1209 * Interruptions enabled in this function:
1210 * - DMA transfer complete
1211 * - DMA half transfer
1212 * - overrun
1213 * Each of these interruptions has its dedicated callback function.
1214 * @param hadc: ADC handle
1215 * @param pData: The destination Buffer address.
1216 * @param Length: The length of data to be transferred from ADC peripheral to memory.
1217 * @retval None
1218 */
HAL_ADC_Start_DMA(ADC_HandleTypeDef * hadc,uint32_t * pData,uint32_t Length)1219 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
1220 {
1221 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
1222
1223 /* Check the parameters */
1224 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1225
1226 /* Process locked */
1227 __HAL_LOCK(hadc);
1228
1229 /* Enable the ADC peripheral */
1230 tmp_hal_status = ADC_Enable(hadc);
1231
1232 /* Start conversion if ADC is effectively enabled */
1233 if (tmp_hal_status == HAL_OK)
1234 {
1235 /* Set ADC state */
1236 /* - Clear state bitfield related to regular group conversion results */
1237 /* - Set state bitfield related to regular group operation */
1238 ADC_STATE_CLR_SET(hadc->State,
1239 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
1240 HAL_ADC_STATE_REG_BUSY);
1241
1242 /* If conversions on group regular are also triggering group injected, */
1243 /* update ADC state. */
1244 if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
1245 {
1246 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
1247 }
1248
1249 /* State machine update: Check if an injected conversion is ongoing */
1250 if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
1251 {
1252 /* Reset ADC error code fields related to conversions on group regular */
1253 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
1254 }
1255 else
1256 {
1257 /* Reset ADC all error code fields */
1258 ADC_CLEAR_ERRORCODE(hadc);
1259 }
1260
1261 /* Process unlocked */
1262 /* Unlock before starting ADC conversions: in case of potential */
1263 /* interruption, to let the process to ADC IRQ Handler. */
1264 __HAL_UNLOCK(hadc);
1265
1266 /* Set the DMA transfer complete callback */
1267 hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
1268
1269 /* Set the DMA half transfer complete callback */
1270 hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
1271
1272 /* Set the DMA error callback */
1273 hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
1274
1275
1276 /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
1277 /* start (in case of SW start): */
1278
1279 /* Clear regular group conversion flag and overrun flag */
1280 /* (To ensure of no unknown state from potential previous ADC operations) */
1281 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
1282
1283 /* Enable ADC overrun interrupt */
1284 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
1285
1286 /* Enable ADC DMA mode */
1287 hadc->Instance->CR2 |= ADC_CR2_DMA;
1288
1289 /* Start the DMA channel */
1290 HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
1291
1292 /* Enable conversion of regular group. */
1293 /* If software start has been selected, conversion starts immediately. */
1294 /* If external trigger has been selected, conversion will start at next */
1295 /* trigger event. */
1296 /* Note: Alternate trigger for single conversion could be to force an */
1297 /* additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/
1298 if (ADC_IS_SOFTWARE_START_REGULAR(hadc))
1299 {
1300 /* Start ADC conversion on regular group */
1301 SET_BIT(hadc->Instance->CR2, ADC_CR2_SWSTART);
1302 }
1303 }
1304
1305 /* Return function status */
1306 return tmp_hal_status;
1307 }
1308
1309 /**
1310 * @brief Stop ADC conversion of regular group (and injected group in
1311 * case of auto_injection mode), disable ADC DMA transfer, disable
1312 * ADC peripheral.
1313 * @note: ADC peripheral disable is forcing stop of potential
1314 * conversion on injected group. If injected group is under use, it
1315 * should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
1316 * @param hadc: ADC handle
1317 * @retval HAL status.
1318 */
HAL_ADC_Stop_DMA(ADC_HandleTypeDef * hadc)1319 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
1320 {
1321 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
1322
1323 /* Check the parameters */
1324 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1325
1326 /* Process locked */
1327 __HAL_LOCK(hadc);
1328
1329 /* Stop potential conversion on going, on regular and injected groups */
1330 /* Disable ADC peripheral */
1331 tmp_hal_status = ADC_ConversionStop_Disable(hadc);
1332
1333 /* Check if ADC is effectively disabled */
1334 if (tmp_hal_status == HAL_OK)
1335 {
1336 /* Disable ADC DMA mode */
1337 hadc->Instance->CR2 &= ~ADC_CR2_DMA;
1338
1339 /* Disable the DMA channel (in case of DMA in circular mode or stop while */
1340 /* DMA transfer is on going) */
1341 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
1342
1343 /* Check if DMA channel effectively disabled */
1344 if (tmp_hal_status == HAL_OK)
1345 {
1346 /* Set ADC state */
1347 ADC_STATE_CLR_SET(hadc->State,
1348 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
1349 HAL_ADC_STATE_READY);
1350 }
1351 else
1352 {
1353 /* Update ADC state machine to error */
1354 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
1355 }
1356
1357 /* Disable ADC overrun interrupt */
1358 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
1359 }
1360
1361 /* Process unlocked */
1362 __HAL_UNLOCK(hadc);
1363
1364 /* Return function status */
1365 return tmp_hal_status;
1366 }
1367
1368 /**
1369 * @brief Get ADC regular group conversion result.
1370 * @note Reading register DR automatically clears ADC flag EOC
1371 * (ADC group regular end of unitary conversion).
1372 * @note This function does not clear ADC flag EOS
1373 * (ADC group regular end of sequence conversion).
1374 * Occurrence of flag EOS rising:
1375 * - If sequencer is composed of 1 rank, flag EOS is equivalent
1376 * to flag EOC.
1377 * - If sequencer is composed of several ranks, during the scan
1378 * sequence flag EOC only is raised, at the end of the scan sequence
1379 * both flags EOC and EOS are raised.
1380 * To clear this flag, either use function:
1381 * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
1382 * model polling: @ref HAL_ADC_PollForConversion()
1383 * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
1384 * @param hadc: ADC handle
1385 * @retval ADC group regular conversion data
1386 */
HAL_ADC_GetValue(ADC_HandleTypeDef * hadc)1387 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
1388 {
1389 /* Check the parameters */
1390 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1391
1392 /* Note: EOC flag is not cleared here by software because automatically */
1393 /* cleared by hardware when reading register DR. */
1394
1395 /* Return ADC converted value */
1396 return hadc->Instance->DR;
1397 }
1398
1399 /**
1400 * @brief Handles ADC interrupt request
1401 * @param hadc: ADC handle
1402 * @retval None
1403 */
HAL_ADC_IRQHandler(ADC_HandleTypeDef * hadc)1404 void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
1405 {
1406 /* Check the parameters */
1407 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1408 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
1409 assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
1410
1411
1412 /* ========== Check End of Conversion flag for regular group ========== */
1413 if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC))
1414 {
1415 if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) )
1416 {
1417 /* Update state machine on conversion status if not in error state */
1418 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
1419 {
1420 /* Set ADC state */
1421 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
1422 }
1423
1424 /* Determine whether any further conversion upcoming on group regular */
1425 /* by external trigger, continuous mode or scan sequence on going. */
1426 /* Note: On STM32L1, there is no independent flag of end of sequence. */
1427 /* The test of scan sequence on going is done either with scan */
1428 /* sequence disabled or with end of conversion flag set to */
1429 /* of end of sequence. */
1430 if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
1431 (hadc->Init.ContinuousConvMode == DISABLE) &&
1432 (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
1433 HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) )
1434 {
1435 /* Disable ADC end of single conversion interrupt on group regular */
1436 /* Note: Overrun interrupt was enabled with EOC interrupt in */
1437 /* HAL_ADC_Start_IT(), but is not disabled here because can be used */
1438 /* by overrun IRQ process below. */
1439 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
1440
1441 /* Set ADC state */
1442 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
1443
1444 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
1445 {
1446 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
1447 }
1448 }
1449
1450 /* Conversion complete callback */
1451 HAL_ADC_ConvCpltCallback(hadc);
1452
1453 /* Clear regular group conversion flag */
1454 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
1455 }
1456 }
1457
1458 /* ========== Check End of Conversion flag for injected group ========== */
1459 if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC))
1460 {
1461 if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC))
1462 {
1463 /* Update state machine on conversion status if not in error state */
1464 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
1465 {
1466 /* Set ADC state */
1467 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
1468 }
1469
1470 /* Determine whether any further conversion upcoming on group injected */
1471 /* by external trigger, scan sequence on going or by automatic injected */
1472 /* conversion from group regular (same conditions as group regular */
1473 /* interruption disabling above). */
1474 if(ADC_IS_SOFTWARE_START_INJECTED(hadc) &&
1475 (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) ||
1476 HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) &&
1477 (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
1478 (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
1479 (hadc->Init.ContinuousConvMode == DISABLE) ) ) )
1480 {
1481 /* Disable ADC end of single conversion interrupt on group injected */
1482 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
1483
1484 /* Set ADC state */
1485 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
1486
1487 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
1488 {
1489 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
1490 }
1491 }
1492
1493 /* Conversion complete callback */
1494 HAL_ADCEx_InjectedConvCpltCallback(hadc);
1495
1496 /* Clear injected group conversion flag */
1497 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC));
1498 }
1499 }
1500
1501 /* ========== Check Analog watchdog flags ========== */
1502 if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD))
1503 {
1504 if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD))
1505 {
1506 /* Set ADC state */
1507 SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
1508
1509 /* Level out of window callback */
1510 HAL_ADC_LevelOutOfWindowCallback(hadc);
1511
1512 /* Clear the ADC analog watchdog flag */
1513 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
1514 }
1515 }
1516
1517 /* ========== Check Overrun flag ========== */
1518 if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_OVR))
1519 {
1520 if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR))
1521 {
1522 /* Note: On STM32L1, ADC overrun can be set through other parameters */
1523 /* refer to description of parameter "EOCSelection" for more */
1524 /* details. */
1525
1526 /* Set ADC error code to overrun */
1527 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
1528
1529 /* Clear ADC overrun flag */
1530 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
1531
1532 /* Error callback */
1533 HAL_ADC_ErrorCallback(hadc);
1534
1535 /* Clear the Overrun flag */
1536 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
1537 }
1538 }
1539
1540 }
1541
1542 /**
1543 * @brief Conversion complete callback in non blocking mode
1544 * @param hadc: ADC handle
1545 * @retval None
1546 */
HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef * hadc)1547 __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
1548 {
1549 /* Prevent unused argument(s) compilation warning */
1550 UNUSED(hadc);
1551
1552 /* NOTE : This function should not be modified. When the callback is needed,
1553 function HAL_ADC_ConvCpltCallback must be implemented in the user file.
1554 */
1555 }
1556
1557 /**
1558 * @brief Conversion DMA half-transfer callback in non blocking mode
1559 * @param hadc: ADC handle
1560 * @retval None
1561 */
HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef * hadc)1562 __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
1563 {
1564 /* Prevent unused argument(s) compilation warning */
1565 UNUSED(hadc);
1566
1567 /* NOTE : This function should not be modified. When the callback is needed,
1568 function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
1569 */
1570 }
1571
1572 /**
1573 * @brief Analog watchdog callback in non blocking mode.
1574 * @param hadc: ADC handle
1575 * @retval None
1576 */
HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef * hadc)1577 __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
1578 {
1579 /* Prevent unused argument(s) compilation warning */
1580 UNUSED(hadc);
1581
1582 /* NOTE : This function should not be modified. When the callback is needed,
1583 function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file.
1584 */
1585 }
1586
1587 /**
1588 * @brief ADC error callback in non blocking mode
1589 * (ADC conversion with interruption or transfer by DMA)
1590 * @note In case of error due to overrun when using ADC with DMA transfer
1591 * (HAL ADC handle paramater "ErrorCode" to state "HAL_ADC_ERROR_OVR"):
1592 * - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()".
1593 * - If needed, restart a new ADC conversion using function
1594 * "HAL_ADC_Start_DMA()"
1595 * (this function is also clearing overrun flag)
1596 * @param hadc: ADC handle
1597 * @retval None
1598 */
HAL_ADC_ErrorCallback(ADC_HandleTypeDef * hadc)1599 __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
1600 {
1601 /* Prevent unused argument(s) compilation warning */
1602 UNUSED(hadc);
1603
1604 /* NOTE : This function should not be modified. When the callback is needed,
1605 function HAL_ADC_ErrorCallback must be implemented in the user file.
1606 */
1607 }
1608
1609
1610 /**
1611 * @}
1612 */
1613
1614 /** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
1615 * @brief Peripheral Control functions
1616 *
1617 @verbatim
1618 ===============================================================================
1619 ##### Peripheral Control functions #####
1620 ===============================================================================
1621 [..] This section provides functions allowing to:
1622 (+) Configure channels on regular group
1623 (+) Configure the analog watchdog
1624
1625 @endverbatim
1626 * @{
1627 */
1628
1629 /**
1630 * @brief Configures the the selected channel to be linked to the regular
1631 * group.
1632 * @note In case of usage of internal measurement channels:
1633 * Vbat/VrefInt/TempSensor.
1634 * These internal paths can be be disabled using function
1635 * HAL_ADC_DeInit().
1636 * @note Possibility to update parameters on the fly:
1637 * This function initializes channel into regular group, following
1638 * calls to this function can be used to reconfigure some parameters
1639 * of structure "ADC_ChannelConfTypeDef" on the fly, without reseting
1640 * the ADC.
1641 * The setting of these parameters is conditioned to ADC state.
1642 * For parameters constraints, see comments of structure
1643 * "ADC_ChannelConfTypeDef".
1644 * @param hadc: ADC handle
1645 * @param sConfig: Structure of ADC channel for regular group.
1646 * @retval HAL status
1647 */
HAL_ADC_ConfigChannel(ADC_HandleTypeDef * hadc,ADC_ChannelConfTypeDef * sConfig)1648 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
1649 {
1650 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
1651 __IO uint32_t wait_loop_index = 0;
1652
1653 /* Check the parameters */
1654 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1655 assert_param(IS_ADC_CHANNEL(sConfig->Channel));
1656 assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
1657 assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
1658
1659 /* Process locked */
1660 __HAL_LOCK(hadc);
1661
1662
1663 /* Regular sequence configuration */
1664 /* For Rank 1 to 6 */
1665 if (sConfig->Rank < 7)
1666 {
1667 MODIFY_REG(hadc->Instance->SQR5,
1668 ADC_SQR5_RK(ADC_SQR5_SQ1, sConfig->Rank),
1669 ADC_SQR5_RK(sConfig->Channel, sConfig->Rank) );
1670 }
1671 /* For Rank 7 to 12 */
1672 else if (sConfig->Rank < 13)
1673 {
1674 MODIFY_REG(hadc->Instance->SQR4,
1675 ADC_SQR4_RK(ADC_SQR4_SQ7, sConfig->Rank),
1676 ADC_SQR4_RK(sConfig->Channel, sConfig->Rank) );
1677 }
1678 /* For Rank 13 to 18 */
1679 else if (sConfig->Rank < 19)
1680 {
1681 MODIFY_REG(hadc->Instance->SQR3,
1682 ADC_SQR3_RK(ADC_SQR3_SQ13, sConfig->Rank),
1683 ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) );
1684 }
1685 /* For Rank 19 to 24 */
1686 else if (sConfig->Rank < 25)
1687 {
1688 MODIFY_REG(hadc->Instance->SQR2,
1689 ADC_SQR2_RK(ADC_SQR2_SQ19, sConfig->Rank),
1690 ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) );
1691 }
1692 /* For Rank 25 to 28 */
1693 else
1694 {
1695 MODIFY_REG(hadc->Instance->SQR1,
1696 ADC_SQR1_RK(ADC_SQR1_SQ25, sConfig->Rank),
1697 ADC_SQR1_RK(sConfig->Channel, sConfig->Rank) );
1698 }
1699
1700
1701 /* Channel sampling time configuration */
1702 /* For channels 0 to 9 */
1703 if (sConfig->Channel < ADC_CHANNEL_10)
1704 {
1705 MODIFY_REG(hadc->Instance->SMPR3,
1706 ADC_SMPR3(ADC_SMPR3_SMP0, sConfig->Channel),
1707 ADC_SMPR3(sConfig->SamplingTime, sConfig->Channel) );
1708 }
1709 /* For channels 10 to 19 */
1710 else if (sConfig->Channel < ADC_CHANNEL_20)
1711 {
1712 MODIFY_REG(hadc->Instance->SMPR2,
1713 ADC_SMPR2(ADC_SMPR2_SMP10, sConfig->Channel),
1714 ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) );
1715 }
1716 /* For channels 20 to 26 for devices Cat.1, Cat.2, Cat.3 */
1717 /* For channels 20 to 29 for devices Cat4, Cat.5 */
1718 else if (sConfig->Channel <= ADC_SMPR1_CHANNEL_MAX)
1719 {
1720 MODIFY_REG(hadc->Instance->SMPR1,
1721 ADC_SMPR1(ADC_SMPR1_SMP20, sConfig->Channel),
1722 ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) );
1723 }
1724 /* For channels 30 to 31 for devices Cat4, Cat.5 */
1725 else
1726 {
1727 ADC_SMPR0_CHANNEL_SET(hadc, sConfig->SamplingTime, sConfig->Channel);
1728 }
1729
1730 /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */
1731 /* and VREFINT measurement path. */
1732 if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) ||
1733 (sConfig->Channel == ADC_CHANNEL_VREFINT) )
1734 {
1735 if (READ_BIT(ADC->CCR, ADC_CCR_TSVREFE) == RESET)
1736 {
1737 SET_BIT(ADC->CCR, ADC_CCR_TSVREFE);
1738
1739 if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR))
1740 {
1741 /* Delay for temperature sensor stabilization time */
1742 /* Compute number of CPU cycles to wait for */
1743 wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000));
1744 while(wait_loop_index != 0)
1745 {
1746 wait_loop_index--;
1747 }
1748 }
1749 }
1750 }
1751
1752 /* Process unlocked */
1753 __HAL_UNLOCK(hadc);
1754
1755 /* Return function status */
1756 return tmp_hal_status;
1757 }
1758
1759 /**
1760 * @brief Configures the analog watchdog.
1761 * @note Analog watchdog thresholds can be modified while ADC conversion
1762 * is on going.
1763 * In this case, some constraints must be taken into account:
1764 * the programmed threshold values are effective from the next
1765 * ADC EOC (end of unitary conversion).
1766 * Considering that registers write delay may happen due to
1767 * bus activity, this might cause an uncertainty on the
1768 * effective timing of the new programmed threshold values.
1769 * @param hadc: ADC handle
1770 * @param AnalogWDGConfig: Structure of ADC analog watchdog configuration
1771 * @retval HAL status
1772 */
HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef * hadc,ADC_AnalogWDGConfTypeDef * AnalogWDGConfig)1773 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
1774 {
1775 /* Check the parameters */
1776 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1777 assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
1778 assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
1779 assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, AnalogWDGConfig->HighThreshold));
1780 assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, AnalogWDGConfig->LowThreshold));
1781
1782 if((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) ||
1783 (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) ||
1784 (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) )
1785 {
1786 assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
1787 }
1788
1789 /* Process locked */
1790 __HAL_LOCK(hadc);
1791
1792 /* Analog watchdog configuration */
1793
1794 /* Configure ADC Analog watchdog interrupt */
1795 if(AnalogWDGConfig->ITMode == ENABLE)
1796 {
1797 /* Enable the ADC Analog watchdog interrupt */
1798 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD);
1799 }
1800 else
1801 {
1802 /* Disable the ADC Analog watchdog interrupt */
1803 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD);
1804 }
1805
1806 /* Configuration of analog watchdog: */
1807 /* - Set the analog watchdog enable mode: regular and/or injected groups, */
1808 /* one or all channels. */
1809 /* - Set the Analog watchdog channel (is not used if watchdog */
1810 /* mode "all channels": ADC_CFGR_AWD1SGL=0). */
1811 hadc->Instance->CR1 &= ~( ADC_CR1_AWDSGL |
1812 ADC_CR1_JAWDEN |
1813 ADC_CR1_AWDEN |
1814 ADC_CR1_AWDCH );
1815
1816 hadc->Instance->CR1 |= ( AnalogWDGConfig->WatchdogMode |
1817 AnalogWDGConfig->Channel );
1818
1819 /* Set the high threshold */
1820 hadc->Instance->HTR = AnalogWDGConfig->HighThreshold;
1821
1822 /* Set the low threshold */
1823 hadc->Instance->LTR = AnalogWDGConfig->LowThreshold;
1824
1825 /* Process unlocked */
1826 __HAL_UNLOCK(hadc);
1827
1828 /* Return function status */
1829 return HAL_OK;
1830 }
1831
1832
1833 /**
1834 * @}
1835 */
1836
1837
1838 /** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
1839 * @brief Peripheral State functions
1840 *
1841 @verbatim
1842 ===============================================================================
1843 ##### Peripheral State and Errors functions #####
1844 ===============================================================================
1845 [..]
1846 This subsection provides functions to get in run-time the status of the
1847 peripheral.
1848 (+) Check the ADC state
1849 (+) Check the ADC error code
1850
1851 @endverbatim
1852 * @{
1853 */
1854
1855 /**
1856 * @brief return the ADC state
1857 * @param hadc: ADC handle
1858 * @retval HAL state
1859 */
HAL_ADC_GetState(ADC_HandleTypeDef * hadc)1860 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
1861 {
1862 /* Return ADC state */
1863 return hadc->State;
1864 }
1865
1866 /**
1867 * @brief Return the ADC error code
1868 * @param hadc: ADC handle
1869 * @retval ADC Error Code
1870 */
HAL_ADC_GetError(ADC_HandleTypeDef * hadc)1871 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
1872 {
1873 return hadc->ErrorCode;
1874 }
1875
1876 /**
1877 * @}
1878 */
1879
1880 /**
1881 * @}
1882 */
1883
1884 /** @defgroup ADC_Private_Functions ADC Private Functions
1885 * @{
1886 */
1887
1888 /**
1889 * @brief Enable the selected ADC.
1890 * @note Prerequisite condition to use this function: ADC must be disabled
1891 * and voltage regulator must be enabled (done into HAL_ADC_Init()).
1892 * @note If low power mode AutoPowerOff is enabled, power-on/off phases are
1893 * performed automatically by hardware.
1894 * In this mode, this function is useless and must not be called because
1895 * flag ADC_FLAG_RDY is not usable.
1896 * Therefore, this function must be called under condition of
1897 * "if (hadc->Init.LowPowerAutoPowerOff != ENABLE)".
1898 * @param hadc: ADC handle
1899 * @retval HAL status.
1900 */
ADC_Enable(ADC_HandleTypeDef * hadc)1901 HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
1902 {
1903 uint32_t tickstart = 0;
1904 __IO uint32_t wait_loop_index = 0;
1905
1906 /* ADC enable and wait for ADC ready (in case of ADC is disabled or */
1907 /* enabling phase not yet completed: flag ADC ready not yet set). */
1908 /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */
1909 /* causes: ADC clock not running, ...). */
1910 if (ADC_IS_ENABLE(hadc) == RESET)
1911 {
1912 /* Enable the Peripheral */
1913 __HAL_ADC_ENABLE(hadc);
1914
1915 /* Delay for ADC stabilization time */
1916 /* Compute number of CPU cycles to wait for */
1917 wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
1918 while(wait_loop_index != 0)
1919 {
1920 wait_loop_index--;
1921 }
1922
1923 /* Get tick count */
1924 tickstart = HAL_GetTick();
1925
1926 /* Wait for ADC effectively enabled */
1927 while(ADC_IS_ENABLE(hadc) == RESET)
1928 {
1929 if((HAL_GetTick() - tickstart ) > ADC_ENABLE_TIMEOUT)
1930 {
1931 /* Update ADC state machine to error */
1932 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
1933
1934 /* Set ADC error code to ADC IP internal error */
1935 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
1936
1937 /* Process unlocked */
1938 __HAL_UNLOCK(hadc);
1939
1940 return HAL_ERROR;
1941 }
1942 }
1943 }
1944
1945 /* Return HAL status */
1946 return HAL_OK;
1947 }
1948
1949 /**
1950 * @brief Stop ADC conversion and disable the selected ADC
1951 * @note Prerequisite condition to use this function: ADC conversions must be
1952 * stopped to disable the ADC.
1953 * @param hadc: ADC handle
1954 * @retval HAL status.
1955 */
ADC_ConversionStop_Disable(ADC_HandleTypeDef * hadc)1956 HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc)
1957 {
1958 uint32_t tickstart = 0;
1959
1960 /* Verification if ADC is not already disabled */
1961 if (ADC_IS_ENABLE(hadc) != RESET)
1962 {
1963 /* Disable the ADC peripheral */
1964 __HAL_ADC_DISABLE(hadc);
1965
1966 /* Get tick count */
1967 tickstart = HAL_GetTick();
1968
1969 /* Wait for ADC effectively disabled */
1970 while(ADC_IS_ENABLE(hadc) != RESET)
1971 {
1972 if((HAL_GetTick() - tickstart ) > ADC_DISABLE_TIMEOUT)
1973 {
1974 /* Update ADC state machine to error */
1975 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
1976
1977 /* Set ADC error code to ADC IP internal error */
1978 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
1979
1980 return HAL_ERROR;
1981 }
1982 }
1983 }
1984
1985 /* Return HAL status */
1986 return HAL_OK;
1987 }
1988
1989 /**
1990 * @brief DMA transfer complete callback.
1991 * @param hdma: pointer to DMA handle.
1992 * @retval None
1993 */
ADC_DMAConvCplt(DMA_HandleTypeDef * hdma)1994 static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
1995 {
1996 /* Retrieve ADC handle corresponding to current DMA handle */
1997 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
1998
1999 /* Update state machine on conversion status if not in error state */
2000 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))
2001 {
2002 /* Update ADC state machine */
2003 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
2004
2005 /* Determine whether any further conversion upcoming on group regular */
2006 /* by external trigger, continuous mode or scan sequence on going. */
2007 /* Note: On STM32L1, there is no independent flag of end of sequence. */
2008 /* The test of scan sequence on going is done either with scan */
2009 /* sequence disabled or with end of conversion flag set to */
2010 /* of end of sequence. */
2011 if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
2012 (hadc->Init.ContinuousConvMode == DISABLE) &&
2013 (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
2014 HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) )
2015 {
2016 /* Disable ADC end of single conversion interrupt on group regular */
2017 /* Note: Overrun interrupt was enabled with EOC interrupt in */
2018 /* HAL_ADC_Start_IT(), but is not disabled here because can be used */
2019 /* by overrun IRQ process below. */
2020 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
2021
2022 /* Set ADC state */
2023 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
2024
2025 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
2026 {
2027 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
2028 }
2029 }
2030
2031 /* Conversion complete callback */
2032 HAL_ADC_ConvCpltCallback(hadc);
2033 }
2034 else
2035 {
2036 /* Call DMA error callback */
2037 hadc->DMA_Handle->XferErrorCallback(hdma);
2038 }
2039 }
2040
2041 /**
2042 * @brief DMA half transfer complete callback.
2043 * @param hdma: pointer to DMA handle.
2044 * @retval None
2045 */
ADC_DMAHalfConvCplt(DMA_HandleTypeDef * hdma)2046 static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
2047 {
2048 /* Retrieve ADC handle corresponding to current DMA handle */
2049 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
2050
2051 /* Half conversion callback */
2052 HAL_ADC_ConvHalfCpltCallback(hadc);
2053 }
2054
2055 /**
2056 * @brief DMA error callback
2057 * @param hdma: pointer to DMA handle.
2058 * @retval None
2059 */
ADC_DMAError(DMA_HandleTypeDef * hdma)2060 static void ADC_DMAError(DMA_HandleTypeDef *hdma)
2061 {
2062 /* Retrieve ADC handle corresponding to current DMA handle */
2063 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
2064
2065 /* Set ADC state */
2066 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
2067
2068 /* Set ADC error code to DMA error */
2069 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
2070
2071 /* Error callback */
2072 HAL_ADC_ErrorCallback(hadc);
2073 }
2074
2075 /**
2076 * @}
2077 */
2078
2079 #endif /* HAL_ADC_MODULE_ENABLED */
2080 /**
2081 * @}
2082 */
2083
2084 /**
2085 * @}
2086 */
2087
2088 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
2089
