1 /**
2 ******************************************************************************
3 * @file stm32l0xx_hal_cortex.c
4 * @author MCD Application Team
5 * @brief CORTEX HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the CORTEX:
8 * + Initialization and de-initialization functions
9 * + Peripheral Control functions
10 *
11 @verbatim
12 ==============================================================================
13 ##### How to use this driver #####
14 ==============================================================================
15
16 [..]
17 *** How to configure Interrupts using CORTEX HAL driver ***
18 ===========================================================
19 [..]
20 This section provide functions allowing to configure the NVIC interrupts (IRQ).
21 The Cortex-M0+ exceptions are managed by CMSIS functions.
22 (#) Enable and Configure the priority of the selected IRQ Channels.
23 The priority can be 0..3.
24
25 -@- Lower priority values gives higher priority.
26 -@- Priority Order:
27 (#@) Lowest priority.
28 (#@) Lowest hardware priority (IRQn position).
29
30 (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority()
31
32 (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ()
33
34 [..]
35 *** How to configure Systick using CORTEX HAL driver ***
36 ========================================================
37 [..]
38 Setup SysTick Timer for time base
39
40 (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which
41 is a CMSIS function that:
42 (++) Configures the SysTick Reload register with value passed as function parameter.
43 (++) Configures the SysTick IRQ priority to the lowest value (0x03).
44 (++) Resets the SysTick Counter register.
45 (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
46 (++) Enables the SysTick Interrupt.
47 (++) Starts the SysTick Counter.
48
49 (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the function
50 HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
51 HAL_SYSTICK_Config() function call. The HAL_SYSTICK_CLKSourceConfig() function is defined
52 inside the stm32l0xx_hal_cortex.c file.
53
54 (+) You can change the SysTick IRQ priority by calling the
55 HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
56 call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
57
58 (+) To adjust the SysTick time base, use the following formula:
59
60 Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
61 (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
62 (++) Reload Value should not exceed 0xFFFFFF
63
64 @endverbatim
65 ******************************************************************************
66 * @attention
67 *
68 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
69 *
70 * Redistribution and use in source and binary forms, with or without modification,
71 * are permitted provided that the following conditions are met:
72 * 1. Redistributions of source code must retain the above copyright notice,
73 * this list of conditions and the following disclaimer.
74 * 2. Redistributions in binary form must reproduce the above copyright notice,
75 * this list of conditions and the following disclaimer in the documentation
76 * and/or other materials provided with the distribution.
77 * 3. Neither the name of STMicroelectronics nor the names of its contributors
78 * may be used to endorse or promote products derived from this software
79 * without specific prior written permission.
80 *
81 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
82 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
83 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
84 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
85 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
86 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
87 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
88 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
89 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
90 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
91 *
92 ******************************************************************************
93 */
94
95 /* Includes ------------------------------------------------------------------*/
96 #include "stm32l0xx_hal.h"
97
98 /** @addtogroup STM32L0xx_HAL_Driver
99 * @{
100 */
101
102 #ifdef HAL_CORTEX_MODULE_ENABLED
103
104 /** @addtogroup CORTEX
105 * @brief CORTEX HAL module driver
106 * @{
107 */
108
109 /* Private types -------------------------------------------------------------*/
110 /* Private variables ---------------------------------------------------------*/
111 /* Private constants ---------------------------------------------------------*/
112 /* Private macros ------------------------------------------------------------*/
113 /* Private functions ---------------------------------------------------------*/
114 /* Exported functions --------------------------------------------------------*/
115
116 /** @addtogroup CORTEX_Exported_Functions
117 * @{
118 */
119
120
121 /** @addtogroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
122 * @brief Initialization and Configuration functions
123 *
124 @verbatim
125 ==============================================================================
126 ##### Initialization and de-initialization functions #####
127 ==============================================================================
128 [..]
129 This section provides the CORTEX HAL driver functions allowing to configure Interrupts
130 Systick functionalities
131
132 @endverbatim
133 * @{
134 */
135
136 /**
137 * @brief Sets the priority of an interrupt.
138 * @param IRQn: External interrupt number .
139 * This parameter can be an enumerator of IRQn_Type enumeration
140 * (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file)
141 * @param PreemptPriority: The pre-emption priority for the IRQn channel.
142 * This parameter can be a value between 0 and 3.
143 * A lower priority value indicates a higher priority
144 * @param SubPriority: The subpriority level for the IRQ channel.
145 * with stm32l0xx devices, this parameter is a dummy value and it is ignored, because
146 * no subpriority supported in Cortex M0+ based products.
147 * @retval None
148 */
HAL_NVIC_SetPriority(IRQn_Type IRQn,uint32_t PreemptPriority,uint32_t SubPriority)149 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
150 {
151 /* Check the parameters */
152 assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
153 NVIC_SetPriority(IRQn,PreemptPriority);
154 }
155
156 /**
157 * @brief Enables a device specific interrupt in the NVIC interrupt controller.
158 * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
159 * function should be called before.
160 * @param IRQn External interrupt number .
161 * This parameter can be an enumerator of IRQn_Type enumeration
162 * (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file)
163 * @retval None
164 */
HAL_NVIC_EnableIRQ(IRQn_Type IRQn)165 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
166 {
167 /* Check the parameters */
168 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
169
170 /* Enable interrupt */
171 NVIC_EnableIRQ(IRQn);
172 }
173
174 /**
175 * @brief Disables a device specific interrupt in the NVIC interrupt controller.
176 * @param IRQn External interrupt number .
177 * This parameter can be an enumerator of IRQn_Type enumeration
178 * (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file)
179 * @retval None
180 */
HAL_NVIC_DisableIRQ(IRQn_Type IRQn)181 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
182 {
183 /* Check the parameters */
184 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
185
186 /* Disable interrupt */
187 NVIC_DisableIRQ(IRQn);
188 }
189
190 /**
191 * @brief Initiates a system reset request to reset the MCU.
192 * @retval None
193 */
HAL_NVIC_SystemReset(void)194 void HAL_NVIC_SystemReset(void)
195 {
196 /* System Reset */
197 NVIC_SystemReset();
198 }
199
200 /**
201 * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer.
202 * Counter is in free running mode to generate periodic interrupts.
203 * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
204 * @retval status: - 0 Function succeeded.
205 * - 1 Function failed.
206 */
HAL_SYSTICK_Config(uint32_t TicksNumb)207 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
208 {
209 return SysTick_Config(TicksNumb);
210 }
211 /**
212 * @}
213 */
214
215 /** @addtogroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
216 * @brief Cortex control functions
217 *
218 @verbatim
219 ==============================================================================
220 ##### Peripheral Control functions #####
221 ==============================================================================
222 [..]
223 This subsection provides a set of functions allowing to control the CORTEX
224 (NVIC, SYSTICK) functionalities.
225
226
227 @endverbatim
228 * @{
229 */
230
231
232 /**
233 * @brief Gets the priority of an interrupt.
234 * @param IRQn: External interrupt number.
235 * This parameter can be an enumerator of IRQn_Type enumeration
236 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l0xxxx.h))
237 * @retval None
238 */
HAL_NVIC_GetPriority(IRQn_Type IRQn)239 uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn)
240 {
241 /* Get priority for Cortex-M system or device specific interrupts */
242 return NVIC_GetPriority(IRQn);
243 }
244
245 /**
246 * @brief Sets Pending bit of an external interrupt.
247 * @param IRQn: External interrupt number
248 * This parameter can be an enumerator of IRQn_Type enumeration
249 * (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file)
250 * @retval None
251 */
HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)252 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
253 {
254 /* Set interrupt pending */
255 NVIC_SetPendingIRQ(IRQn);
256 }
257
258 /**
259 * @brief Gets Pending Interrupt (reads the pending register in the NVIC
260 * and returns the pending bit for the specified interrupt).
261 * @param IRQn: External interrupt number .
262 * This parameter can be an enumerator of IRQn_Type enumeration
263 * (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file)
264 * @retval status: - 0 Interrupt status is not pending.
265 * - 1 Interrupt status is pending.
266 */
HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)267 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
268 {
269 /* Return 1 if pending else 0 */
270 return NVIC_GetPendingIRQ(IRQn);
271 }
272
273 /**
274 * @brief Clears the pending bit of an external interrupt.
275 * @param IRQn: External interrupt number .
276 * This parameter can be an enumerator of IRQn_Type enumeration
277 * (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file)
278 * @retval None
279 */
HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)280 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
281 {
282 /* Clear pending interrupt */
283 NVIC_ClearPendingIRQ(IRQn);
284 }
285
286
287 /**
288 * @brief Configures the SysTick clock source.
289 * @param CLKSource: specifies the SysTick clock source.
290 * This parameter can be one of the following values:
291 * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
292 * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
293 * @retval None
294 */
HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)295 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
296 {
297 /* Check the parameters */
298 assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
299 if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
300 {
301 SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
302 }
303 else
304 {
305 SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
306 }
307 }
308
309 /**
310 * @brief This function handles SYSTICK interrupt request.
311 * @retval None
312 */
HAL_SYSTICK_IRQHandler(void)313 void HAL_SYSTICK_IRQHandler(void)
314 {
315 HAL_SYSTICK_Callback();
316 }
317
318 /**
319 * @brief SYSTICK callback.
320 * @retval None
321 */
HAL_SYSTICK_Callback(void)322 __weak void HAL_SYSTICK_Callback(void)
323 {
324 /* NOTE : This function Should not be modified, when the callback is needed,
325 the HAL_SYSTICK_Callback could be implemented in the user file
326 */
327 }
328
329 #if (__MPU_PRESENT == 1)
330 /**
331 * @brief Initialize and configure the Region and the memory to be protected.
332 * @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains
333 * the initialization and configuration information.
334 * @retval None
335 */
HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef * MPU_Init)336 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
337 {
338 /* Check the parameters */
339 assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
340 assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
341
342 /* Set the Region number */
343 MPU->RNR = MPU_Init->Number;
344
345 if ((MPU_Init->Enable) == MPU_REGION_ENABLE)
346 {
347 /* Check the parameters */
348 assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
349 assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
350 assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
351 assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
352 assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
353 assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
354 assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
355
356 /* Set the base adsress and set the 4 LSB to 0 */
357 MPU->RBAR = (MPU_Init->BaseAddress) & 0xfffffff0U;
358
359 /* Fill the field RASR */
360 MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
361 ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
362 ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
363 ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
364 ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
365 ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
366 ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
367 ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
368 }
369 else
370 {
371 MPU->RBAR = 0x00U;
372 MPU->RASR = 0x00U;
373 }
374 }
375 #endif /* __MPU_PRESENT */
376
377
378 /**
379 * @}
380 */
381
382 /**
383 * @}
384 */
385
386 /**
387 * @}
388 */
389
390 #endif /* HAL_CORTEX_MODULE_ENABLED */
391 /**
392 * @}
393 */
394
395 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
396
397
