1
2 /**
3 * \file
4 *
5 * \brief Generic Clock Controller related functionality.
6 *
7 * Copyright (C) 2015 Atmel Corporation. All rights reserved.
8 *
9 * \asf_license_start
10 *
11 * \page License
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions are met:
15 *
16 * 1. Redistributions of source code must retain the above copyright notice,
17 * this list of conditions and the following disclaimer.
18 *
19 * 2. Redistributions in binary form must reproduce the above copyright notice,
20 * this list of conditions and the following disclaimer in the documentation
21 * and/or other materials provided with the distribution.
22 *
23 * 3. The name of Atmel may not be used to endorse or promote products derived
24 * from this software without specific prior written permission.
25 *
26 * 4. This software may only be redistributed and used in connection with an
27 * Atmel microcontroller product.
28 *
29 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
30 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
31 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
32 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
33 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
35 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
37 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
38 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
39 * POSSIBILITY OF SUCH DAMAGE.
40 *
41 * \asf_license_stop
42 *
43 */
44
45 #include <hpl_gclk_config.h>
46 #include <hpl_init.h>
47 #include <utils_assert.h>
48
49 /**
50 * \brief Initializes generators
51
52 */
_gclk_init_generators(void)53 void _gclk_init_generators(void)
54 {
55
56 #if CONF_GCLK_GEN_0_GENEN == 1
57 hri_gclk_write_GENCTRL_reg(GCLK,
58 0,
59 GCLK_GENCTRL_DIV(CONF_GCLK_GEN_0_DIV)
60 | (CONF_GCLK_GEN_0_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
61 | (CONF_GCLK_GEN_0_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos)
62 | (CONF_GCLK_GEN_0_OE << GCLK_GENCTRL_OE_Pos)
63 | (CONF_GCLK_GEN_0_OOV << GCLK_GENCTRL_OOV_Pos)
64 | (CONF_GCLK_GEN_0_IDC << GCLK_GENCTRL_IDC_Pos)
65 | (CONF_GCLK_GEN_0_GENEN << GCLK_GENCTRL_GENEN_Pos)
66 | CONF_GCLK_GEN_0_SOURCE);
67 #endif
68 #if CONF_GCLK_GEN_1_GENEN == 1
69 hri_gclk_write_GENCTRL_reg(GCLK,
70 1,
71 GCLK_GENCTRL_DIV(CONF_GCLK_GEN_1_DIV)
72 | (CONF_GCLK_GEN_1_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
73 | (CONF_GCLK_GEN_1_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos)
74 | (CONF_GCLK_GEN_1_OE << GCLK_GENCTRL_OE_Pos)
75 | (CONF_GCLK_GEN_1_OOV << GCLK_GENCTRL_OOV_Pos)
76 | (CONF_GCLK_GEN_1_IDC << GCLK_GENCTRL_IDC_Pos)
77 | (CONF_GCLK_GEN_1_GENEN << GCLK_GENCTRL_GENEN_Pos)
78 | CONF_GCLK_GEN_1_SOURCE);
79 #endif
80 #if CONF_GCLK_GEN_2_GENEN == 1
81 hri_gclk_write_GENCTRL_reg(GCLK,
82 2,
83 GCLK_GENCTRL_DIV(CONF_GCLK_GEN_2_DIV)
84 | (CONF_GCLK_GEN_2_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
85 | (CONF_GCLK_GEN_2_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos)
86 | (CONF_GCLK_GEN_2_OE << GCLK_GENCTRL_OE_Pos)
87 | (CONF_GCLK_GEN_2_OOV << GCLK_GENCTRL_OOV_Pos)
88 | (CONF_GCLK_GEN_2_IDC << GCLK_GENCTRL_IDC_Pos)
89 | (CONF_GCLK_GEN_2_GENEN << GCLK_GENCTRL_GENEN_Pos)
90 | CONF_GCLK_GEN_2_SOURCE);
91 #endif
92 #if CONF_GCLK_GEN_3_GENEN == 1
93 hri_gclk_write_GENCTRL_reg(GCLK,
94 3,
95 GCLK_GENCTRL_DIV(CONF_GCLK_GEN_3_DIV)
96 | (CONF_GCLK_GEN_3_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
97 | (CONF_GCLK_GEN_3_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos)
98 | (CONF_GCLK_GEN_3_OE << GCLK_GENCTRL_OE_Pos)
99 | (CONF_GCLK_GEN_3_OOV << GCLK_GENCTRL_OOV_Pos)
100 | (CONF_GCLK_GEN_3_IDC << GCLK_GENCTRL_IDC_Pos)
101 | (CONF_GCLK_GEN_3_GENEN << GCLK_GENCTRL_GENEN_Pos)
102 | CONF_GCLK_GEN_3_SOURCE);
103 #endif
104 #if CONF_GCLK_GEN_4_GENEN == 1
105 hri_gclk_write_GENCTRL_reg(GCLK,
106 4,
107 GCLK_GENCTRL_DIV(CONF_GCLK_GEN_4_DIV)
108 | (CONF_GCLK_GEN_4_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
109 | (CONF_GCLK_GEN_4_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos)
110 | (CONF_GCLK_GEN_4_OE << GCLK_GENCTRL_OE_Pos)
111 | (CONF_GCLK_GEN_4_OOV << GCLK_GENCTRL_OOV_Pos)
112 | (CONF_GCLK_GEN_4_IDC << GCLK_GENCTRL_IDC_Pos)
113 | (CONF_GCLK_GEN_4_GENEN << GCLK_GENCTRL_GENEN_Pos)
114 | CONF_GCLK_GEN_4_SOURCE);
115 #endif
116 #if CONF_GCLK_GEN_5_GENEN == 1
117 hri_gclk_write_GENCTRL_reg(GCLK,
118 5,
119 GCLK_GENCTRL_DIV(CONF_GCLK_GEN_5_DIV)
120 | (CONF_GCLK_GEN_5_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
121 | (CONF_GCLK_GEN_5_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos)
122 | (CONF_GCLK_GEN_5_OE << GCLK_GENCTRL_OE_Pos)
123 | (CONF_GCLK_GEN_5_OOV << GCLK_GENCTRL_OOV_Pos)
124 | (CONF_GCLK_GEN_5_IDC << GCLK_GENCTRL_IDC_Pos)
125 | (CONF_GCLK_GEN_5_GENEN << GCLK_GENCTRL_GENEN_Pos)
126 | CONF_GCLK_GEN_5_SOURCE);
127 #endif
128 #if CONF_GCLK_GEN_6_GENEN == 1
129 hri_gclk_write_GENCTRL_reg(GCLK,
130 6,
131 GCLK_GENCTRL_DIV(CONF_GCLK_GEN_6_DIV)
132 | (CONF_GCLK_GEN_6_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
133 | (CONF_GCLK_GEN_6_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos)
134 | (CONF_GCLK_GEN_6_OE << GCLK_GENCTRL_OE_Pos)
135 | (CONF_GCLK_GEN_6_OOV << GCLK_GENCTRL_OOV_Pos)
136 | (CONF_GCLK_GEN_6_IDC << GCLK_GENCTRL_IDC_Pos)
137 | (CONF_GCLK_GEN_6_GENEN << GCLK_GENCTRL_GENEN_Pos)
138 | CONF_GCLK_GEN_6_SOURCE);
139 #endif
140 #if CONF_GCLK_GEN_7_GENEN == 1
141 hri_gclk_write_GENCTRL_reg(GCLK,
142 7,
143 GCLK_GENCTRL_DIV(CONF_GCLK_GEN_7_DIV)
144 | (CONF_GCLK_GEN_7_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
145 | (CONF_GCLK_GEN_7_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos)
146 | (CONF_GCLK_GEN_7_OE << GCLK_GENCTRL_OE_Pos)
147 | (CONF_GCLK_GEN_7_OOV << GCLK_GENCTRL_OOV_Pos)
148 | (CONF_GCLK_GEN_7_IDC << GCLK_GENCTRL_IDC_Pos)
149 | (CONF_GCLK_GEN_7_GENEN << GCLK_GENCTRL_GENEN_Pos)
150 | CONF_GCLK_GEN_7_SOURCE);
151 #endif
152 #if CONF_GCLK_GEN_8_GENEN == 1
153 hri_gclk_write_GENCTRL_reg(GCLK,
154 8,
155 GCLK_GENCTRL_DIV(CONF_GCLK_GEN_8_DIV)
156 | (CONF_GCLK_GEN_8_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
157 | (CONF_GCLK_GEN_8_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos)
158 | (CONF_GCLK_GEN_8_OE << GCLK_GENCTRL_OE_Pos)
159 | (CONF_GCLK_GEN_8_OOV << GCLK_GENCTRL_OOV_Pos)
160 | (CONF_GCLK_GEN_8_IDC << GCLK_GENCTRL_IDC_Pos)
161 | (CONF_GCLK_GEN_8_GENEN << GCLK_GENCTRL_GENEN_Pos)
162 | CONF_GCLK_GEN_8_SOURCE);
163 #endif
164 }
165
