1
2 /**
3 * \file
4 *
5 * \brief EIC related functionality implementation.
6 *
7 * Copyright (C) 2015-2017 Atmel Corporation. All rights reserved.
8 *
9 * \asf_license_start
10 *
11 * \page License
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions are met:
15 *
16 * 1. Redistributions of source code must retain the above copyright notice,
17 * this list of conditions and the following disclaimer.
18 *
19 * 2. Redistributions in binary form must reproduce the above copyright notice,
20 * this list of conditions and the following disclaimer in the documentation
21 * and/or other materials provided with the distribution.
22 *
23 * 3. The name of Atmel may not be used to endorse or promote products derived
24 * from this software without specific prior written permission.
25 *
26 * 4. This software may only be redistributed and used in connection with an
27 * Atmel microcontroller product.
28 *
29 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
30 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
31 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
32 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
33 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
35 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
37 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
38 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
39 * POSSIBILITY OF SUCH DAMAGE.
40 *
41 * \asf_license_stop
42 *
43 */
44 #include <compiler.h>
45 #include <hpl_eic_config.h>
46 #include <hpl_ext_irq.h>
47 #include <string.h>
48 #include <utils.h>
49 #include <utils_assert.h>
50
51 #ifdef __MINGW32__
52 #define ffs __builtin_ffs
53 #endif
54 #if defined(__CC_ARM) || defined(__ICCARM__)
55 /* Find the first bit set */
ffs(int v)56 static int ffs(int v)
57 {
58 int i, bit = 1;
59 for (i = 0; i < sizeof(int) * 8; i++) {
60 if (v & bit) {
61 return i + 1;
62 }
63 bit <<= 1;
64 }
65 return 0;
66 }
67 #endif
68
69 /**
70 * \brief Invalid external interrupt and pin numbers
71 */
72 #define INVALID_EXTINT_NUMBER 0xFF
73 #define INVALID_PIN_NUMBER 0xFFFFFFFF
74
75 #ifndef CONFIG_EIC_EXTINT_MAP
76 /** Dummy mapping to pass compiling. */
77 #define CONFIG_EIC_EXTINT_MAP \
78 { \
79 INVALID_EXTINT_NUMBER, INVALID_PIN_NUMBER \
80 }
81 #endif
82
83 #define EXT_IRQ_AMOUNT 4
84
85 /**
86 * \brief EXTINTx and pin number map
87 */
88 struct _eic_map {
89 uint8_t extint;
90 uint32_t pin;
91 };
92
93 /**
94 * \brief PIN and EXTINT map for enabled external interrupts
95 */
96 static const struct _eic_map _map[] = {CONFIG_EIC_EXTINT_MAP};
97
98 /**
99 * \brief The callback to upper layer's interrupt processing routine
100 */
101 static void (*callback)(const uint32_t pin);
102
103 static void _ext_irq_handler(void);
104
105 /**
106 * \brief Initialize external interrupt module
107 */
_ext_irq_init(void (* cb)(const uint32_t pin))108 int32_t _ext_irq_init(void (*cb)(const uint32_t pin))
109 {
110 hri_eic_wait_for_sync(EIC, EIC_SYNCBUSY_SWRST);
111 if (hri_eic_get_CTRLA_ENABLE_bit(EIC)) {
112 return ERR_DENIED;
113 }
114 hri_eic_set_CTRLA_SWRST_bit(EIC);
115 hri_eic_wait_for_sync(EIC, EIC_SYNCBUSY_SWRST);
116
117 hri_eic_write_CTRLA_CKSEL_bit(EIC, CONF_EIC_CKSEL);
118
119 hri_eic_write_NMICTRL_reg(
120 EIC, (CONF_EIC_NMIFILTEN << EIC_NMICTRL_NMIFILTEN_Pos) | EIC_NMICTRL_NMISENSE(CONF_EIC_NMISENSE) | 0);
121
122 hri_eic_write_EVCTRL_reg(EIC,
123 (CONF_EIC_EXTINTEO0 << 0) | (CONF_EIC_EXTINTEO1 << 1) | (CONF_EIC_EXTINTEO2 << 2)
124 | (CONF_EIC_EXTINTEO3 << 3)
125 | (CONF_EIC_EXTINTEO4 << 4)
126 | (CONF_EIC_EXTINTEO5 << 5)
127 | (CONF_EIC_EXTINTEO6 << 6)
128 | (CONF_EIC_EXTINTEO7 << 7)
129 | (CONF_EIC_EXTINTEO8 << 8)
130 | (CONF_EIC_EXTINTEO9 << 9)
131 | (CONF_EIC_EXTINTEO10 << 10)
132 | (CONF_EIC_EXTINTEO11 << 11)
133 | (CONF_EIC_EXTINTEO12 << 12)
134 | (CONF_EIC_EXTINTEO13 << 13)
135 | (CONF_EIC_EXTINTEO14 << 14)
136 | (CONF_EIC_EXTINTEO15 << 15)
137 | 0);
138
139 hri_eic_write_CONFIG_reg(EIC,
140 0,
141 (CONF_EIC_FILTEN0 << EIC_CONFIG_FILTEN0_Pos) | EIC_CONFIG_SENSE0(CONF_EIC_SENSE0)
142 | (CONF_EIC_FILTEN1 << EIC_CONFIG_FILTEN1_Pos)
143 | EIC_CONFIG_SENSE1(CONF_EIC_SENSE1)
144 | (CONF_EIC_FILTEN2 << EIC_CONFIG_FILTEN2_Pos)
145 | EIC_CONFIG_SENSE2(CONF_EIC_SENSE2)
146 | (CONF_EIC_FILTEN3 << EIC_CONFIG_FILTEN3_Pos)
147 | EIC_CONFIG_SENSE3(CONF_EIC_SENSE3)
148 | (CONF_EIC_FILTEN4 << EIC_CONFIG_FILTEN4_Pos)
149 | EIC_CONFIG_SENSE4(CONF_EIC_SENSE4)
150 | (CONF_EIC_FILTEN5 << EIC_CONFIG_FILTEN5_Pos)
151 | EIC_CONFIG_SENSE5(CONF_EIC_SENSE5)
152 | (CONF_EIC_FILTEN6 << EIC_CONFIG_FILTEN6_Pos)
153 | EIC_CONFIG_SENSE6(CONF_EIC_SENSE6)
154 | (CONF_EIC_FILTEN7 << EIC_CONFIG_FILTEN7_Pos)
155 | EIC_CONFIG_SENSE7(CONF_EIC_SENSE7)
156 | 0);
157
158 hri_eic_write_CONFIG_reg(EIC,
159 1,
160 (CONF_EIC_FILTEN8 << EIC_CONFIG_FILTEN0_Pos) | EIC_CONFIG_SENSE0(CONF_EIC_SENSE8)
161 | (CONF_EIC_FILTEN9 << EIC_CONFIG_FILTEN1_Pos)
162 | EIC_CONFIG_SENSE1(CONF_EIC_SENSE9)
163 | (CONF_EIC_FILTEN10 << EIC_CONFIG_FILTEN2_Pos)
164 | EIC_CONFIG_SENSE2(CONF_EIC_SENSE10)
165 | (CONF_EIC_FILTEN11 << EIC_CONFIG_FILTEN3_Pos)
166 | EIC_CONFIG_SENSE3(CONF_EIC_SENSE11)
167 | (CONF_EIC_FILTEN12 << EIC_CONFIG_FILTEN4_Pos)
168 | EIC_CONFIG_SENSE4(CONF_EIC_SENSE12)
169 | (CONF_EIC_FILTEN13 << EIC_CONFIG_FILTEN5_Pos)
170 | EIC_CONFIG_SENSE5(CONF_EIC_SENSE13)
171 | (CONF_EIC_FILTEN14 << EIC_CONFIG_FILTEN6_Pos)
172 | EIC_CONFIG_SENSE6(CONF_EIC_SENSE14)
173 | (CONF_EIC_FILTEN15 << EIC_CONFIG_FILTEN7_Pos)
174 | EIC_CONFIG_SENSE7(CONF_EIC_SENSE15)
175 | 0);
176
177 hri_eic_set_CTRLA_ENABLE_bit(EIC);
178 NVIC_DisableIRQ(EIC_IRQn);
179 NVIC_ClearPendingIRQ(EIC_IRQn);
180 NVIC_EnableIRQ(EIC_IRQn);
181
182 callback = cb;
183
184 return ERR_NONE;
185 }
186
187 /**
188 * \brief De-initialize external interrupt module
189 */
_ext_irq_deinit(void)190 int32_t _ext_irq_deinit(void)
191 {
192 NVIC_DisableIRQ(EIC_IRQn);
193 callback = NULL;
194
195 hri_eic_clear_CTRLA_ENABLE_bit(EIC);
196 hri_eic_set_CTRLA_SWRST_bit(EIC);
197
198 return ERR_NONE;
199 }
200
201 /**
202 * \brief Enable / disable external irq
203 */
_ext_irq_enable(const uint32_t pin,const bool enable)204 int32_t _ext_irq_enable(const uint32_t pin, const bool enable)
205 {
206 uint8_t extint = INVALID_EXTINT_NUMBER;
207 uint8_t i = 0;
208
209 for (; i < ARRAY_SIZE(_map); i++) {
210 if (_map[i].pin == pin) {
211 extint = _map[i].extint;
212 break;
213 }
214 }
215 if (INVALID_EXTINT_NUMBER == extint) {
216 return -1;
217 }
218
219 if (enable) {
220 hri_eic_set_INTEN_reg(EIC, 1ul << extint);
221 } else {
222 hri_eic_clear_INTEN_reg(EIC, 1ul << extint);
223 hri_eic_clear_INTFLAG_reg(EIC, 1ul << extint);
224 }
225
226 return ERR_NONE;
227 }
228
229 /**
230 * \brief Inter EIC interrupt handler
231 */
_ext_irq_handler(void)232 static void _ext_irq_handler(void)
233 {
234 volatile uint32_t flags = hri_eic_read_INTFLAG_reg(EIC);
235 int8_t pos;
236 uint32_t pin = INVALID_PIN_NUMBER;
237
238 hri_eic_clear_INTFLAG_reg(EIC, flags);
239
240 ASSERT(callback);
241
242 while (flags) {
243 pos = ffs(flags) - 1;
244 while (-1 != pos) {
245 uint8_t lower = 0, middle, upper = EXT_IRQ_AMOUNT;
246
247 while (upper >= lower) {
248 middle = (upper + lower) >> 1;
249 if (_map[middle].extint == pos) {
250 pin = _map[middle].pin;
251 break;
252 }
253 if (_map[middle].extint < pos) {
254 lower = middle + 1;
255 } else {
256 upper = middle - 1;
257 }
258 }
259
260 if (INVALID_PIN_NUMBER != pin) {
261 callback(pin);
262 }
263 flags &= ~(1ul << pos);
264 pos = ffs(flags) - 1;
265 }
266 flags = hri_eic_read_INTFLAG_reg(EIC);
267 hri_eic_clear_INTFLAG_reg(EIC, flags);
268 }
269 }
270
271 /**
272 * \brief EIC interrupt handler
273 */
EIC_Handler(void)274 void EIC_Handler(void)
275 {
276 _ext_irq_handler();
277 }
278
