1 /*
2  * Copyright (c) 2019-2024, Arm Limited. All rights reserved.
3  * Copyright (c) 2019-2024 Cypress Semiconductor Corporation (an Infineon company)
4  * or an affiliate of Cypress Semiconductor Corporation. All rights reserved.
5  *
6  * SPDX-License-Identifier: BSD-3-Clause
7  */
8 
9 /* -------------------------------------- Includes ----------------------------------- */
10 #include "tfm_hal_device_header.h"
11 #include "cmsis_compiler.h"
12 
13 #include "cy_device.h"
14 #include "cy_device_headers.h"
15 #include "cy_ipc_drv.h"
16 #include "cy_sysint.h"
17 
18 #include "spe_ipc_config.h"
19 #include "tfm_hal_mailbox.h"
20 #include "platform_multicore.h"
21 
22 /* -------------------------------------- HAL API ------------------------------------ */
23 
tfm_mailbox_hal_notify_peer(void)24 int32_t tfm_mailbox_hal_notify_peer(void)
25 {
26     cy_en_ipcdrv_status_t status;
27 
28     status = Cy_IPC_Drv_SendMsgWord(Cy_IPC_Drv_GetIpcBaseAddress(IPC_TX_CHAN),
29                                     IPC_TX_NOTIFY_MASK,
30                                     PSA_CLIENT_CALL_REPLY_MAGIC);
31 
32     if (status == CY_IPC_DRV_SUCCESS) {
33         return MAILBOX_SUCCESS;
34     } else {
35         return MAILBOX_CHAN_BUSY;
36     }
37 }
38 
mailbox_ipc_config(void)39 static void mailbox_ipc_config(void)
40 {
41     Cy_SysInt_SetIntSource(PSA_CLIENT_CALL_NVIC_IRQn, PSA_CLIENT_CALL_IPC_INTR);
42 
43     NVIC_SetPriority(PSA_CLIENT_CALL_NVIC_IRQn, PSA_CLIENT_CALL_IRQ_PRIORITY);
44 
45     NVIC_EnableIRQ(PSA_CLIENT_CALL_NVIC_IRQn);
46 }
47 
tfm_mailbox_hal_init(struct secure_mailbox_queue_t * s_queue)48 int32_t tfm_mailbox_hal_init(struct secure_mailbox_queue_t *s_queue)
49 {
50     struct mailbox_init_t *ns_init = NULL;
51 
52     /* Inform NSPE that NSPE mailbox initialization can start */
53     platform_mailbox_send_msg_data(NS_MAILBOX_INIT_ENABLE);
54 
55     platform_mailbox_wait_for_notify();
56 
57     /* Receive the address of NSPE mailbox queue */
58     platform_mailbox_fetch_msg_ptr((void **)&ns_init);
59 
60     /*
61      * FIXME
62      * Necessary sanity check of the address of NPSE mailbox queue should
63      * be implemented there.
64      */
65     if (ns_init->slot_count > NUM_MAILBOX_QUEUE_SLOT) {
66         return MAILBOX_INIT_ERROR;
67     }
68 
69     s_queue->ns_status = ns_init->status;
70     s_queue->ns_slot_count = ns_init->slot_count;
71     s_queue->ns_slots = ns_init->slots;
72 
73     mailbox_ipc_config();
74 
75     /* Inform NSPE that SPE mailbox service is ready */
76     platform_mailbox_send_msg_data(S_MAILBOX_READY);
77 
78     return MAILBOX_SUCCESS;
79 }
80 
tfm_mailbox_hal_enter_critical(void)81 void tfm_mailbox_hal_enter_critical(void)
82 {
83     IPC_STRUCT_Type* ipc_struct =
84         Cy_IPC_Drv_GetIpcBaseAddress(IPC_PSA_MAILBOX_LOCK_CHAN);
85     while(CY_IPC_DRV_SUCCESS != Cy_IPC_Drv_LockAcquire (ipc_struct))
86     {
87     }
88 }
89 
tfm_mailbox_hal_exit_critical(void)90 void tfm_mailbox_hal_exit_critical(void)
91 {
92     IPC_STRUCT_Type* ipc_struct =
93         Cy_IPC_Drv_GetIpcBaseAddress(IPC_PSA_MAILBOX_LOCK_CHAN);
94     Cy_IPC_Drv_LockRelease(ipc_struct, CY_IPC_NO_NOTIFICATION);
95 }
96