1 /**
2 ******************************************************************************
3 * @file stm32u5xx_hal_rcc_ex.c
4 * @author MCD Application Team
5 * @brief Extended RCC HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities RCC extended peripheral:
8 * + Extended Peripheral Control functions
9 * + Extended Clock management functions
10 * + Extended Clock Recovery System Control functions
11 *
12 ******************************************************************************
13 * @attention
14 *
15 * Copyright (c) 2021 STMicroelectronics.
16 * All rights reserved.
17 *
18 * This software component is licensed by ST under BSD 3-Clause license,
19 * the "License"; You may not use this file except in compliance with the
20 * License. You may obtain a copy of the License at:
21 * opensource.org/licenses/BSD-3-Clause
22 *
23 ******************************************************************************
24 */
25
26 /* Includes ------------------------------------------------------------------*/
27 #include "stm32u5xx_hal.h"
28
29 /** @addtogroup STM32U5xx_HAL_Driver
30 * @{
31 */
32
33 /** @defgroup RCCEx RCCEx
34 * @brief RCC Extended HAL module driver
35 * @{
36 */
37
38 #ifdef HAL_RCC_MODULE_ENABLED
39
40 /* Private typedef -----------------------------------------------------------*/
41 /* Private defines -----------------------------------------------------------*/
42 /** @defgroup RCCEx_Private_Constants RCCEx Private Constants
43 * @{
44 */
45 #define PLL1_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */
46 #define PLL2_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */
47 #define PLL3_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */
48
49 #define LSCO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
50
51 #define LSCO_GPIO_PORT GPIOA
52
53 #define LSCO_PIN GPIO_PIN_2
54
55 /**
56 * @}
57 */
58
59 /* Private macros ------------------------------------------------------------*/
60 /** @addtogroup RCCEx_Private_Macros
61 * @{
62 */
63
64 #define IS_RCC_PLL2CLOCKOUT_VALUE(VALUE) ((0x00010000U <= (VALUE)) && ((VALUE) <= 0x00070000U))
65
66 #define IS_RCC_PLL3CLOCKOUT_VALUE(VALUE) ((0x00010000U <= (VALUE)) && ((VALUE) <= 0x00070000U))
67
68 #define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \
69 ((__SOURCE__) == RCC_LSCOSOURCE_LSE))
70
71 #define IS_RCC_MSIPLLMODE_SELECT(__SOURCE__) (((__SOURCE__) == RCC_MSISPLL_MODE_SEL) || \
72 ((__SOURCE__) == RCC_MSIKPLL_MODE_SEL))
73
74 #define IS_RCC_PERIPHCLOCK(__SELECTION__) ((((__SELECTION__) & RCC_PERIPHCLOCK_ALL) != 0x00u) && \
75 (((__SELECTION__) & ~RCC_PERIPHCLOCK_ALL) == 0x00u))
76
77 #define IS_RCC_USART1CLKSOURCE(__SOURCE__) \
78 (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \
79 ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \
80 ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI) || \
81 ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE))
82
83 #define IS_RCC_USART2CLKSOURCE(__SOURCE__) \
84 (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \
85 ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \
86 ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI) || \
87 ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE))
88
89 #define IS_RCC_USART3CLKSOURCE(__SOURCE__) \
90 (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \
91 ((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \
92 ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI) || \
93 ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE))
94
95 #define IS_RCC_UART4CLKSOURCE(__SOURCE__) \
96 (((__SOURCE__) == RCC_UART4CLKSOURCE_PCLK1) || \
97 ((__SOURCE__) == RCC_UART4CLKSOURCE_SYSCLK) || \
98 ((__SOURCE__) == RCC_UART4CLKSOURCE_HSI) || \
99 ((__SOURCE__) == RCC_UART4CLKSOURCE_LSE))
100
101 #define IS_RCC_UART5CLKSOURCE(__SOURCE__) \
102 (((__SOURCE__) == RCC_UART5CLKSOURCE_PCLK1) || \
103 ((__SOURCE__) == RCC_UART5CLKSOURCE_SYSCLK) || \
104 ((__SOURCE__) == RCC_UART5CLKSOURCE_HSI) || \
105 ((__SOURCE__) == RCC_UART5CLKSOURCE_LSE))
106
107 #define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) \
108 (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK3) || \
109 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \
110 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI) || \
111 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \
112 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_MSIK))
113
114 #define IS_RCC_I2C1CLKSOURCE(__SOURCE__) \
115 (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \
116 ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \
117 ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI)|| \
118 ((__SOURCE__) == RCC_I2C1CLKSOURCE_MSIK))
119
120 #define IS_RCC_I2C2CLKSOURCE(__SOURCE__) \
121 (((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \
122 ((__SOURCE__) == RCC_I2C2CLKSOURCE_SYSCLK)|| \
123 ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI)|| \
124 ((__SOURCE__) == RCC_I2C2CLKSOURCE_MSIK))
125
126 #define IS_RCC_I2C3CLKSOURCE(__SOURCE__) \
127 (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK3) || \
128 ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK ) || \
129 ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI ) || \
130 ((__SOURCE__) == RCC_I2C3CLKSOURCE_MSIK))
131
132 #define IS_RCC_I2C4CLKSOURCE(__SOURCE__) \
133 (((__SOURCE__) == RCC_I2C4CLKSOURCE_PCLK1) || \
134 ((__SOURCE__) == RCC_I2C4CLKSOURCE_SYSCLK)|| \
135 ((__SOURCE__) == RCC_I2C4CLKSOURCE_HSI)|| \
136 ((__SOURCE__) == RCC_I2C4CLKSOURCE_MSIK))
137
138 #define IS_RCC_SAI1CLK(__SOURCE__) \
139 (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL2) || \
140 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL3) || \
141 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL1) || \
142 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN) || \
143 ((__SOURCE__) == RCC_SAI1CLKSOURCE_HSI))
144
145 #define IS_RCC_SAI2CLK(__SOURCE__) \
146 (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL2) || \
147 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL3) || \
148 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL1) || \
149 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN) || \
150 ((__SOURCE__) == RCC_SAI2CLKSOURCE_HSI))
151
152 #define IS_RCC_LPTIM1CLK(__SOURCE__) \
153 (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_MSIK) || \
154 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \
155 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI) || \
156 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE))
157
158 #define IS_RCC_LPTIM2CLK(__SOURCE__) \
159 (((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK1) || \
160 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI) || \
161 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_HSI) || \
162 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE))
163
164 #define IS_RCC_LPTIM34CLK(__SOURCE__) \
165 (((__SOURCE__) == RCC_LPTIM34CLKSOURCE_MSIK) || \
166 ((__SOURCE__) == RCC_LPTIM34CLKSOURCE_LSI) || \
167 ((__SOURCE__) == RCC_LPTIM34CLKSOURCE_HSI) || \
168 ((__SOURCE__) == RCC_LPTIM34CLKSOURCE_LSE))
169
170 #define IS_RCC_FDCAN1CLK(__SOURCE__) \
171 (((__SOURCE__) == RCC_FDCAN1CLKSOURCE_HSE) || \
172 ((__SOURCE__) == RCC_FDCAN1CLKSOURCE_PLL1) || \
173 ((__SOURCE__) == RCC_FDCAN1CLKSOURCE_PLL2))
174
175 #define IS_RCC_SDMMCCLKSOURCE(__SOURCE__) \
176 (((__SOURCE__) == RCC_SDMMCCLKSOURCE_CLK48) || \
177 ((__SOURCE__) == RCC_SDMMCCLKSOURCE_PLL1))
178
179 #define IS_RCC_RNGCLKSOURCE(__SOURCE__) \
180 (((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48) || \
181 ((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48_DIV2) || \
182 ((__SOURCE__) == RCC_RNGCLKSOURCE_HSI))
183
184 #define IS_RCC_SAESCLKSOURCE(__SOURCE__) \
185 (((__SOURCE__) == RCC_SAESCLKSOURCE_SHSI) || \
186 ((__SOURCE__) == RCC_SAESCLKSOURCE_SHSI_DIV2))
187
188 #define IS_RCC_ADCDACCLKSOURCE(__SOURCE__) \
189 (((__SOURCE__) == RCC_ADCDACCLKSOURCE_HCLK) || \
190 ((__SOURCE__) == RCC_ADCDACCLKSOURCE_SYSCLK) || \
191 ((__SOURCE__) == RCC_ADCDACCLKSOURCE_PLL2) || \
192 ((__SOURCE__) == RCC_ADCDACCLKSOURCE_HSE) || \
193 ((__SOURCE__) == RCC_ADCDACCLKSOURCE_HSI) || \
194 ((__SOURCE__) == RCC_ADCDACCLKSOURCE_MSIK))
195
196 #define IS_RCC_MDF1CLKSOURCE(__SOURCE__) \
197 (((__SOURCE__) == RCC_MDF1CLKSOURCE_HCLK) || \
198 ((__SOURCE__) == RCC_MDF1CLKSOURCE_PLL1) || \
199 ((__SOURCE__) == RCC_MDF1CLKSOURCE_PLL3) || \
200 ((__SOURCE__) == RCC_MDF1CLKSOURCE_PIN) || \
201 ((__SOURCE__) == RCC_MDF1CLKSOURCE_MSIK))
202
203 #define IS_RCC_ADF1CLKSOURCE(__SOURCE__) \
204 (((__SOURCE__) == RCC_ADF1CLKSOURCE_HCLK) || \
205 ((__SOURCE__) == RCC_ADF1CLKSOURCE_PLL1) || \
206 ((__SOURCE__) == RCC_ADF1CLKSOURCE_PLL3) || \
207 ((__SOURCE__) == RCC_ADF1CLKSOURCE_PIN) || \
208 ((__SOURCE__) == RCC_ADF1CLKSOURCE_MSIK))
209
210 #define IS_RCC_OSPICLKSOURCE(__SOURCE__) \
211 (((__SOURCE__) == RCC_OSPICLKSOURCE_SYSCLK) || \
212 ((__SOURCE__) == RCC_OSPICLKSOURCE_MSIK) || \
213 ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL1) ||\
214 ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL2))
215
216 #define IS_RCC_CLK48CLKSOURCE(__SOURCE__)\
217 (((__SOURCE__) == RCC_CLK48CLKSOURCE_HSI48)|| \
218 ((__SOURCE__) == RCC_CLK48CLKSOURCE_PLL2) || \
219 ((__SOURCE__) == RCC_CLK48CLKSOURCE_PLL1) || \
220 ((__SOURCE__) == RCC_CLK48CLKSOURCE_MSIK))
221
222 #define IS_RCC_SPI1CLKSOURCE(__SOURCE__) \
223 (((__SOURCE__) == RCC_SPI1CLKSOURCE_PCLK2) || \
224 ((__SOURCE__) == RCC_SPI1CLKSOURCE_SYSCLK) || \
225 ((__SOURCE__) == RCC_SPI1CLKSOURCE_HSI)|| \
226 ((__SOURCE__) == RCC_SPI1CLKSOURCE_MSIK))
227
228 #define IS_RCC_SPI2CLKSOURCE(__SOURCE__) \
229 (((__SOURCE__) == RCC_SPI2CLKSOURCE_PCLK1) || \
230 ((__SOURCE__) == RCC_SPI2CLKSOURCE_SYSCLK) || \
231 ((__SOURCE__) == RCC_SPI2CLKSOURCE_HSI)|| \
232 ((__SOURCE__) == RCC_SPI2CLKSOURCE_MSIK))
233
234 #define IS_RCC_SPI3CLKSOURCE(__SOURCE__) \
235 (((__SOURCE__) == RCC_SPI3CLKSOURCE_PCLK3) || \
236 ((__SOURCE__) == RCC_SPI3CLKSOURCE_SYSCLK) || \
237 ((__SOURCE__) == RCC_SPI3CLKSOURCE_HSI)|| \
238 ((__SOURCE__) == RCC_SPI3CLKSOURCE_MSIK))
239
240 #define IS_RCC_DAC1CLKSOURCE(__SOURCE__) \
241 (((__SOURCE__) == RCC_DAC1CLKSOURCE_LSE) || \
242 ((__SOURCE__) == RCC_DAC1CLKSOURCE_LSI))
243
244 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \
245 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
246 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
247 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32))
248 #if defined(CRS)
249
250 #define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \
251 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \
252 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB))
253
254 #define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) || \
255 ((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \
256 ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \
257 ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128))
258
259 #define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \
260 ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING))
261
262 #define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU))
263
264 #define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU))
265
266 #define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU))
267
268 #define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \
269 ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN))
270
271 #endif /* CRS */
272
273 /* Private variables ---------------------------------------------------------*/
274 /* Private function prototypes -----------------------------------------------*/
275 /** @defgroup RCCEx_Private_Functions RCCEx Private Functions
276 * @{
277 */
278 static HAL_StatusTypeDef RCCEx_PLLSource_Enable(uint32_t PllSource);
279 static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *Pll2);
280 static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *Pll3);
281 /**
282 * @}
283 */
284
285 /* Exported functions --------------------------------------------------------*/
286
287 /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
288 * @{
289 */
290
291 /** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
292 * @brief Extended Peripheral Control functions
293 *
294 @verbatim
295 ===============================================================================
296 ##### Extended Peripheral Control functions #####
297 ===============================================================================
298 [..]
299 This subsection provides a set of functions allowing to control the RCC Clocks
300 frequencies.
301 [..]
302 (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
303 select the RTC clock source; in this case the Backup domain will be reset in
304 order to modify the RTC Clock source, as consequence RTC registers (including
305 the backup registers) are set to their reset values.
306
307 @endverbatim
308 * @{
309 */
310 /**
311 * @brief Initialize the RCC extended peripherals clocks according to the specified
312 * parameters in the RCC_PeriphCLKInitTypeDef.
313 * @param pPeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
314 * contains a field PeriphClockSelection which can be a combination of the following values:
315 * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock
316 * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
317 * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock
318 * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock
319 * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock
320 * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock
321 * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock
322 * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
323 * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
324 * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock
325 * @arg @ref RCC_PERIPHCLK_LPTIM34 LPTIM34 peripheral clock
326 * @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock
327 * @arg @ref RCC_PERIPHCLK_SAES SAES peripheral clock
328 * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock
329 * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock
330 * @arg @ref RCC_PERIPHCLK_ADCDAC ADC1,ADC4,DAC peripheral clock
331 * @arg @ref RCC_PERIPHCLK_MDF1 MDF1 peripheral clock
332 * @arg @ref RCC_PERIPHCLK_ADF1 ADF1 peripheral clock
333 * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
334 * @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock
335 * @arg @ref RCC_PERIPHCLK_CLK48 CLK48 peripheral clock
336 * @arg @ref RCC_PERIPHCLK_SDMMC SDMMC peripheral clock
337 * @arg @ref RCC_PERIPHCLK_SPI1 SPI1 peripheral clock
338 * @arg @ref RCC_PERIPHCLK_SPI2 SPI2 peripheral clock
339 * @arg @ref RCC_PERIPHCLK_SPI3 SPI3 peripheral clock
340 * @arg @ref RCC_PERIPHCLK_OSPI OSPI peripheral clock
341 * @arg @ref RCC_PERIPHCLK_FDCAN1 FDCAN1 peripheral clock
342 * @arg @ref RCC_PERIPHCLK_DAC1 DAC1 peripheral clock
343 *
344 * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
345 * the RTC clock source: in this case the access to Backup domain is enabled.
346 *
347 * @retval HAL status
348 */
HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef * pPeriphClkInit)349 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphClkInit)
350 {
351 uint32_t tmpregister;
352 uint32_t tickstart;
353 HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */
354 HAL_StatusTypeDef status = HAL_OK; /* Final status */
355
356 /* Check the parameters */
357 assert_param(IS_RCC_PERIPHCLOCK(pPeriphClkInit->PeriphClockSelection));
358
359 /*-------------------------- USART1 clock source configuration -------------------*/
360 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
361 {
362 /* Check the parameters */
363 assert_param(IS_RCC_USART1CLKSOURCE(pPeriphClkInit->Usart1ClockSelection));
364
365 /* Configure the USART1 clock source */
366 __HAL_RCC_USART1_CONFIG(pPeriphClkInit->Usart1ClockSelection);
367 }
368
369 /*-------------------------- USART2 clock source configuration -------------------*/
370 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
371 {
372 /* Check the parameters */
373 assert_param(IS_RCC_USART2CLKSOURCE(pPeriphClkInit->Usart2ClockSelection));
374
375 /* Configure the USART2 clock source */
376 __HAL_RCC_USART2_CONFIG(pPeriphClkInit->Usart2ClockSelection);
377 }
378
379 /*-------------------------- USART3 clock source configuration -------------------*/
380 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
381 {
382 /* Check the parameters */
383 assert_param(IS_RCC_USART3CLKSOURCE(pPeriphClkInit->Usart3ClockSelection));
384
385 /* Configure the USART3 clock source */
386 __HAL_RCC_USART3_CONFIG(pPeriphClkInit->Usart3ClockSelection);
387 }
388
389 /*-------------------------- UART4 clock source configuration --------------------*/
390 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
391 {
392 /* Check the parameters */
393 assert_param(IS_RCC_UART4CLKSOURCE(pPeriphClkInit->Uart4ClockSelection));
394
395 /* Configure the UART4 clock source */
396 __HAL_RCC_UART4_CONFIG(pPeriphClkInit->Uart4ClockSelection);
397 }
398
399 /*-------------------------- UART5 clock source configuration --------------------*/
400 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
401 {
402 /* Check the parameters */
403 assert_param(IS_RCC_UART5CLKSOURCE(pPeriphClkInit->Uart5ClockSelection));
404
405 /* Configure the UART5 clock source */
406 __HAL_RCC_UART5_CONFIG(pPeriphClkInit->Uart5ClockSelection);
407 }
408
409 /*-------------------------- LPUART1 clock source configuration ------------------*/
410 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
411 {
412 /* Check the parameters */
413 assert_param(IS_RCC_LPUART1CLKSOURCE(pPeriphClkInit->Lpuart1ClockSelection));
414
415 /* Configure the LPUART1 clock source */
416 __HAL_RCC_LPUART1_CONFIG(pPeriphClkInit->Lpuart1ClockSelection);
417 }
418
419 /*-------------------------- I2C1 clock source configuration ---------------------*/
420 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
421 {
422 /* Check the parameters */
423 assert_param(IS_RCC_I2C1CLKSOURCE(pPeriphClkInit->I2c1ClockSelection));
424
425 /* Configure the I2C1 clock source */
426 __HAL_RCC_I2C1_CONFIG(pPeriphClkInit->I2c1ClockSelection);
427 }
428
429 /*-------------------------- I2C2 clock source configuration ---------------------*/
430 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
431 {
432 /* Check the parameters */
433 assert_param(IS_RCC_I2C2CLKSOURCE(pPeriphClkInit->I2c2ClockSelection));
434
435 /* Configure the I2C2 clock source */
436 __HAL_RCC_I2C2_CONFIG(pPeriphClkInit->I2c2ClockSelection);
437 }
438
439 /*-------------------------- I2C3 clock source configuration ---------------------*/
440 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
441 {
442 /* Check the parameters */
443 assert_param(IS_RCC_I2C3CLKSOURCE(pPeriphClkInit->I2c3ClockSelection));
444
445 /* Configure the I2C3 clock source */
446 __HAL_RCC_I2C3_CONFIG(pPeriphClkInit->I2c3ClockSelection);
447 }
448
449 /*-------------------------- I2C4 clock source configuration ---------------------*/
450 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
451 {
452 /* Check the parameters */
453 assert_param(IS_RCC_I2C4CLKSOURCE(pPeriphClkInit->I2c4ClockSelection));
454
455 /* Configure the I2C4 clock source */
456 __HAL_RCC_I2C4_CONFIG(pPeriphClkInit->I2c4ClockSelection);
457 }
458
459 /*-------------------------- LPTIM1 clock source configuration -------------------*/
460 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1))
461 {
462 assert_param(IS_RCC_LPTIM1CLK(pPeriphClkInit->Lptim1ClockSelection));
463 __HAL_RCC_LPTIM1_CONFIG(pPeriphClkInit->Lptim1ClockSelection);
464 }
465
466 /*-------------------------- LPTIM2 clock source configuration -------------------*/
467 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2))
468 {
469 assert_param(IS_RCC_LPTIM2CLK(pPeriphClkInit->Lptim2ClockSelection));
470 __HAL_RCC_LPTIM2_CONFIG(pPeriphClkInit->Lptim2ClockSelection);
471 }
472
473 /*-------------------------- LPTIM34 clock source configuration -------------------*/
474 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM34) == (RCC_PERIPHCLK_LPTIM34))
475 {
476 assert_param(IS_RCC_LPTIM34CLK(pPeriphClkInit->Lptim34ClockSelection));
477 __HAL_RCC_LPTIM34_CONFIG(pPeriphClkInit->Lptim34ClockSelection);
478 }
479
480 /*-------------------------- SAI1 clock source configuration ---------------------*/
481 if ((((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1))
482 {
483 /* Check the parameters */
484 assert_param(IS_RCC_SAI1CLK(pPeriphClkInit->Sai1ClockSelection));
485
486 switch (pPeriphClkInit->Sai1ClockSelection)
487 {
488 case RCC_SAI1CLKSOURCE_PLL1: /* PLL is used as clock source for SAI1*/
489 /* Enable SAI Clock output generated from System PLL */
490 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP);
491 /* SAI1 clock source config set later after clock selection check */
492 break;
493
494 case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI1*/
495 /* PLL2 P input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */
496 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
497 /* SAI1 clock source config set later after clock selection check */
498 break;
499
500 case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI1*/
501 /* PLL3 P input clock, parameters M, N & P configuration clock output (PLL3ClockOut) */
502 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
503 /* SAI1 clock source config set later after clock selection check */
504 break;
505
506 case RCC_SAI1CLKSOURCE_PIN: /* External clock is used as source of SAI1 clock*/
507 /* SAI1 clock source configuration done later after clock selection check */
508 break;
509
510 case RCC_SAI1CLKSOURCE_HSI: /* HSI is used as source of SAI1 clock*/
511 /* SAI1 clock source config set later after clock selection check */
512 break;
513
514 default:
515 ret = HAL_ERROR;
516 break;
517 }
518
519 if (ret == HAL_OK)
520 {
521 /* Set the source of SAI1 clock*/
522 __HAL_RCC_SAI1_CONFIG(pPeriphClkInit->Sai1ClockSelection);
523 }
524 else
525 {
526 /* set overall return value */
527 status = ret;
528 }
529 }
530
531 /*-------------------------- SAI2 clock source configuration ---------------------*/
532 if ((((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2))
533 {
534 /* Check the parameters */
535 assert_param(IS_RCC_SAI2CLK(pPeriphClkInit->Sai2ClockSelection));
536
537 switch (pPeriphClkInit->Sai2ClockSelection)
538 {
539 case RCC_SAI2CLKSOURCE_PLL1: /* PLL is used as clock source for SAI2*/
540 /* Enable SAI Clock output generated from System PLL */
541 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP);
542 /* SAI2 clock source config set later after clock selection check */
543 break;
544
545 case RCC_SAI2CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/
546 /* PLL2 P input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */
547 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
548 /* SAI2 clock source config set later after clock selection check */
549 break;
550
551 case RCC_SAI2CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2*/
552 /* PLL3 P input clock, parameters M, N & P configuration and clock output (PLL3ClockOut) */
553 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
554 /* SAI2 clock source config set later after clock selection check */
555 break;
556
557 case RCC_SAI2CLKSOURCE_PIN: /* External clock is used as source of SAI2 clock*/
558 /* SAI2 clock source configuration done later after clock selection check */
559 break;
560 case RCC_SAI2CLKSOURCE_HSI: /* HSI is used as source of SAI2 clock*/
561 /* SAI2 clock source config set later after clock selection check */
562 break;
563
564 default:
565 ret = HAL_ERROR;
566 break;
567 }
568
569 if (ret == HAL_OK)
570 {
571 /* Set the source of SAI2 clock*/
572 __HAL_RCC_SAI2_CONFIG(pPeriphClkInit->Sai2ClockSelection);
573 }
574 else
575 {
576 /* set overall return value */
577 status = ret;
578 }
579 }
580
581 /*-------------------------- ADCDAC clock source configuration ----------------------*/
582 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADCDAC) == RCC_PERIPHCLK_ADCDAC)
583 {
584 /* Check the parameters */
585 assert_param(IS_RCC_ADCDACCLKSOURCE(pPeriphClkInit->AdcDacClockSelection));
586
587 switch (pPeriphClkInit->AdcDacClockSelection)
588 {
589 case RCC_ADCDACCLKSOURCE_PLL2:
590 /* PLL2 input clock, parameters M, N,P, & R configuration and clock output (PLL2ClockOut) */
591 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
592 break;
593
594 case RCC_ADCDACCLKSOURCE_SYSCLK:
595 case RCC_ADCDACCLKSOURCE_HCLK:
596 case RCC_ADCDACCLKSOURCE_HSE:
597 case RCC_ADCDACCLKSOURCE_HSI:
598 case RCC_ADCDACCLKSOURCE_MSIK:
599 break;
600 default:
601 ret = HAL_ERROR;
602 break;
603 }
604
605 if (ret == HAL_OK)
606 {
607 /* Configure the ADC1 interface clock source */
608 __HAL_RCC_ADCDAC_CONFIG(pPeriphClkInit->AdcDacClockSelection);
609 }
610 else
611 {
612 /* set overall return value */
613 status = ret;
614 }
615 }
616
617 /*-------------------------- MDF1 clock source configuration -------------------*/
618 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_MDF1) == RCC_PERIPHCLK_MDF1)
619 {
620 /* Check the parameters */
621 assert_param(IS_RCC_MDF1CLKSOURCE(pPeriphClkInit->Mdf1ClockSelection));
622
623 switch (pPeriphClkInit->Mdf1ClockSelection)
624 {
625 case RCC_MDF1CLKSOURCE_PLL1:
626 /* Enable PLL1 Clock output generated from System PLL */
627 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP);
628 break;
629 case RCC_MDF1CLKSOURCE_PLL3:
630 /* PLL3 Q input clock, parameters M, N & Q configuration and clock output (PLL3ClockOut) */
631 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
632 break;
633 case RCC_MDF1CLKSOURCE_HCLK:
634 break;
635 case RCC_MDF1CLKSOURCE_PIN:
636 break;
637 case RCC_MDF1CLKSOURCE_MSIK:
638 break;
639 default:
640 ret = HAL_ERROR;
641 break;
642 }
643
644 if (ret == HAL_OK)
645 {
646 /* Configure the MDF1 interface clock source */
647 __HAL_RCC_MDF1_CONFIG(pPeriphClkInit->Mdf1ClockSelection);
648 }
649 else
650 {
651 /* set overall return value */
652 status = ret;
653 }
654 }
655
656 /*-------------------------- ADF1 clock source configuration -------------------*/
657 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADF1) == RCC_PERIPHCLK_ADF1)
658 {
659 /* Check the parameters */
660 assert_param(IS_RCC_ADF1CLKSOURCE(pPeriphClkInit->Adf1ClockSelection));
661
662 switch (pPeriphClkInit->Adf1ClockSelection)
663 {
664 case RCC_ADF1CLKSOURCE_PLL1:
665 /* Enable PLL1 Clock output generated from System PLL */
666 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP);
667 break;
668 case RCC_ADF1CLKSOURCE_PLL3:
669 /* PLL3 Q input clock, parameters M, N & Q configuration and clock output (PLL3ClockOut) */
670 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
671 break;
672 case RCC_ADF1CLKSOURCE_HCLK:
673 break;
674 case RCC_ADF1CLKSOURCE_PIN:
675 break;
676 case RCC_ADF1CLKSOURCE_MSIK:
677 break;
678 default:
679 ret = HAL_ERROR;
680 break;
681 }
682
683 if (ret == HAL_OK)
684 {
685 /* Configure the ADF1 interface clock source */
686 __HAL_RCC_ADF1_CONFIG(pPeriphClkInit->Adf1ClockSelection);
687 }
688 else
689 {
690 /* set overall return value */
691 status = ret;
692 }
693 }
694
695 /*-------------------------- RTC clock source configuration ----------------------*/
696 if ((pPeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
697 {
698 FlagStatus pwrclkchanged = RESET;
699 /* Check for RTC Parameters used to output RTCCLK */
700 assert_param(IS_RCC_RTCCLKSOURCE(pPeriphClkInit->RTCClockSelection));
701
702 /* Enable Power Clock */
703 if (__HAL_RCC_PWR_IS_CLK_DISABLED())
704 {
705 __HAL_RCC_PWR_CLK_ENABLE();
706 pwrclkchanged = SET;
707 }
708 /* Enable write access to Backup domain */
709 SET_BIT(PWR->DBPR, PWR_DBPR_DBP);
710
711 /* Wait for Backup domain Write protection disable */
712 tickstart = HAL_GetTick();
713
714 while (HAL_IS_BIT_CLR(PWR->DBPR, PWR_DBPR_DBP))
715 {
716 if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
717 {
718 ret = HAL_TIMEOUT;
719 break;
720 }
721 }
722
723 if (ret == HAL_OK)
724 {
725 /* Reset the Backup domain only if the RTC Clock source selection is modified from default */
726 tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL);
727
728 if ((tmpregister != RCC_RTCCLKSOURCE_NO_CLK) && (tmpregister != pPeriphClkInit->RTCClockSelection))
729 {
730 /* Store the content of BDCR register before the reset of Backup Domain */
731 tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL));
732 /* RTC Clock selection can be changed only if the Backup Domain is reset */
733 __HAL_RCC_BACKUPRESET_FORCE();
734 __HAL_RCC_BACKUPRESET_RELEASE();
735 /* Restore the Content of BDCR register */
736 RCC->BDCR = tmpregister;
737 }
738
739 /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
740 if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON))
741 {
742 /* Get Start Tick*/
743 tickstart = HAL_GetTick();
744
745 /* Wait till LSE is ready */
746 while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
747 {
748 if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
749 {
750 ret = HAL_TIMEOUT;
751 break;
752 }
753 }
754 }
755
756 if (ret == HAL_OK)
757 {
758 /* Apply new RTC clock source selection */
759 __HAL_RCC_RTC_CONFIG(pPeriphClkInit->RTCClockSelection);
760 }
761 else
762 {
763 /* set overall return value */
764 status = ret;
765 }
766 }
767 else
768 {
769 /* set overall return value */
770 status = ret;
771 }
772
773 /* Restore clock configuration if changed */
774 if (pwrclkchanged == SET)
775 {
776 __HAL_RCC_PWR_CLK_DISABLE();
777 }
778 }
779
780 /*-------------------------------------- CK48 Configuration -----------------------------------*/
781 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
782 {
783 /* Check the parameters */
784 assert_param(IS_RCC_CLK48CLKSOURCE(pPeriphClkInit->Clk48ClockSelection));
785
786 switch (pPeriphClkInit->Clk48ClockSelection)
787 {
788 case RCC_CLK48CLKSOURCE_PLL2:
789 /* PLL2 input clock, parameters M, N,P,Q & R configuration and clock output (PLL2ClockOut) */
790 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
791 break;
792 case RCC_CLK48CLKSOURCE_PLL1:
793 /* Enable CLK48 Clock output generated from System PLL */
794 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
795 break;
796 case RCC_CLK48CLKSOURCE_HSI48:
797 break;
798 case RCC_CLK48CLKSOURCE_MSIK:
799 break;
800 default:
801 ret = HAL_ERROR;
802 break;
803 }
804 if (ret == HAL_OK)
805 {
806 /* Configure the CLK48 source */
807 __HAL_RCC_CLK48_CONFIG(pPeriphClkInit->Clk48ClockSelection);
808 }
809 else
810 {
811 /* set overall return value */
812 status = ret;
813 }
814 }
815
816 /*------------------------------ RNG Configuration -------------------------*/
817 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG)
818 {
819
820 /* Check the parameters */
821 assert_param(IS_RCC_RNGCLKSOURCE(pPeriphClkInit->RngClockSelection));
822
823 switch (pPeriphClkInit->RngClockSelection)
824 {
825 case RCC_RNGCLKSOURCE_HSI48_DIV2: /* HSI48/2 is used as clock source for RNG*/
826 /* RNG clock source configuration done later after clock selection check */
827 break;
828 case RCC_RNGCLKSOURCE_HSI: /* HSI is used as clock source for RNG*/
829 /* RNG clock source configuration done later after clock selection check */
830 break;
831 case RCC_RNGCLKSOURCE_HSI48:
832 /* HSI48 oscillator is used as source of RNG clock */
833 /* RNG clock source configuration done later after clock selection check */
834 break;
835 default:
836 ret = HAL_ERROR;
837 break;
838 }
839
840 if (ret == HAL_OK)
841 {
842 /* Set the source of RNG clock*/
843 __HAL_RCC_RNG_CONFIG(pPeriphClkInit->RngClockSelection);
844 }
845 else
846 {
847 /* set overall return value */
848 status = ret;
849 }
850 }
851
852 /*-------------------------- SAES clock source configuration ----------------*/
853 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAES) == RCC_PERIPHCLK_SAES)
854 {
855 /* Check the parameters */
856 assert_param(IS_RCC_SAESCLKSOURCE(pPeriphClkInit->SaesClockSelection));
857
858 /* Configure the SAES clock source */
859 __HAL_RCC_SAES_CONFIG(pPeriphClkInit->SaesClockSelection);
860 }
861
862 /*-------------------------- SDMMC1/2 clock source configuration -------------------*/
863 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC) == (RCC_PERIPHCLK_SDMMC))
864 {
865 /* Check the parameters */
866 assert_param(IS_RCC_SDMMCCLKSOURCE(pPeriphClkInit->SdmmcClockSelection));
867
868 if (pPeriphClkInit->SdmmcClockSelection == RCC_SDMMCCLKSOURCE_PLL1)
869 {
870 /* Enable PLL1 P CLK output */
871 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP);
872 }
873
874 /* Configure the SDMMC1/2 clock source */
875 __HAL_RCC_SDMMC_CONFIG(pPeriphClkInit->SdmmcClockSelection);
876 }
877
878 /*-------------------------- SPI1 clock source configuration ----------------*/
879 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI1) == RCC_PERIPHCLK_SPI1)
880 {
881 /* Check the parameters */
882 assert_param(IS_RCC_SPI1CLKSOURCE(pPeriphClkInit->Spi1ClockSelection));
883
884 /* Configure the SPI1 clock source */
885 __HAL_RCC_SPI1_CONFIG(pPeriphClkInit->Spi1ClockSelection);
886 }
887
888 /*-------------------------- SPI2 clock source configuration ----------------*/
889 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI2) == RCC_PERIPHCLK_SPI2)
890 {
891 /* Check the parameters */
892 assert_param(IS_RCC_SPI2CLKSOURCE(pPeriphClkInit->Spi2ClockSelection));
893
894 /* Configure the SPI2 clock source */
895 __HAL_RCC_SPI2_CONFIG(pPeriphClkInit->Spi2ClockSelection);
896 }
897
898 /*-------------------------- SPI3 clock source configuration ----------------*/
899 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI3) == RCC_PERIPHCLK_SPI3)
900 {
901 /* Check the parameters */
902 assert_param(IS_RCC_SPI3CLKSOURCE(pPeriphClkInit->Spi3ClockSelection));
903
904 /* Configure the SPI3 clock source */
905 __HAL_RCC_SPI3_CONFIG(pPeriphClkInit->Spi3ClockSelection);
906 }
907
908 /*-------------------------- OctoSPIx clock source configuration ----------------*/
909 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI)
910 {
911 /* Check the parameters */
912 assert_param(IS_RCC_OSPICLKSOURCE(pPeriphClkInit->OspiClockSelection));
913
914 if (pPeriphClkInit->OspiClockSelection == RCC_OSPICLKSOURCE_PLL1)
915 {
916 /* Enable PLL1 Q CLK output */
917 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
918 }
919 if (pPeriphClkInit->OspiClockSelection == RCC_OSPICLKSOURCE_PLL2)
920 {
921 /* Enable PLL2 Q CLK output */
922 __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVQ);
923 }
924 /* Configure the OctoSPI clock source */
925 __HAL_RCC_OSPI_CONFIG(pPeriphClkInit->OspiClockSelection);
926 }
927
928 /*-------------------------- FDCAN1 kernel clock source configuration -------------*/
929 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN1) == (RCC_PERIPHCLK_FDCAN1))
930 {
931 assert_param(IS_RCC_FDCAN1CLK(pPeriphClkInit->Fdcan1ClockSelection));
932
933 switch (pPeriphClkInit->Fdcan1ClockSelection)
934 {
935 case RCC_FDCAN1CLKSOURCE_HSE: /* HSE is used as source of FDCAN1 kernel clock*/
936 /* FDCAN1 kernel clock source config set later after clock selection check */
937 break;
938 case RCC_FDCAN1CLKSOURCE_PLL1: /* PLL1 is used as clock source for FDCAN1 kernel clock*/
939 /* Enable 48M2 Clock output generated from System PLL */
940 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
941 /* FDCAN1 kernel clock source config set later after clock selection check */
942 break;
943 case RCC_FDCAN1CLKSOURCE_PLL2: /* PLL2 is used as clock source for FDCAN1 kernel clock*/
944 /* PLL2 input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */
945 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
946 /* FDCAN1 kernel clock source config set later after clock selection check */
947 break;
948 default:
949 ret = HAL_ERROR;
950 break;
951 }
952 if (ret == HAL_OK)
953 {
954 /* Set the source of FDCAN1 kernel clock*/
955 __HAL_RCC_FDCAN1_CONFIG(pPeriphClkInit->Fdcan1ClockSelection);
956 }
957 else
958 {
959 /* set overall return value */
960 status = ret;
961 }
962 }
963
964 /*-------------------------- DAC1 clock source configuration ----------------*/
965 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DAC1) == RCC_PERIPHCLK_DAC1)
966 {
967 /* Check the parameters */
968 assert_param(IS_RCC_DAC1CLKSOURCE(pPeriphClkInit->Dac1ClockSelection));
969
970 /* Configure the DAC1 clock source */
971 __HAL_RCC_DAC1_CONFIG(pPeriphClkInit->Dac1ClockSelection);
972 }
973
974 return status;
975 }
976
977 /**
978 * @brief Get the RCC_ClkInitStruct according to the internal RCC configuration registers.
979 * @param pPeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
980 * returns the configuration information for the Extended Peripherals
981 * clocks(USART1, USART2, USART3, UART4, UART5, LPUART, I2C1, I2C2, I2C3, LPTIM1, LPTIM2, SAI1, SAI2,
982 * SAES, ADC1, ADC4, MDF1, MDF2, RTC, CLK48, SDMMC1, I2C4, SPI12, SPI3, OSPI, FDCAN1, DAC1).
983 * @retval None
984 */
HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef * pPeriphClkInit)985 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphClkInit)
986 {
987 /* Set all possible values for the extended clock type parameter------------*/
988 pPeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
989 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_LPUART1 | \
990 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \
991 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM34 | RCC_PERIPHCLK_LPTIM2 | \
992 RCC_PERIPHCLK_SAES | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \
993 RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_MDF1 | RCC_PERIPHCLK_ADF1 | \
994 RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_CLK48 | RCC_PERIPHCLK_SDMMC | \
995 RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_SPI1 | \
996 RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_OSPI | \
997 RCC_PERIPHCLK_FDCAN1 | RCC_PERIPHCLK_DAC1;
998
999 /* Get the PLL2 Clock configuration -----------------------------------------------*/
1000 pPeriphClkInit->PLL2.PLL2Source = (uint32_t)((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2SRC) >> RCC_PLL2CFGR_PLL2SRC_Pos);
1001 pPeriphClkInit->PLL2.PLL2M = (uint32_t)((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2M) >> RCC_PLL2CFGR_PLL2M_Pos) + 1U;
1002 pPeriphClkInit->PLL2.PLL2N = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2N) >> RCC_PLL2DIVR_PLL2N_Pos) + 1U;
1003 pPeriphClkInit->PLL2.PLL2P = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2P) >> RCC_PLL2DIVR_PLL2P_Pos) + 1U;
1004 pPeriphClkInit->PLL2.PLL2Q = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2Q) >> RCC_PLL2DIVR_PLL2Q_Pos) + 1U;
1005 pPeriphClkInit->PLL2.PLL2R = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2R) >> RCC_PLL2DIVR_PLL2R_Pos) + 1U;
1006 pPeriphClkInit->PLL2.PLL2RGE = (uint32_t)((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2RGE) >> RCC_PLL2CFGR_PLL2RGE_Pos);
1007 pPeriphClkInit->PLL2.PLL2FRACN = (uint32_t)((RCC->PLL2FRACR & RCC_PLL2FRACR_PLL2FRACN) >> \
1008 RCC_PLL2FRACR_PLL2FRACN_Pos);
1009
1010 /* Get the PLL3 Clock configuration -----------------------------------------------*/
1011 pPeriphClkInit->PLL3.PLL3Source = (uint32_t)((RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3SRC) >> RCC_PLL3CFGR_PLL3SRC_Pos);
1012 pPeriphClkInit->PLL3.PLL3M = (uint32_t)((RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3M) >> RCC_PLL3CFGR_PLL3M_Pos) + 1U;
1013 pPeriphClkInit->PLL3.PLL3N = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3N) >> RCC_PLL3DIVR_PLL3N_Pos) + 1U;
1014 pPeriphClkInit->PLL3.PLL3P = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3P) >> RCC_PLL3DIVR_PLL3P_Pos) + 1U;
1015 pPeriphClkInit->PLL3.PLL3Q = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3Q) >> RCC_PLL3DIVR_PLL3Q_Pos) + 1U;
1016 pPeriphClkInit->PLL3.PLL3R = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3R) >> RCC_PLL3DIVR_PLL3R_Pos) + 1U;
1017 pPeriphClkInit->PLL3.PLL3RGE = (uint32_t)((RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3RGE) >> RCC_PLL3CFGR_PLL3RGE_Pos);
1018 pPeriphClkInit->PLL3.PLL3FRACN = (uint32_t)((RCC->PLL3FRACR & RCC_PLL3FRACR_PLL3FRACN) >> \
1019 RCC_PLL3FRACR_PLL3FRACN_Pos);
1020
1021 /* Get the USART1 clock source ---------------------------------------------*/
1022 pPeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE();
1023
1024 /* Get the USART2 clock source ---------------------------------------------*/
1025 pPeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE();
1026
1027 /* Get the USART3 clock source ---------------------------------------------*/
1028 pPeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE();
1029
1030 /* Get the UART4 clock source ----------------------------------------------*/
1031 pPeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE();
1032
1033 /* Get the UART5 clock source ----------------------------------------------*/
1034 pPeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE();
1035
1036 /* Get the LPUART1 clock source --------------------------------------------*/
1037 pPeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE();
1038
1039 /* Get the I2C1 clock source -----------------------------------------------*/
1040 pPeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();
1041
1042 /* Get the I2C2 clock source -----------------------------------------------*/
1043 pPeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE();
1044
1045 /* Get the I2C3 clock source -----------------------------------------------*/
1046 pPeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE();
1047
1048 /* Get the I2C4 clock source -----------------------------------------------*/
1049 pPeriphClkInit->I2c4ClockSelection = __HAL_RCC_GET_I2C4_SOURCE();
1050
1051 /* Get the LPTIM1 clock source ---------------------------------------------*/
1052 pPeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE();
1053
1054 /* Get the LPTIM2 clock source ---------------------------------------------*/
1055 pPeriphClkInit->Lptim2ClockSelection = __HAL_RCC_GET_LPTIM2_SOURCE();
1056
1057 /* Get the LPTIM34 clock source --------------------------------------------*/
1058 pPeriphClkInit->Lptim34ClockSelection = __HAL_RCC_GET_LPTIM34_SOURCE();
1059
1060 /* Get the FDCAN1 clock source ---------------------------------------------*/
1061 pPeriphClkInit->Fdcan1ClockSelection = __HAL_RCC_GET_FDCAN1_SOURCE();
1062
1063 /* Get the MDF1 clock source -----------------------------------------------*/
1064 pPeriphClkInit->Mdf1ClockSelection = __HAL_RCC_GET_MDF1_SOURCE();
1065
1066 /* Get the ADF1 clock source -----------------------------------------------*/
1067 pPeriphClkInit->Adf1ClockSelection = __HAL_RCC_GET_ADF1_SOURCE();
1068
1069 /* Get the SAES clock source -----------------------------------------------*/
1070 pPeriphClkInit->SaesClockSelection = __HAL_RCC_GET_SAES_SOURCE();
1071
1072 /* Get the SAI1 clock source -----------------------------------------------*/
1073 pPeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();
1074
1075 /* Get the SAI2 clock source -----------------------------------------------*/
1076 pPeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE();
1077
1078 /* Get the CLK48 clock source ----------------------------------------------*/
1079 pPeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();
1080
1081 /* Get the SDMMC clock source ----------------------------------------------*/
1082 pPeriphClkInit->SdmmcClockSelection = __HAL_RCC_GET_SDMMC_SOURCE();
1083
1084 /* Get the ADCDAC clock source ---------------------------------------------*/
1085 pPeriphClkInit->AdcDacClockSelection = __HAL_RCC_GET_ADCDAC_SOURCE();
1086
1087 /* Get the DAC1 clock source -----------------------------------------------*/
1088 pPeriphClkInit->Dac1ClockSelection = __HAL_RCC_GET_DAC1_SOURCE();
1089
1090 /* Get the OSPI clock source -----------------------------------------------*/
1091 pPeriphClkInit->OspiClockSelection = __HAL_RCC_GET_OSPI_SOURCE();
1092
1093 /* Get the SPI1 clock source -----------------------------------------------*/
1094 pPeriphClkInit->Spi1ClockSelection = __HAL_RCC_GET_SPI1_SOURCE();
1095
1096 /* Get the SPI2 clock source -----------------------------------------------*/
1097 pPeriphClkInit->Spi2ClockSelection = __HAL_RCC_GET_SPI2_SOURCE();
1098
1099 /* Get the SPI3 clock source -----------------------------------------------*/
1100 pPeriphClkInit->Spi3ClockSelection = __HAL_RCC_GET_SPI3_SOURCE();
1101
1102 /* Get the RTC clock source ------------------------------------------------*/
1103 pPeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE();
1104
1105 /* Get the RNG clock source ------------------------------------------------*/
1106 pPeriphClkInit->RngClockSelection = __HAL_RCC_GET_RNG_SOURCE();
1107 }
1108
1109 /**
1110 * @brief Returns the PLL1 clock frequencies :PLL1_P_Frequency,PLL1_R_Frequency and PLL1_Q_Frequency
1111 * @note The PLL1 clock frequencies computed by this function is not the real
1112 * frequency in the chip. It is calculated based on the predefined
1113 * constant and the selected clock source:
1114 * @note The function returns values based on HSE_VALUE, HSI_VALUE or MSI Value multiplied/divided by the PLL
1115 * factors.
1116 * @note This function can be used by the user application to compute the
1117 * baud-rate for the communication peripherals or configure other parameters.
1118 *
1119 * @note Each time PLL1CLK changes, this function must be called to update the
1120 * right PLL1CLK value. Otherwise, any configuration based on this function will be incorrect.
1121 * @param PLL1_Clocks structure.
1122 * @retval None
1123 */
HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef * PLL1_Clocks)1124 void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef *PLL1_Clocks)
1125 {
1126 uint32_t pll1source;
1127 uint32_t pll1m;
1128 uint32_t pll1n;
1129 uint32_t pll1fracen;
1130 float_t fracn1;
1131 float_t pll1vco;
1132
1133 pll1n = (RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N);
1134 pll1source = (RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC);
1135 pll1m = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos) + 1U;
1136 pll1fracen = RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1FRACEN;
1137 fracn1 = (float_t)(uint32_t)(pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_PLL1FRACN) >> \
1138 RCC_PLL1FRACR_PLL1FRACN_Pos));
1139
1140 if (pll1m != 0U)
1141 {
1142 switch (pll1source)
1143 {
1144
1145 case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1146 pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \
1147 (fracn1 / (float_t)0x2000) + (float_t)1);
1148 break;
1149 case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
1150 pll1vco = ((float_t)MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)] / (float_t)pll1m) * \
1151 ((float_t)pll1n + (fracn1 / (float_t)0x2000) + (float_t)1);
1152 break;
1153 case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1154 pll1vco = ((float_t)HSE_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \
1155 (fracn1 / (float_t)0x2000) + (float_t)1);
1156 break;
1157 default:
1158 pll1vco = ((float_t)MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)] / (float_t)pll1m) * \
1159 ((float_t)pll1n + (fracn1 / (float_t)0x2000) + (float_t)1);
1160 break;
1161 }
1162
1163 if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL1_DIVP) != 0U)
1164 {
1165 PLL1_Clocks->PLL1_P_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & \
1166 RCC_PLL1DIVR_PLL1P) >> RCC_PLL1DIVR_PLL1P_Pos) + \
1167 (float_t)1));
1168 }
1169 else
1170 {
1171 PLL1_Clocks->PLL1_P_Frequency = 0U;
1172 }
1173
1174 if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL1_DIVQ) != 0U)
1175 {
1176 PLL1_Clocks->PLL1_Q_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & \
1177 RCC_PLL1DIVR_PLL1Q) >> RCC_PLL1DIVR_PLL1Q_Pos) + \
1178 (float_t)1));
1179 }
1180 else
1181 {
1182 PLL1_Clocks->PLL1_Q_Frequency = 0U;
1183 }
1184
1185 if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL1_DIVR) != 0U)
1186 {
1187 PLL1_Clocks->PLL1_R_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & \
1188 RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + \
1189 (float_t)1));
1190 }
1191 else
1192 {
1193 PLL1_Clocks->PLL1_R_Frequency = 0U;
1194 }
1195
1196 }
1197 else
1198 {
1199 PLL1_Clocks->PLL1_P_Frequency = 0U;
1200 PLL1_Clocks->PLL1_Q_Frequency = 0U;
1201 PLL1_Clocks->PLL1_R_Frequency = 0U;
1202 }
1203 }
1204
1205 /**
1206 * @brief Returns the PLL2 clock frequencies :PLL2_P_Frequency,PLL2_R_Frequency and PLL2_Q_Frequency
1207 * @note The PLL2 clock frequencies computed by this function is not the real
1208 * frequency in the chip. It is calculated based on the predefined
1209 * constant and the selected clock source:
1210 * @note The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL
1211 * factors.
1212 * @note This function can be used by the user application to compute the
1213 * baud-rate for the communication peripherals or configure other parameters.
1214 *
1215 * @note Each time PLL2CLK changes, this function must be called to update the
1216 * right PLL2CLK value. Otherwise, any configuration based on this function will be incorrect.
1217 * @param PLL2_Clocks structure.
1218 * @retval None
1219 */
HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef * PLL2_Clocks)1220 void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef *PLL2_Clocks)
1221 {
1222 uint32_t pll2source;
1223 uint32_t pll2m;
1224 uint32_t pll2n;
1225 uint32_t pll2fracen;
1226 float_t fracn2;
1227 float_t pll2vco;
1228
1229 /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL2M) * PLL2N
1230 PLL2xCLK = PLL2_VCO / PLL2x */
1231 pll2n = (RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2N);
1232 pll2source = (RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2SRC);
1233 pll2m = ((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2M) >> RCC_PLL2CFGR_PLL2M_Pos) + 1U;
1234 pll2fracen = RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2FRACEN;
1235 fracn2 = (float_t)(uint32_t)(pll2fracen * ((RCC->PLL2FRACR & RCC_PLL2FRACR_PLL2FRACN) >> \
1236 RCC_PLL2FRACR_PLL2FRACN_Pos));
1237
1238 if (pll2m != 0U)
1239 {
1240 switch (pll2source)
1241 {
1242 case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1243 pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2N) + \
1244 (fracn2 / (float_t)0x2000) + (float_t)1);
1245 break;
1246
1247 case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
1248 pll2vco = ((float_t)MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)] / (float_t)pll2m) * \
1249 ((float_t)pll2n + (fracn2 / (float_t)0x2000) + (float_t)1);
1250 break;
1251
1252 case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1253 pll2vco = ((float_t)HSE_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2N) + \
1254 (fracn2 / (float_t)0x2000) + (float_t)1);
1255 break;
1256
1257 default:
1258 pll2vco = ((float_t)MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)] / (float_t) pll2m) \
1259 * ((float_t)pll2n + (fracn2 / (float_t)0x2000) + (float_t)1);
1260 break;
1261 }
1262 if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL2_DIVP) != 0U)
1263 {
1264 PLL2_Clocks->PLL2_P_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & \
1265 RCC_PLL2DIVR_PLL2P) >> RCC_PLL2DIVR_PLL2P_Pos) + \
1266 (float_t)1));
1267 }
1268 else
1269 {
1270 PLL2_Clocks->PLL2_P_Frequency = 0U;
1271 }
1272 if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL2_DIVQ) != 0U)
1273 {
1274 PLL2_Clocks->PLL2_Q_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & \
1275 RCC_PLL2DIVR_PLL2Q) >> RCC_PLL2DIVR_PLL2Q_Pos) + \
1276 (float_t)1));
1277 }
1278 else
1279 {
1280 PLL2_Clocks->PLL2_Q_Frequency = 0U;
1281 }
1282 if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL2_DIVR) != 0U)
1283 {
1284 PLL2_Clocks->PLL2_R_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & \
1285 RCC_PLL2DIVR_PLL2R) >> RCC_PLL2DIVR_PLL2R_Pos) + \
1286 (float_t)1));
1287 }
1288 else
1289 {
1290 PLL2_Clocks->PLL2_R_Frequency = 0U;
1291 }
1292 }
1293 else
1294 {
1295 PLL2_Clocks->PLL2_P_Frequency = 0U;
1296 PLL2_Clocks->PLL2_Q_Frequency = 0U;
1297 PLL2_Clocks->PLL2_R_Frequency = 0U;
1298 }
1299 }
1300
1301 /**
1302 * @brief Returns the PLL3 clock frequencies :PLL3_P_Frequency,PLL3_R_Frequency and PLL3_Q_Frequency
1303 * @note The PLL3 clock frequencies computed by this function is not the real
1304 * frequency in the chip. It is calculated based on the predefined
1305 * constant and the selected clock source:
1306 * @note The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL
1307 * factors.
1308 * @note This function can be used by the user application to compute the
1309 * baud-rate for the communication peripherals or configure other parameters.
1310 *
1311 * @note Each time PLL3CLK changes, this function must be called to update the
1312 * right PLL3CLK value. Otherwise, any configuration based on this function will be incorrect.
1313 * @param PLL3_Clocks structure.
1314 * @retval None
1315 */
HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef * PLL3_Clocks)1316 void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *PLL3_Clocks)
1317 {
1318 uint32_t pll3source;
1319 uint32_t pll3m;
1320 uint32_t pll3n;
1321 uint32_t pll3fracen;
1322 float_t fracn3;
1323 float_t pll3vco;
1324
1325 /* PLL3_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL3M) * PLL3N
1326 PLL3xCLK = PLL3_VCO / PLLxR
1327 */
1328
1329 pll3n = (RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3N);
1330 pll3source = (RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3SRC);
1331 pll3m = ((RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3M) >> RCC_PLL3CFGR_PLL3M_Pos) + 1U;
1332 pll3fracen = RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3FRACEN;
1333 fracn3 = (float_t)(uint32_t)(pll3fracen * ((RCC->PLL3FRACR & RCC_PLL3FRACR_PLL3FRACN) >> \
1334 RCC_PLL3FRACR_PLL3FRACN_Pos));
1335
1336 if (pll3m != 0U)
1337 {
1338 switch (pll3source)
1339 {
1340 case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1341 pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3N) + \
1342 (fracn3 / (float_t)0x2000) + (float_t)1);
1343
1344 break;
1345 case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
1346 pll3vco = ((float_t)MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)] / (float_t)pll3m) * \
1347 ((float_t)pll3n + (fracn3 / (float_t)0x2000) + (float_t)1);
1348 break;
1349
1350 case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1351 pll3vco = ((float_t)HSE_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3N) + \
1352 (fracn3 / (float_t)0x2000) + (float_t)1);
1353 break;
1354
1355 default:
1356 pll3vco = ((float_t)MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)] / (float_t)pll3m) * \
1357 ((float_t)pll3n + (fracn3 / (float_t)0x2000) + (float_t)1);
1358 break;
1359 }
1360
1361 if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL3_DIVP) != 0U)
1362 {
1363 PLL3_Clocks->PLL3_P_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & \
1364 RCC_PLL3DIVR_PLL3P) >> RCC_PLL3DIVR_PLL3P_Pos) + \
1365 (float_t)1));
1366 }
1367 else
1368 {
1369 PLL3_Clocks->PLL3_P_Frequency = 0U;
1370 }
1371
1372 if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL3_DIVQ) != 0U)
1373 {
1374 PLL3_Clocks->PLL3_Q_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & \
1375 RCC_PLL3DIVR_PLL3Q) >> RCC_PLL3DIVR_PLL3Q_Pos) + \
1376 (float_t)1));
1377 }
1378 else
1379 {
1380 PLL3_Clocks->PLL3_Q_Frequency = 0U;
1381 }
1382
1383 if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL3_DIVR) != 0U)
1384 {
1385 PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & \
1386 RCC_PLL3DIVR_PLL3R) >> RCC_PLL3DIVR_PLL3R_Pos) + \
1387 (float_t)1));
1388 }
1389 else
1390 {
1391 PLL3_Clocks->PLL3_R_Frequency = 0U;
1392 }
1393
1394 }
1395 else
1396 {
1397 PLL3_Clocks->PLL3_P_Frequency = 0U;
1398 PLL3_Clocks->PLL3_Q_Frequency = 0U;
1399 PLL3_Clocks->PLL3_R_Frequency = 0U;
1400 }
1401 }
1402
1403 /**
1404 * @brief Return the peripheral clock frequency for peripherals
1405 * @note Return 0 if peripheral clock identifier not managed by this API
1406 * @param PeriphClk Peripheral clock identifier
1407 * This parameter can be one of the following values:
1408 * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock
1409 * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
1410 * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock
1411 * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock
1412 * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock
1413 * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock
1414 * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock
1415 * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
1416 * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
1417 * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock
1418 * @arg @ref RCC_PERIPHCLK_LPTIM34 LPTIM34 peripheral clock
1419 * @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock
1420 * @arg @ref RCC_PERIPHCLK_SAES SAES peripheral clock
1421 * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock
1422 * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock
1423 * @arg @ref RCC_PERIPHCLK_ADCDAC ADC1,ADC4, DAC1 peripheral clock
1424 * @arg @ref RCC_PERIPHCLK_MDF1 MDF1 peripheral clock
1425 * @arg @ref RCC_PERIPHCLK_MDF1 MDF1 peripheral clock
1426 * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
1427 * @arg @ref RCC_PERIPHCLK_CLK48 CLK48 peripheral clock
1428 * @arg @ref RCC_PERIPHCLK_SDMMC SDMMC peripheral clock
1429 * @arg @ref RCC_PERIPHCLK_SPI1 SPI1 peripheral clock
1430 * @arg @ref RCC_PERIPHCLK_SPI2 SPI2 peripheral clock
1431 * @arg @ref RCC_PERIPHCLK_SPI3 SPI3 peripheral clock
1432 * @arg @ref RCC_PERIPHCLK_OSPI OSPI peripheral clock
1433 * @arg @ref RCC_PERIPHCLK_FDCAN1 FDCAN1 peripheral clock
1434 * @arg @ref RCC_PERIPHCLK_DAC1 DAC1 peripheral clock
1435 * @retval Frequency in Hz
1436 */
HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)1437 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
1438 {
1439 PLL1_ClocksTypeDef pll1_clocks;
1440 PLL2_ClocksTypeDef pll2_clocks;
1441 PLL3_ClocksTypeDef pll3_clocks;
1442
1443 uint32_t frequency;
1444 uint32_t srcclk;
1445
1446 /* Check the parameters */
1447 assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
1448
1449 if (PeriphClk == RCC_PERIPHCLK_RTC)
1450 {
1451 /* Get the current RTC source */
1452 srcclk = __HAL_RCC_GET_RTC_SOURCE();
1453
1454 /* Check if LSE is ready and if RTC clock selection is LSE */
1455 if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_RTCCLKSOURCE_LSE))
1456 {
1457 frequency = LSE_VALUE;
1458 }
1459 /* Check if LSI is ready and if RTC clock selection is LSI */
1460 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_RTCCLKSOURCE_LSI))
1461 {
1462 if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIPREDIV))
1463 {
1464 frequency = LSI_VALUE / 128U;
1465 }
1466 else
1467 {
1468 frequency = LSI_VALUE;
1469 }
1470 }
1471 /* Check if HSE is ready and if RTC clock selection is HSI_DIV32*/
1472 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_RTCCLKSOURCE_HSE_DIV32))
1473 {
1474 frequency = HSE_VALUE / 32U;
1475 }
1476 /* Clock not enabled for RTC*/
1477 else
1478 {
1479 frequency = 0U;
1480 }
1481 }
1482 else
1483 {
1484 /* Other external peripheral clock source than RTC */
1485 switch (PeriphClk)
1486 {
1487 case RCC_PERIPHCLK_SAI1:
1488
1489 srcclk = __HAL_RCC_GET_SAI1_SOURCE();
1490
1491 switch (srcclk)
1492 {
1493 case RCC_SAI1CLKSOURCE_PLL1: /* PLL1P is the clock source for SAI1 */
1494
1495 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
1496 frequency = pll1_clocks.PLL1_P_Frequency;
1497 break;
1498
1499 case RCC_SAI1CLKSOURCE_PLL2: /* PLL2P is the clock source for SAI1 */
1500
1501 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
1502 frequency = pll2_clocks.PLL2_P_Frequency;
1503 break;
1504
1505 case RCC_SAI1CLKSOURCE_PLL3: /* PLLI3P is the clock source for SAI1 */
1506
1507 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
1508 frequency = pll3_clocks.PLL3_P_Frequency;
1509 break;
1510
1511 case RCC_SAI1CLKSOURCE_PIN:
1512
1513 frequency = EXTERNAL_SAI1_CLOCK_VALUE;
1514 break;
1515
1516 case RCC_SAI1CLKSOURCE_HSI: /* HSI is the clock source for SAI1 */
1517
1518 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
1519 {
1520 frequency = HSI_VALUE;
1521 }
1522 else
1523 {
1524 frequency = 0U;
1525 }
1526 break;
1527
1528 default :
1529 {
1530 frequency = 0U;
1531 break;
1532 }
1533 }
1534 break;
1535
1536 case RCC_PERIPHCLK_SAI2:
1537
1538 srcclk = __HAL_RCC_GET_SAI2_SOURCE();
1539
1540 switch (srcclk)
1541 {
1542 case RCC_SAI2CLKSOURCE_PLL1: /* PLL1P is the clock source for SAI1 */
1543
1544 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
1545 frequency = pll1_clocks.PLL1_P_Frequency;
1546 break;
1547
1548 case RCC_SAI2CLKSOURCE_PLL2: /* PLL2P is the clock source for SAI1 */
1549
1550 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
1551 frequency = pll2_clocks.PLL2_P_Frequency;
1552 break;
1553
1554 case RCC_SAI2CLKSOURCE_PLL3: /* PLLI3P is the clock source for SAI1 */
1555
1556 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
1557 frequency = pll3_clocks.PLL3_P_Frequency;
1558 break;
1559
1560 case RCC_SAI2CLKSOURCE_PIN:
1561
1562 frequency = EXTERNAL_SAI1_CLOCK_VALUE;
1563 break;
1564
1565 case RCC_SAI2CLKSOURCE_HSI: /* HSI is the clock source for SAI1 */
1566
1567 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
1568 {
1569 frequency = HSI_VALUE;
1570 }
1571 else
1572 {
1573 frequency = 0U;
1574 }
1575 break;
1576
1577 default :
1578
1579 frequency = 0U;
1580 break;
1581
1582 }
1583 break;
1584 case RCC_PERIPHCLK_SAES:
1585 /* Get the current SAES source */
1586 srcclk = __HAL_RCC_GET_SAES_SOURCE();
1587
1588 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (srcclk == RCC_SAESCLKSOURCE_SHSI))
1589 {
1590 frequency = HSI_VALUE;
1591 }
1592 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (srcclk == RCC_SAESCLKSOURCE_SHSI_DIV2))
1593 {
1594 frequency = HSI_VALUE >> 1U;
1595 }
1596 /* Clock not enabled for SAES */
1597 else
1598 {
1599 frequency = 0U;
1600 }
1601 break;
1602
1603 case RCC_PERIPHCLK_CLK48:
1604
1605 srcclk = __HAL_RCC_GET_CLK48_SOURCE();
1606
1607 switch (srcclk)
1608 {
1609 case RCC_CLK48CLKSOURCE_PLL1: /* PLL1Q */
1610
1611 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
1612 frequency = pll1_clocks.PLL1_Q_Frequency;
1613 break;
1614
1615 case RCC_CLK48CLKSOURCE_PLL2: /* PLL2Q */
1616
1617 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
1618 frequency = pll2_clocks.PLL2_Q_Frequency;
1619 break;
1620
1621 case RCC_CLK48CLKSOURCE_HSI48: /* HSI48 */
1622
1623 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSI48RDY))
1624 {
1625 frequency = HSI48_VALUE;
1626 }
1627 else
1628 {
1629 frequency = 0U;
1630 }
1631 break;
1632
1633 case RCC_CLK48CLKSOURCE_MSIK: /* MSIK frequency range in HZ */
1634
1635 frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
1636 break;
1637
1638 default :
1639
1640 frequency = 0U;
1641 break;
1642
1643 }
1644 break;
1645
1646 case RCC_PERIPHCLK_SDMMC:
1647 srcclk = __HAL_RCC_GET_SDMMC_SOURCE();
1648 if (srcclk == RCC_SDMMCCLKSOURCE_CLK48)
1649 {
1650 srcclk = __HAL_RCC_GET_CLK48_SOURCE();
1651
1652 switch (srcclk)
1653 {
1654 case RCC_CLK48CLKSOURCE_PLL1: /* PLL1Q */
1655 {
1656 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
1657 frequency = pll1_clocks.PLL1_Q_Frequency;
1658 break;
1659 }
1660 case RCC_CLK48CLKSOURCE_PLL2: /* PLL2Q */
1661 {
1662 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
1663 frequency = pll2_clocks.PLL2_Q_Frequency;
1664 break;
1665 }
1666 case RCC_CLK48CLKSOURCE_HSI48: /* HSI48 */
1667 {
1668 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSI48RDY))
1669 {
1670 frequency = HSI48_VALUE;
1671 }
1672 else
1673 {
1674 frequency = 0U;
1675 }
1676 break;
1677 }
1678 case RCC_CLK48CLKSOURCE_MSIK: /* MSIK frequency range in HZ */
1679 {
1680 frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
1681 break;
1682 }
1683 default :
1684 {
1685 frequency = 0U;
1686 break;
1687 }
1688 }
1689 break;
1690 }
1691 else if (srcclk == RCC_SDMMCCLKSOURCE_PLL1)
1692 {
1693 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
1694 frequency = pll1_clocks.PLL1_P_Frequency;
1695 }
1696 else
1697 {
1698 frequency = 0U;
1699 }
1700 break;
1701
1702 case RCC_PERIPHCLK_USART1:
1703 /* Get the current USART1 source */
1704 srcclk = __HAL_RCC_GET_USART1_SOURCE();
1705
1706 if (srcclk == RCC_USART1CLKSOURCE_PCLK2)
1707 {
1708 frequency = HAL_RCC_GetPCLK2Freq();
1709 }
1710 else if (srcclk == RCC_USART1CLKSOURCE_SYSCLK)
1711 {
1712 frequency = HAL_RCC_GetSysClockFreq();
1713 }
1714 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART1CLKSOURCE_HSI))
1715 {
1716 frequency = HSI_VALUE;
1717 }
1718 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART1CLKSOURCE_LSE))
1719 {
1720 frequency = LSE_VALUE;
1721 }
1722 /* Clock not enabled for USART1 */
1723 else
1724 {
1725 frequency = 0U;
1726 }
1727 break;
1728
1729 case RCC_PERIPHCLK_USART2:
1730 /* Get the current USART2 source */
1731 srcclk = __HAL_RCC_GET_USART2_SOURCE();
1732
1733 if (srcclk == RCC_USART2CLKSOURCE_PCLK1)
1734 {
1735 frequency = HAL_RCC_GetPCLK1Freq();
1736 }
1737 else if (srcclk == RCC_USART2CLKSOURCE_SYSCLK)
1738 {
1739 frequency = HAL_RCC_GetSysClockFreq();
1740 }
1741 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART2CLKSOURCE_HSI))
1742 {
1743 frequency = HSI_VALUE;
1744 }
1745 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART2CLKSOURCE_LSE))
1746 {
1747 frequency = LSE_VALUE;
1748 }
1749 /* Clock not enabled for USART2 */
1750 else
1751 {
1752 frequency = 0U;
1753 }
1754 break;
1755
1756 case RCC_PERIPHCLK_USART3:
1757 /* Get the current USART3 source */
1758 srcclk = __HAL_RCC_GET_USART3_SOURCE();
1759
1760 if (srcclk == RCC_USART3CLKSOURCE_PCLK1)
1761 {
1762 frequency = HAL_RCC_GetPCLK1Freq();
1763 }
1764 else if (srcclk == RCC_USART3CLKSOURCE_SYSCLK)
1765 {
1766 frequency = HAL_RCC_GetSysClockFreq();
1767 }
1768 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART3CLKSOURCE_HSI))
1769 {
1770 frequency = HSI_VALUE;
1771 }
1772 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART3CLKSOURCE_LSE))
1773 {
1774 frequency = LSE_VALUE;
1775 }
1776 /* Clock not enabled for USART3 */
1777 else
1778 {
1779 frequency = 0U;
1780 }
1781 break;
1782
1783 case RCC_PERIPHCLK_UART4:
1784 /* Get the current UART4 source */
1785 srcclk = __HAL_RCC_GET_UART4_SOURCE();
1786
1787 if (srcclk == RCC_UART4CLKSOURCE_PCLK1)
1788 {
1789 frequency = HAL_RCC_GetPCLK1Freq();
1790 }
1791 else if (srcclk == RCC_UART4CLKSOURCE_SYSCLK)
1792 {
1793 frequency = HAL_RCC_GetSysClockFreq();
1794 }
1795 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_UART4CLKSOURCE_HSI))
1796 {
1797 frequency = HSI_VALUE;
1798 }
1799 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_UART4CLKSOURCE_LSE))
1800 {
1801 frequency = LSE_VALUE;
1802 }
1803 /* Clock not enabled for UART4 */
1804 else
1805 {
1806 frequency = 0U;
1807 }
1808 break;
1809
1810 case RCC_PERIPHCLK_UART5:
1811 /* Get the current UART5 source */
1812 srcclk = __HAL_RCC_GET_UART5_SOURCE();
1813
1814 if (srcclk == RCC_UART5CLKSOURCE_PCLK1)
1815 {
1816 frequency = HAL_RCC_GetPCLK1Freq();
1817 }
1818 else if (srcclk == RCC_UART5CLKSOURCE_SYSCLK)
1819 {
1820 frequency = HAL_RCC_GetSysClockFreq();
1821 }
1822 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_UART5CLKSOURCE_HSI))
1823 {
1824 frequency = HSI_VALUE;
1825 }
1826 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_UART5CLKSOURCE_LSE))
1827 {
1828 frequency = LSE_VALUE;
1829 }
1830 /* Clock not enabled for UART5 */
1831 else
1832 {
1833 frequency = 0U;
1834 }
1835 break;
1836
1837 case RCC_PERIPHCLK_LPUART1:
1838 /* Get the current LPUART1 source */
1839 srcclk = __HAL_RCC_GET_LPUART1_SOURCE();
1840
1841 if (srcclk == RCC_LPUART1CLKSOURCE_PCLK3)
1842 {
1843 frequency = HAL_RCC_GetPCLK3Freq();
1844 }
1845 else if (srcclk == RCC_LPUART1CLKSOURCE_SYSCLK)
1846 {
1847 frequency = HAL_RCC_GetSysClockFreq();
1848 }
1849 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPUART1CLKSOURCE_HSI))
1850 {
1851 frequency = HSI_VALUE;
1852 }
1853 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPUART1CLKSOURCE_LSE))
1854 {
1855 frequency = LSE_VALUE;
1856 }
1857 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) && (srcclk == RCC_LPUART1CLKSOURCE_MSIK))
1858 {
1859 frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
1860 }
1861 /* Clock not enabled for LPUART1 */
1862 else
1863 {
1864 frequency = 0U;
1865 }
1866 break;
1867
1868 case RCC_PERIPHCLK_ADCDAC:
1869
1870 srcclk = __HAL_RCC_GET_ADCDAC_SOURCE();
1871
1872 if (srcclk == RCC_ADCDACCLKSOURCE_SYSCLK)
1873 {
1874 frequency = HAL_RCC_GetSysClockFreq();
1875 }
1876 else if (srcclk == RCC_ADCDACCLKSOURCE_PLL2)
1877 {
1878 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
1879 frequency = pll2_clocks.PLL2_R_Frequency;
1880 }
1881 else if (srcclk == RCC_ADCDACCLKSOURCE_HCLK)
1882 {
1883 frequency = HAL_RCC_GetHCLKFreq();
1884 break;
1885 }
1886 else if (srcclk == RCC_ADCDACCLKSOURCE_MSIK)
1887 {
1888 frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)];
1889 break;
1890 }
1891 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_ADCDACCLKSOURCE_HSE))
1892 {
1893 frequency = HSE_VALUE;
1894 }
1895 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_ADCDACCLKSOURCE_HSI))
1896 {
1897 frequency = HSI_VALUE;
1898 }
1899 /* Clock not enabled for ADC */
1900 else
1901 {
1902 frequency = 0U;
1903 }
1904 break;
1905
1906 case RCC_PERIPHCLK_MDF1:
1907 /* Get the current MDF1 source */
1908 srcclk = __HAL_RCC_GET_MDF1_SOURCE();
1909
1910 switch (srcclk)
1911 {
1912 case RCC_MDF1CLKSOURCE_PLL1:
1913
1914 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
1915 frequency = pll1_clocks.PLL1_P_Frequency;
1916 break;
1917
1918 case RCC_MDF1CLKSOURCE_PLL3:
1919
1920 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
1921 frequency = pll3_clocks.PLL3_Q_Frequency;
1922 break;
1923
1924 case RCC_MDF1CLKSOURCE_HCLK:
1925
1926 frequency = HAL_RCC_GetHCLKFreq();
1927 break;
1928
1929 case RCC_MDF1CLKSOURCE_PIN:
1930
1931 frequency = EXTERNAL_SAI1_CLOCK_VALUE;
1932 break;
1933
1934 case RCC_MDF1CLKSOURCE_MSIK:
1935
1936 frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
1937 break;
1938
1939 default:
1940
1941 frequency = 0U;
1942 break;
1943
1944 }
1945 break;
1946
1947 case RCC_PERIPHCLK_ADF1:
1948 /* Get the current ADF1 source */
1949 srcclk = __HAL_RCC_GET_ADF1_SOURCE();
1950
1951 switch (srcclk)
1952 {
1953 case RCC_ADF1CLKSOURCE_PLL1:
1954
1955 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
1956 frequency = pll1_clocks.PLL1_P_Frequency;
1957 break;
1958
1959 case RCC_ADF1CLKSOURCE_PLL3:
1960
1961 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
1962 frequency = pll3_clocks.PLL3_Q_Frequency;
1963 break;
1964
1965 case RCC_ADF1CLKSOURCE_HCLK:
1966
1967 frequency = HAL_RCC_GetHCLKFreq();
1968 break;
1969
1970 case RCC_ADF1CLKSOURCE_PIN:
1971
1972 frequency = EXTERNAL_SAI1_CLOCK_VALUE;
1973 break;
1974
1975 case RCC_ADF1CLKSOURCE_MSIK:
1976
1977 frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
1978 break;
1979
1980 default:
1981
1982 frequency = 0U;
1983 break;
1984 }
1985 break;
1986
1987 case RCC_PERIPHCLK_I2C1:
1988 /* Get the current I2C1 source */
1989 srcclk = __HAL_RCC_GET_I2C1_SOURCE();
1990
1991 if (srcclk == RCC_I2C1CLKSOURCE_PCLK1)
1992 {
1993 frequency = HAL_RCC_GetPCLK1Freq();
1994 }
1995 else if (srcclk == RCC_I2C1CLKSOURCE_SYSCLK)
1996 {
1997 frequency = HAL_RCC_GetSysClockFreq();
1998 }
1999 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C1CLKSOURCE_HSI))
2000 {
2001 frequency = HSI_VALUE;
2002 }
2003 /* Clock not enabled for I2C1 */
2004 else
2005 {
2006 frequency = 0U;
2007 }
2008 break;
2009
2010 case RCC_PERIPHCLK_I2C2:
2011 /* Get the current I2C2 source */
2012 srcclk = __HAL_RCC_GET_I2C2_SOURCE();
2013
2014 if (srcclk == RCC_I2C2CLKSOURCE_PCLK1)
2015 {
2016 frequency = HAL_RCC_GetPCLK1Freq();
2017 }
2018 else if (srcclk == RCC_I2C2CLKSOURCE_SYSCLK)
2019 {
2020 frequency = HAL_RCC_GetSysClockFreq();
2021 }
2022 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C2CLKSOURCE_HSI))
2023 {
2024 frequency = HSI_VALUE;
2025 }
2026 /* Clock not enabled for I2C2 */
2027 else
2028 {
2029 frequency = 0U;
2030 }
2031 break;
2032
2033 case RCC_PERIPHCLK_I2C3:
2034 /* Get the current I2C3 source */
2035 srcclk = __HAL_RCC_GET_I2C3_SOURCE();
2036
2037 switch (srcclk)
2038 {
2039 case RCC_I2C3CLKSOURCE_PCLK3:
2040 {
2041 frequency = HAL_RCC_GetPCLK3Freq();
2042 break;
2043 }
2044 case RCC_I2C3CLKSOURCE_HSI:
2045 {
2046 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
2047 {
2048 frequency = HSI_VALUE;
2049 }
2050 else
2051 {
2052 frequency = 0U;
2053 }
2054 break;
2055 }
2056 case RCC_I2C3CLKSOURCE_SYSCLK:
2057 {
2058 frequency = HAL_RCC_GetSysClockFreq();
2059 break;
2060 }
2061 case RCC_I2C3CLKSOURCE_MSIK:
2062 {
2063 frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)];
2064 break;
2065 }
2066 default:
2067 {
2068 frequency = 0U;
2069 break;
2070 }
2071 }
2072 break;
2073
2074 case RCC_PERIPHCLK_I2C4:
2075 /* Get the current I2C4 source */
2076 srcclk = __HAL_RCC_GET_I2C4_SOURCE();
2077
2078 if (srcclk == RCC_I2C4CLKSOURCE_PCLK1)
2079 {
2080 frequency = HAL_RCC_GetPCLK1Freq();
2081 }
2082 else if (srcclk == RCC_I2C4CLKSOURCE_SYSCLK)
2083 {
2084 frequency = HAL_RCC_GetSysClockFreq();
2085 }
2086 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C4CLKSOURCE_HSI))
2087 {
2088 frequency = HSI_VALUE;
2089 }
2090 /* Clock not enabled for I2C4 */
2091 else
2092 {
2093 frequency = 0U;
2094 }
2095 break;
2096
2097 case RCC_PERIPHCLK_LPTIM34:
2098 /* Get the current LPTIM34 source */
2099 srcclk = __HAL_RCC_GET_LPTIM34_SOURCE();
2100
2101 if (srcclk == RCC_LPTIM34CLKSOURCE_MSIK)
2102 {
2103 frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
2104 }
2105 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_LPTIM34CLKSOURCE_LSI))
2106 {
2107 frequency = LSI_VALUE;
2108 }
2109 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPTIM34CLKSOURCE_HSI))
2110 {
2111 frequency = HSI_VALUE;
2112 }
2113 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPTIM34CLKSOURCE_LSE))
2114 {
2115 frequency = LSE_VALUE;
2116 }
2117 /* Clock not enabled for LPTIM34 */
2118 else
2119 {
2120 frequency = 0U;
2121 }
2122 break;
2123
2124 case RCC_PERIPHCLK_LPTIM1:
2125 /* Get the current LPTIM1 source */
2126 srcclk = __HAL_RCC_GET_LPTIM1_SOURCE();
2127
2128 if (srcclk == RCC_LPTIM1CLKSOURCE_MSIK)
2129 {
2130 frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
2131 }
2132 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_LSI))
2133 {
2134 frequency = LSI_VALUE;
2135 }
2136 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_HSI))
2137 {
2138 frequency = HSI_VALUE;
2139 }
2140 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_LSE))
2141 {
2142 frequency = LSE_VALUE;
2143 }
2144 /* Clock not enabled for LPTIM1 */
2145 else
2146 {
2147 frequency = 0U;
2148 }
2149 break;
2150
2151 case RCC_PERIPHCLK_LPTIM2:
2152 /* Get the current LPTIM2 source */
2153 srcclk = __HAL_RCC_GET_LPTIM2_SOURCE();
2154
2155 if (srcclk == RCC_LPTIM2CLKSOURCE_PCLK1)
2156 {
2157 frequency = HAL_RCC_GetPCLK1Freq();
2158 }
2159 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_LPTIM2CLKSOURCE_LSI))
2160 {
2161 frequency = LSI_VALUE;
2162 }
2163 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPTIM2CLKSOURCE_HSI))
2164 {
2165 frequency = HSI_VALUE;
2166 }
2167 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPTIM2CLKSOURCE_LSE))
2168 {
2169 frequency = LSE_VALUE;
2170 }
2171 /* Clock not enabled for LPTIM2 */
2172 else
2173 {
2174 frequency = 0U;
2175 }
2176 break;
2177
2178 case RCC_PERIPHCLK_FDCAN1:
2179 /* Get the current FDCAN1 kernel source */
2180 srcclk = __HAL_RCC_GET_FDCAN1_SOURCE();
2181
2182 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_FDCAN1CLKSOURCE_HSE))
2183 {
2184 frequency = HSE_VALUE;
2185 }
2186 else if (srcclk == RCC_FDCAN1CLKSOURCE_PLL1) /* PLL1 ? */
2187 {
2188 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
2189 frequency = pll1_clocks.PLL1_Q_Frequency;
2190 }
2191 else if (srcclk == RCC_FDCAN1CLKSOURCE_PLL2) /* PLL2 ? */
2192 {
2193 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
2194 frequency = pll2_clocks.PLL2_P_Frequency;
2195 }
2196 /* Clock not enabled for FDCAN1 */
2197 else
2198 {
2199 frequency = 0U;
2200 }
2201 break;
2202
2203 case RCC_PERIPHCLK_SPI1:
2204 /* Get the current SPI1 kernel source */
2205 srcclk = __HAL_RCC_GET_SPI1_SOURCE();
2206 switch (srcclk)
2207 {
2208 case RCC_SPI1CLKSOURCE_PCLK2:
2209
2210 frequency = HAL_RCC_GetPCLK2Freq();
2211 break;
2212
2213 case RCC_SPI1CLKSOURCE_SYSCLK:
2214
2215 frequency = HAL_RCC_GetSysClockFreq();
2216 break;
2217
2218 case RCC_SPI1CLKSOURCE_HSI:
2219
2220 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
2221 {
2222 frequency = HSI_VALUE;
2223 }
2224 else
2225 {
2226 frequency = 0U;
2227 }
2228 break;
2229
2230 case RCC_SPI1CLKSOURCE_MSIK:
2231
2232 frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
2233 break;
2234
2235 default:
2236
2237 frequency = 0U;
2238 break;
2239
2240 }
2241 break;
2242
2243 case RCC_PERIPHCLK_SPI2:
2244 /* Get the current SPI2 kernel source */
2245 srcclk = __HAL_RCC_GET_SPI2_SOURCE();
2246 switch (srcclk)
2247 {
2248 case RCC_SPI2CLKSOURCE_PCLK1:
2249
2250 frequency = HAL_RCC_GetPCLK1Freq();
2251 break;
2252
2253 case RCC_SPI2CLKSOURCE_SYSCLK:
2254
2255 frequency = HAL_RCC_GetSysClockFreq();
2256 break;
2257
2258 case RCC_SPI2CLKSOURCE_HSI:
2259
2260 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
2261 {
2262 frequency = HSI_VALUE;
2263 }
2264 else
2265 {
2266 frequency = 0U;
2267 }
2268 break;
2269
2270 case RCC_SPI2CLKSOURCE_MSIK:
2271
2272 frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
2273 break;
2274
2275 default:
2276
2277 frequency = 0U;
2278 break;
2279
2280 }
2281 break;
2282
2283 case RCC_PERIPHCLK_SPI3:
2284 /* Get the current SPI3 kernel source */
2285 srcclk = __HAL_RCC_GET_SPI3_SOURCE();
2286 switch (srcclk)
2287 {
2288 case RCC_SPI3CLKSOURCE_PCLK3:
2289
2290 frequency = HAL_RCC_GetPCLK3Freq();
2291 break;
2292
2293 case RCC_SPI3CLKSOURCE_SYSCLK:
2294
2295 frequency = HAL_RCC_GetSysClockFreq();
2296 break;
2297
2298 case RCC_SPI3CLKSOURCE_HSI:
2299
2300 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
2301 {
2302 frequency = HSI_VALUE;
2303 }
2304 else
2305 {
2306 frequency = 0U;
2307 }
2308 break;
2309
2310 case RCC_SPI3CLKSOURCE_MSIK:
2311
2312 frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
2313 break;
2314
2315 default:
2316
2317 frequency = 0U;
2318 break;
2319 }
2320 break;
2321
2322 case RCC_PERIPHCLK_OSPI:
2323 /* Get the current OSPI kernel source */
2324 srcclk = __HAL_RCC_GET_OSPI_SOURCE();
2325
2326 switch (srcclk)
2327 {
2328 case RCC_OSPICLKSOURCE_PLL2:
2329
2330 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
2331 frequency = pll2_clocks.PLL2_Q_Frequency;
2332 break;
2333
2334 case RCC_OSPICLKSOURCE_PLL1:
2335
2336 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
2337 frequency = pll1_clocks.PLL1_Q_Frequency;
2338 break;
2339
2340 case RCC_OSPICLKSOURCE_SYSCLK:
2341
2342 frequency = HAL_RCC_GetSysClockFreq();
2343 break;
2344
2345 case RCC_OSPICLKSOURCE_MSIK:
2346
2347 frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
2348 break;
2349
2350 default:
2351
2352 frequency = 0U;
2353 break;
2354 }
2355 break;
2356
2357 case RCC_PERIPHCLK_DAC1:
2358 /* Get the current DAC1 kernel source */
2359 srcclk = __HAL_RCC_GET_DAC1_SOURCE();
2360 /* Check if LSE is ready and if DAC1 clock selection is LSE */
2361 if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_DAC1CLKSOURCE_LSE))
2362 {
2363 frequency = LSE_VALUE;
2364 }
2365 /* Check if LSI is ready and if DAC1 clock selection is LSI */
2366 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_DAC1CLKSOURCE_LSI))
2367 {
2368 frequency = LSI_VALUE;
2369 }
2370 /* Clock not enabled for DAC1*/
2371 else
2372 {
2373 frequency = 0U;
2374 }
2375 break;
2376
2377 default:
2378 frequency = 0U;
2379 break;
2380 }
2381 }
2382 return (frequency);
2383 }
2384
2385 /**
2386 * @}
2387 */
2388
2389 /** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions
2390 * @brief Extended Clock management functions
2391 *
2392 @verbatim
2393 ===============================================================================
2394 ##### Extended clock management functions #####
2395 ===============================================================================
2396 [..]
2397 This subsection provides a set of functions allowing to control the
2398 activation or deactivation of MSI PLL-mode, PLL2, PLL3, LSE CSS,
2399 Low speed clock output and clock after wake-up from STOP mode.
2400 @endverbatim
2401 * @{
2402 */
2403
2404 /**
2405 * @brief Enable PLL2.
2406 * @param PLL2Init pointer to an RCC_PLL2InitTypeDef structure that
2407 * contains the configuration information for the PLL2
2408 * @retval HAL status
2409 */
HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef * PLL2Init)2410 HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init)
2411 {
2412 uint32_t tickstart;
2413 HAL_StatusTypeDef status = HAL_OK;
2414
2415 /* check for PLL2 Parameters used to output PLL2CLK */
2416 assert_param(IS_RCC_PLLSOURCE(PLL2Init->PLL2Source));
2417 assert_param(IS_RCC_PLLM_VALUE(PLL2Init->PLL2M));
2418 assert_param(IS_RCC_PLLN_VALUE(PLL2Init->PLL2N));
2419 assert_param(IS_RCC_PLLP_VALUE(PLL2Init->PLL2P));
2420 assert_param(IS_RCC_PLLQ_VALUE(PLL2Init->PLL2Q));
2421 assert_param(IS_RCC_PLLR_VALUE(PLL2Init->PLL2R));
2422 assert_param(IS_RCC_PLL2CLOCKOUT_VALUE(PLL2Init->PLL2ClockOut));
2423
2424 /* Disable the PLL2 */
2425 __HAL_RCC_PLL2_DISABLE();
2426
2427 /* Get Start Tick*/
2428 tickstart = HAL_GetTick();
2429
2430 /* Wait till PLL2 is ready to be updated */
2431 while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != 0U)
2432 {
2433 if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
2434 {
2435 status = HAL_TIMEOUT;
2436 break;
2437 }
2438 }
2439
2440 if (status == HAL_OK)
2441 {
2442 /* Make sure PLL2Source is ready */
2443 status = RCCEx_PLLSource_Enable(PLL2Init->PLL2Source);
2444
2445 if (status == HAL_OK)
2446 {
2447 /* Configure the PLL2 clock source, multiplication factor N, */
2448 /* and division factors M, P, Q and R */
2449 __HAL_RCC_PLL2_CONFIG(PLL2Init->PLL2Source, PLL2Init->PLL2M, PLL2Init->PLL2N,
2450 PLL2Init->PLL2P, PLL2Init->PLL2Q, PLL2Init->PLL2R);
2451
2452 /* Disable PLL2FRACN */
2453 __HAL_RCC_PLL2FRACN_DISABLE();
2454
2455 /* Configure PLL PLL2FRACN */
2456 __HAL_RCC_PLL2FRACN_CONFIG(PLL2Init->PLL2FRACN);
2457
2458 /* Enable PLL2FRACN */
2459 __HAL_RCC_PLL2FRACN_ENABLE();
2460
2461 /* Select PLL2 input reference frequency range: VCI */
2462 __HAL_RCC_PLL2_VCIRANGE(PLL2Init->PLL2RGE);
2463
2464 /* Configure the PLL2 Clock output(s) */
2465 __HAL_RCC_PLL2CLKOUT_ENABLE(PLL2Init->PLL2ClockOut);
2466
2467 /* Enable the PLL2 again by setting PLL2ON to 1*/
2468 __HAL_RCC_PLL2_ENABLE();
2469
2470 /* Get Start Tick*/
2471 tickstart = HAL_GetTick();
2472
2473 /* Wait till PLL2 is ready */
2474 while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) == 0U)
2475 {
2476 if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
2477 {
2478 status = HAL_TIMEOUT;
2479 break;
2480 }
2481 }
2482 }
2483 }
2484 return status;
2485 }
2486
2487 /**
2488 * @brief Disable PLL2.
2489 * @retval HAL status
2490 */
HAL_RCCEx_DisablePLL2(void)2491 HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void)
2492 {
2493 uint32_t tickstart;
2494 HAL_StatusTypeDef status = HAL_OK;
2495
2496 /* Disable the PLL2 */
2497 __HAL_RCC_PLL2_DISABLE();
2498
2499 /* Get Start Tick*/
2500 tickstart = HAL_GetTick();
2501
2502 /* Wait till PLL2 is ready */
2503 while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != 0U)
2504 {
2505 if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
2506 {
2507 status = HAL_TIMEOUT;
2508 break;
2509 }
2510 }
2511
2512 /* To save power disable the PLL2 Source, FRACN and Clock outputs */
2513 CLEAR_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2PEN | RCC_PLL2CFGR_PLL2QEN | RCC_PLL2CFGR_PLL2REN | RCC_PLL2CFGR_PLL2SRC | \
2514 RCC_PLL2CFGR_PLL2FRACEN);
2515
2516 return status;
2517 }
2518
2519 /**
2520 * @brief Enable PLL3.
2521 * @param PLL3Init pointer to an RCC_PLL3InitTypeDef structure that
2522 * contains the configuration information for the PLL3
2523 * @retval HAL status
2524 */
HAL_RCCEx_EnablePLL3(RCC_PLL3InitTypeDef * PLL3Init)2525 HAL_StatusTypeDef HAL_RCCEx_EnablePLL3(RCC_PLL3InitTypeDef *PLL3Init)
2526 {
2527 uint32_t tickstart;
2528 HAL_StatusTypeDef status = HAL_OK;
2529
2530 /* check for PLL3 Parameters used to output PLL3CLK */
2531 assert_param(IS_RCC_PLLSOURCE(PLL3Init->PLL3Source));
2532 assert_param(IS_RCC_PLLM_VALUE(PLL3Init->PLL3M));
2533 assert_param(IS_RCC_PLLN_VALUE(PLL3Init->PLL3N));
2534 assert_param(IS_RCC_PLLP_VALUE(PLL3Init->PLL3P));
2535 assert_param(IS_RCC_PLL3CLOCKOUT_VALUE(PLL3Init->PLL3ClockOut));
2536
2537 /* Disable the PLL3 */
2538 __HAL_RCC_PLL3_DISABLE();
2539
2540 /* Get Start Tick*/
2541 tickstart = HAL_GetTick();
2542
2543 /* Wait till PLL3 is ready to be updated */
2544 while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != 0U)
2545 {
2546 if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE)
2547 {
2548 status = HAL_TIMEOUT;
2549 break;
2550 }
2551 }
2552
2553 if (status == HAL_OK)
2554 {
2555 /* Make sure PLL3Source is ready */
2556 status = RCCEx_PLLSource_Enable(PLL3Init->PLL3Source);
2557
2558 if (status == HAL_OK)
2559 {
2560 /* Configure the PLL3 clock source, multiplication factor N, */
2561 /* and division factors M and P */
2562 __HAL_RCC_PLL3_CONFIG(PLL3Init->PLL3Source, PLL3Init->PLL3M, PLL3Init->PLL3N, PLL3Init->PLL3P, PLL3Init->PLL3Q, \
2563 PLL3Init->PLL3R);
2564
2565 /* Disable PLL3FRACN . */
2566 __HAL_RCC_PLL3FRACN_DISABLE();
2567
2568 /* Configure PLL PLL3FRACN */
2569 __HAL_RCC_PLL3FRACN_CONFIG(PLL3Init->PLL3FRACN);
2570
2571 /* Enable PLL3FRACN . */
2572 __HAL_RCC_PLL3FRACN_ENABLE();
2573
2574 /* Select PLL3 input reference frequency range: VCI */
2575 __HAL_RCC_PLL3_VCIRANGE(PLL3Init->PLL3RGE);
2576
2577 /* Configure the PLL3 Clock output(s) */
2578 __HAL_RCC_PLL3CLKOUT_ENABLE(PLL3Init->PLL3ClockOut);
2579
2580 /* Enable the PLL3 again by setting PLL3ON to 1*/
2581 __HAL_RCC_PLL3_ENABLE();
2582
2583 /* Get Start Tick*/
2584 tickstart = HAL_GetTick();
2585
2586 /* Wait till PLL3 is ready */
2587 while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) == 0U)
2588 {
2589 if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE)
2590 {
2591 status = HAL_TIMEOUT;
2592 break;
2593 }
2594 }
2595 }
2596 }
2597 return status;
2598 }
2599
2600 /**
2601 * @brief Disable PLL3.
2602 * @retval HAL status
2603 */
HAL_RCCEx_DisablePLL3(void)2604 HAL_StatusTypeDef HAL_RCCEx_DisablePLL3(void)
2605 {
2606 uint32_t tickstart;
2607 HAL_StatusTypeDef status = HAL_OK;
2608
2609 /* Disable the PLL3 */
2610 __HAL_RCC_PLL3_DISABLE();
2611
2612 /* Get Start Tick*/
2613 tickstart = HAL_GetTick();
2614
2615 /* Wait till PLL3 is ready */
2616 while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != 0U)
2617 {
2618 if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE)
2619 {
2620 status = HAL_TIMEOUT;
2621 break;
2622 }
2623 }
2624
2625 /* To save power disable the PLL3 Source and Clock outputs */
2626 CLEAR_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3PEN | RCC_PLL3CFGR_PLL3QEN | RCC_PLL3CFGR_PLL3REN | RCC_PLL3CFGR_PLL3SRC | \
2627 RCC_PLL3CFGR_PLL3FRACEN);
2628
2629 return status;
2630 }
2631
2632 /**
2633 * @brief Select which MSI output clock uses the PLL mode.
2634 * @note Prior to disable PLL-mode (MSIPLLEN = 0) before call HAL_RCCEx_EnableMSIPLLModeSelection.
2635 * @note The MSI kernel clock output uses the same oscillator source than the MSI system
2636 * clock output, then the PLL mode is applied to the both clocks outputs.
2637 * @param MSIPLLModeSelection specifies which MSI output clock uses the PLL mode.
2638 * This parameter can be one of the following values:
2639 * @arg @ref RCC_MSISPLL_MODE_SEL PLL mode applied to MSIS (MSI system) clock output
2640 * @arg @ref RCC_MSIKPLL_MODE_SEL PLL mode applied to MSIK (MSI kernel) clock output
2641 * @retval HAL status
2642 */
HAL_RCCEx_EnableMSIPLLModeSelection(uint32_t MSIPLLModeSelection)2643 HAL_StatusTypeDef HAL_RCCEx_EnableMSIPLLModeSelection(uint32_t MSIPLLModeSelection)
2644 {
2645 HAL_StatusTypeDef status = HAL_ERROR;
2646
2647 assert_param(IS_RCC_MSIPLLMODE_SELECT(MSIPLLModeSelection));
2648 if (READ_BIT(RCC->CR, RCC_CR_MSIPLLEN) == 0U)
2649 {
2650 /* This bit is used only if PLL mode is disabled (MSIPLLEN = 0) */
2651 if (MSIPLLModeSelection == RCC_MSISPLL_MODE_SEL)
2652 {
2653 SET_BIT(RCC->CR, RCC_CR_MSIPLLSEL);
2654 }
2655 else
2656 {
2657 CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLSEL);
2658 }
2659 status = HAL_OK;
2660 }
2661
2662 return status;
2663 }
2664
2665 /**
2666 * @brief Enable the fast PLL mode start-up of the MSI clock
2667 * @note Prior to enable PLL-mode (MSIPLLEN = 1) before call HAL_RCCEx_EnableMSIPLLFastStartup.
2668 * @note The fast start-up feature is not active the first time the PLL mode is selected. The
2669 * fast start-up is active when the MSI in PLL mode returns from switch off.
2670 * @retval HAL status
2671 */
HAL_RCCEx_EnableMSIPLLFastStartup(void)2672 HAL_StatusTypeDef HAL_RCCEx_EnableMSIPLLFastStartup(void)
2673 {
2674 HAL_StatusTypeDef status = HAL_ERROR;
2675
2676 if (READ_BIT(RCC->CR, RCC_CR_MSIPLLEN) == RCC_CR_MSIPLLEN)
2677 {
2678 /* This bit is used only if PLL mode is selected (MSIPLLEN = 1) */
2679 SET_BIT(RCC->CR, RCC_CR_MSIPLLFAST);
2680 status = HAL_OK;
2681 }
2682
2683 return status;
2684 }
2685
2686 /**
2687 * @brief Disable the fast PLL mode start-up of the MSI clock
2688 * @note the MSI fast startup mode disabled only when PLL-mode is enabled
2689 * @retval HAL status
2690 */
HAL_RCCEx_DisableMSIPLLFastStartup(void)2691 HAL_StatusTypeDef HAL_RCCEx_DisableMSIPLLFastStartup(void)
2692 {
2693 HAL_StatusTypeDef status = HAL_ERROR;
2694
2695 if (READ_BIT(RCC->CR, RCC_CR_MSIPLLEN) == RCC_CR_MSIPLLEN)
2696 {
2697 /* This bit is used only if PLL mode is selected (MSIPLLEN = 1) */
2698 CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLFAST);
2699 status = HAL_OK;
2700 }
2701 return status;
2702 }
2703
2704 /**
2705 * @brief Configure the oscillator clock source for wakeup from Stop and CSS backup clock.
2706 * @param WakeUpClk Wakeup clock
2707 * This parameter can be one of the following values:
2708 * @arg @ref RCC_STOP_WAKEUPCLOCK_MSI MSI oscillator selection
2709 * @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI oscillator selection
2710 * @note This function shall not be called after the Clock Security System on HSE has been
2711 * enabled.
2712 * @retval None
2713 */
HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk)2714 void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk)
2715 {
2716 assert_param(IS_RCC_STOP_WAKEUPCLOCK(WakeUpClk));
2717
2718 __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(WakeUpClk);
2719 }
2720
2721 /**
2722 * @brief Configure the oscillator Kernel clock source for wakeup from Stop
2723 * @param WakeUpClk: Kernel Wakeup clock
2724 * This parameter can be one of the following values:
2725 * @arg RCC_STOP_KERWAKEUPCLOCK_MSI: MSI oscillator selection
2726 * @arg RCC_STOP_KERWAKEUPCLOCK_HSI: HSI oscillator selection
2727 * @retval None
2728 */
HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk)2729 void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk)
2730 {
2731 assert_param(IS_RCC_STOP_KERWAKEUPCLOCK(WakeUpClk));
2732
2733 __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(WakeUpClk);
2734 }
2735
2736 /**
2737 * @brief Configure the MSI range after standby mode.
2738 * @note After Standby its frequency can be selected between 3 possible values (1, 3.072 or 4 MHz).
2739 * @param MSIRange MSI range
2740 * This parameter can be one of the following values:
2741 * @arg @ref RCC_MSIRANGE_4 Range 4 around 4 MHz (reset value)
2742 * @arg @ref RCC_MSIRANGE_5 Range 5 around 2 MHz
2743 * @arg @ref RCC_MSIRANGE_6 Range 6 around 1.5 MHz
2744 * @arg @ref RCC_MSIRANGE_7 Range 7 around 1 MHz
2745 * @arg @ref RCC_MSIRANGE_8 Range 8 around 3.072 MHz
2746 * @retval None
2747 */
HAL_RCCEx_StandbyMSIRangeConfig(uint32_t MSIRange)2748 void HAL_RCCEx_StandbyMSIRangeConfig(uint32_t MSIRange)
2749 {
2750 assert_param(IS_RCC_MSI_STANDBY_CLOCK_RANGE(MSIRange));
2751
2752 __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(MSIRange);
2753 }
2754
2755 /**
2756 * @brief Enable the LSE Clock Security System.
2757 * @note Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled
2758 * with HAL_RCC_OscConfig() and the LSE oscillator clock is to be selected as RTC
2759 * clock with HAL_RCCEx_PeriphCLKConfig().
2760 * @retval None
2761 */
HAL_RCCEx_EnableLSECSS(void)2762 void HAL_RCCEx_EnableLSECSS(void)
2763 {
2764 SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
2765 }
2766
2767 /**
2768 * @brief Disable the LSE Clock Security System.
2769 * @note LSE Clock Security System can only be disabled after a LSE failure detection.
2770 * @retval None
2771 */
HAL_RCCEx_DisableLSECSS(void)2772 void HAL_RCCEx_DisableLSECSS(void)
2773 {
2774 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
2775 }
2776
2777 /**
2778 * @brief Handle the RCC LSE Clock Security System interrupt request.
2779 * @retval None
2780 */
HAL_RCCEx_LSECSS_IRQHandler(void)2781 void HAL_RCCEx_LSECSS_IRQHandler(void)
2782 {
2783 if (READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) != 0U)
2784 {
2785 /* RCC LSE Clock Security System interrupt user callback */
2786 HAL_RCCEx_LSECSS_Callback();
2787 }
2788 }
2789
2790 /**
2791 * @brief RCCEx LSE Clock Security System interrupt callback.
2792 * @retval none
2793 */
HAL_RCCEx_LSECSS_Callback(void)2794 __weak void HAL_RCCEx_LSECSS_Callback(void)
2795 {
2796 /* NOTE : This function should not be modified, when the callback is needed,
2797 the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file
2798 */
2799 }
2800
2801 /**
2802 * @brief Select the Low Speed clock source to output on LSCO pin (PA2).
2803 * @param LSCOSource specifies the Low Speed clock source to output.
2804 * This parameter can be one of the following values:
2805 * @arg @ref RCC_LSCOSOURCE_LSI LSI clock selected as LSCO source
2806 * @arg @ref RCC_LSCOSOURCE_LSE LSE clock selected as LSCO source
2807 * @retval None
2808 */
HAL_RCCEx_EnableLSCO(uint32_t LSCOSource)2809 void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource)
2810 {
2811 GPIO_InitTypeDef gpio_initstruct;
2812 FlagStatus pwrclkchanged = RESET;
2813 FlagStatus backupchanged = RESET;
2814
2815 /* Check the parameters */
2816 assert_param(IS_RCC_LSCOSOURCE(LSCOSource));
2817
2818 /* LSCO Pin Clock Enable */
2819 LSCO_CLK_ENABLE();
2820
2821 /* Configure the LSCO pin in analog mode */
2822 gpio_initstruct.Pin = LSCO_PIN;
2823 gpio_initstruct.Mode = GPIO_MODE_ANALOG;
2824 gpio_initstruct.Speed = GPIO_SPEED_FREQ_HIGH;
2825 gpio_initstruct.Pull = GPIO_NOPULL;
2826 HAL_GPIO_Init(LSCO_GPIO_PORT, &gpio_initstruct);
2827
2828 /* Update LSCOSEL clock source in Backup Domain control register */
2829 if (__HAL_RCC_PWR_IS_CLK_DISABLED())
2830 {
2831 __HAL_RCC_PWR_CLK_ENABLE();
2832 pwrclkchanged = SET;
2833 }
2834 if (HAL_IS_BIT_CLR(PWR->DBPR, PWR_DBPR_DBP))
2835 {
2836 HAL_PWR_EnableBkUpAccess();
2837 backupchanged = SET;
2838 }
2839
2840 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL | RCC_BDCR_LSCOEN, LSCOSource | RCC_BDCR_LSCOEN);
2841
2842 if (backupchanged == SET)
2843 {
2844 HAL_PWR_DisableBkUpAccess();
2845 }
2846 if (pwrclkchanged == SET)
2847 {
2848 __HAL_RCC_PWR_CLK_DISABLE();
2849 }
2850 }
2851
2852 /**
2853 * @brief Disable the Low Speed clock output.
2854 * @retval None
2855 */
HAL_RCCEx_DisableLSCO(void)2856 void HAL_RCCEx_DisableLSCO(void)
2857 {
2858 FlagStatus pwrclkchanged = RESET;
2859 FlagStatus backupchanged = RESET;
2860
2861 /* Update LSCOEN bit in Backup Domain control register */
2862 if (__HAL_RCC_PWR_IS_CLK_DISABLED())
2863 {
2864 __HAL_RCC_PWR_CLK_ENABLE();
2865 pwrclkchanged = SET;
2866 }
2867 if (HAL_IS_BIT_CLR(PWR->DBPR, PWR_DBPR_DBP))
2868 {
2869 /* Enable access to the backup domain */
2870 HAL_PWR_EnableBkUpAccess();
2871 backupchanged = SET;
2872 }
2873
2874 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
2875
2876 /* Restore previous configuration */
2877 if (backupchanged == SET)
2878 {
2879 /* Disable access to the backup domain */
2880 HAL_PWR_DisableBkUpAccess();
2881 }
2882 if (pwrclkchanged == SET)
2883 {
2884 __HAL_RCC_PWR_CLK_DISABLE();
2885 }
2886 }
2887
2888 /**
2889 * @brief Enable the PLL-mode of the MSI.
2890 * @note Prior to enable the PLL-mode of the MSI for automatic hardware
2891 * calibration LSE oscillator is to be enabled with HAL_RCC_OscConfig().
2892 * @retval None
2893 */
HAL_RCCEx_EnableMSIPLLMode(void)2894 void HAL_RCCEx_EnableMSIPLLMode(void)
2895 {
2896 SET_BIT(RCC->CR, RCC_CR_MSIPLLEN);
2897 }
2898
2899 /**
2900 * @brief Disable the PLL-mode of the MSI.
2901 * @note PLL-mode of the MSI is automatically reset when LSE oscillator is disabled.
2902 * @retval None
2903 */
HAL_RCCEx_DisableMSIPLLMode(void)2904 void HAL_RCCEx_DisableMSIPLLMode(void)
2905 {
2906 CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLEN);
2907 }
2908
2909 /**
2910 * @}
2911 */
2912
2913 #if defined(CRS)
2914
2915 /** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions
2916 * @brief Extended Clock Recovery System Control functions
2917 *
2918 @verbatim
2919 ===============================================================================
2920 ##### Extended Clock Recovery System Control functions #####
2921 ===============================================================================
2922 [..]
2923 For devices with Clock Recovery System feature (CRS), RCC Extension HAL driver can be used as follows:
2924
2925 (#) In System clock config, HSI48 needs to be enabled
2926
2927 (#) Enable CRS clock in IP MSP init which will use CRS functions
2928
2929 (#) Call CRS functions as follows:
2930 (##) Prepare synchronization configuration necessary for HSI48 calibration
2931 (+++) Default values can be set for frequency Error Measurement (reload and error limit)
2932 and also HSI48 oscillator smooth trimming.
2933 (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate
2934 directly reload value with target and sychronization frequencies values
2935 (##) Call function HAL_RCCEx_CRSConfig which
2936 (+++) Resets CRS registers to their default values.
2937 (+++) Configures CRS registers with synchronization configuration
2938 (+++) Enables automatic calibration and frequency error counter feature
2939 Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the
2940 periodic USB SOF will not be generated by the host. No SYNC signal will therefore be
2941 provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock
2942 precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs
2943 should be used as SYNC signal.
2944
2945 (##) A polling function is provided to wait for complete synchronization
2946 (+++) Call function HAL_RCCEx_CRSWaitSynchronization()
2947 (+++) According to CRS status, user can decide to adjust again the calibration or continue
2948 application if synchronization is OK
2949
2950 (#) User can retrieve information related to synchronization in calling function
2951 HAL_RCCEx_CRSGetSynchronizationInfo()
2952
2953 (#) Regarding synchronization status and synchronization information, user can try a new calibration
2954 in changing synchronization configuration and call again HAL_RCCEx_CRSConfig.
2955 Note: When the SYNC event is detected during the downcounting phase (before reaching the zero value),
2956 it means that the actual frequency is lower than the target (and so, that the TRIM value should be
2957 incremented), while when it is detected during the upcounting phase it means that the actual frequency
2958 is higher (and that the TRIM value should be decremented).
2959
2960 (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go
2961 through CRS Handler (CRS_IRQn/CRS_IRQHandler)
2962 (++) Call function HAL_RCCEx_CRSConfig()
2963 (++) Enable CRS_IRQn (thanks to NVIC functions)
2964 (++) Enable CRS interrupt (__HAL_RCC_CRS_ENABLE_IT)
2965 (++) Implement CRS status management in the following user callbacks called from
2966 HAL_RCCEx_CRS_IRQHandler():
2967 (+++) HAL_RCCEx_CRS_SyncOkCallback()
2968 (+++) HAL_RCCEx_CRS_SyncWarnCallback()
2969 (+++) HAL_RCCEx_CRS_ExpectedSyncCallback()
2970 (+++) HAL_RCCEx_CRS_ErrorCallback()
2971
2972 (#) To force a SYNC EVENT, user can use the function HAL_RCCEx_CRSSoftwareSynchronizationGenerate().
2973 This function can be called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler)
2974
2975 @endverbatim
2976 * @{
2977 */
2978
2979 /**
2980 * @brief Start automatic synchronization for polling mode
2981 * @param pInit Pointer on RCC_CRSInitTypeDef structure
2982 * @retval None
2983 */
HAL_RCCEx_CRSConfig(const RCC_CRSInitTypeDef * const pInit)2984 void HAL_RCCEx_CRSConfig(const RCC_CRSInitTypeDef *const pInit)
2985 {
2986 uint32_t value;
2987
2988 /* Check the parameters */
2989 assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler));
2990 assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source));
2991 assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity));
2992 assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue));
2993 assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue));
2994 assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue));
2995
2996 /* CONFIGURATION */
2997
2998 /* Before configuration, reset CRS registers to their default values*/
2999 __HAL_RCC_CRS_FORCE_RESET();
3000 __HAL_RCC_CRS_RELEASE_RESET();
3001
3002 /* Set the SYNCDIV[2:0] bits according to Prescaler value */
3003 /* Set the SYNCSRC[1:0] bits according to Source value */
3004 /* Set the SYNCSPOL bit according to Polarity value */
3005 value = (pInit->Prescaler | pInit->Source | pInit->Polarity);
3006 /* Set the RELOAD[15:0] bits according to ReloadValue value */
3007 value |= pInit->ReloadValue;
3008 /* Set the FELIM[7:0] bits according to ErrorLimitValue value */
3009 value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_Pos);
3010 WRITE_REG(CRS->CFGR, value);
3011
3012 /* Adjust HSI48 oscillator smooth trimming */
3013 /* Set the TRIM[5:0] bits according to RCC_CRS_HSI48CalibrationValue value */
3014 MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_Pos));
3015
3016 /* START AUTOMATIC SYNCHRONIZATION*/
3017
3018 /* Enable Automatic trimming & Frequency error counter */
3019 SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN);
3020 }
3021
3022 /**
3023 * @brief Generate the software synchronization event
3024 * @retval None
3025 */
HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void)3026 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void)
3027 {
3028 SET_BIT(CRS->CR, CRS_CR_SWSYNC);
3029 }
3030
3031 /**
3032 * @brief Return synchronization info
3033 * @param pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure
3034 * @retval None
3035 */
HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef * pSynchroInfo)3036 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo)
3037 {
3038 /* Check the parameter */
3039 assert_param(pSynchroInfo != (void *) NULL);
3040
3041 /* Get the reload value */
3042 pSynchroInfo->ReloadValue = (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
3043
3044 /* Get HSI48 oscillator smooth trimming */
3045 pSynchroInfo->HSI48CalibrationValue = (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos);
3046
3047 /* Get Frequency error capture */
3048 pSynchroInfo->FreqErrorCapture = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos);
3049
3050 /* Get Frequency error direction */
3051 pSynchroInfo->FreqErrorDirection = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
3052 }
3053
3054 /**
3055 * @brief Wait for CRS Synchronization status.
3056 * @param Timeout Duration of the timeout
3057 * @note Timeout is based on the maximum time to receive a SYNC event based on synchronization
3058 * frequency.
3059 * @note If Timeout set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned.
3060 * @retval Combination of Synchronization status
3061 * This parameter can be a combination of the following values:
3062 * @arg @ref RCC_CRS_TIMEOUT
3063 * @arg @ref RCC_CRS_SYNCOK
3064 * @arg @ref RCC_CRS_SYNCWARN
3065 * @arg @ref RCC_CRS_SYNCERR
3066 * @arg @ref RCC_CRS_SYNCMISS
3067 * @arg @ref RCC_CRS_TRIMOVF
3068 */
HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)3069 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
3070 {
3071 uint32_t crsstatus = RCC_CRS_NONE;
3072 uint32_t tickstart;
3073
3074 /* Get timeout */
3075 tickstart = HAL_GetTick();
3076
3077 /* Wait for CRS flag or timeout detection */
3078 do
3079 {
3080 if (Timeout != HAL_MAX_DELAY)
3081 {
3082 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
3083 {
3084 crsstatus = RCC_CRS_TIMEOUT;
3085 }
3086 }
3087 /* Check CRS SYNCOK flag */
3088 if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK))
3089 {
3090 /* CRS SYNC event OK */
3091 crsstatus |= RCC_CRS_SYNCOK;
3092
3093 /* Clear CRS SYNC event OK bit */
3094 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK);
3095 }
3096
3097 /* Check CRS SYNCWARN flag */
3098 if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN))
3099 {
3100 /* CRS SYNC warning */
3101 crsstatus |= RCC_CRS_SYNCWARN;
3102
3103 /* Clear CRS SYNCWARN bit */
3104 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN);
3105 }
3106
3107 /* Check CRS TRIM overflow flag */
3108 if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF))
3109 {
3110 /* CRS SYNC Error */
3111 crsstatus |= RCC_CRS_TRIMOVF;
3112
3113 /* Clear CRS Error bit */
3114 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF);
3115 }
3116
3117 /* Check CRS Error flag */
3118 if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR))
3119 {
3120 /* CRS SYNC Error */
3121 crsstatus |= RCC_CRS_SYNCERR;
3122
3123 /* Clear CRS Error bit */
3124 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR);
3125 }
3126
3127 /* Check CRS SYNC Missed flag */
3128 if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS))
3129 {
3130 /* CRS SYNC Missed */
3131 crsstatus |= RCC_CRS_SYNCMISS;
3132
3133 /* Clear CRS SYNC Missed bit */
3134 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS);
3135 }
3136
3137 /* Check CRS Expected SYNC flag */
3138 if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC))
3139 {
3140 /* frequency error counter reached a zero value */
3141 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC);
3142 }
3143 } while (RCC_CRS_NONE == crsstatus);
3144
3145 return crsstatus;
3146 }
3147
3148 /**
3149 * @brief Handle the Clock Recovery System interrupt request.
3150 * @retval None
3151 */
HAL_RCCEx_CRS_IRQHandler(void)3152 void HAL_RCCEx_CRS_IRQHandler(void)
3153 {
3154 uint32_t crserror = RCC_CRS_NONE;
3155 /* Get current IT flags and IT sources values */
3156 uint32_t itflags = READ_REG(CRS->ISR);
3157 uint32_t itsources = READ_REG(CRS->CR);
3158
3159 /* Check CRS SYNCOK flag */
3160 if (((itflags & RCC_CRS_FLAG_SYNCOK) != 0U) && ((itsources & RCC_CRS_IT_SYNCOK) != 0U))
3161 {
3162 /* Clear CRS SYNC event OK flag */
3163 WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
3164
3165 /* user callback */
3166 HAL_RCCEx_CRS_SyncOkCallback();
3167 }
3168 /* Check CRS SYNCWARN flag */
3169 else if (((itflags & RCC_CRS_FLAG_SYNCWARN) != 0U) && ((itsources & RCC_CRS_IT_SYNCWARN) != 0U))
3170 {
3171 /* Clear CRS SYNCWARN flag */
3172 WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
3173
3174 /* user callback */
3175 HAL_RCCEx_CRS_SyncWarnCallback();
3176 }
3177 /* Check CRS Expected SYNC flag */
3178 else if (((itflags & RCC_CRS_FLAG_ESYNC) != 0U) && ((itsources & RCC_CRS_IT_ESYNC) != 0U))
3179 {
3180 /* frequency error counter reached a zero value */
3181 WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
3182
3183 /* user callback */
3184 HAL_RCCEx_CRS_ExpectedSyncCallback();
3185 }
3186 /* Check CRS Error flags */
3187 else
3188 {
3189 if (((itflags & RCC_CRS_FLAG_ERR) != 0U) && ((itsources & RCC_CRS_IT_ERR) != 0U))
3190 {
3191 if ((itflags & RCC_CRS_FLAG_SYNCERR) != 0U)
3192 {
3193 crserror |= RCC_CRS_SYNCERR;
3194 }
3195 if ((itflags & RCC_CRS_FLAG_SYNCMISS) != 0U)
3196 {
3197 crserror |= RCC_CRS_SYNCMISS;
3198 }
3199 if ((itflags & RCC_CRS_FLAG_TRIMOVF) != 0U)
3200 {
3201 crserror |= RCC_CRS_TRIMOVF;
3202 }
3203
3204 /* Clear CRS Error flags */
3205 WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
3206
3207 /* user error callback */
3208 HAL_RCCEx_CRS_ErrorCallback(crserror);
3209 }
3210 }
3211 }
3212
3213 /**
3214 * @brief RCCEx Clock Recovery System SYNCOK interrupt callback.
3215 * @retval none
3216 */
HAL_RCCEx_CRS_SyncOkCallback(void)3217 __weak void HAL_RCCEx_CRS_SyncOkCallback(void)
3218 {
3219 /* NOTE : This function should not be modified, when the callback is needed,
3220 the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the user file
3221 */
3222 }
3223
3224 /**
3225 * @brief RCCEx Clock Recovery System SYNCWARN interrupt callback.
3226 * @retval none
3227 */
HAL_RCCEx_CRS_SyncWarnCallback(void)3228 __weak void HAL_RCCEx_CRS_SyncWarnCallback(void)
3229 {
3230 /* NOTE : This function should not be modified, when the callback is needed,
3231 the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file
3232 */
3233 }
3234
3235 /**
3236 * @brief RCCEx Clock Recovery System Expected SYNC interrupt callback.
3237 * @retval none
3238 */
HAL_RCCEx_CRS_ExpectedSyncCallback(void)3239 __weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void)
3240 {
3241 /* NOTE : This function should not be modified, when the callback is needed,
3242 the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file
3243 */
3244 }
3245
3246 /**
3247 * @brief RCCEx Clock Recovery System Error interrupt callback.
3248 * @param Error Combination of Error status.
3249 * This parameter can be a combination of the following values:
3250 * @arg @ref RCC_CRS_SYNCERR
3251 * @arg @ref RCC_CRS_SYNCMISS
3252 * @arg @ref RCC_CRS_TRIMOVF
3253 * @retval none
3254 */
HAL_RCCEx_CRS_ErrorCallback(uint32_t Error)3255 __weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error)
3256 {
3257 /* Prevent unused argument(s) compilation warning */
3258 UNUSED(Error);
3259
3260 /* NOTE : This function should not be modified, when the callback is needed,
3261 the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the user file
3262 */
3263 }
3264
3265 /**
3266 * @}
3267 */
3268
3269 #endif /* CRS */
3270
3271 /**
3272 * @}
3273 */
3274
3275 /** @addtogroup RCCEx_Private_Functions
3276 * @{
3277 */
3278 /**
3279 * @brief Configure the PLL 1 source clock.
3280 * @param PllSource PLL1 source clock it can be :
3281 * RCC_PLLSOURCE_NONE
3282 * RCC_PLLSOURCE_MSI
3283 * RCC_PLLSOURCE_HSI
3284 * RCC_PLLSOURCE_HSE
3285 *
3286 * @retval HAL status
3287 */
RCCEx_PLLSource_Enable(uint32_t PllSource)3288 static HAL_StatusTypeDef RCCEx_PLLSource_Enable(uint32_t PllSource)
3289 {
3290 uint32_t tickstart;
3291 HAL_StatusTypeDef status = HAL_OK;
3292
3293 switch (PllSource)
3294 {
3295 case RCC_PLLSOURCE_MSI:
3296 /* Check whether MSI in not ready and enable it */
3297 if (READ_BIT(RCC->CR, RCC_CR_MSISRDY) == 0U)
3298 {
3299 /* Enable the Internal Multi Speed oscillator (MSI). */
3300 __HAL_RCC_MSI_ENABLE();
3301
3302 /* Get timeout */
3303 tickstart = HAL_GetTick();
3304
3305 /* Wait till MSI is ready */
3306 while (READ_BIT(RCC->CR, RCC_CR_MSISRDY) == 0U)
3307 {
3308 if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
3309 {
3310 status = HAL_TIMEOUT;
3311 break;
3312 }
3313 }
3314 }
3315 break;
3316
3317 case RCC_PLLSOURCE_HSI:
3318 /* Check whether HSI in not ready and enable it */
3319 if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
3320 {
3321 /* Enable the Internal High Speed oscillator (HSI) */
3322 __HAL_RCC_HSI_ENABLE();
3323
3324 /* Get timeout */
3325 tickstart = HAL_GetTick();
3326
3327 /* Wait till MSI is ready */
3328 while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
3329 {
3330 if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
3331 {
3332 status = HAL_TIMEOUT;
3333 break;
3334 }
3335 }
3336 }
3337 break;
3338
3339 case RCC_PLLSOURCE_HSE:
3340 /* Check whether HSE in not ready and enable it */
3341 if (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
3342 {
3343 /* Enable the External High Speed oscillator (HSE) */
3344 SET_BIT(RCC->CR, RCC_CR_HSEON);
3345
3346 /* Get Start Tick*/
3347 tickstart = HAL_GetTick();
3348
3349 /* Wait till HSE is ready */
3350 while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
3351 {
3352 if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
3353 {
3354 status = HAL_TIMEOUT;
3355 break;
3356 }
3357 }
3358 }
3359 break;
3360
3361 default:
3362 status = HAL_ERROR;
3363 break;
3364 }
3365
3366 return status;
3367 }
3368
3369 /**
3370 * @brief Configure the PLL2 VCI ranges, multiplication and division factors and enable it
3371 * @param pll2: Pointer to an RCC_PLL2InitTypeDef structure that
3372 * contains the configuration parameters as well as VCI clock ranges.
3373 * @note PLL2 is temporary disable to apply new parameters
3374 *
3375 * @retval HAL status
3376 */
RCCEx_PLL2_Config(RCC_PLL2InitTypeDef * pll2)3377 static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2)
3378 {
3379
3380 uint32_t tickstart;
3381 assert_param(IS_RCC_PLLSOURCE(pll2->PLL2Source));
3382 assert_param(IS_RCC_PLLM_VALUE(pll2->PLL2M));
3383 assert_param(IS_RCC_PLLN_VALUE(pll2->PLL2N));
3384 assert_param(IS_RCC_PLLP_VALUE(pll2->PLL2P));
3385 assert_param(IS_RCC_PLLQ_VALUE(pll2->PLL2Q));
3386 assert_param(IS_RCC_PLLR_VALUE(pll2->PLL2R));
3387
3388 /* Disable PLL2 */
3389 __HAL_RCC_PLL2_DISABLE();
3390
3391 /* Get Start Tick*/
3392 tickstart = HAL_GetTick();
3393
3394 /* Wait till PLL is ready */
3395 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U)
3396 {
3397 if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
3398 {
3399 return HAL_TIMEOUT;
3400 }
3401 }
3402
3403 /* Configure PLL2 multiplication and division factors */
3404 __HAL_RCC_PLL2_CONFIG(pll2->PLL2Source,
3405 pll2->PLL2M,
3406 pll2->PLL2N,
3407 pll2->PLL2P,
3408 pll2->PLL2Q,
3409 pll2->PLL2R);
3410
3411 /* Select PLL2 input reference frequency range: VCI */
3412 __HAL_RCC_PLL2_VCIRANGE(pll2->PLL2RGE);
3413
3414 /* Configure the PLL2 Clock output(s) */
3415 __HAL_RCC_PLL2CLKOUT_ENABLE(pll2->PLL2ClockOut);
3416
3417 /* Disable PLL2FRACN */
3418 __HAL_RCC_PLL2FRACN_DISABLE();
3419
3420 /* Configures PLL2 clock Fractional Part Of The Multiplication Factor */
3421 __HAL_RCC_PLL2FRACN_CONFIG(pll2->PLL2FRACN);
3422
3423 /* Enable PLL2FRACN */
3424 __HAL_RCC_PLL2FRACN_ENABLE();
3425
3426 /* Enable PLL2 */
3427 __HAL_RCC_PLL2_ENABLE();
3428
3429 /* Get Start Tick*/
3430 tickstart = HAL_GetTick();
3431
3432 /* Wait till PLL2 is ready */
3433 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U)
3434 {
3435 if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
3436 {
3437 return HAL_TIMEOUT;
3438 }
3439 }
3440 return HAL_OK;
3441
3442 }
3443
3444 /**
3445 * @brief Configure the parameters N & P & optionally M of PLL3 and enable PLL3 output clock(s).
3446 * @param pll3 pointer to an RCC_PLL3InitTypeDef structure that
3447 * contains the configuration parameters N & P & optionally M as well as PLL3 output clock(s)
3448 * @note PLL3 is temporary disable to apply new parameters
3449 * @retval HAL status
3450 */
RCCEx_PLL3_Config(RCC_PLL3InitTypeDef * pll3)3451 static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3)
3452 {
3453 uint32_t tickstart;
3454 assert_param(IS_RCC_PLLSOURCE(pll3->PLL3Source));
3455 assert_param(IS_RCC_PLLM_VALUE(pll3->PLL3M));
3456 assert_param(IS_RCC_PLLN_VALUE(pll3->PLL3N));
3457 assert_param(IS_RCC_PLLP_VALUE(pll3->PLL3P));
3458 assert_param(IS_RCC_PLLQ_VALUE(pll3->PLL3Q));
3459 assert_param(IS_RCC_PLLR_VALUE(pll3->PLL3R));
3460
3461 /* Disable PLL3 */
3462 __HAL_RCC_PLL3_DISABLE();
3463
3464 /* Get Start Tick*/
3465 tickstart = HAL_GetTick();
3466
3467 /* Wait till PLL is ready */
3468 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U)
3469 {
3470 if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE)
3471 {
3472 return HAL_TIMEOUT;
3473 }
3474 }
3475
3476 /* Configure PLL3 multiplication and division factors */
3477 __HAL_RCC_PLL3_CONFIG(pll3->PLL3Source,
3478 pll3->PLL3M,
3479 pll3->PLL3N,
3480 pll3->PLL3P,
3481 pll3->PLL3Q,
3482 pll3->PLL3R);
3483
3484 /* Select PLL3 input reference frequency range: VCI */
3485 __HAL_RCC_PLL3_VCIRANGE(pll3->PLL3RGE);
3486
3487 /* Configure the PLL3 Clock output(s) */
3488 __HAL_RCC_PLL3CLKOUT_ENABLE(pll3->PLL3ClockOut);
3489
3490 /* Disable PLL3FRACN */
3491 __HAL_RCC_PLL3FRACN_DISABLE();
3492
3493 /* Configures PLL3 clock Fractional Part Of The Multiplication Factor */
3494 __HAL_RCC_PLL3FRACN_CONFIG(pll3->PLL3FRACN);
3495
3496 /* Enable PLL3FRACN */
3497 __HAL_RCC_PLL3FRACN_ENABLE();
3498
3499 /* Enable PLL3 */
3500 __HAL_RCC_PLL3_ENABLE();
3501
3502 /* Get Start Tick*/
3503 tickstart = HAL_GetTick();
3504
3505 /* Wait till PLL3 is ready */
3506 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U)
3507 {
3508 if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE)
3509 {
3510 return HAL_TIMEOUT;
3511 }
3512 }
3513 return HAL_OK;
3514 }
3515
3516 /**
3517 * @}
3518 */
3519
3520 #endif /* HAL_RCC_MODULE_ENABLED */
3521 /**
3522 * @}
3523 */
3524
3525 /**
3526 * @}
3527 */
3528
3529 /**
3530 * @}
3531 */
3532
3533
