1 /**
2 ******************************************************************************
3 * @file stm32u5xx_hal_rcc.c
4 * @author MCD Application Team
5 * @brief RCC HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Reset and Clock Control (RCC) peripheral:
8 * + Initialization and de-initialization functions
9 * + Peripheral Control functions
10 *
11 ******************************************************************************
12 * @attention
13 *
14 * Copyright (c) 2021 STMicroelectronics.
15 * All rights reserved.
16 *
17 * This software component is licensed by ST under BSD 3-Clause license,
18 * the "License"; You may not use this file except in compliance with the
19 * License. You may obtain a copy of the License at:
20 * opensource.org/licenses/BSD-3-Clause
21 *
22 ******************************************************************************
23 @verbatim
24 ==============================================================================
25 ##### RCC specific features #####
26 ==============================================================================
27 [..]
28 After reset the device is running from Multiple Speed Internal oscillator
29 (4 MHz) with Flash 0 wait state. Flash prefetch buffer, D-Cache
30 and I-Cache are disabled, and all peripherals are off except internal
31 SRAM, Flash and JTAG.
32
33 (+) There is no prescaler on High speed (AHBs) and Low speed (APBs) busses:
34 all peripherals mapped on these busses are running at MSI speed.
35 (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
36 (+) All GPIOs are in analog mode, except the JTAG pins which
37 are assigned to be used for debug purpose.
38
39 [..]
40 Once the device started from reset, the user application has to:
41 (+) Configure the clock source to be used to drive the System clock
42 (if the application needs higher frequency/performance)
43 (+) Configure the System clock frequency and Flash settings
44 (+) Configure the AHB and APB busses prescalers
45 (+) Enable the clock for the peripheral(s) to be used
46 (+) Configure the clock source(s) for peripherals which clocks are not
47 derived from the System clock (SAIx, SYSTICK, RTC, ADC, USB OTG FS/SDMMC1/RNG)
48
49 @endverbatim
50 ******************************************************************************
51 */
52
53 /* Includes ------------------------------------------------------------------*/
54 #include "stm32u5xx_hal.h"
55
56 /** @addtogroup STM32U5xx_HAL_Driver
57 * @{
58 */
59
60 /** @defgroup RCC RCC
61 * @brief RCC HAL module driver
62 * @{
63 */
64
65 #ifdef HAL_RCC_MODULE_ENABLED
66
67 /* Private typedef -----------------------------------------------------------*/
68 /* Private constants ---------------------------------------------------------*/
69 /** @defgroup RCC_Private_Constants RCC Private Constants
70 * @{
71 */
72 #define PLLDIVR_RESET_VALUE (0x01010280U)
73 /**
74 * @}
75 */
76 /* Private macros ------------------------------------------------------------*/
77 /** @addtogroup RCC_Private_Macros
78 * @{
79 */
80 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \
81 (((__OSCILLATOR__) & ~RCC_OSCILLATORTYPE_ALL) == 0x00U))
82
83 #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
84 ((__HSE__) == RCC_HSE_BYPASS) || ((__HSE__) == RCC_HSE_BYPASS_DIGITAL))
85
86 #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
87 ((__LSE__) == RCC_LSE_BYPASS))
88
89 #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
90
91 #define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)( RCC_ICSCR3_HSITRIM >>\
92 RCC_ICSCR3_HSITRIM_Pos))
93
94 #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
95
96 #define IS_RCC_LSIDIV(__LSIDIV__) (((__LSIDIV__) == RCC_LSI_DIV1) || ((__LSIDIV__) == RCC_LSI_DIV128))
97
98 #define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON))
99
100 #define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 255U)
101
102 #define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON))
103
104 #define IS_RCC_SHSI(__SHSI__) (((__SHSI__) == RCC_SHSI_OFF) || ((__SHSI__) == RCC_SHSI_ON))
105
106 #define IS_RCC_MSIK(__MSIK__) (((__MSIK__) == RCC_MSIK_OFF) || ((__MSIK__) == RCC_MSIK_ON))
107
108 #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || \
109 ((PLL) == RCC_PLL_ON))
110
111 #define IS_RCC_PLLMBOOST_VALUE(VALUE) (((VALUE) == RCC_PLLMBOOST_DIV1) || \
112 ((VALUE) == RCC_PLLMBOOST_DIV2) || \
113 ((VALUE) == RCC_PLLMBOOST_DIV4) || \
114 ((VALUE) == RCC_PLLMBOOST_DIV6) || \
115 ((VALUE) == RCC_PLLMBOOST_DIV8) || \
116 ((VALUE) == RCC_PLLMBOOST_DIV10) || \
117 ((VALUE) == RCC_PLLMBOOST_DIV12) || \
118 ((VALUE) == RCC_PLLMBOOST_DIV14) || \
119 ((VALUE) == RCC_PLLMBOOST_DIV16))
120
121 #define IS_RCC_PLLCLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL1_DIVP) || \
122 ((VALUE) == RCC_PLL1_DIVQ) || \
123 ((VALUE) == RCC_PLL1_DIVR))
124
125 #define IS_RCC_PLLRGE_VALUE(VALUE) (((VALUE) == RCC_PLLVCIRANGE_0) || \
126 ((VALUE) == RCC_PLLVCIRANGE_1))
127
128 #define IS_RCC_PLLFRACN_VALUE(VALUE) ((VALUE) <= 8191U)
129
130 #define IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 0x1FU))
131
132 #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) || \
133 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
134 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
135 ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
136
137 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \
138 ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \
139 ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \
140 ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
141 ((__HCLK__) == RCC_SYSCLK_DIV512))
142
143 #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
144 ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
145 ((__PCLK__) == RCC_HCLK_DIV16))
146
147 #define IS_RCC_MCO(__MCOX__) ((__MCOX__) == RCC_MCO1)
148
149 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \
150 ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \
151 ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \
152 ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \
153 ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \
154 ((__SOURCE__) == RCC_MCO1SOURCE_PLL1CLK) || \
155 ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \
156 ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \
157 ((__SOURCE__) == RCC_MCO1SOURCE_HSI48)|| \
158 ((__SOURCE__) == RCC_MCO1SOURCE_MSIK))
159
160 #define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \
161 ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \
162 ((__DIV__) == RCC_MCODIV_16))
163
164 #define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \
165 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \
166 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \
167 ((__DRIVE__) == RCC_LSEDRIVE_HIGH))
168
169 #define IS_RCC_ITEM_ATTRIBUTES(ITEM) ((0U < (ITEM)) && ((ITEM) <= 0x1FFFU))
170
171 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
172 #define IS_RCC_ATTRIBUTES(ATTRIBUTES) (((ATTRIBUTES) == RCC_SEC_PRIV) || \
173 ((ATTRIBUTES) == RCC_SEC_NPRIV) || \
174 ((ATTRIBUTES) == RCC_NSEC_PRIV) || \
175 ((ATTRIBUTES) == RCC_NSEC_NPRIV))
176 #else
177 #define IS_RCC_ATTRIBUTES(ATTRIBUTES) (((ATTRIBUTES) == RCC_NSEC_NPRIV) || ((ATTRIBUTES) == RCC_NSEC_PRIV))
178 #endif /* __ARM_FEATURE_CMSE */
179 /**
180 * @}
181 */
182
183 /* Private define ------------------------------------------------------------*/
184 /** @defgroup RCC_Private_Constants RCC Private Constants
185 * @{
186 */
187 #define LSI_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */
188 #define HSI48_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */
189 #define SHSI_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */
190 #define MSIK_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */
191 #define PLL_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */
192 #define CLOCKSWITCH_TIMEOUT_VALUE 5000UL /* 5 s */
193 #define EPOD_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */
194 /**
195 * @}
196 */
197
198 /* Private macro -------------------------------------------------------------*/
199 /** @defgroup RCC_Private_Macros RCC Private Macros
200 * @{
201 */
202
203 #define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
204
205 #define MCO1_GPIO_PORT GPIOA
206
207 #define MCO1_PIN GPIO_PIN_8
208
209 #define RCC_PLL_OSCSOURCE_CONFIG(__HAL_RCC_PLLSOURCE__) \
210 (MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (uint32_t)(__HAL_RCC_PLLSOURCE__)))
211 /**
212 * @}
213 */
214
215 /* Private variables ---------------------------------------------------------*/
216
217 /* Private function prototypes -----------------------------------------------*/
218 /** @defgroup RCC_Private_Functions RCC Private Functions
219 * @{
220 */
221 static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange);
222 /**
223 * @}
224 */
225
226 /* Exported functions --------------------------------------------------------*/
227
228 /** @defgroup RCC_Exported_Functions RCC Exported Functions
229 * @{
230 */
231
232 /** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
233 * @brief Initialization and Configuration functions
234 *
235 @verbatim
236 ===============================================================================
237 ##### Initialization and de-initialization functions #####
238 ===============================================================================
239 [..]
240 This section provides functions allowing to configure the internal and external oscillators
241 (HSE, HSI, LSE, MSI, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1
242 and APB2).
243
244 [..] Internal/external clock and PLL configuration
245 (+) HSI (high-speed internal): 16 MHz factory-trimmed RC used directly or through
246 the PLL as System clock source.
247
248 (+) MSI (Multiple Speed Internal): Its frequency is software trimmable from 100KHZ to 48MHZ.
249 It can be used to generate the clock for the USB OTG FS (48 MHz).
250 The number of flash wait states is automatically adjusted when MSI range is updated with
251 HAL_RCC_OscConfig() and the MSI is used as System clock source.
252
253 (+) LSI (low-speed internal): 32 KHz low consumption RC used as IWDG and/or RTC
254 clock source.
255
256 (+) HSE (high-speed external): 4 to 48 MHz crystal oscillator used directly or
257 through the PLL as System clock source. Can be used also optionally as RTC clock source.
258
259 (+) LSE (low-speed external): 32.768 KHz oscillator used optionally as RTC clock source.
260
261 (+) PLL (clocked by HSI, HSE or MSI) providing up to three independent output clocks:
262 (++) The first output is used to generate the high speed system clock (up to 80MHz).
263 (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
264 the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).
265 (++) The third output is used to generate an accurate clock to achieve
266 high-quality audio performance on SAI interface.
267
268 (+) PLL2 (clocked by HSI, HSE or MSI) providing up to three independent output clocks:
269 (++) The first output is used to generate SAR ADC1 clock.
270 (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
271 the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).
272 (++) The Third output is used to generate an accurate clock to achieve
273 high-quality audio performance on SAI interface.
274
275 (+) PLL3 (clocked by HSI , HSE or MSI) providing up to two independent output clocks:
276 (++) The first output is used to generate SAR ADC4 clock.
277 (++) The second output is used to generate an accurate clock to achieve
278 high-quality audio performance on SAI interface.
279
280 (+) CSS (Clock security system): once enabled, if a HSE clock failure occurs
281 (HSE used directly or through PLL as System clock source), the System clock
282 is automatically switched to HSI and an interrupt is generated if enabled.
283 The interrupt is linked to the Cortex-M4 NMI (Non-Maskable Interrupt)
284 exception vector.
285
286 (+) MCO (microcontroller clock output): used to output MSI, LSI, HSI, LSE, HSE or
287 main PLL clock (through a configurable prescaler) on PA8 pin.
288
289 [..] System, AHB and APB busses clocks configuration
290 (+) Several clock sources can be used to drive the System clock (SYSCLK): MSI, HSI,
291 HSE and main PLL.
292 The AHB clock (HCLK) is derived from System clock through configurable
293 prescaler and used to clock the CPU, memory and peripherals mapped
294 on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
295 from AHB clock through configurable prescalers and used to clock
296 the peripherals mapped on these busses. You can use
297 "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
298
299 -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
300
301 (+@) SAI: the SAI clock can be derived either from a specific PLL (PLL2) or (PLL3) or
302 from an external clock mapped on the SAI_CKIN pin.
303 You have to use HAL_RCCEx_PeriphCLKConfig() function to configure this clock.
304 (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
305 divided by 2 to 31.
306 You have to use __HAL_RCC_RTC_ENABLE() and HAL_RCCEx_PeriphCLKConfig() function
307 to configure this clock.
308 (+@) USB OTG FS, SDMMC1 and RNG: USB OTG FS requires a frequency equal to 48 MHz
309 to work correctly, while the SDMMC1 and RNG peripherals require a frequency
310 equal or lower than to 48 MHz. This clock is derived of the main PLL or PLL2
311 through PLLQ divider. You have to enable the peripheral clock and use
312 HAL_RCCEx_PeriphCLKConfig() function to configure this clock.
313 (+@) IWDG clock which is always the LSI clock.
314
315
316 (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 80 MHz.
317 The clock source frequency should be adapted depending on the device voltage range
318 as listed in the Reference Manual "Clock source frequency versus voltage scaling" chapter.
319
320 @endverbatim
321
322
323 Table 1. HCLK clock frequency for STM32U5xx devices
324 +-------------------------------------------------------+----------------------------------------+
325 | Latency | HCLK clock frequency (MHz) 0.9V-1.2V |
326 | |-------------------------------------|---------------------+------------------|
327 | | voltage range 1 | voltage range 2 | voltage range 3 | voltage range 4 |
328 | | 1.1 V - 1.2V | 1.0 V - 1.1V | 0.9 V - 1.0V | 0.9V |
329 |-----------------|------------------|------------------|---------------------|------------------|
330 |0WS(1 CPU cycles)| 0 < HCLK <= 32 | 0 < HCLK <= 25 | 0 < HCLK <= 12.5 | 0 < HCLK <= 8 |
331 |-----------------|------------------|------------------|---------------------|------------------|
332 |1WS(2 CPU cycles)| 32 < HCLK <= 64 | 25 < HCLK <= 50 | 12.5 < HCLK <= 25 | 8 < HCLK <= 16 |
333 |-----------------|------------------|------------------|---------------------|------------------|
334 |2WS(3 CPU cycles)| 64 < HCLK <= 96 | 50 < HCLK <= 75 | 25 < HCLK <= 37.5 | 16 < HCLK <= 24 |
335 |-----------------|------------------|------------------|---------------------|------------------|
336 |3WS(4 CPU cycles)| 96 < HCLK <= 128 | 75 < HCLK <= 100 | 37.5 < HCLK <= 50 | - |
337 |-----------------|------------------|------------------|---------------------|------------------|
338 |4WS(5 CPU cycles)|128 < HCLK <= 160 | - | - | - |
339 +-----------------+------------------+------------------+---------------------+------------------+
340 * @{
341 */
342
343 /**
344 * @brief Reset the RCC clock configuration to the default reset state.
345 * @note The default reset state of the clock configuration is given below:
346 * - MSI ON and used as system clock source
347 * - HSE, HSI, PLL, PLL2 and PLLISAI2 OFF
348 * - AHB, APB1 and APB2 prescaler set to 1
349 * - CSS, MCO1 OFF
350 * - All interrupts disabled
351 * - All interrupt and reset flags cleared
352 * @note This function doesn't modify the configuration of the
353 * - Peripheral clocks
354 * - LSI, LSE and RTC clocks
355 * @retval HAL status
356 */
HAL_RCC_DeInit(void)357 HAL_StatusTypeDef HAL_RCC_DeInit(void)
358 {
359 uint32_t tickstart;
360
361 /* Increasing the CPU frequency */
362 if (FLASH_LATENCY_DEFAULT > __HAL_FLASH_GET_LATENCY())
363 {
364 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
365 __HAL_FLASH_SET_LATENCY(FLASH_LATENCY_DEFAULT);
366
367 /* Check that the new number of wait states is taken into account to access the Flash
368 memory by reading the FLASH_ACR register */
369 if (__HAL_FLASH_GET_LATENCY() != FLASH_LATENCY_DEFAULT)
370 {
371 return HAL_ERROR;
372 }
373 }
374
375 tickstart = HAL_GetTick();
376
377 /* Set MSION bit */
378 SET_BIT(RCC->CR, RCC_CR_MSISON);
379
380 /* Insure MSIRDY bit is set before writing default MSIRANGE value */
381 while (READ_BIT(RCC->CR, RCC_CR_MSISRDY) == 0U)
382 {
383 if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
384 {
385 return HAL_TIMEOUT;
386 }
387 }
388
389 /* Set MSIRANGE default value */
390 MODIFY_REG(RCC->ICSCR1, RCC_ICSCR1_MSISRANGE, RCC_MSIRANGE_4);
391
392 /* Set MSITRIM default value */
393 WRITE_REG(RCC->ICSCR2, 0x00084210U);
394
395 /* Set MSIKRANGE default value */
396 MODIFY_REG(RCC->ICSCR1, RCC_ICSCR1_MSIKRANGE, RCC_MSIKRANGE_4);
397
398 /* Set MSIRGSEL default value */
399 MODIFY_REG(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL, 0x0U);
400
401 tickstart = HAL_GetTick();
402
403 /* Reset CFGR register (MSI is selected as system clock source) */
404 CLEAR_REG(RCC->CFGR1);
405 CLEAR_REG(RCC->CFGR2);
406
407 /* Wait till clock switch is ready */
408 while (READ_BIT(RCC->CFGR1, RCC_CFGR1_SWS) != 0U)
409 {
410 if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
411 {
412 return HAL_TIMEOUT;
413 }
414 }
415
416 /* Reset MSIKON, HSECSSON , HSEON, HSEBYP, HSION, HSIKERON, PLL1ON, PLL2ON, PLL3ON bits */
417 CLEAR_BIT(RCC->CR, RCC_CR_MSIKON | RCC_CR_MSIPLLSEL | RCC_CR_MSIPLLFAST | RCC_CR_MSIKERON | RCC_CR_CSSON | \
418 RCC_CR_HSION | RCC_CR_HSIKERON | RCC_CR_PLL1ON | RCC_CR_PLL2ON | RCC_CR_PLL3ON | RCC_CR_HSI48ON | \
419 RCC_CR_HSEON | RCC_CR_SHSION);
420
421 /* Reset HSEBYP & HSEEXT bits */
422 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP | RCC_CR_HSEEXT);
423
424 tickstart = HAL_GetTick();
425
426 /* Clear PLL1ON bit */
427 CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON);
428
429 /* Wait till PLL1 is disabled */
430 while (READ_BIT(RCC->CR, RCC_CR_PLL1RDY) != 0U)
431 {
432 if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
433 {
434 return HAL_TIMEOUT;
435 }
436 }
437
438 tickstart = HAL_GetTick();
439
440 /* Reset PLL2N bit */
441 CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON);
442
443 /* Wait till PLL2 is disabled */
444 while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != 0U)
445 {
446 if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
447 {
448 return HAL_TIMEOUT;
449 }
450 }
451
452 tickstart = HAL_GetTick();
453
454 /* Reset PLL3 bit */
455 CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON);
456
457 /* Wait till PLL3 is disabled */
458 while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != 0U)
459 {
460 if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
461 {
462 return HAL_TIMEOUT;
463 }
464 }
465
466 /* Reset PLL1CFGR register */
467 CLEAR_REG(RCC->PLL1CFGR);
468
469 /* Reset PLL1DIVR register */
470 WRITE_REG(RCC->PLL1DIVR, PLLDIVR_RESET_VALUE);
471
472 /* Reset PLL1FRACR register */
473 CLEAR_REG(RCC->PLL1FRACR);
474
475 /* Reset PLL2CFGR register */
476 CLEAR_REG(RCC->PLL2CFGR);
477
478 /* Reset PLL2DIVR register */
479 WRITE_REG(RCC->PLL2DIVR, PLLDIVR_RESET_VALUE);
480
481 /* Reset PLL2FRACR register */
482 CLEAR_REG(RCC->PLL2FRACR);
483
484 /* Reset PLL3CFGR register */
485 CLEAR_REG(RCC->PLL3CFGR);
486
487 /* Reset PLL3DIVR register */
488 WRITE_REG(RCC->PLL3DIVR, PLLDIVR_RESET_VALUE);
489
490 /* Reset PLL3FRACR register */
491 CLEAR_REG(RCC->PLL3FRACR);
492
493 /* Disable all interrupts */
494 CLEAR_REG(RCC->CIER);
495
496 /* Clear all interrupts flags */
497 WRITE_REG(RCC->CICR, 0xFFFFFFFFU);
498
499 /* Reset all CSR flags */
500 SET_BIT(RCC->CSR, RCC_CSR_RMVF);
501
502 /* Update the SystemCoreClock global variable */
503 SystemCoreClock = MSI_VALUE;
504
505 /* Decreasing the number of wait states because of lower CPU frequency */
506 if (FLASH_LATENCY_DEFAULT < __HAL_FLASH_GET_LATENCY())
507 {
508 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
509 __HAL_FLASH_SET_LATENCY(FLASH_LATENCY_DEFAULT);
510
511 /* Check that the new number of wait states is taken into account to access the Flash
512 memory by reading the FLASH_ACR register */
513 if (__HAL_FLASH_GET_LATENCY() != FLASH_LATENCY_DEFAULT)
514 {
515 return HAL_ERROR;
516 }
517 }
518
519 /* Adapt Systick interrupt period */
520 return (HAL_InitTick(TICK_INT_PRIORITY));
521
522 }
523
524 /**
525 * @brief Initialize the RCC Oscillators according to the specified parameters in the
526 * RCC_OscInitTypeDef.
527 * @param pRCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
528 * contains the configuration information for the RCC Oscillators.
529 * @note The PLL is not disabled when used as system clock.
530 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
531 * supported by this function. User should request a transition to LSE Off
532 * first and then LSE On or LSE Bypass.
533 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
534 * supported by this function. User should request a transition to HSE Off
535 * first and then HSE On or HSE Bypass.
536 * @retval HAL status
537 */
HAL_RCC_OscConfig(RCC_OscInitTypeDef * pRCC_OscInitStruct)538 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *pRCC_OscInitStruct)
539 {
540 uint32_t tickstart;
541 HAL_StatusTypeDef status;
542 uint32_t sysclk_source;
543 uint32_t pll_config;
544 FlagStatus pwrboosten = RESET;
545
546 /* Check Null pointer */
547 if (pRCC_OscInitStruct == NULL)
548 {
549 return HAL_ERROR;
550 }
551
552 /* Check the parameters */
553 assert_param(IS_RCC_OSCILLATORTYPE(pRCC_OscInitStruct->OscillatorType));
554
555 sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();
556 pll_config = __HAL_RCC_GET_PLL_OSCSOURCE();
557
558 /*----------------------------- MSI Configuration --------------------------*/
559 if (((pRCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)
560 {
561 /* Check the parameters */
562 assert_param(IS_RCC_MSI(pRCC_OscInitStruct->MSIState));
563 assert_param(IS_RCC_MSICALIBRATION_VALUE(pRCC_OscInitStruct->MSICalibrationValue));
564 assert_param(IS_RCC_MSI_CLOCK_RANGE(pRCC_OscInitStruct->MSIClockRange));
565
566 /*Check if MSI is used as system clock or as PLL source when PLL is selected as system clock*/
567
568 if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI) ||
569 ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_MSI)))
570 {
571 if ((READ_BIT(RCC->CR, RCC_CR_MSISRDY) != 0U) && (pRCC_OscInitStruct->MSIState == RCC_MSI_OFF))
572 {
573 return HAL_ERROR;
574 }
575
576 /* Otherwise, just the calibration and MSI range change are allowed */
577 else
578 {
579 /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
580 must be correctly programmed according to the frequency of the CPU clock
581 (HCLK) and the supply voltage of the device */
582 if (pRCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE())
583 {
584 /* First increase number of wait states update if necessary */
585 if (RCC_SetFlashLatencyFromMSIRange(pRCC_OscInitStruct->MSIClockRange) != HAL_OK)
586 {
587 return HAL_ERROR;
588 }
589
590 /* Selects the Multiple Speed oscillator (MSI) clock range */
591 __HAL_RCC_MSI_RANGE_CONFIG(pRCC_OscInitStruct->MSIClockRange);
592 /* Adjusts the Multiple Speed oscillator (MSI) calibration value */
593 __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST((pRCC_OscInitStruct->MSICalibrationValue), \
594 (pRCC_OscInitStruct->MSIClockRange));
595 }
596 else
597 {
598 /* Else, keep current flash latency while decreasing applies */
599 /* Selects the Multiple Speed oscillator (MSI) clock range */
600 __HAL_RCC_MSI_RANGE_CONFIG(pRCC_OscInitStruct->MSIClockRange);
601 /* Adjusts the Multiple Speed oscillator (MSI) calibration value */
602 __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST((pRCC_OscInitStruct->MSICalibrationValue), \
603 (pRCC_OscInitStruct->MSIClockRange));
604
605 /* Decrease number of wait states update if necessary */
606 if (RCC_SetFlashLatencyFromMSIRange(pRCC_OscInitStruct->MSIClockRange) != HAL_OK)
607 {
608 return HAL_ERROR;
609 }
610 }
611
612 /* Update the SystemCoreClock global variable */
613 (void) HAL_RCC_GetHCLKFreq();
614 /* Configure the source of time base considering new system clocks settings*/
615 status = HAL_InitTick(uwTickPrio);
616 if (status != HAL_OK)
617 {
618 return status;
619 }
620 }
621 }
622 else
623 {
624 /* Check the MSI State */
625 if (pRCC_OscInitStruct->MSIState != RCC_MSI_OFF)
626 {
627 /* Enable the Internal High Speed oscillator (MSI) */
628 __HAL_RCC_MSI_ENABLE();
629
630 tickstart = HAL_GetTick();
631
632 /* Wait till MSI is ready */
633 while (READ_BIT(RCC->CR, RCC_CR_MSISRDY) == 0U)
634 {
635 if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
636 {
637 return HAL_TIMEOUT;
638 }
639 }
640 /* Selects the Multiple Speed oscillator (MSI) clock range */
641 __HAL_RCC_MSI_RANGE_CONFIG(pRCC_OscInitStruct->MSIClockRange);
642 /* Adjusts the Multiple Speed oscillator (MSI) calibration value */
643 __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST((pRCC_OscInitStruct->MSICalibrationValue), \
644 (pRCC_OscInitStruct->MSIClockRange));
645
646 }
647 else
648 {
649 /* Disable the Internal High Speed oscillator (MSI) */
650 __HAL_RCC_MSI_DISABLE();
651
652 tickstart = HAL_GetTick();
653
654 /* Wait till MSI is ready */
655 while (READ_BIT(RCC->CR, RCC_CR_MSISRDY) != 0U)
656 {
657 if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
658 {
659 return HAL_TIMEOUT;
660 }
661 }
662 }
663 }
664 }
665 /*------------------------------- HSE Configuration ------------------------*/
666 if (((pRCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
667 {
668 /* Check the parameters */
669 assert_param(IS_RCC_HSE(pRCC_OscInitStruct->HSEState));
670
671 /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
672 if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE) ||
673 ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSE)))
674 {
675 if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (pRCC_OscInitStruct->HSEState == RCC_HSE_OFF))
676 {
677 return HAL_ERROR;
678 }
679 }
680 else
681 {
682 /* Set the new HSE configuration ---------------------------------------*/
683 __HAL_RCC_HSE_CONFIG(pRCC_OscInitStruct->HSEState);
684
685 /* Check the HSE State */
686 if (pRCC_OscInitStruct->HSEState != RCC_HSE_OFF)
687 {
688 tickstart = HAL_GetTick();
689
690 /* Wait till HSE is ready */
691 while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
692 {
693 if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
694 {
695 return HAL_TIMEOUT;
696 }
697 }
698 }
699 else
700 {
701 tickstart = HAL_GetTick();
702
703 /* Wait till HSE is disabled */
704 while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
705 {
706 if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
707 {
708 return HAL_TIMEOUT;
709 }
710 }
711 }
712 }
713 }
714 /*----------------------------- HSI Configuration --------------------------*/
715 if (((pRCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
716 {
717 /* Check the parameters */
718 assert_param(IS_RCC_HSI(pRCC_OscInitStruct->HSIState));
719 assert_param(IS_RCC_HSI_CALIBRATION_VALUE(pRCC_OscInitStruct->HSICalibrationValue));
720
721 /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
722 if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSI) ||
723 ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSI)))
724 {
725 /* When HSI is used as system clock it will not be disabled */
726 if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (pRCC_OscInitStruct->HSIState == RCC_HSI_OFF))
727 {
728 return HAL_ERROR;
729 }
730 /* Otherwise, just the calibration is allowed */
731 else
732 {
733 /* Adjusts the Internal High Speed oscillator (HSI) calibration value */
734 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(pRCC_OscInitStruct->HSICalibrationValue);
735 }
736 }
737 else
738 {
739 /* Check the HSI State */
740 if (pRCC_OscInitStruct->HSIState != RCC_HSI_OFF)
741 {
742 /* Enable the Internal High Speed oscillator (HSI) */
743 __HAL_RCC_HSI_ENABLE();
744
745 tickstart = HAL_GetTick();
746
747 /* Wait till HSI is ready */
748 while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
749 {
750 if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
751 {
752 return HAL_TIMEOUT;
753 }
754 }
755
756 /* Adjusts the Internal High Speed oscillator (HSI) calibration value */
757 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(pRCC_OscInitStruct->HSICalibrationValue);
758 }
759 else
760 {
761 /* Disable the Internal High Speed oscillator (HSI) */
762 __HAL_RCC_HSI_DISABLE();
763
764 tickstart = HAL_GetTick();
765
766 /* Wait till HSI is disabled */
767 while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
768 {
769 if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
770 {
771 return HAL_TIMEOUT;
772 }
773 }
774 }
775 }
776 }
777 /*------------------------------ LSI Configuration -------------------------*/
778 if (((pRCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
779 {
780 /* Check the parameters */
781 assert_param(IS_RCC_LSI(pRCC_OscInitStruct->LSIState));
782
783 FlagStatus pwrclkchanged = RESET;
784
785 /* Update LSI configuration in Backup Domain control register */
786 /* Requires to enable write access to Backup Domain of necessary */
787 if (__HAL_RCC_PWR_IS_CLK_DISABLED())
788 {
789 __HAL_RCC_PWR_CLK_ENABLE();
790 pwrclkchanged = SET;
791 }
792
793 if (HAL_IS_BIT_CLR(PWR->DBPR, PWR_DBPR_DBP))
794 {
795 /* Enable write access to Backup domain */
796 SET_BIT(PWR->DBPR, PWR_DBPR_DBP);
797
798 /* Wait for Backup domain Write protection disable */
799 tickstart = HAL_GetTick();
800
801 while (HAL_IS_BIT_CLR(PWR->DBPR, PWR_DBPR_DBP))
802 {
803 if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
804 {
805 return HAL_TIMEOUT;
806 }
807 }
808 }
809 /* Check the LSI State */
810 if (pRCC_OscInitStruct->LSIState != RCC_LSI_OFF)
811 {
812 uint32_t bdcr_temp = RCC->BDCR;
813
814 /* Check LSI division factor */
815 assert_param(IS_RCC_LSIDIV(pRCC_OscInitStruct->LSIDiv));
816
817 if (pRCC_OscInitStruct->LSIDiv != (bdcr_temp & RCC_BDCR_LSIPREDIV))
818 {
819 if (((bdcr_temp & RCC_BDCR_LSIRDY) == RCC_BDCR_LSIRDY) && \
820 ((bdcr_temp & RCC_BDCR_LSION) != RCC_BDCR_LSION))
821 {
822 /* If LSIRDY is set while LSION is not enabled, LSIPREDIV can't be updated */
823 /* The LSIPREDIV cannot be changed if the LSI is used by the IWDG or by the RTC */
824 return HAL_ERROR;
825 }
826
827 /* Turn off LSI before changing RCC_BDCR_LSIPREDIV */
828 if ((bdcr_temp & RCC_BDCR_LSION) == RCC_BDCR_LSION)
829 {
830 __HAL_RCC_LSI_DISABLE();
831
832 tickstart = HAL_GetTick();
833
834 /* Wait till LSI is disabled */
835 while (READ_BIT(RCC->BDCR, RCC_BDCR_LSIRDY) != 0U)
836 {
837 if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
838 {
839 return HAL_TIMEOUT;
840 }
841 }
842 }
843
844 /* Set LSI division factor */
845 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSIPREDIV, pRCC_OscInitStruct->LSIDiv);
846 }
847
848 /* Enable the Internal Low Speed oscillator (LSI) */
849 __HAL_RCC_LSI_ENABLE();
850
851 tickstart = HAL_GetTick();
852
853 /* Wait till LSI is ready */
854 while (READ_BIT(RCC->BDCR, RCC_BDCR_LSIRDY) == 0U)
855 {
856 if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
857 {
858 return HAL_TIMEOUT;
859 }
860 }
861 }
862 else
863 {
864 /* Disable the Internal Low Speed oscillator (LSI) */
865 __HAL_RCC_LSI_DISABLE();
866
867 tickstart = HAL_GetTick();
868
869 /* Wait till LSI is disabled */
870 while (READ_BIT(RCC->BDCR, RCC_BDCR_LSIRDY) != 0U)
871 {
872 if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
873 {
874 return HAL_TIMEOUT;
875 }
876 }
877 }
878 /* Restore clock configuration if changed */
879 if (pwrclkchanged == SET)
880 {
881 __HAL_RCC_PWR_CLK_DISABLE();
882 }
883 }
884 /*------------------------------ LSE Configuration -------------------------*/
885 if (((pRCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
886 {
887 FlagStatus pwrclkchanged = RESET;
888
889 /* Check the parameters */
890 assert_param(IS_RCC_LSE(pRCC_OscInitStruct->LSEState));
891
892 /* Update LSE configuration in Backup Domain control register */
893 /* Requires to enable write access to Backup Domain of necessary */
894 if (__HAL_RCC_PWR_IS_CLK_DISABLED())
895 {
896 __HAL_RCC_PWR_CLK_ENABLE();
897 pwrclkchanged = SET;
898 }
899
900 if (HAL_IS_BIT_CLR(PWR->DBPR, PWR_DBPR_DBP))
901 {
902 /* Enable write access to Backup domain */
903 SET_BIT(PWR->DBPR, PWR_DBPR_DBP);
904
905 /* Wait for Backup domain Write protection disable */
906 tickstart = HAL_GetTick();
907
908 while (HAL_IS_BIT_CLR(PWR->DBPR, PWR_DBPR_DBP))
909 {
910 if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
911 {
912 return HAL_TIMEOUT;
913 }
914 }
915 }
916
917 /* Set the new LSE configuration -----------------------------------------*/
918 if ((pRCC_OscInitStruct->LSEState & RCC_BDCR_LSEON) != 0U)
919 {
920 if ((pRCC_OscInitStruct->LSEState & RCC_BDCR_LSEBYP) != 0U)
921 {
922 /* LSE oscillator bypass enable */
923 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
924 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
925 }
926 else
927 {
928 /* LSE oscillator enable */
929 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
930 }
931 }
932 else
933 {
934 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
935 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
936 }
937
938 /* Check the LSE State */
939 if (pRCC_OscInitStruct->LSEState != RCC_LSE_OFF)
940 {
941 tickstart = HAL_GetTick();
942
943 /* Wait till LSE is ready */
944 while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
945 {
946 if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
947 {
948 return HAL_TIMEOUT;
949 }
950 }
951
952 /* Enable LSESYS additionally if requested */
953 if ((pRCC_OscInitStruct->LSEState & RCC_BDCR_LSESYSEN) != 0U)
954 {
955 SET_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN);
956
957 /* Wait till LSESYS is ready */
958 while (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) == 0U)
959 {
960 if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
961 {
962 return HAL_TIMEOUT;
963 }
964 }
965 }
966 else
967 {
968 /* Make sure LSESYSEN/LSESYSRDY are reset */
969 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN);
970
971 /* Wait till LSESYSRDY is cleared */
972 while (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) != 0U)
973 {
974 if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
975 {
976 return HAL_TIMEOUT;
977 }
978 }
979 }
980 }
981 else
982 {
983 tickstart = HAL_GetTick();
984
985 /* Wait till LSE is disabled */
986 while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
987 {
988 if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
989 {
990 return HAL_TIMEOUT;
991 }
992 }
993
994 if (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN) != 0U)
995 {
996 /* Reset LSESYSEN once LSE is disabled */
997 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN);
998
999 /* Wait till LSESYSRDY is cleared */
1000 while (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) != 0U)
1001 {
1002 if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
1003 {
1004 return HAL_TIMEOUT;
1005 }
1006 }
1007 }
1008 }
1009
1010 /* Restore clock configuration if changed */
1011 if (pwrclkchanged == SET)
1012 {
1013 __HAL_RCC_PWR_CLK_DISABLE();
1014 }
1015 }
1016 /*------------------------------ HSI48 Configuration -----------------------*/
1017 if (((pRCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
1018 {
1019 /* Check the parameters */
1020 assert_param(IS_RCC_HSI48(pRCC_OscInitStruct->HSI48State));
1021
1022 /* Check the HSI48 State */
1023 if (pRCC_OscInitStruct->HSI48State != RCC_HSI48_OFF)
1024 {
1025 /* Enable the Internal High Speed oscillator (HSI48) */
1026 __HAL_RCC_HSI48_ENABLE();
1027
1028 tickstart = HAL_GetTick();
1029
1030 /* Wait till HSI48 is ready */
1031 while (READ_BIT(RCC->CR, RCC_CR_HSI48RDY) == 0U)
1032 {
1033 if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
1034 {
1035 return HAL_TIMEOUT;
1036 }
1037 }
1038 }
1039 else
1040 {
1041 /* Disable the Internal High Speed oscillator (HSI48) */
1042 __HAL_RCC_HSI48_DISABLE();
1043
1044 tickstart = HAL_GetTick();
1045
1046 /* Wait till HSI48 is disabled */
1047 while (READ_BIT(RCC->CR, RCC_CR_HSI48RDY) != 0U)
1048 {
1049 if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
1050 {
1051 return HAL_TIMEOUT;
1052 }
1053 }
1054 }
1055 }
1056
1057 /*------------------------------ SHSI Configuration -----------------------*/
1058 if (((pRCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_SHSI) == RCC_OSCILLATORTYPE_SHSI)
1059 {
1060 /* Check the parameters */
1061 assert_param(IS_RCC_SHSI(pRCC_OscInitStruct->SHSIState));
1062
1063 /* Check the SHSI State */
1064 if (pRCC_OscInitStruct->SHSIState != RCC_SHSI_OFF)
1065 {
1066 /* Enable the Secure Internal High Speed oscillator (SHSI) */
1067 __HAL_RCC_SHSI_ENABLE();
1068
1069 tickstart = HAL_GetTick();
1070
1071 /* Wait till SHSI is ready */
1072 while (READ_BIT(RCC->CR, RCC_CR_SHSIRDY) == 0U)
1073 {
1074 if ((HAL_GetTick() - tickstart) > SHSI_TIMEOUT_VALUE)
1075 {
1076 return HAL_TIMEOUT;
1077 }
1078 }
1079 }
1080 else
1081 {
1082 /* Disable the Secure Internal High Speed oscillator (SHSI) */
1083 __HAL_RCC_SHSI_DISABLE();
1084
1085 tickstart = HAL_GetTick();
1086
1087 /* Wait till SHSI is disabled */
1088 while (READ_BIT(RCC->CR, RCC_CR_SHSIRDY) != 0U)
1089 {
1090 if ((HAL_GetTick() - tickstart) > SHSI_TIMEOUT_VALUE)
1091 {
1092 return HAL_TIMEOUT;
1093 }
1094 }
1095 }
1096 }
1097 /*------------------------------ MSIK Configuration -----------------------*/
1098 if (((pRCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSIK) == RCC_OSCILLATORTYPE_MSIK)
1099 {
1100 /* Check the parameters */
1101 assert_param(IS_RCC_MSIK(pRCC_OscInitStruct->MSIKState));
1102 assert_param(IS_RCC_MSIK_CLOCK_RANGE(pRCC_OscInitStruct->MSIKClockRange));
1103 assert_param(IS_RCC_MSICALIBRATION_VALUE(pRCC_OscInitStruct->MSICalibrationValue));
1104
1105 /* Check the MSIK State */
1106 if (pRCC_OscInitStruct->MSIKState != RCC_MSIK_OFF)
1107 {
1108
1109 /* Selects the Multiple Speed of kernel high speed oscillator (MSIK) clock range .*/
1110 __HAL_RCC_MSIK_RANGE_CONFIG(pRCC_OscInitStruct->MSIKClockRange);
1111 /* Adjusts the Multiple Speed of kernel high speed oscillator (MSIK) calibration value.*/
1112 __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST((pRCC_OscInitStruct->MSICalibrationValue), \
1113 (pRCC_OscInitStruct->MSIClockRange));
1114
1115 /* Enable the Internal kernel High Speed oscillator (MSIK) */
1116 __HAL_RCC_MSIK_ENABLE();
1117
1118 tickstart = HAL_GetTick();
1119
1120 /* Wait till MSIK is ready */
1121 while (READ_BIT(RCC->CR, RCC_CR_MSIKRDY) == 0U)
1122 {
1123 if ((HAL_GetTick() - tickstart) > MSIK_TIMEOUT_VALUE)
1124 {
1125 return HAL_TIMEOUT;
1126 }
1127 }
1128 }
1129 else
1130 {
1131 /* Disable the Internal High Speed Kernel oscillator (MSIK) */
1132 __HAL_RCC_MSIK_DISABLE();
1133
1134 tickstart = HAL_GetTick();
1135
1136 /* Wait till MSIK is disabled */
1137 while (READ_BIT(RCC->CR, RCC_CR_MSIKRDY) != 0U)
1138 {
1139 if ((HAL_GetTick() - tickstart) > MSIK_TIMEOUT_VALUE)
1140 {
1141 return HAL_TIMEOUT;
1142 }
1143 }
1144 }
1145 }
1146 /*-------------------------------- PLL Configuration -----------------------*/
1147 /* Check the parameters */
1148 assert_param(IS_RCC_PLL(pRCC_OscInitStruct->PLL.PLLState));
1149
1150 if ((pRCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
1151 {
1152 /* Check if the PLL is used as system clock or not */
1153 if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
1154 {
1155 if ((pRCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
1156 {
1157 /* Check the parameters */
1158 assert_param(IS_RCC_PLLMBOOST_VALUE(pRCC_OscInitStruct->PLL.PLLMBOOST));
1159 assert_param(IS_RCC_PLLSOURCE(pRCC_OscInitStruct->PLL.PLLSource));
1160 assert_param(IS_RCC_PLLM_VALUE(pRCC_OscInitStruct->PLL.PLLM));
1161 assert_param(IS_RCC_PLLN_VALUE(pRCC_OscInitStruct->PLL.PLLN));
1162 assert_param(IS_RCC_PLLP_VALUE(pRCC_OscInitStruct->PLL.PLLP));
1163 assert_param(IS_RCC_PLLQ_VALUE(pRCC_OscInitStruct->PLL.PLLQ));
1164 assert_param(IS_RCC_PLLR_VALUE(pRCC_OscInitStruct->PLL.PLLR));
1165
1166 /* Disable the main PLL */
1167 __HAL_RCC_PLL_DISABLE();
1168
1169 tickstart = HAL_GetTick();
1170
1171 /* Wait till PLL is ready */
1172 while (READ_BIT(RCC->CR, RCC_CR_PLL1RDY) != 0U)
1173 {
1174 if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
1175 {
1176 return HAL_TIMEOUT;
1177 }
1178 }
1179
1180 /* Enable PWR CLK */
1181 __HAL_RCC_PWR_CLK_ENABLE();
1182
1183 /*Disable EPOD to configure PLL1MBOOST*/
1184 if (READ_BIT(PWR->VOSR, PWR_VOSR_BOOSTEN) == PWR_VOSR_BOOSTEN)
1185 {
1186 pwrboosten = SET;
1187 }
1188 CLEAR_BIT(PWR->VOSR, PWR_VOSR_BOOSTEN);
1189
1190 /* Configure the main PLL clock source, multiplication and division factors */
1191 __HAL_RCC_PLL_CONFIG(pRCC_OscInitStruct->PLL.PLLSource,
1192 pRCC_OscInitStruct->PLL.PLLMBOOST,
1193 pRCC_OscInitStruct->PLL.PLLM,
1194 pRCC_OscInitStruct->PLL.PLLN,
1195 pRCC_OscInitStruct->PLL.PLLP,
1196 pRCC_OscInitStruct->PLL.PLLQ,
1197 pRCC_OscInitStruct->PLL.PLLR);
1198
1199 assert_param(IS_RCC_PLLFRACN_VALUE(pRCC_OscInitStruct->PLL.PLLFRACN));
1200
1201 /* Disable PLL1FRACN */
1202 __HAL_RCC_PLLFRACN_DISABLE();
1203
1204 /* Configure PLL PLL1FRACN */
1205 __HAL_RCC_PLLFRACN_CONFIG(pRCC_OscInitStruct->PLL.PLLFRACN);
1206
1207 /* Enable PLL1FRACN */
1208 __HAL_RCC_PLLFRACN_ENABLE();
1209
1210 assert_param(IS_RCC_PLLRGE_VALUE(pRCC_OscInitStruct->PLL.PLLRGE));
1211
1212 /* Select PLL1 input reference frequency range: VCI */
1213 __HAL_RCC_PLL_VCIRANGE(pRCC_OscInitStruct->PLL.PLLRGE);
1214
1215 if (pwrboosten == SET)
1216 {
1217 /* Enable the EPOD to reach max frequency */
1218 SET_BIT(PWR->VOSR, PWR_VOSR_BOOSTEN);
1219 }
1220
1221 /*Disable PWR clk */
1222 __HAL_RCC_PWR_CLK_DISABLE();
1223
1224 /* Enable PLL System Clock output */
1225 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVR);
1226
1227 /* Enable the main PLL */
1228 __HAL_RCC_PLL_ENABLE();
1229
1230 tickstart = HAL_GetTick();
1231
1232 /* Wait till PLL is ready */
1233 while (READ_BIT(RCC->CR, RCC_CR_PLL1RDY) == 0U)
1234 {
1235 if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
1236 {
1237 return HAL_TIMEOUT;
1238 }
1239 }
1240 }
1241 else
1242 {
1243 /* Disable the main PLL */
1244 __HAL_RCC_PLL_DISABLE();
1245
1246 /* Disable main PLL outputs to save power if no PLLs on */
1247 __HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLL1_DIVP | RCC_PLL1_DIVQ | RCC_PLL1_DIVR);
1248
1249 tickstart = HAL_GetTick();
1250
1251 /* Wait till PLL is disabled */
1252 while (READ_BIT(RCC->CR, RCC_CR_PLL1RDY) != 0U)
1253 {
1254 if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
1255 {
1256 return HAL_TIMEOUT;
1257 }
1258 }
1259 }
1260 }
1261 else
1262 {
1263 return HAL_ERROR;
1264 }
1265 }
1266 return HAL_OK;
1267 }
1268
1269 /**
1270 * @brief Initialize the CPU, AHB and APB busses clocks according to the specified
1271 * parameters in the pRCC_ClkInitStruct.
1272 * @param pRCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that
1273 * contains the configuration information for the RCC peripheral.
1274 * @param FLatency FLASH Latency
1275 * This parameter can be one of the following values:
1276 * @arg FLASH_LATENCY_0 FLASH 0 Latency cycle
1277 * @arg FLASH_LATENCY_1 FLASH 1 Latency cycle
1278 * @arg FLASH_LATENCY_2 FLASH 2 Latency cycles
1279 * @arg FLASH_LATENCY_3 FLASH 3 Latency cycles
1280 * @arg FLASH_LATENCY_4 FLASH 4 Latency cycles
1281 * @arg FLASH_LATENCY_5 FLASH 5 Latency cycles
1282 *
1283 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
1284 * and updated by HAL_RCC_GetHCLKFreq() function called within this function
1285 *
1286 * @note The MSI is used by default as system clock source after
1287 * startup from Reset, wake-up from STANDBY mode. After restart from Reset,
1288 * the MSI frequency is set to its default value 4 MHz.
1289 * @note The HSI can be selected as system clock source after wakeup
1290 * from STOP modes or in case of failure of the HSE used directly or indirectly
1291 * as system clock (if the Clock Security System CSS is enabled).
1292 * @note A switch from one clock source to another occurs only if the target
1293 * clock source is ready (clock stable after startup delay or PLL locked).
1294 * If a clock source which is not yet ready is selected, the switch will
1295 * occur when the clock source is ready.
1296 * @note You can use HAL_RCC_GetClockConfig() function to know which clock is
1297 * currently used as system clock source.
1298 *
1299 * @note Depending on the device voltage range, the software has to set correctly
1300 * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
1301 * (for more details refer to section above "Initialization/de-initialization functions")
1302 * @retval HAL status
1303 */
HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef * const pRCC_ClkInitStruct,uint32_t FLatency)1304 HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *const pRCC_ClkInitStruct, uint32_t FLatency)
1305 {
1306 HAL_StatusTypeDef status;
1307 uint32_t tickstart;
1308
1309 /* Check Null pointer */
1310 if (pRCC_ClkInitStruct == NULL)
1311 {
1312 return HAL_ERROR;
1313 }
1314
1315 /* Check the parameters */
1316 assert_param(IS_RCC_CLOCKTYPE(pRCC_ClkInitStruct->ClockType));
1317 assert_param(IS_FLASH_LATENCY(FLatency));
1318
1319 /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
1320 must be correctly programmed according to the frequency of the CPU clock
1321 (HCLK) and the supply voltage of the device */
1322
1323 /* Increasing the number of wait states because of higher CPU frequency */
1324 if (FLatency > __HAL_FLASH_GET_LATENCY())
1325 {
1326 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
1327 __HAL_FLASH_SET_LATENCY(FLatency);
1328
1329 /* Check that the new number of wait states is taken into account to access the Flash
1330 memory by reading the FLASH_ACR register */
1331 if (__HAL_FLASH_GET_LATENCY() != FLatency)
1332 {
1333 return HAL_ERROR;
1334 }
1335 }
1336
1337 /*------------------------- SYSCLK Configuration ---------------------------*/
1338 if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
1339 {
1340 assert_param(IS_RCC_SYSCLKSOURCE(pRCC_ClkInitStruct->SYSCLKSource));
1341
1342 /* PLL is selected as System Clock Source */
1343 if (pRCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
1344 {
1345 __HAL_RCC_PWR_CLK_ENABLE();
1346 tickstart = HAL_GetTick();
1347 /* Check if EPOD is enabled */
1348 if (READ_BIT(PWR->VOSR, PWR_VOSR_BOOSTEN) != 0U)
1349 {
1350 /* Wait till BOOST is ready */
1351 while (READ_BIT(PWR->VOSR, PWR_VOSR_BOOSTRDY) == 0U)
1352 {
1353 if ((HAL_GetTick() - tickstart) > EPOD_TIMEOUT_VALUE)
1354 {
1355 return HAL_TIMEOUT;
1356 }
1357 }
1358 }
1359
1360 __HAL_RCC_PWR_CLK_DISABLE();
1361
1362 /* Check the PLL ready flag */
1363 if (READ_BIT(RCC->CR, RCC_CR_PLL1RDY) == 0U)
1364 {
1365 return HAL_ERROR;
1366 }
1367 }
1368 else
1369 {
1370 /* HSE is selected as System Clock Source */
1371 if (pRCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
1372 {
1373 /* Check the HSE ready flag */
1374 if (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
1375 {
1376 return HAL_ERROR;
1377 }
1378 }
1379 /* MSI is selected as System Clock Source */
1380 else if (pRCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI)
1381 {
1382 /* Check the MSI ready flag */
1383 if (READ_BIT(RCC->CR, RCC_CR_MSISRDY) == 0U)
1384 {
1385 return HAL_ERROR;
1386 }
1387 }
1388 /* HSI is selected as System Clock Source */
1389 else
1390 {
1391 /* Check the HSI ready flag */
1392 if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
1393 {
1394 return HAL_ERROR;
1395 }
1396 }
1397 }
1398
1399 MODIFY_REG(RCC->CFGR1, RCC_CFGR1_SW, pRCC_ClkInitStruct->SYSCLKSource);
1400
1401 tickstart = HAL_GetTick();
1402
1403 if (pRCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
1404 {
1405 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
1406 {
1407 if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
1408 {
1409 return HAL_TIMEOUT;
1410 }
1411 }
1412 }
1413 else
1414 {
1415 if (pRCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
1416 {
1417 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
1418 {
1419 if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
1420 {
1421 return HAL_TIMEOUT;
1422 }
1423 }
1424 }
1425 else if (pRCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI)
1426 {
1427 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI)
1428 {
1429 if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
1430 {
1431 return HAL_TIMEOUT;
1432 }
1433 }
1434 }
1435 else
1436 {
1437 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
1438 {
1439 if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
1440 {
1441 return HAL_TIMEOUT;
1442 }
1443 }
1444 }
1445 }
1446 }
1447
1448 /*-------------------------- HCLK Configuration --------------------------*/
1449 if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
1450 {
1451 assert_param(IS_RCC_HCLK(pRCC_ClkInitStruct->AHBCLKDivider));
1452 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_HPRE, pRCC_ClkInitStruct->AHBCLKDivider);
1453 }
1454
1455 /*-------------------------- PCLK1 Configuration ---------------------------*/
1456 if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
1457 {
1458 assert_param(IS_RCC_PCLK(pRCC_ClkInitStruct->APB1CLKDivider));
1459 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE1, pRCC_ClkInitStruct->APB1CLKDivider);
1460 }
1461
1462 /*-------------------------- PCLK2 Configuration ---------------------------*/
1463 if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
1464 {
1465 assert_param(IS_RCC_PCLK(pRCC_ClkInitStruct->APB2CLKDivider));
1466 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE2, ((pRCC_ClkInitStruct->APB2CLKDivider) << 4));
1467 }
1468
1469 /*-------------------------- PCLK3 Configuration ---------------------------*/
1470 if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK3) == RCC_CLOCKTYPE_PCLK3)
1471 {
1472 assert_param(IS_RCC_PCLK(pRCC_ClkInitStruct->APB3CLKDivider));
1473 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_PPRE3, pRCC_ClkInitStruct->APB3CLKDivider);
1474 }
1475
1476 /* Decreasing the number of wait states because of lower CPU frequency */
1477 if (FLatency < __HAL_FLASH_GET_LATENCY())
1478 {
1479 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
1480 __HAL_FLASH_SET_LATENCY(FLatency);
1481
1482 /* Check that the new number of wait states is taken into account to access the Flash
1483 memory by reading the FLASH_ACR register */
1484 if (__HAL_FLASH_GET_LATENCY() != FLatency)
1485 {
1486 return HAL_ERROR;
1487 }
1488 }
1489
1490 /* Update the SystemCoreClock global variable */
1491 SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos];
1492
1493 /* Configure the source of time base considering new system clocks settings*/
1494 status = HAL_InitTick(uwTickPrio);
1495
1496 return status;
1497 }
1498
1499 /**
1500 * @}
1501 */
1502
1503 /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
1504 * @brief RCC clocks control functions
1505 *
1506 @verbatim
1507 ===============================================================================
1508 ##### Peripheral Control functions #####
1509 ===============================================================================
1510 [..]
1511 This subsection provides a set of functions allowing to:
1512
1513 (+) Output clock to MCO pin.
1514 (+) Retrieve current clock frequencies.
1515 (+) Enable the Clock Security System.
1516
1517 @endverbatim
1518 * @{
1519 */
1520
1521 /**
1522 * @brief Select the clock source to output on MCO pin(PA8).
1523 * @note PA8 should be configured in alternate function mode.
1524 * @param RCC_MCOx specifies the output direction for the clock source.
1525 * For STM32U5xx family this parameter can have only one value:
1526 * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8).
1527 * @param RCC_MCOSource specifies the clock source to output.
1528 * This parameter can be one of the following values:
1529 * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled, no clock on MCO
1530 * @arg @ref RCC_MCO1SOURCE_SYSCLK system clock selected as MCO source
1531 * @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source
1532 * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source
1533 * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee
1534 * @arg @ref RCC_MCO1SOURCE_PLL1CLK main PLL clock selected as MCO source
1535 * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source
1536 * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source
1537 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48
1538 * @param RCC_MCODiv specifies the MCO prescaler.
1539 * This parameter can be one of the following values:
1540 * @arg @ref RCC_MCODIV_1 no division applied to MCO clock
1541 * @arg @ref RCC_MCODIV_2 division by 2 applied to MCO clock
1542 * @arg @ref RCC_MCODIV_4 division by 4 applied to MCO clock
1543 * @arg @ref RCC_MCODIV_8 division by 8 applied to MCO clock
1544 * @arg @ref RCC_MCODIV_16 division by 16 applied to MCO clock
1545 * @retval None
1546 */
HAL_RCC_MCOConfig(uint32_t RCC_MCOx,uint32_t RCC_MCOSource,uint32_t RCC_MCODiv)1547 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
1548 {
1549 GPIO_InitTypeDef gpio_initstruct;
1550 /* Check the parameters */
1551 assert_param(IS_RCC_MCO(RCC_MCOx));
1552 assert_param(IS_RCC_MCODIV(RCC_MCODiv));
1553 assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
1554
1555 /* MCO Clock Enable */
1556 MCO1_CLK_ENABLE();
1557
1558 /* Configure the MCO1 pin in alternate function mode */
1559 gpio_initstruct.Pin = MCO1_PIN;
1560 gpio_initstruct.Mode = GPIO_MODE_AF_PP;
1561 gpio_initstruct.Speed = GPIO_SPEED_FREQ_HIGH;
1562 gpio_initstruct.Pull = GPIO_NOPULL;
1563 gpio_initstruct.Alternate = GPIO_AF0_MCO;
1564 HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio_initstruct);
1565
1566 /* Mask MCOSEL[] and MCOPRE[] bits then set MCO1 clock source and prescaler */
1567 MODIFY_REG(RCC->CFGR1, (RCC_CFGR1_MCOSEL | RCC_CFGR1_MCOPRE), (RCC_MCOSource | RCC_MCODiv));
1568 }
1569
1570 /**
1571 * @brief Return the SYSCLK frequency.
1572 * @note The system frequency computed by this function is not the real
1573 * frequency in the chip. It is calculated based on the predefined
1574 * constant and the selected clock source:
1575 * @note If SYSCLK source is MSI, function returns values based on MSI
1576 * Value as defined by the MSI range.
1577 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
1578 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
1579 * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**),
1580 * HSI_VALUE(*) or MSI Value multiplied/divided by the PLL factors.
1581 * @note (*) HSI_VALUE is a constant defined in stm32u5xx_hal_conf.h file (default value
1582 * 16 MHz) but the real value may vary depending on the variations
1583 * in voltage and temperature.
1584 * @note (**) HSE_VALUE is a constant defined in stm32u5xx_hal_conf.h file (default value
1585 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
1586 * frequency of the crystal used. Otherwise, this function may
1587 * have wrong result.
1588 * @note The result of this function could be not correct when using fractional
1589 * value for HSE crystal.
1590 * @note This function can be used by the user application to compute the
1591 * baudrate for the communication peripherals or configure other parameters.
1592 * @note Each time SYSCLK changes, this function must be called to update the
1593 * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
1594 * @retval SYSCLK frequency
1595 */
HAL_RCC_GetSysClockFreq(void)1596 uint32_t HAL_RCC_GetSysClockFreq(void)
1597 {
1598 uint32_t msirange = 0U;
1599 uint32_t pllsource;
1600 uint32_t pllr;
1601 uint32_t pllm;
1602 uint32_t pllfracen;
1603 uint32_t sysclockfreq = 0U;
1604 uint32_t sysclk_source;
1605 uint32_t pll_oscsource;
1606 float_t fracn1;
1607 float_t pllvco;
1608
1609 sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();
1610 pll_oscsource = __HAL_RCC_GET_PLL_OSCSOURCE();
1611
1612 if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI) ||
1613 ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_oscsource == RCC_PLLSOURCE_MSI)))
1614 {
1615 /* MSI or PLL with MSI source used as system clock source */
1616
1617 /* Get SYSCLK source */
1618 if (READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL) == 0U)
1619 {
1620 /* MSISRANGE from RCC_CSR applies */
1621 msirange = (RCC->CSR & RCC_CSR_MSISSRANGE) >> RCC_CSR_MSISSRANGE_Pos;
1622 }
1623 else
1624 {
1625 /* MSIRANGE from RCC_CR applies */
1626 msirange = (RCC->ICSCR1 & RCC_ICSCR1_MSISRANGE) >> RCC_ICSCR1_MSISRANGE_Pos;
1627 }
1628 /*MSI frequency range in HZ*/
1629 msirange = MSIRangeTable[msirange];
1630
1631 if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI)
1632 {
1633 /* MSI used as system clock source */
1634 sysclockfreq = msirange;
1635 }
1636 }
1637 else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
1638 {
1639 /* HSI used as system clock source */
1640 sysclockfreq = HSI_VALUE;
1641 }
1642 else if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE)
1643 {
1644 /* HSE used as system clock source */
1645 sysclockfreq = HSE_VALUE;
1646 }
1647 else
1648 {
1649 /* Nothing to do */
1650 }
1651
1652 if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK)
1653 {
1654 /* PLL used as system clock source
1655 PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
1656 SYSCLK = PLL_VCO / PLLR
1657 */
1658 pllsource = (RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC);
1659 pllm = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos) + 1U;
1660 pllfracen = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1FRACEN) >> RCC_PLL1CFGR_PLL1FRACEN_Pos);
1661 fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_PLL1FRACN) >> \
1662 RCC_PLL1FRACR_PLL1FRACN_Pos));
1663
1664 if (pllm != 0U)
1665 {
1666 switch (pllsource)
1667 {
1668 case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1669 pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \
1670 (fracn1 / (float_t)0x2000) + (float_t)1U);
1671 break;
1672
1673 case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1674 pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \
1675 (fracn1 / (float_t)0x2000) + (float_t)1U);
1676 break;
1677
1678 case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
1679 default:
1680 pllvco = ((float_t) msirange / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \
1681 (fracn1 / (float_t)0x2000) + (float_t)1U);
1682 break;
1683 }
1684
1685 pllr = (((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1U);
1686 sysclockfreq = (uint32_t)(float_t)((float_t)pllvco / (float_t)pllr);
1687 }
1688 else
1689 {
1690 sysclockfreq = 0;
1691 }
1692 }
1693
1694 return sysclockfreq;
1695 }
1696
1697 /**
1698 * @brief Return the HCLK frequency.
1699 * @note Each time HCLK changes, this function must be called to update the
1700 * right HCLK value. Otherwise, any configuration based on this function will be incorrect.
1701 *
1702 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
1703 * @retval HCLK frequency in Hz
1704 */
HAL_RCC_GetHCLKFreq(void)1705 uint32_t HAL_RCC_GetHCLKFreq(void)
1706 {
1707 SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos];
1708 return SystemCoreClock;
1709 }
1710
1711 /**
1712 * @brief Return the PCLK1 frequency.
1713 * @note Each time PCLK1 changes, this function must be called to update the
1714 * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
1715 * @retval PCLK1 frequency in Hz
1716 */
HAL_RCC_GetPCLK1Freq(void)1717 uint32_t HAL_RCC_GetPCLK1Freq(void)
1718 {
1719 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
1720 return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR2 & RCC_CFGR2_PPRE1) >> RCC_CFGR2_PPRE1_Pos]);
1721 }
1722
1723 /**
1724 * @brief Return the PCLK2 frequency.
1725 * @note Each time PCLK2 changes, this function must be called to update the
1726 * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
1727 * @retval PCLK2 frequency in Hz
1728 */
HAL_RCC_GetPCLK2Freq(void)1729 uint32_t HAL_RCC_GetPCLK2Freq(void)
1730 {
1731 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
1732 return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR2 & RCC_CFGR2_PPRE2) >> RCC_CFGR2_PPRE2_Pos]);
1733 }
1734
1735 /**
1736 * @brief Return the PCLK3 frequency.
1737 * @note Each time PCLK3 changes, this function must be called to update the
1738 * right PCLK3 value. Otherwise, any configuration based on this function will be incorrect.
1739 * @retval PCLK3 frequency in Hz
1740 */
HAL_RCC_GetPCLK3Freq(void)1741 uint32_t HAL_RCC_GetPCLK3Freq(void)
1742 {
1743 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
1744 return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR3 & RCC_CFGR3_PPRE3) >> RCC_CFGR3_PPRE3_Pos]);
1745 }
1746 /**
1747 * @brief Get the pRCC_OscInitStruct according to the internal
1748 * RCC configuration registers.
1749 * @param pRCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
1750 * will be configured.
1751 * @retval None
1752 */
HAL_RCC_GetOscConfig(RCC_OscInitTypeDef * pRCC_OscInitStruct)1753 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *pRCC_OscInitStruct)
1754 {
1755 /* Check the parameters */
1756 assert_param(pRCC_OscInitStruct != (void *)NULL);
1757
1758 /* Set all possible values for the Oscillator type parameter ---------------*/
1759 pRCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_MSI | \
1760 RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_HSI48;
1761
1762 /* Get the HSE configuration -----------------------------------------------*/
1763 if ((RCC->CR & (RCC_CR_HSEBYP | RCC_CR_HSEEXT)) == RCC_CR_HSEBYP)
1764 {
1765 pRCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
1766 }
1767 else if ((RCC->CR & (RCC_CR_HSEBYP | RCC_CR_HSEEXT)) == (RCC_CR_HSEBYP | RCC_CR_HSEEXT))
1768 {
1769 pRCC_OscInitStruct->HSEState = RCC_HSE_BYPASS_DIGITAL;
1770 }
1771 else if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON)
1772 {
1773 pRCC_OscInitStruct->HSEState = RCC_HSE_ON;
1774 }
1775 else
1776 {
1777 pRCC_OscInitStruct->HSEState = RCC_HSE_OFF;
1778 }
1779
1780 /* Get the MSI configuration -----------------------------------------------*/
1781 if ((RCC->CR & RCC_CR_MSISON) == RCC_CR_MSISON)
1782 {
1783 pRCC_OscInitStruct->MSIState = RCC_MSI_ON;
1784 }
1785 else
1786 {
1787 pRCC_OscInitStruct->MSIState = RCC_MSI_OFF;
1788 }
1789
1790 pRCC_OscInitStruct->MSIClockRange = (uint32_t)((RCC->CR & RCC_ICSCR1_MSISRANGE));
1791 if (pRCC_OscInitStruct->MSIClockRange >= RCC_MSIRANGE_12)
1792 {
1793 pRCC_OscInitStruct->MSICalibrationValue = (uint32_t)((RCC->ICSCR2 & RCC_ICSCR2_MSITRIM3) >> \
1794 RCC_ICSCR2_MSITRIM3_Pos);
1795 }
1796 else if (pRCC_OscInitStruct->MSIClockRange >= RCC_MSIRANGE_8)
1797 {
1798 pRCC_OscInitStruct->MSICalibrationValue = (uint32_t)((RCC->ICSCR2 & RCC_ICSCR2_MSITRIM2) >> \
1799 RCC_ICSCR2_MSITRIM2_Pos);
1800 }
1801 else if (pRCC_OscInitStruct->MSIClockRange >= RCC_MSIRANGE_4)
1802 {
1803 pRCC_OscInitStruct->MSICalibrationValue = (uint32_t)((RCC->ICSCR2 & RCC_ICSCR2_MSITRIM1) >> \
1804 RCC_ICSCR2_MSITRIM1_Pos);
1805 }
1806 else /*if (pRCC_OscInitStruct->MSIClockRange >= RCC_MSIRANGE_0)*/
1807 {
1808 pRCC_OscInitStruct->MSICalibrationValue = (uint32_t)((RCC->ICSCR2 & RCC_ICSCR2_MSITRIM0) >> \
1809 RCC_ICSCR2_MSITRIM0_Pos);
1810 }
1811
1812 /* Get the HSI configuration -----------------------------------------------*/
1813 if ((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION)
1814 {
1815 pRCC_OscInitStruct->HSIState = RCC_HSI_ON;
1816 }
1817 else
1818 {
1819 pRCC_OscInitStruct->HSIState = RCC_HSI_OFF;
1820 }
1821
1822 pRCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->ICSCR3 & RCC_ICSCR3_HSITRIM) >> RCC_ICSCR3_HSITRIM_Pos);
1823
1824 /* Get the LSE configuration -----------------------------------------------*/
1825 if ((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
1826 {
1827 pRCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
1828 }
1829 else if ((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
1830 {
1831 pRCC_OscInitStruct->LSEState = RCC_LSE_ON;
1832 }
1833 else
1834 {
1835 pRCC_OscInitStruct->LSEState = RCC_LSE_OFF;
1836 }
1837
1838 /* Get the LSI configuration -----------------------------------------------*/
1839 if ((RCC->BDCR & RCC_BDCR_LSION) == RCC_BDCR_LSION)
1840 {
1841 pRCC_OscInitStruct->LSIState = RCC_LSI_ON;
1842 }
1843 else
1844 {
1845 pRCC_OscInitStruct->LSIState = RCC_LSI_OFF;
1846 }
1847
1848 /* Get the HSI48 configuration ---------------------------------------------*/
1849 if ((RCC->CR & RCC_CR_HSI48ON) == RCC_CR_HSI48ON)
1850 {
1851 pRCC_OscInitStruct->HSI48State = RCC_HSI48_ON;
1852 }
1853 else
1854 {
1855 pRCC_OscInitStruct->HSI48State = RCC_HSI48_OFF;
1856 }
1857
1858 /* Get the PLL configuration -----------------------------------------------*/
1859 if ((RCC->CR & RCC_CR_PLL1ON) == RCC_CR_PLL1ON)
1860 {
1861 pRCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
1862 }
1863 else
1864 {
1865 pRCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
1866 }
1867 pRCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC);
1868 pRCC_OscInitStruct->PLL.PLLM = (uint32_t)(((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos) + 1U);
1869 pRCC_OscInitStruct->PLL.PLLN = (uint32_t)(((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) >> RCC_PLL1DIVR_PLL1N_Pos) + 1U);
1870 pRCC_OscInitStruct->PLL.PLLQ = (uint32_t)(((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1Q) >> RCC_PLL1DIVR_PLL1Q_Pos) + 1U);
1871 pRCC_OscInitStruct->PLL.PLLR = (uint32_t)(((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1U);
1872 pRCC_OscInitStruct->PLL.PLLP = (uint32_t)(((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1P) >> RCC_PLL1DIVR_PLL1P_Pos) + 1U);
1873 pRCC_OscInitStruct->PLL.PLLRGE = (uint32_t)((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1RGE));
1874 pRCC_OscInitStruct->PLL.PLLFRACN = (uint32_t)(((RCC->PLL1FRACR & RCC_PLL1FRACR_PLL1FRACN) >> \
1875 RCC_PLL1FRACR_PLL1FRACN_Pos));
1876 pRCC_OscInitStruct->PLL.PLLMBOOST = (uint32_t)(((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1MBOOST) >> \
1877 RCC_PLL1CFGR_PLL1MBOOST_Pos) + 1U);
1878 }
1879
1880 /**
1881 * @brief Configure the pRCC_ClkInitStruct according to the internal
1882 * RCC configuration registers.
1883 * @param pRCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that
1884 * will be configured.
1885 * @param pFLatency Pointer on the Flash Latency.
1886 * @retval None
1887 */
HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef * pRCC_ClkInitStruct,uint32_t * pFLatency)1888 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *pRCC_ClkInitStruct, uint32_t *pFLatency)
1889 {
1890 /* Check the parameters */
1891 assert_param(pRCC_ClkInitStruct != (void *)NULL);
1892 assert_param(pFLatency != (void *)NULL);
1893
1894 /* Set all possible values for the Clock type parameter --------------------*/
1895 pRCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | \
1896 RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3;
1897
1898 /* Get the SYSCLK configuration --------------------------------------------*/
1899 pRCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR1 & RCC_CFGR1_SW);
1900
1901 /* Get the HCLK configuration ----------------------------------------------*/
1902 pRCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_HPRE);
1903
1904 /* Get the APB1 configuration ----------------------------------------------*/
1905 pRCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PPRE1);
1906
1907 /* Get the APB2 configuration ----------------------------------------------*/
1908 pRCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR2 & RCC_CFGR2_PPRE2) >> 4);
1909
1910 /* Get the APB3 configuration ----------------------------------------------*/
1911 pRCC_ClkInitStruct->APB3CLKDivider = (uint32_t)(RCC->CFGR3 & RCC_CFGR3_PPRE3);
1912
1913 /* Get the Flash Wait State (Latency) configuration ------------------------*/
1914 *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
1915 }
1916
1917 /**
1918 * @brief Get and clear reset flags
1919 * @note Once reset flags are retrieved, this API is clearing them in order
1920 * to isolate next reset reason.
1921 * @retval can be a combination of @ref RCC_Reset_Flag
1922 */
HAL_RCC_GetResetSource(void)1923 uint32_t HAL_RCC_GetResetSource(void)
1924 {
1925 uint32_t reset;
1926
1927 /* Get all reset flags */
1928 reset = RCC->CSR & RCC_RESET_FLAG_ALL;
1929
1930 /* Clear Reset flags */
1931 RCC->CSR |= RCC_CSR_RMVF;
1932
1933 return reset;
1934 }
1935
1936 /**
1937 * @brief Enable the Clock Security System.
1938 * @note If a failure is detected on the HSE oscillator clock, this oscillator
1939 * is automatically disabled and an interrupt is generated to inform the
1940 * software about the failure (Clock Security System Interrupt, CSSI),
1941 * allowing the MCU to perform rescue operations. The CSSI is linked to
1942 * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
1943 * @note The Clock Security System can only be cleared by reset.
1944 * @retval None
1945 */
HAL_RCC_EnableCSS(void)1946 void HAL_RCC_EnableCSS(void)
1947 {
1948 SET_BIT(RCC->CR, RCC_CR_CSSON);
1949 }
1950
1951 /**
1952 * @brief Handle the RCC Clock Security System interrupt request.
1953 * @note This API should be called under the NMI_Handler().
1954 * @retval None
1955 */
HAL_RCC_NMI_IRQHandler(void)1956 void HAL_RCC_NMI_IRQHandler(void)
1957 {
1958 /* Check RCC CSSF interrupt flag */
1959 if (__HAL_RCC_GET_IT(RCC_IT_CSS))
1960 {
1961 /* RCC Clock Security System interrupt user callback */
1962 HAL_RCC_CSSCallback();
1963
1964 /* Clear RCC CSS pending bit */
1965 __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
1966 }
1967 }
1968
1969 /**
1970 * @brief RCC Clock Security System interrupt callback.
1971 * @retval none
1972 */
HAL_RCC_CSSCallback(void)1973 __weak void HAL_RCC_CSSCallback(void)
1974 {
1975 /* NOTE : This function should not be modified, when the callback is needed,
1976 the HAL_RCC_CSSCallback should be implemented in the user file
1977 */
1978 }
1979
1980 /**
1981 * @}
1982 */
1983 /** @defgroup RCC_Exported_Functions_Group3 Attributes management functions
1984 * @brief Attributes management functions.
1985 *
1986 @verbatim
1987 ===============================================================================
1988 ##### RCC attributes functions #####
1989 ===============================================================================
1990 @endverbatim
1991 * @{
1992 */
1993 /**
1994 * @brief Configure the RCC item attribute(s).
1995 * @note Available attributes are to secure items and set RCC as privileged.
1996 * @param Item Item(s) to set attributes on.
1997 * This parameter can be a one or a combination of @ref RCC_items
1998 * @param Attributes specifies the RCC secure/privilege attributes.
1999 * This parameter can be a value of @ref RCC_attributes
2000 * @retval None
2001 */
HAL_RCC_ConfigAttributes(uint32_t Item,uint32_t Attributes)2002 void HAL_RCC_ConfigAttributes(uint32_t Item, uint32_t Attributes)
2003 {
2004 /* Check the parameters */
2005 assert_param(IS_RCC_ITEM_ATTRIBUTES(Item));
2006 assert_param(IS_RCC_ATTRIBUTES(Attributes));
2007
2008 switch (Attributes)
2009 {
2010 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2011 /* Secure Privilege attribute */
2012 case RCC_SEC_PRIV:
2013 SET_BIT(RCC->SECCFGR, Item);
2014 SET_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_SPRIV);
2015 break;
2016 /* Secure Non-Privilege attribute */
2017 case RCC_SEC_NPRIV:
2018 SET_BIT(RCC->SECCFGR, Item);
2019 CLEAR_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_SPRIV);
2020 break;
2021 /* Non-secure Privilege attribute */
2022 case RCC_NSEC_PRIV:
2023 CLEAR_BIT(RCC->SECCFGR, Item);
2024 SET_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV);
2025 break;
2026 /* Non-secure Non-Privilege attribute */
2027 case RCC_NSEC_NPRIV:
2028 CLEAR_BIT(RCC->SECCFGR, Item);
2029 CLEAR_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV);
2030 break;
2031 #else
2032 /* Non-secure Privilege attribute */
2033 case RCC_NSEC_PRIV:
2034 SET_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV);
2035 break;
2036 /* Non-secure Non-Privilege attribute */
2037 case RCC_NSEC_NPRIV:
2038 CLEAR_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV);
2039 break;
2040 #endif /* __ARM_FEATURE_CMSE */
2041 default:
2042 /* Nothing to do */
2043 break;
2044 }
2045 }
2046 /**
2047 * @}
2048 */
2049
2050 /**
2051 * @brief Get the attribute of a RCC item.
2052 * @note Secure and non-secure attributes are only available from secure state
2053 * when the system implements the security (TZEN=1)
2054 * @param Item Single item to get secure/non-secure and privilege/non-privilege attribute from.
2055 * This parameter can be a one value of @ref RCC_items except RCC_ALL.
2056 * @param pAttributes pointer to return the attributes.
2057 * @retval HAL Status.
2058 */
HAL_RCC_GetConfigAttributes(uint32_t Item,uint32_t * pAttributes)2059 HAL_StatusTypeDef HAL_RCC_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes)
2060 {
2061 uint32_t attributes;
2062
2063 /* Check null pointer */
2064 if (pAttributes == NULL)
2065 {
2066 return HAL_ERROR;
2067 }
2068
2069 /* Check the parameters */
2070 assert_param(IS_RCC_ITEM_ATTRIBUTES(Item));
2071
2072 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2073
2074 /* Check item security */
2075 if ((RCC->SECCFGR & Item) == Item)
2076 {
2077 /* Get Secure privileges attribute */
2078 attributes = ((RCC->PRIVCFGR & RCC_PRIVCFGR_SPRIV) == 0U) ? RCC_SEC_NPRIV : RCC_SEC_PRIV;
2079 }
2080 else
2081 {
2082 /* Get Non-Secure privileges attribute */
2083 attributes = ((RCC->PRIVCFGR & RCC_PRIVCFGR_NSPRIV) == 0U) ? RCC_NSEC_NPRIV : RCC_NSEC_PRIV;
2084 }
2085 #else
2086 /* Get Non-Secure privileges attribute */
2087 attributes = ((RCC->PRIVCFGR & RCC_PRIVCFGR_NSPRIV) == 0U) ? RCC_NSEC_NPRIV : RCC_NSEC_PRIV;
2088 #endif /* __ARM_FEATURE_CMSE */
2089
2090 /* return value */
2091 *pAttributes = attributes;
2092
2093 return HAL_OK;
2094 }
2095 /**
2096 * @}
2097 */
2098
2099 /* Private function prototypes -----------------------------------------------*/
2100 /** @addtogroup RCC_Private_Functions
2101 * @{
2102 */
2103 /**
2104 * @brief Update number of Flash wait states in line with MSI range and current
2105 voltage range.
2106 * @param msirange MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_15
2107 * @retval HAL status
2108 */
RCC_SetFlashLatencyFromMSIRange(uint32_t msirange)2109 static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange)
2110 {
2111 uint32_t vos;
2112 uint32_t latency; /* default value 0WS */
2113
2114 if (__HAL_RCC_PWR_IS_CLK_ENABLED())
2115 {
2116 vos = HAL_PWREx_GetVoltageRange();
2117 }
2118 else
2119 {
2120 __HAL_RCC_PWR_CLK_ENABLE();
2121 vos = HAL_PWREx_GetVoltageRange();
2122 __HAL_RCC_PWR_CLK_DISABLE();
2123 }
2124
2125 if ((vos == PWR_REGULATOR_VOLTAGE_SCALE1) || (vos == PWR_REGULATOR_VOLTAGE_SCALE2))
2126 {
2127
2128 if (msirange < RCC_MSIRANGE_1)
2129 {
2130 /* MSI = 48Mhz */
2131 latency = FLASH_LATENCY_1; /* 1WS */
2132 }
2133 else
2134 {
2135 /* MSI < 48Mhz */
2136 latency = FLASH_LATENCY_0; /* 0WS */
2137 }
2138 }
2139 else
2140 {
2141 if (msirange < RCC_MSIRANGE_1)
2142 {
2143 /* MSI = 48Mhz */
2144 if (vos == PWR_REGULATOR_VOLTAGE_SCALE3)
2145 {
2146 latency = FLASH_LATENCY_3; /* 3WS */
2147 }
2148 else
2149 {
2150 return HAL_ERROR;
2151 }
2152 }
2153 else
2154 {
2155 if (msirange > RCC_MSIRANGE_2)
2156
2157 {
2158 if (vos == PWR_REGULATOR_VOLTAGE_SCALE4)
2159 {
2160 if (msirange > RCC_MSIRANGE_3)
2161 {
2162 latency = FLASH_LATENCY_0; /* 1WS */
2163 }
2164 else
2165 {
2166 latency = FLASH_LATENCY_1; /* 0WS */
2167 }
2168 }
2169 else
2170 {
2171 latency = FLASH_LATENCY_0; /* 0WS */
2172 }
2173 }
2174 else
2175 {
2176 if (msirange == RCC_MSIRANGE_1)
2177
2178 {
2179 if (vos == PWR_REGULATOR_VOLTAGE_SCALE3)
2180 {
2181 latency = FLASH_LATENCY_1; /* 1WS */
2182 }
2183 else
2184 {
2185 latency = FLASH_LATENCY_2; /* 2WS */
2186 }
2187 }
2188 else
2189 {
2190 latency = FLASH_LATENCY_1; /* 1WS */
2191 }
2192 }
2193 }
2194 }
2195
2196 __HAL_FLASH_SET_LATENCY(latency);
2197
2198 /* Check that the new number of wait states is taken into account to access the Flash
2199 memory by reading the FLASH_ACR register */
2200 if ((FLASH->ACR & FLASH_ACR_LATENCY) != latency)
2201 {
2202 return HAL_ERROR;
2203 }
2204
2205 return HAL_OK;
2206 }
2207
2208 /**
2209 * @}
2210 */
2211 #endif /* HAL_RCC_MODULE_ENABLED */
2212 /**
2213 * @}
2214 */
2215
2216 /**
2217 * @}
2218 */
2219
