1 /**
2 ******************************************************************************
3 * @file stm32u5xx_hal_pwr_ex.c
4 * @author MCD Application Team
5 * @brief Extended PWR HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Power Controller extension peripheral :
8 * + Power Supply Control Functions
9 * + Low Power Control Functions
10 * + Voltage Monitoring Functions
11 * + Memories Retention Functions
12 * + I/O Pull-Up Pull-Down Configuration Functions
13 *
14 ******************************************************************************
15 * @attention
16 *
17 * Copyright (c) 2021 STMicroelectronics.
18 * All rights reserved.
19 *
20 * This software component is licensed by ST under BSD 3-Clause license,
21 * the "License"; You may not use this file except in compliance with the
22 * License. You may obtain a copy of the License at:
23 * opensource.org/licenses/BSD-3-Clause
24 *
25 ******************************************************************************
26 @verbatim
27 ==============================================================================
28 ##### How to use this driver #####
29 ==============================================================================
30 [..]
31 (#) Call HAL_PWREx_ControlVoltageScaling() and HAL_PWREx_GetVoltageRange() to
32 set / get the voltage scaling range.
33 (+) Voltage scaling can be one of the following values :
34 (++) voltage output scale 1 : 1V2
35 => Used when system clock frequency is up to 160 MHz
36 (++) voltage output scale 2 : 1V1
37 => Used when system clock frequency is up to 100 MHz
38 (++) voltage output scale 3 : 1V0
39 => Used when system clock frequency is up to 50 MHz
40 (++) voltage output scale 4 : 0V9
41 => Used when system clock frequency is up to 24 MHz
42
43 (#) Call HAL_PWREx_EnableFastSoftStart() and HAL_PWREx_DisableFastSoftStart()
44 to enable / disable the fast software startup for the current regulator.
45
46 (#) Call HAL_PWREx_EnterSTOP1Mode() function to enter the whole system to
47 Stop 1 mode. Wake-up from Stop 1 mode could be following to an event or
48 an interrupt according to low power mode intrinsic request called
49 (__WFI() or __WFE()). (Regulator state on U5 devices is managed
50 internally but regulator parameter is kept for product compatibility).
51
52 (#) Call HAL_PWREx_EnterSTOP2Mode() function to enter the whole system to
53 Stop 2 mode. Wake-up from Stop 2 mode could be following to an event or
54 an interrupt according to low power mode intrinsic request called
55 (__WFI() or __WFE()). (Regulator state on U5 devices is managed
56 internally but regulator parameter is kept for product compatibility).
57
58 (#) Call HAL_PWREx_EnterSTOP3Mode() function to enter the whole system to
59 Stop 3 mode. Wake-up from Stop 3 mode could be following to an event or
60 an interrupt according to low power mode intrinsic request called
61 (__WFI() or __WFE()). (Regulator state on U5 devices is managed
62 internally but regulator parameter is kept for product compatibility).
63
64 (#) Call HAL_PWREx_EnterSHUTDOWNMode() function to enter the whole system in
65 Shutdown mode. Wake-up from Shutdown mode can be following to an external
66 reset (NRST pin), a WKUP pin event (configurable rising or falling edge),
67 or an RTC event occurs (alarm, periodic wakeup, timestamp), or a tamper
68 detection.
69
70 (#) Call HAL_PWREx_ConfigSRDDomain() to force in Run mode or to enter in Stop
71 mode Smart Run Domain when the system enters Stop mode (Stop 0/1/2).
72
73 (#) Call HAL_PWREx_EnableUltraLowPowerMode() and
74 HAL_PWREx_DisableUltraLowPowerMode() to enable / disable the BOR ultra
75 low power mode.
76
77 (#) Call HAL_PWREx_S3WU_IRQHandler() function to handle the PWR Stop 3 wake
78 up interrupt request.
79
80 (#) Call HAL_PWREx_EnableBatteryCharging() and
81 HAL_PWREx_DisableBatteryCharging() to enable / disable the battery
82 charging capability when VDD alimentation is available.
83
84 (#) Call HAL_PWREx_EnableVddUSB(), HAL_PWREx_EnableVddIO2() and
85 HAL_PWREx_EnableVddA() to enable respectively VDDUSB, VDDIO2 and VDDA
86 electrical and logical isolation.
87 It is recommanded to disable VDDUSB, VDDIO2 and VDDA electrical and
88 logical isolation through HAL_PWREx_DisableVddUSB(),
89 HAL_PWREx_DisableVddIO2() and HAL_PWREx_DisableVddA().
90
91 (#) Call HAL_PWREx_ConfigPVM() after setting parameters to be configured
92 (event mode and PVD type) in order to set up the Peripheral Voltage
93 Monitor, then use HAL_PWREx_EnableUVM(), HAL_PWREx_EnableIO2VM(),
94 HAL_PWREx_EnableAVM1() and HAL_PWREx_EnableAVM2() functions to start the
95 PVM VDDx monitoring and use HAL_PWREx_DisableUVM(),
96 HAL_PWREx_DisableIO2VM(), HAL_PWREx_DisableAVM1() and
97 HAL_PWREx_DisableAVM2() to stop the PVM VDDx monitoring.
98 (+) PVM monitored voltages are :
99 (++) VDDUSB versus 1V2
100 (++) VDDIO2 versus 0V9
101 (++) VDDA versus 1V6
102 (++) VDDA versus 1V8
103
104 (#) Call HAL_PWREx_EnableMonitoring() and HAL_PWREx_DisableMonitoring() to
105 enable / disable the VBAT and temperature monitoring.
106
107 (#) Call HAL_PWREx_EnableUCPDStandbyMode() and
108 HAL_PWREx_DisableUCPDStandbyMode() to enable / disable the UCPD
109 configuration memorization in Standby mode.
110
111 (#) Call HAL_PWREx_EnableUCPDDeadBattery() and
112 HAL_PWREx_DisableUCPDDeadBattery() to enable / disable the dead battery
113 behavior.
114
115 (#) Call HAL_PWREx_PVD_PVM_IRQHandler() function to handle the PWR PVD and
116 PVM interrupt request.
117
118 (#) Call HAL_PWREx_EnableSRAM2ContentStandbyRetention() and
119 HAL_PWREx_DisableSRAM2ContentStandbyRetention() to
120 enable / disable the SRAM2 content retention in Stop 3 and Standby low
121 power modes.
122
123 (#) Call HAL_PWREx_EnableRAMsContentStopRetention() and
124 HAL_PWREx_DisableRAMsContentStopRetention() to
125 enable / disable the RAMs content retention in Stop mode (Stop 0/1/2/3).
126 (+) Retained RAM can be one of the following RAMs :
127 (++) SRAM1
128 (++) SRAM2
129 (++) SRAM3
130 (++) SRAM4
131 (++) ICACHE
132 (++) DMA2DRAM
133 (++) PKA32RAM
134 (++) DCACHE1
135 (++) FMAC
136 (++) FDCAN
137 (++) USB
138
139 (#) Call HAL_PWREx_EnableRAMsContentRunRetention() and
140 HAL_PWREx_DisableRAMsContentRunRetention() to
141 enable / disable the RAMs content retention in Run mode.
142 (+) Retained RAM can be one of the following RAMs :
143 (++) SRAM1
144 (++) SRAM2
145 (++) SRAM3
146 (++) SRAM4
147
148 (#) Call HAL_PWREx_EnableFlashFastWakeUp() and
149 HAL_PWREx_DisableFlashFastWakeUp() to enable / disable the flash memory
150 fast wakeup from Stop mode (Stop 0/1).
151
152 (#) Call HAL_PWREx_EnableSRAM4FastWakeUp() and
153 HAL_PWREx_DisableSRAM4FastWakeUp() to enable / disable the SRAM4 memory
154 fast wakeup from Stop mode (Stop 0/1/2).
155
156 (#) Call HAL_PWREx_EnableBkupRAMRetention() and
157 HAL_PWREx_DisableBkupRAMRetention() to enable / disable the Backup RAM
158 content retention in Standby, Shutdown and VBAT modes.
159
160 (#) Call HAL_PWREx_EnablePullUpPullDownConfig() and
161 HAL_PWREx_DisablePullUpPullDownConfig() to I/O enable / disable pull-up
162 and pull-down configuration.
163
164 (#) Call HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() to
165 apply repectively pull-up and pull-down to selected I/O.
166 Call HAL_PWREx_DisableGPIOPullUp() and HAL_PWREx_DisableGPIOPullDown() to
167 disable applied repectively pull-up and pull-down to selected I/O.
168
169 @endverbatim
170 ******************************************************************************
171 */
172
173 /* Includes ------------------------------------------------------------------*/
174 #include "stm32u5xx_hal.h"
175
176 /** @addtogroup STM32U5xx_HAL_Driver
177 * @{
178 */
179
180 /** @defgroup PWREx PWREx
181 * @brief PWR Extended HAL module driver
182 * @{
183 */
184
185 #if defined (HAL_PWR_MODULE_ENABLED)
186
187 /* Private typedef -----------------------------------------------------------*/
188 /* Private define ------------------------------------------------------------*/
189
190 /** @defgroup PWR_Extended_Private_Defines PWR Extended Private Defines
191 * @{
192 */
193 /*!< PORTI pins mask */
194 #define PWR_PORTI_AVAILABLE_PINS (0xFFU)
195 /*!< Time out value of flags setting */
196 #define PWR_FLAG_SETTING_DELAY (0x32U)
197
198 /** @defgroup PWR_PVM_Mode_Mask PWR PVM Mode Mask
199 * @{
200 */
201 #define PVM_RISING_EDGE (0x01U) /*!< Mask for rising edge set as PVM trigger */
202 #define PVM_FALLING_EDGE (0x02U) /*!< Mask for falling edge set as PVM trigger */
203 #define PVM_MODE_IT (0x04U) /*!< Mask for interruption yielded by PVM threshold crossing */
204 #define PVM_MODE_EVT (0x08U) /*!< Mask for event yielded by PVM threshold crossing */
205 /**
206 * @}
207 */
208
209 /**
210 * @}
211 */
212
213 /* Private macro -------------------------------------------------------------*/
214 /* Private variables ---------------------------------------------------------*/
215 /* Private function prototypes -----------------------------------------------*/
216 /* Exported functions --------------------------------------------------------*/
217
218 /** @defgroup PWREx_Exported_Functions PWR Extended Exported Functions
219 * @{
220 */
221
222 /** @defgroup PWREx_Exported_Functions_Group1 Power Supply Control Functions
223 * @brief Power supply control functions
224 *
225 @verbatim
226 ===============================================================================
227 ##### Power supply control functions #####
228 ===============================================================================
229 [..]
230 This section provides functions allowing to control power supply.
231
232 [..]
233 (+) The STM32U5 Series devices embed two regulators : one LDO (linear
234 voltage regulator) and one SMPS (step down converter) in parallel to
235 provide the VCORE supply for digital peripherals, SRAM1, SRAM2, SRAM3
236 and SRAM4 and embedded Flash memory.
237
238 (+) The SMPS allows the power consumption to be reduced but some
239 peripherals can be perturbed by the noise generated by the SMPS,
240 requiring the application to switch to LDO when running this
241 peripheral in order to reach the best performances.
242
243 (+) The LDO and the SMPS regulators have two modes: Main regulator mode
244 (used when performance is needed), and Low-power regulator mode. LDO
245 or SMPS can be used in all voltage scaling ranges, and in all Stop
246 modes.
247
248 (+) After reset, the regulator is the LDO, in Range 4. Switching to SMPS
249 provides lower consumption in particular at high VDD voltage. It is
250 possible to switch from LDO to SMPS, or from SMPS to LDO on the fly in
251 any range, by configuring the REGSEL bit. It is recommended to switch
252 first to SMPS before changing the voltage range.
253
254 (+) When exiting the Stop or Standby modes, the regulator is the same than
255 when entering low power modes. The voltage range is the Range 4.
256
257 (+) Both regulators can provide four different voltages (voltage scaling)
258 and can operate in Stop modes.
259 Voltage scaling ranges can be one of the following values :
260 (++) voltage output scale 1 : 1V2
261 => Used when system clock frequency is up to 160 MHz
262 (++) voltage output scale 2 : 1V1
263 => Used when system clock frequency is up to 100 MHz
264 (++) voltage output scale 3 : 1V0
265 => Used when system clock frequency is up to 50 MHz
266 (++) voltage output scale 4 : 0V9
267 => Used when system clock frequency is up to 24 MHz
268
269 @endverbatim
270 * @{
271 */
272
273 /**
274 * @brief Configure the main internal regulator output voltage to achieve
275 * a tradeoff between performance and power consumption.
276 * @param VoltageScaling : Specifies the regulator output voltage scale.
277 * This parameter can be one of the following values :
278 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 : Regulator voltage output scale 1.
279 * Provides a typical output voltage at 1.2 V.
280 * Used when system clock frequency is up to 160 MHz.
281 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 : Regulator voltage output scale 2.
282 * Provides a typical output voltage at 1.1 V.
283 * Used when system clock frequency is up to 100 MHz.
284 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE3 : Regulator voltage output scale 3.
285 * Provides a typical output voltage at 1.0 V.
286 * Used when system clock frequency is up to 50 MHz.
287 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE4 : Regulator voltage output scale 4.
288 * Provides a typical output voltage at 0.9 V.
289 * Used when system clock frequency is up to 24 MHz.
290 * @note Before moving to voltage scaling 2, it is mandatory to ensure that
291 * the system frequency is between 50 MHz and 100 MHz.
292 * @note Before moving to voltage scaling 3, it is mandatory to ensure that
293 * the system frequency is between 24 MHz and 50 MHz.
294 * @note Before moving to voltage scaling 4, it is mandatory to ensure that
295 * the system frequency is below 24 MHz.
296 * @retval HAL Status.
297 */
HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)298 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
299 {
300 uint32_t timeout;
301 uint32_t vos_old;
302
303 /* Check the parameter */
304 assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
305
306 /* Get the current voltage scale applied */
307 vos_old = READ_BIT(PWR->SVMSR, PWR_SVMSR_ACTVOS);
308
309 /* No change, nothing to do */
310 if (vos_old == VoltageScaling)
311 {
312 return HAL_OK;
313 }
314
315 /* Check voltage scaling level */
316 /*
317 * The Embedded power distribution (EPOD) must be enabled before switching to
318 * voltage scale 1 / 2 from voltage scale lower.
319 */
320 if (VoltageScaling > PWR_REGULATOR_VOLTAGE_SCALE3)
321 {
322 MODIFY_REG(PWR->VOSR, (PWR_VOSR_VOS | PWR_VOSR_BOOSTEN), (VoltageScaling | PWR_VOSR_BOOSTEN));
323 }
324 else
325 {
326 MODIFY_REG(PWR->VOSR, (PWR_VOSR_VOS | PWR_VOSR_BOOSTEN), VoltageScaling);
327 }
328
329 /* Wait until VOSRDY is rised */
330 timeout = ((PWR_FLAG_SETTING_DELAY * (SystemCoreClock / 1000U)) / 1000U) + 1U;
331 while (HAL_IS_BIT_CLR(PWR->VOSR, PWR_VOSR_VOSRDY) && (timeout != 0U))
332 {
333 timeout--;
334 }
335
336 /* Check time out */
337 if (timeout != 0U)
338 {
339 /* Wait until ACTVOSRDY is rised */
340 timeout = ((PWR_FLAG_SETTING_DELAY * (SystemCoreClock / 1000U)) / 1000U) + 1U;
341 while ((HAL_IS_BIT_CLR(PWR->SVMSR, PWR_SVMSR_ACTVOSRDY)) && (timeout != 0U))
342 {
343 timeout--;
344 }
345 }
346
347 /* Check time out */
348 if (timeout == 0U)
349 {
350 return HAL_TIMEOUT;
351 }
352
353 return HAL_OK;
354 }
355
356 /**
357 * @brief Return Voltage Scaling Range.
358 * @retval Applied voltage scaling value.
359 */
HAL_PWREx_GetVoltageRange(void)360 uint32_t HAL_PWREx_GetVoltageRange(void)
361 {
362 return (PWR->SVMSR & PWR_SVMSR_ACTVOS);
363 }
364
365 /**
366 * @brief Configure the system Power Supply.
367 * @param SupplySource : Specifies the Power Supply source to set after a
368 * system startup.
369 * This parameter can be one of the following values :
370 * @arg PWR_LDO_SUPPLY : The LDO regulator supplies the Vcore Power Domains.
371 * @arg PWR_SMPS_SUPPLY : The SMPS regulator supplies the Vcore Power Domains.
372 * @retval HAL Status.
373 */
HAL_PWREx_ConfigSupply(uint32_t SupplySource)374 HAL_StatusTypeDef HAL_PWREx_ConfigSupply(uint32_t SupplySource)
375 {
376 uint32_t timeout;
377
378 /* Check the parameter */
379 assert_param(IS_PWR_SUPPLY(SupplySource));
380
381 /* Set maximum time out */
382 timeout = ((PWR_FLAG_SETTING_DELAY * (SystemCoreClock / 1000U)) / 1000U) + 1U;
383
384 /* Configure the LDO as system regulator supply */
385 if (SupplySource == PWR_LDO_SUPPLY)
386 {
387 /* Set the power supply configuration */
388 CLEAR_BIT(PWR->CR3, PWR_CR3_REGSEL);
389
390 /* Wait until system switch on new regulator */
391 while (HAL_IS_BIT_SET(PWR->SVMSR, PWR_SVMSR_REGS) && (timeout != 0U))
392 {
393 timeout--;
394 }
395 }
396 /* Configure the SMPS as system regulator supply */
397 else
398 {
399 /* Set the power supply configuration */
400 SET_BIT(PWR->CR3, PWR_CR3_REGSEL);
401
402 /* Wait until system switch on new regulator */
403 while (HAL_IS_BIT_CLR(PWR->SVMSR, PWR_SVMSR_REGS) && (timeout != 0U))
404 {
405 timeout--;
406 }
407 }
408
409 /* Check time out */
410 if (timeout == 0U)
411 {
412 return HAL_TIMEOUT;
413 }
414
415 return HAL_OK;
416 }
417
418 /**
419 * @brief Get the power supply configuration.
420 * @retval The supply configured.
421 */
HAL_PWREx_GetSupplyConfig(void)422 uint32_t HAL_PWREx_GetSupplyConfig(void)
423 {
424 return (PWR->SVMSR & PWR_SVMSR_REGS);
425 }
426
427 /**
428 * @brief Enable fast soft start for the current regulator.
429 * @retval None.
430 */
HAL_PWREx_EnableFastSoftStart(void)431 void HAL_PWREx_EnableFastSoftStart(void)
432 {
433 SET_BIT(PWR->CR3, PWR_CR3_FSTEN);
434 }
435
436 /**
437 * @brief Disable fast soft start for the current regulator.
438 * @retval None.
439 */
HAL_PWREx_DisableFastSoftStart(void)440 void HAL_PWREx_DisableFastSoftStart(void)
441 {
442 CLEAR_BIT(PWR->CR3, PWR_CR3_FSTEN);
443 }
444 /**
445 * @}
446 */
447
448
449 /** @defgroup PWREx_Exported_Functions_Group2 Low Power Control Functions
450 * @brief Low power control functions
451 *
452 @verbatim
453 ===============================================================================
454 ##### Low power control functions #####
455 ===============================================================================
456 [..]
457 This section provides functions allowing to control low power modes.
458
459 *** Low Power modes configuration ***
460 =====================================
461 [..]
462 This section presents 4 principles low power modes :
463 (+) Stop 1 mode : Cortex-M33 is stopped, clocks are stopped and the
464 regulator is in low power mode. Several peripheral can
465 operate in this mode.
466
467 (+) Stop 2 mode : Cortex-M33 is stopped, clocks are stopped and the
468 regulator is in low power mode. Only autonomous
469 peripherals can operate in this mode.
470
471 (+) Stop 3 mode : Cortex-M33 is stopped, clocks are stopped and the
472 regulator is in low power mode. No peripheral can
473 operate in this mode. Only RAMs content is preserved.
474
475 (+) Shutdown mode : All PWR domains enter Shutdown mode and the VCORE
476 supply regulator is powered off. The SRAMs and
477 register contents are lost except for registers in the
478 Backup domain.
479
480 *** Stop 1 mode ***
481 ===================
482 [..]
483 The Stop 1 mode is based on the Cortex-M33 Deepsleep mode combined with
484 the peripheral clock gating. The voltage regulator is configured in low
485 power mode. In Stop 1 mode, all clocks in the VCORE domain are stopped.
486 The PLL, MSIS, MSIK, HSI16 and HSE oscillators are disabled.
487 Some peripherals with the LPBAM capability can switch on HSI16 or MSIS or
488 MSIK for transferring data. All SRAMs and register contents are preserved,
489 but the SRAMs can be totally or partially switched off to further reduced
490 consumption.
491 The BOR is always available in Stop 1 mode.
492
493 (+) Entry:
494 The Stop 1 mode is entered by using the HAL_PWREx_EnterSTOP1Mode()
495 function.
496
497 (++) PWR_STOPENTRY_WFI: enter Stop 1 mode with WFI instruction.
498 (++) PWR_STOPENTRY_WFE: enter Stop 1 mode with WFE instruction.
499
500 (+) Exit:
501 Any EXTI line configured in interrupt mode (the corresponding EXTI
502 interrupt vector must be enabled in the NVIC). The interrupt source
503 can be external interrupts or peripherals with wakeup capability.
504 Any peripheral interrupt occurring when the AHB/APB clocks are present
505 due to an autonomous peripheral clock request (the peripheral vector
506 must be enabled in the NVIC)
507 Any EXTI line configured in event mode.
508
509 *** Stop 2 mode ***
510 ===================
511 [..]
512 The Stop 2 mode is based on the Cortex-M33 Deepsleep mode combined with
513 peripheral clock gating. In Stop 2 mode, all clocks in the VCORE domain
514 are stopped.
515 The PLL, MSIS, MSIK, HSI16 and HSE oscillators are disabled.
516 Some peripherals with the LPBAM capability can switch on HSI16 or MSIS or
517 MSIK for transferring data. All SRAMs and register contents are preserved,
518 but the SRAMs can be totally or partially switched off to further reduce
519 consumption.
520 The BOR is always available in Stop 2 mode.
521
522 (+) Entry:
523 The Stop 2 mode is entered by using the HAL_PWREx_EnterSTOP2Mode()
524 function.
525
526 (++) PWR_STOPENTRY_WFI: enter Stop 2 mode with WFI instruction.
527 (++) PWR_STOPENTRY_WFE: enter Stop 2 mode with WFE instruction.
528
529 (+) Exit:
530 Any EXTI line configured in interrupt mode (the corresponding EXTI
531 interrupt vector must be enabled in the NVIC). The interrupt source
532 can be external interrupts or peripherals with wakeup capability.
533 Any peripheral interrupt occurring when the AHB/APB clocks are present
534 due to an autonomous peripheral clock request (the peripheral vector
535 must be enabled in the NVIC)
536 Any EXTI line configured in event mode.
537
538 *** Stop 3 mode ***
539 ===================
540 [..]
541 The Stop 3 mode is based on the Cortex�-M33 Deepsleep mode combined with
542 peripheral clock gating. In Stop 3 mode, all clocks in the VCORE domain
543 are stopped.
544 The PLL, MSIS, MSIK, HSI16 and HSE oscillators are disabled.
545 All SRAMs and register contents are preserved, but the SRAMs can be
546 totally or partially switched off to further reduce consumption.
547 The BOR is always available in Stop 3 mode.
548
549 (+) Entry:
550 The Stop 3 mode is entered by using the HAL_PWREx_EnterSTOP3Mode()
551 function.
552
553 (++) PWR_STOPENTRY_WFI: enter Stop 3 mode with WFI instruction.
554 (++) PWR_STOPENTRY_WFE: enter Stop 3 mode with WFE instruction.
555
556 (+) Exit:
557 WKUPx pin edge, RTC or TAMP event, external Reset in NRST pin, IWDG
558 Reset, BOR reset.
559
560 *** Shutdown mode ***
561 ====================
562 [..]
563 The lowest power consumption is reached in Shutdown mode. It is based on
564 the Deepsleep mode with the voltage regulator disabled. The VCORE domain
565 is consequently powered off.
566 The PLL, HSI16, MSIS, MSIK and HSE oscillators are also switched off.
567 The SRAMs and register contents are lost except for registers in the
568 Backup domain.
569 The BOR is not available in Shutdown mode.
570 No power voltage monitoring is possible in this mode, therefore the switch
571 to Backup domain is not supported.
572
573 (+) Entry:
574 The Shutdown mode is entered by using the HAL_PWREx_EnterSHUTDOWNMode()
575 function.
576
577 (+) Exit:
578 WKUPx pin edge, RTC/TAMP event, external Reset in NRST pin.
579
580 @endverbatim
581 * @{
582 */
583
584 /**
585 * @brief Enter the whole system to Stop 1 mode.
586 * @note Stop 1 offers the largest number of active peripherals and wakeup
587 * sources, a smaller wakeup time but a higher consumption.
588 * @note Stop mode achieves the lowest power consumption while retaining
589 * the content of SRAM and registers. All clocks in the VCORE domain
590 * are stopped. The PLL, the MSI (MSIS and MSIK) RC, the HSI16 RC and
591 * the HSE crystal oscillators are disabled. The LSE or LSI is still
592 * running.
593 * @note The system clock when exiting from Stop mode can be either MSIS up
594 * to 24 MHz or HSI16, depending on software configuration.
595 * @param STOPEntry : Specifies if Stop mode is entered with WFI or WFE
596 * instruction.
597 * This parameter can be one of the following values :
598 * @arg @ref PWR_STOPENTRY_WFI enter Stop mode with Wait
599 * For Interrupt request.
600 * @arg @ref PWR_STOPENTRY_WFE enter Stop mode with Wait
601 * For Event request.
602 * @retval None.
603 */
HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry)604 void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry)
605 {
606 /* Check the parameters */
607 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
608
609 /* Stop 1 mode */
610 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_0);
611
612 /* Set SLEEPDEEP bit of Cortex System Control Register */
613 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
614
615 /* Select Stop mode entry */
616 if (STOPEntry == PWR_STOPENTRY_WFI)
617 {
618 /* Request Wait For Interrupt */
619 __WFI();
620 }
621 else
622 {
623 /* Request Wait For Event */
624 __SEV();
625 __WFE();
626 __WFE();
627 }
628
629 /* Reset SLEEPDEEP bit of Cortex System Control Register */
630 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
631 }
632
633 /**
634 * @brief Enter the whole system to Stop 2 mode.
635 * @note In Stop 2 mode, all clocks in the VCORE domain are stopped. The PLL,
636 * MSIS, MSIK, HSI16 and HSE oscillators are disabled.
637 * @note Stop mode achieves the lowest power consumption while retaining
638 * the content of SRAM and registers. All clocks in the VCORE domain
639 * are stopped. The PLL, the MSI (MSIS and MSIK) RC, the HSI16 RC and
640 * the HSE crystal oscillators are disabled. The LSE or LSI is still
641 * running.
642 * @note The system clock when exiting from Stop mode can be either MSIS up
643 * to 24 MHz or HSI16, depending on software configuration.
644 * @param STOPEntry : Specifies if Stop mode is entered with WFI or WFE
645 * instruction.
646 * This parameter can be one of the following values :
647 * @arg @ref PWR_STOPENTRY_WFI enter Stop mode with Wait
648 * For Interrupt request.
649 * @arg @ref PWR_STOPENTRY_WFE enter Stop mode with Wait
650 * For Event request.
651 * @retval None.
652 */
HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry)653 void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry)
654 {
655 /* Check the parameters */
656 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
657
658 /* Stop 2 mode */
659 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_1);
660
661 /* Set SLEEPDEEP bit of Cortex System Control Register */
662 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
663
664 /* Select Stop mode entry */
665 if (STOPEntry == PWR_STOPENTRY_WFI)
666 {
667 /* Request Wait For Interrupt */
668 __WFI();
669 }
670 else
671 {
672 /* Request Wait For Event */
673 __SEV();
674 __WFE();
675 __WFE();
676 }
677
678 /* Reset SLEEPDEEP bit of Cortex System Control Register */
679 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
680 }
681
682 /**
683 * @brief Enter the whole system to Stop 3 mode.
684 * @note Stop 3 is the lowest power mode with full retention, but the
685 * functional peripherals and sources of wakeup are reduced to the same
686 * ones than in Standby mode.
687 * @note Stop mode achieves the lowest power consumption while retaining
688 * the content of SRAM and registers. All clocks in the VCORE domain
689 * are stopped. The PLL, the MSI (MSIS and MSIK) RC, the HSI16 RC and
690 * the HSE crystal oscillators are disabled. The LSE or LSI is still
691 * running.
692 * @note The system clock when exiting from Stop mode can be either MSIS up
693 * to 24 MHz or HSI16, depending on software configuration.
694 * @param STOPEntry : Specifies if Stop mode is entered with WFI or WFE
695 * instruction.
696 * This parameter can be one of the following values :
697 * @arg @ref PWR_STOPENTRY_WFI enter Stop mode with Wait
698 * For Interrupt request.
699 * @arg @ref PWR_STOPENTRY_WFE enter Stop mode with Wait
700 * For Event request.
701 * @retval None.
702 */
HAL_PWREx_EnterSTOP3Mode(uint8_t STOPEntry)703 void HAL_PWREx_EnterSTOP3Mode(uint8_t STOPEntry)
704 {
705 /* Check the parameter */
706 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
707
708 /* Set Stop mode 3 */
709 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, (PWR_CR1_LPMS_0 | PWR_CR1_LPMS_1));
710
711 /* Set SLEEPDEEP bit of Cortex System Control Register */
712 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
713
714 /* Select Stop mode entry */
715 if (STOPEntry == PWR_STOPENTRY_WFI)
716 {
717 /* Request Wait For Interrupt */
718 __WFI();
719 }
720 else
721 {
722 /* Request Wait For Event */
723 __SEV();
724 __WFE();
725 __WFE();
726 }
727
728 /* Reset SLEEPDEEP bit of Cortex System Control Register */
729 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
730 }
731
732 /**
733 * @brief Enter the whole system to Shutdown mode.
734 * @note Shutdown mode allows the lowest power consumption. The internal
735 * regulator is switched off so that the VCORE domain is powered off.
736 * The PLL, the HSI16, the MSI (MSIS and MSIK), the LSI and the HSE
737 * oscillators are also switched off.
738 * @note The SRAMs and register contents are lost except for registers in the
739 * Backup domain. The BOR is not available in Shutdown mode. No power
740 * voltage monitoring is possible in this mode, therefore the switch to
741 * Backup domain is not supported.
742 * @retval None.
743 */
HAL_PWREx_EnterSHUTDOWNMode(void)744 void HAL_PWREx_EnterSHUTDOWNMode(void)
745 {
746 /* Set Shutdown mode */
747 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, (PWR_CR1_LPMS_1 | PWR_CR1_LPMS_2));
748
749 /* Set SLEEPDEEP bit of Cortex System Control Register */
750 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
751
752 /* This option is used to ensure that store operations are completed */
753 #if defined (__CC_ARM)
754 __force_stores();
755 #endif /* (__CC_ARM)*/
756 /* Request Wait For Interrupt */
757 __WFI();
758 }
759
760 /**
761 * @brief Configure the SRD domain when the System in Stop 0/1/2 mode.
762 * @param SRDState : Specifies the SRD state.
763 * This parameter can be one of the following values :
764 * @arg PWR_SRD_DOMAIN_STOP : SRD in Stop mode when system
765 * goes to Stop 0/1/2 mode
766 * @arg PWR_SRD_DOMAIN_RUN : SRD in Run mode when system
767 * goes to Stop 0/1/2 mode
768 * @retval None.
769 */
HAL_PWREx_ConfigSRDDomain(uint32_t SRDState)770 void HAL_PWREx_ConfigSRDDomain(uint32_t SRDState)
771 {
772 /* Check the parameter */
773 assert_param(IS_PWR_SRD_STATE(SRDState));
774
775 /* Config the SRD domain */
776 MODIFY_REG(PWR->CR2, PWR_CR2_SRDRUN, SRDState);
777 }
778
779 /**
780 * @brief Enable BOR ultra-low power mode.
781 * @note BOR operating can be in discontinuous (ultra-low power) mode in
782 * Stop 1, Stop 2, Stop 3 and Standby modes and when the regulator is
783 * in Range 4 (Run, Sleep or Stop 0 mode).
784 * @retval None.
785 */
HAL_PWREx_EnableUltraLowPowerMode(void)786 void HAL_PWREx_EnableUltraLowPowerMode(void)
787 {
788 SET_BIT(PWR->CR1, PWR_CR1_ULPMEN);
789 }
790
791 /**
792 * @brief Disable BOR ultra-low power mode.
793 * @retval None.
794 */
HAL_PWREx_DisableUltraLowPowerMode(void)795 void HAL_PWREx_DisableUltraLowPowerMode(void)
796 {
797 CLEAR_BIT(PWR->CR1, PWR_CR1_ULPMEN);
798 }
799
800 /**
801 * @brief This function handles the PWR Wake up from Stop 3 interrupt request.
802 * @note This API should be called under the PWR_S3WU_IRQHandler().
803 * @param WakeUpPin : Specifies the wakeup pin interrupt to be handled.
804 * This parameter can be a combination of @ref PWR_WakeUp_Pins.
805 * @retval None.
806 */
HAL_PWREx_S3WU_IRQHandler(uint32_t WakeUpPin)807 void HAL_PWREx_S3WU_IRQHandler(uint32_t WakeUpPin)
808 {
809 /* Check PWR wake up line 1 */
810 if ((WakeUpPin & PWR_WAKEUP_PIN1) != 0U)
811 {
812 if (READ_BIT(PWR->WUSR, PWR_WUSR_WUF1) != 0U)
813 {
814 /* Clear PWR wake up flag line 1 */
815 SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF1);
816
817 /* PWR S3WU interrupt user callback */
818 HAL_PWREx_S3WUCallback(WakeUpPin);
819 }
820 }
821
822 /* Check PWR wake up line 2 */
823 if ((WakeUpPin & PWR_WAKEUP_PIN2) != 0U)
824 {
825 if (READ_BIT(PWR->WUSR, PWR_WUSR_WUF2) != 0U)
826 {
827 /* Clear PWR wake up flag line 2 */
828 SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF2);
829
830 /* PWR S3WU interrupt user callback */
831 HAL_PWREx_S3WUCallback(WakeUpPin);
832 }
833 }
834
835 /* Check PWR wake up line 3 */
836 if ((WakeUpPin & PWR_WAKEUP_PIN3) != 0U)
837 {
838 if (READ_BIT(PWR->WUSR, PWR_WUSR_WUF3) != 0U)
839 {
840 /* Clear PWR wake up flag line 3 */
841 SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF3);
842
843 /* PWR S3WU interrupt user callback */
844 HAL_PWREx_S3WUCallback(WakeUpPin);
845 }
846 }
847
848 /* Check PWR wake up line 4 */
849 if ((WakeUpPin & PWR_WAKEUP_PIN4) != 0U)
850 {
851 if (READ_BIT(PWR->WUSR, PWR_WUSR_WUF4) != 0U)
852 {
853 /* Clear PWR wake up flag line 4 */
854 SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF4);
855
856 /* PWR S3WU interrupt user callback */
857 HAL_PWREx_S3WUCallback(WakeUpPin);
858 }
859 }
860
861 /* Check PWR wake up line 5 */
862 if ((WakeUpPin & PWR_WAKEUP_PIN5) != 0U)
863 {
864 if (READ_BIT(PWR->WUSR, PWR_WUSR_WUF5) != 0U)
865 {
866 /* Clear PWR wake up flag line 5 */
867 SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF5);
868
869 /* PWR S3WU interrupt user callback */
870 HAL_PWREx_S3WUCallback(WakeUpPin);
871 }
872 }
873
874 /* Check PWR wake up line 6 */
875 if ((WakeUpPin & PWR_WAKEUP_PIN6) != 0U)
876 {
877 if (READ_BIT(PWR->WUSR, PWR_WUSR_WUF6) != 0U)
878 {
879 /* Clear PWR wake up flag line 6 */
880 SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF6);
881
882 /* PWR S3WU interrupt user callback */
883 HAL_PWREx_S3WUCallback(WakeUpPin);
884 }
885 }
886
887 /* Check PWR wake up line 7 */
888 if ((WakeUpPin & PWR_WAKEUP_PIN7) != 0U)
889 {
890 if (READ_BIT(PWR->WUSR, PWR_WUSR_WUF7) != 0U)
891 {
892 /* Clear PWR wake up flag line 7 */
893 SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF7);
894
895 /* PWR S3WU interrupt user callback */
896 HAL_PWREx_S3WUCallback(WakeUpPin);
897 }
898 }
899
900 /* Check PWR wake up line 8 */
901 if ((WakeUpPin & PWR_WAKEUP_PIN8) != 0U)
902 {
903 if (READ_BIT(PWR->WUSR, PWR_WUSR_WUF8) != 0U)
904 {
905 /* Clear PWR wake up flag line 8 */
906 SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF8);
907
908 /* PWR S3WU interrupt user callback */
909 HAL_PWREx_S3WUCallback(WakeUpPin);
910 }
911 }
912 }
913
914 /**
915 * @brief PWR S3WU interrupt callback.
916 * @param WakeUpPin : Specifies the wakeup pin interrupt to be handled.
917 * This parameter can be a combination of @ref PWR_WakeUp_Pins.
918 * @retval None.
919 */
HAL_PWREx_S3WUCallback(uint32_t WakeUpPin)920 __weak void HAL_PWREx_S3WUCallback(uint32_t WakeUpPin)
921 {
922 /* Prevent unused argument(s) compilation warning */
923 UNUSED(WakeUpPin);
924
925 /* NOTE : This function should not be modified; when the callback is needed,
926 HAL_PWREx_S3WU_IRQHandler() API can be implemented in the user file
927 */
928 }
929 /**
930 * @}
931 */
932
933 /** @defgroup PWREx_Exported_Functions_Group3 Voltage Monitoring Functions
934 * @brief Voltage monitoring functions
935 *
936 @verbatim
937 ===============================================================================
938 ##### Voltage Monitoring Functions #####
939 ===============================================================================
940 [..]
941 This section provides functions allowing voltage monitoring.
942
943 *** PVM configuration ***
944 =========================
945 [..]
946 (+) The supplies (VDDA, VDDIO2 and VDDUSB) can be independent from VDD and
947 can be monitored with four peripheral voltage monitoring (PVM):
948
949 (++) The UVM monitors the USB supply VDDUSB. VDDUSBRDY indicates if
950 the VDDUSB independent power supply is higher or lower than the
951 VUVM threshold.
952 (++) The IO2VM monitors the PG[15:2] supply VDDIO2. VDDIO2RDY
953 indicates if the VDDIO2 independent power supply is higher or
954 lower than the VIO2VM threshold.
955 (++) The AVM1 monitors the analog supply VDDA. VDDA1RDY indicates if
956 the VDDA independent power supply is higher or lower than the
957 VAVM1 threshold.
958 (++) The AVM2 monitors the analog supply VDDA. VDDA2RDY indicates if
959 the VDDA independent power supply is higher or lower than the
960 VAVM2 threshold.
961
962 (+) Each PVM output is connected to an EXTI line and can generate an
963 interrupt if enabled through the EXTI registers. The PVMx output
964 interrupt is generated when the independent power supply drops below
965 the PVM threshold and/or when it rises above the PVM threshold,
966 depending on EXTI line rising/falling edge configuration.
967
968 (+) Each PVM can remain active in Stop 0, Stop 1, Stop 2 modes, and the
969 PVM interrupt can wake up from the Stop mode. The PVM is not
970 functional in Stop 3 mode.
971
972 *** VBAT charging ***
973 =====================
974 [..]
975 When VDD is present, it is possible to charge the external battery on VBAT
976 through an internal resistance.
977 The VBAT charging is done either through a 5 kOhm resistor or through a 1.5
978 kOhm resistor depending on the VBRS bit value in the PWR_BDCR2 register.
979 The battery charging is enabled by setting VBE bit in the PWR_BDCR2
980 register. It is automatically disabled in VBAT mode.
981
982 *** Backup domain monitoring ***
983 ================================
984 [..]
985 When the Backup domain voltage and temperature monitoring is enabled
986 (MONEN = 1 in the PWR_BDCR1 register), the Backup domain voltage and the
987 temperature are monitored.
988 If the Backup domain voltage monitoring internal tamper is enabled in the
989 TAMP peripheral (ITAMP1E = 1 in the TAMP_CR1 register), a tamper event is
990 generated when the Backup domain voltage is above the functional range.
991 In case the Backup domain voltage is below the functional range,
992 a Brownout reset is generated, erasing all device including Backup domain.
993
994 *** Backup domain battery ***
995 =============================
996 [..]
997 (+) To retain the content of the backup registers and supply the RTC
998 function when VDD is turned off, the VBAT pin can be connected to an
999 optional backup voltage supplied by a battery or by another source.
1000 The VBAT pin powers the RTC unit, the LSE oscillator and the PC13 to
1001 PC15 I/Os, allowing the RTC to operate even when the main power supply
1002 is turned off. The backup SRAM is optionally powered by VBAT pin when
1003 the BREN bit is set in the PWR Backup domain control register 1
1004 (PWR_BDCR1).
1005 The switch to the VBAT supply is controlled by the power down reset
1006 embedded in the Reset block.
1007
1008 (+) After exiting reset, the USB Type-C �dead battery� behavior is enabled,
1009 which may have a pull-down effect on CC1 and CC2 pins. It is
1010 recommended to disable it in all cases, either to stop this pull-down
1011 or to handover control to the UCPD (the UCPD must be initialized
1012 before doing the disable).
1013
1014 @endverbatim
1015 * @{
1016 */
1017
1018 /**
1019 * @brief Configure the voltage monitor threshold detected by the Peripheral
1020 * voltage monitoring (PVM).
1021 * @param pConfigPVM : Pointer to a PWR_PVMTypeDef structure that contains the
1022 * PVM configuration information (PVMType and EventMode).
1023 * @retval HAL Status.
1024 */
HAL_PWREx_ConfigPVM(PWR_PVMTypeDef * pConfigPVM)1025 HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *pConfigPVM)
1026 {
1027 /* Check the PVM parameter */
1028 if (pConfigPVM == NULL)
1029 {
1030 return HAL_ERROR;
1031 }
1032
1033 /* Check the parameters */
1034 assert_param(IS_PWR_PVM_TYPE(pConfigPVM->PVMType));
1035 assert_param(IS_PWR_PVM_MODE(pConfigPVM->Mode));
1036
1037 /* Check the peripheral voltage monitor type */
1038 switch (pConfigPVM->PVMType)
1039 {
1040 case PWR_UVM: /* Independent USB voltage monitor */
1041
1042 /* Disable EXTI UVM event and interrupt */
1043 __HAL_PWR_UVM_EXTI_DISABLE_EVENT();
1044 __HAL_PWR_UVM_EXTI_DISABLE_IT();
1045 __HAL_PWR_UVM_EXTI_DISABLE_RISING_EDGE();
1046 __HAL_PWR_UVM_EXTI_DISABLE_FALLING_EDGE();
1047
1048 /* Configure the UVM in interrupt mode */
1049 if ((pConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
1050 {
1051 __HAL_PWR_UVM_EXTI_ENABLE_IT();
1052 }
1053
1054 /* Configure the UVM in event mode */
1055 if ((pConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
1056 {
1057 __HAL_PWR_UVM_EXTI_ENABLE_EVENT();
1058 }
1059
1060 /* Configure the UVM in rising edge */
1061 if ((pConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
1062 {
1063 __HAL_PWR_UVM_EXTI_ENABLE_RISING_EDGE();
1064 }
1065
1066 /* Configure the UVM in falling edge */
1067 if ((pConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
1068 {
1069 __HAL_PWR_UVM_EXTI_ENABLE_FALLING_EDGE();
1070 }
1071
1072 break;
1073
1074 case PWR_IO2VM: /* Independent I/Os voltage monitor */
1075
1076 /* Disable EXTI IO2VM event and interrupt */
1077 __HAL_PWR_IO2VM_EXTI_DISABLE_EVENT();
1078 __HAL_PWR_IO2VM_EXTI_DISABLE_IT();
1079 __HAL_PWR_IO2VM_EXTI_DISABLE_RISING_EDGE();
1080 __HAL_PWR_IO2VM_EXTI_DISABLE_FALLING_EDGE();
1081
1082 /* Configure the IO2VM in interrupt mode */
1083 if ((pConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
1084 {
1085 __HAL_PWR_IO2VM_EXTI_ENABLE_IT();
1086 }
1087
1088 /* Configure the IO2VM in event mode */
1089 if ((pConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
1090 {
1091 __HAL_PWR_IO2VM_EXTI_ENABLE_EVENT();
1092 }
1093
1094 /* Configure the IO2VM in rising edge */
1095 if ((pConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
1096 {
1097 __HAL_PWR_IO2VM_EXTI_ENABLE_RISING_EDGE();
1098 }
1099
1100 /* Configure the IO2VM in falling edge */
1101 if ((pConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
1102 {
1103 __HAL_PWR_IO2VM_EXTI_ENABLE_FALLING_EDGE();
1104 }
1105
1106 break;
1107
1108 case PWR_AVM1: /* VDDA Independent analog supply voltage monitor 1 (1.6V threshold) */
1109
1110 /* Disable EXTI AVM1 event and interrupt */
1111 __HAL_PWR_AVM1_EXTI_DISABLE_EVENT();
1112 __HAL_PWR_AVM1_EXTI_DISABLE_IT();
1113 __HAL_PWR_AVM1_EXTI_DISABLE_RISING_EDGE();
1114 __HAL_PWR_AVM1_EXTI_DISABLE_FALLING_EDGE();
1115
1116 /* Configure the AVM1 in interrupt mode */
1117 if ((pConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
1118 {
1119 __HAL_PWR_AVM1_EXTI_ENABLE_IT();
1120 }
1121
1122 /* Configure the AVM1 in event mode */
1123 if ((pConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
1124 {
1125 __HAL_PWR_AVM1_EXTI_ENABLE_EVENT();
1126 }
1127
1128 /* Configure the AVM1 in rising edge */
1129 if ((pConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
1130 {
1131 __HAL_PWR_AVM1_EXTI_ENABLE_RISING_EDGE();
1132 }
1133
1134 /* Configure the AVM1 in falling edge */
1135 if ((pConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
1136 {
1137 __HAL_PWR_AVM1_EXTI_ENABLE_FALLING_EDGE();
1138 }
1139
1140 break;
1141
1142 case PWR_AVM2: /* VDDA Independent analog supply voltage monitor 2 (1.8V threshold) */
1143
1144 /* Disable EXTI AVM2 event and interrupt */
1145 __HAL_PWR_AVM2_EXTI_DISABLE_EVENT();
1146 __HAL_PWR_AVM2_EXTI_DISABLE_IT();
1147 __HAL_PWR_AVM2_EXTI_DISABLE_RISING_EDGE();
1148 __HAL_PWR_AVM2_EXTI_DISABLE_FALLING_EDGE();
1149
1150 /* Configure the AVM2 in interrupt mode */
1151 if ((pConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
1152 {
1153 __HAL_PWR_AVM2_EXTI_ENABLE_IT();
1154 }
1155
1156 /* Configure the AVM2 in event mode */
1157 if ((pConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
1158 {
1159 __HAL_PWR_AVM2_EXTI_ENABLE_EVENT();
1160 }
1161
1162 /* Configure the AVM2 in rising edge */
1163 if ((pConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
1164 {
1165 __HAL_PWR_AVM2_EXTI_ENABLE_RISING_EDGE();
1166 }
1167
1168 /* Configure the AVM2 in falling edge */
1169 if ((pConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
1170 {
1171 __HAL_PWR_AVM2_EXTI_ENABLE_FALLING_EDGE();
1172 }
1173
1174 break;
1175
1176 default: /* No valid voltage monitor selected */
1177 return HAL_ERROR;
1178 break;
1179 }
1180
1181 return HAL_OK;
1182 }
1183
1184 /**
1185 * @brief Enable VDDUSB supply.
1186 * @note Remove VDDUSB electrical and logical isolation, once VDDUSB supply
1187 * is present for consumption saving.
1188 * @retval None.
1189 */
HAL_PWREx_EnableVddUSB(void)1190 void HAL_PWREx_EnableVddUSB(void)
1191 {
1192 SET_BIT(PWR->SVMCR, PWR_SVMCR_USV);
1193 }
1194
1195 /**
1196 * @brief Disable VDDUSB supply.
1197 * @retval None.
1198 */
HAL_PWREx_DisableVddUSB(void)1199 void HAL_PWREx_DisableVddUSB(void)
1200 {
1201 CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_USV);
1202 }
1203
1204 /**
1205 * @brief Enable VDDIO2 supply.
1206 * @note Remove VDDIO2 electrical and logical isolation, once VDDIO2 supply
1207 * is present for consumption saving.
1208 * @retval None.
1209 */
HAL_PWREx_EnableVddIO2(void)1210 void HAL_PWREx_EnableVddIO2(void)
1211 {
1212 SET_BIT(PWR->SVMCR, PWR_SVMCR_IO2SV);
1213 }
1214
1215 /**
1216 * @brief Disable VDDIO2 supply.
1217 * @retval None.
1218 */
HAL_PWREx_DisableVddIO2(void)1219 void HAL_PWREx_DisableVddIO2(void)
1220 {
1221 CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_IO2SV);
1222 }
1223
1224 /**
1225 * @brief Enable VDDA supply.
1226 * @note Remove VDDA electrical and logical isolation, once VDDA supply is
1227 * present for consumption saving.
1228 * @retval None.
1229 */
HAL_PWREx_EnableVddA(void)1230 void HAL_PWREx_EnableVddA(void)
1231 {
1232 SET_BIT(PWR->SVMCR, PWR_SVMCR_ASV);
1233 }
1234
1235 /**
1236 * @brief Disable VDDA supply.
1237 * @retval None.
1238 */
HAL_PWREx_DisableVddA(void)1239 void HAL_PWREx_DisableVddA(void)
1240 {
1241 CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_ASV);
1242 }
1243
1244 /**
1245 * @brief Enable the UVM Voltage Monitoring : VDDUSB versus 1.2 V.
1246 * @retval None.
1247 */
HAL_PWREx_EnableUVM(void)1248 void HAL_PWREx_EnableUVM(void)
1249 {
1250 SET_BIT(PWR->SVMCR, PWR_SVMCR_UVMEN);
1251 }
1252
1253 /**
1254 * @brief Disable the UVM Voltage Monitoring : VDDUSB versus 1.2 V.
1255 * @retval None.
1256 */
HAL_PWREx_DisableUVM(void)1257 void HAL_PWREx_DisableUVM(void)
1258 {
1259 CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_UVMEN);
1260 }
1261
1262 /**
1263 * @brief Enable the IO2VM Voltage Monitoring : VDDIO2 versus 0.9 V.
1264 * @retval None.
1265 */
HAL_PWREx_EnableIO2VM(void)1266 void HAL_PWREx_EnableIO2VM(void)
1267 {
1268 SET_BIT(PWR->SVMCR, PWR_SVMCR_IO2VMEN);
1269 }
1270
1271 /**
1272 * @brief Disable the IO2VM Voltage Monitoring : VDDIO2 versus 0.9 V.
1273 * @retval None.
1274 */
HAL_PWREx_DisableIO2VM(void)1275 void HAL_PWREx_DisableIO2VM(void)
1276 {
1277 CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_IO2VMEN);
1278 }
1279
1280 /**
1281 * @brief Enable the AVM1 Voltage Monitoring : VDDA versus 1.6 V.
1282 * @retval None.
1283 */
HAL_PWREx_EnableAVM1(void)1284 void HAL_PWREx_EnableAVM1(void)
1285 {
1286 SET_BIT(PWR->SVMCR, PWR_SVMCR_AVM1EN);
1287 }
1288
1289 /**
1290 * @brief Disable the AVM1 Voltage Monitoring : VDDA versus 1.6 V.
1291 * @retval None.
1292 */
HAL_PWREx_DisableAVM1(void)1293 void HAL_PWREx_DisableAVM1(void)
1294 {
1295 CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_AVM1EN);
1296 }
1297
1298 /**
1299 * @brief Enable the AVM2 Voltage Monitoring : VDDA versus 1.8 V.
1300 * @retval None.
1301 */
HAL_PWREx_EnableAVM2(void)1302 void HAL_PWREx_EnableAVM2(void)
1303 {
1304 SET_BIT(PWR->SVMCR, PWR_SVMCR_AVM2EN);
1305 }
1306
1307 /**
1308 * @brief Disable the AVM2 Voltage Monitoring : VDDA versus 1.8 V.
1309 * @retval None.
1310 */
HAL_PWREx_DisableAVM2(void)1311 void HAL_PWREx_DisableAVM2(void)
1312 {
1313 CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_AVM2EN);
1314 }
1315
1316 /**
1317 * @brief Enable the VBAT and temperature monitoring.
1318 * @retval None.
1319 */
HAL_PWREx_EnableMonitoring(void)1320 void HAL_PWREx_EnableMonitoring(void)
1321 {
1322 SET_BIT(PWR->BDCR1, PWR_BDCR1_MONEN);
1323 }
1324
1325 /**
1326 * @brief Disable the VBAT and temperature monitoring.
1327 * @retval None.
1328 */
HAL_PWREx_DisableMonitoring(void)1329 void HAL_PWREx_DisableMonitoring(void)
1330 {
1331 CLEAR_BIT(PWR->BDCR1, PWR_BDCR1_MONEN);
1332 }
1333
1334 /**
1335 * @brief Enable UCPD configuration memorization in Standby mode.
1336 * @retval None.
1337 */
HAL_PWREx_EnableUCPDStandbyMode(void)1338 void HAL_PWREx_EnableUCPDStandbyMode(void)
1339 {
1340 SET_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_STDBY);
1341 }
1342
1343 /**
1344 * @brief Disable UCPD configuration memorization in Standby mode.
1345 * @note This function must be called on exiting the Standby mode and before
1346 * any UCPD configuration update.
1347 * @retval None.
1348 */
HAL_PWREx_DisableUCPDStandbyMode(void)1349 void HAL_PWREx_DisableUCPDStandbyMode(void)
1350 {
1351 CLEAR_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_STDBY);
1352 }
1353
1354 /**
1355 * @brief Enable dead battery behavior.
1356 * @note After exiting reset, the USB Type-C �dead battery� behavior is
1357 * enabled, which may have a pull-down effect on CC1 and CC2 pins.
1358 * It is recommended to disable it in all cases, either to stop this
1359 * pull-down or to handover control to the UCPD (the UCPD must be
1360 * initialized before doing the disable).
1361 * @retval None.
1362 */
HAL_PWREx_EnableUCPDDeadBattery(void)1363 void HAL_PWREx_EnableUCPDDeadBattery(void)
1364 {
1365 CLEAR_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_DBDIS);
1366 }
1367
1368 /**
1369 * @brief Disable dead battery behavior.
1370 * @note After exiting reset, the USB Type-C �dead battery� behavior is
1371 * enabled, which may have a pull-down effect on CC1 and CC2 pins.
1372 * It is recommended to disable it in all cases, either to stop this
1373 * pull-down or to handover control to the UCPD (the UCPD must be
1374 * initialized before doing the disable).
1375 * @retval None.
1376 */
HAL_PWREx_DisableUCPDDeadBattery(void)1377 void HAL_PWREx_DisableUCPDDeadBattery(void)
1378 {
1379 SET_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_DBDIS);
1380 }
1381
1382 /**
1383 * @brief Enable the Battery charging.
1384 * @note When VDD is present, charge the external battery through an internal
1385 * resistor.
1386 * @param ResistorValue : Specifies the charging resistor.
1387 * This parameter can be one of the following values :
1388 * @arg PWR_BATTERY_CHARGING_RESISTOR_5 : 5 KOhm resistor.
1389 * @arg PWR_BATTERY_CHARGING_RESISTOR_1_5 : 1.5 KOhm resistor.
1390 * @retval None.
1391 */
HAL_PWREx_EnableBatteryCharging(uint32_t ResistorValue)1392 void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorValue)
1393 {
1394 /* Check the parameter */
1395 assert_param(IS_PWR_BATTERY_RESISTOR_SELECT(ResistorValue));
1396
1397 /* Specify the charging resistor */
1398 MODIFY_REG(PWR->BDCR2, PWR_BDCR2_VBRS, ResistorValue);
1399
1400 /* Enable the Battery charging */
1401 SET_BIT(PWR->BDCR2, PWR_BDCR2_VBE);
1402 }
1403
1404 /**
1405 * @brief Disable the Battery charging.
1406 * @retval None.
1407 */
HAL_PWREx_DisableBatteryCharging(void)1408 void HAL_PWREx_DisableBatteryCharging(void)
1409 {
1410 CLEAR_BIT(PWR->BDCR2, PWR_BDCR2_VBE);
1411 }
1412
1413 /**
1414 * @brief This function handles the PWR PVD/PVM interrupt request.
1415 * @note This API should be called under the PVD_PVM_IRQHandler().
1416 * @retval None.
1417 */
HAL_PWREx_PVD_PVM_IRQHandler(void)1418 void HAL_PWREx_PVD_PVM_IRQHandler(void)
1419 {
1420 uint32_t rising_flag;
1421 uint32_t falling_flag;
1422
1423 /* Get pending flags */
1424 rising_flag = READ_REG(EXTI->RPR1);
1425 falling_flag = READ_REG(EXTI->FPR1);
1426
1427 /* Check PWR exti flags for PVD */
1428 if (((rising_flag | falling_flag) & PWR_EXTI_LINE_PVD) != 0U)
1429 {
1430 /* PWR PVD interrupt user callback */
1431 HAL_PWR_PVDCallback();
1432
1433 /* Clear PVD exti pending bit */
1434 WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_PVD);
1435 WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_PVD);
1436 }
1437
1438 /* Check PWR exti flags for UVM */
1439 if (((rising_flag | falling_flag) & PWR_EXTI_LINE_UVM) != 0U)
1440 {
1441 /* PWR UVM interrupt user callback */
1442 HAL_PWREx_UVMCallback();
1443
1444 /* Clear UVM exti pending bit */
1445 WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_UVM);
1446 WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_UVM);
1447 }
1448
1449 /* Check PWR exti flags for IO2VM */
1450 if (((rising_flag | falling_flag) & PWR_EXTI_LINE_IO2VM) != 0U)
1451 {
1452 /* PWR IO2VM interrupt user callback */
1453 HAL_PWREx_IO2VMCallback();
1454
1455 /* Clear IO2VM exti pending bit */
1456 WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_IO2VM);
1457 WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_IO2VM);
1458 }
1459
1460 /* Check PWR exti flags for AVM1 */
1461 if (((rising_flag | falling_flag) & PWR_EXTI_LINE_AVM1) != 0U)
1462 {
1463 /* PWR AVM1 interrupt user callback */
1464 HAL_PWREx_AVM1Callback();
1465
1466 /* Clear AVM1 exti pending bit */
1467 WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_AVM1);
1468 WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_AVM1);
1469 }
1470
1471 /* Check PWR exti flags for AVM2 */
1472 if (((rising_flag | falling_flag) & PWR_EXTI_LINE_AVM2) != 0U)
1473 {
1474 /* PWR AVM2 interrupt user callback */
1475 HAL_PWREx_AVM2Callback();
1476
1477 /* Clear AVM2 exti pending bit */
1478 WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_AVM2);
1479 WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_AVM2);
1480 }
1481 }
1482
1483 /**
1484 * @brief PWR UVM interrupt callback.
1485 * @retval None.
1486 */
HAL_PWREx_UVMCallback(void)1487 __weak void HAL_PWREx_UVMCallback(void)
1488 {
1489 /* NOTE : This function should not be modified; when the callback is needed,
1490 HAL_PWREx_UVMCallback() API can be implemented in the user file
1491 */
1492 }
1493
1494 /**
1495 * @brief PWR IO2VM interrupt callback.
1496 * @retval None.
1497 */
HAL_PWREx_IO2VMCallback(void)1498 __weak void HAL_PWREx_IO2VMCallback(void)
1499 {
1500 /* NOTE : This function should not be modified; when the callback is needed,
1501 HAL_PWREx_IO2VMCallback() API can be implemented in the user file
1502 */
1503 }
1504
1505 /**
1506 * @brief PWR AVM1 interrupt callback.
1507 * @retval None.
1508 */
HAL_PWREx_AVM1Callback(void)1509 __weak void HAL_PWREx_AVM1Callback(void)
1510 {
1511 /* NOTE : This function should not be modified; when the callback is needed,
1512 HAL_PWREx_AVM1Callback() API can be implemented in the user file
1513 */
1514 }
1515
1516 /**
1517 * @brief PWR AVM2 interrupt callback.
1518 * @retval None.
1519 */
HAL_PWREx_AVM2Callback(void)1520 __weak void HAL_PWREx_AVM2Callback(void)
1521 {
1522 /* NOTE : This function should not be modified; when the callback is needed,
1523 HAL_PWREx_AVM2Callback() API can be implemented in the user file
1524 */
1525 }
1526 /**
1527 * @}
1528 */
1529
1530 /** @defgroup PWREx_Exported_Functions_Group4 Memories Retention Functions
1531 * @brief Memories retention functions
1532 *
1533 @verbatim
1534 ===============================================================================
1535 ##### Memories Retention Functions #####
1536 ===============================================================================
1537 [..]
1538 Several STM32U5 devices RAMs are configurable to keep / lose RAMs content
1539 during Stop mode (Stop 0/1/2/3).
1540 (+) Retained content RAMs in Stop modes are :
1541 (++) SRAM1
1542 (++) SRAM2
1543 (++) SRAM3
1544 (++) SRAM4
1545 (++) ICACHE
1546 (++) DMA2DRAM
1547 (++) PKA32RAM
1548 (++) DCACHE
1549 (++) FMAC
1550 (++) FDCAN
1551 (++) USB
1552
1553 [..]
1554 Several STM32U5 devices RAMs are configurable to keep / lose RAMs content
1555 during Run mode.
1556 (+) Retained content RAMs in Run modes are :
1557 (++) SRAM1
1558 (++) SRAM2
1559 (++) SRAM3
1560 (++) SRAM4
1561
1562 [..]
1563 SRAM2 is configurable to keep / lose its content in Stop 3 and Standby
1564 modes. The SRAM2 retention feature granularity is at pages level.
1565
1566 [..]
1567 BKPRAM is configurable to keep / lose its content in Standby, Shutdown and
1568 VBAT modes.
1569
1570 @endverbatim
1571 * @{
1572 */
1573
1574 /**
1575 * @brief Enable SRAM2 page(s) content retention in Stop 3 and Standby mode.
1576 * @note When RRSx bit is set, SRAM2 is powered by the low-power regulator in
1577 * Stop 3 and Standby mode and its content is kept.
1578 * @param SRAM2Pages : Specifies the SRAM2 pages.
1579 * This parameter can be one of the following values :
1580 * @arg PWR_SRAM2_PAGE1_STANDBY_RETENTION : SRAM2 page 1 retention.
1581 * @arg PWR_SRAM2_PAGE2_STANDBY_RETENTION : SRAM2 page 2 retention.
1582 * @arg PWR_SRAM2_FULL_STANDBY_RETENTION : SRAM2 page 1 and page 2 retention.
1583 * @retval None.
1584 */
HAL_PWREx_EnableSRAM2ContentStandbyRetention(uint32_t SRAM2Pages)1585 void HAL_PWREx_EnableSRAM2ContentStandbyRetention(uint32_t SRAM2Pages)
1586 {
1587 /* Check the parameters */
1588 assert_param(IS_PWR_SRAM2_STANDBY_RETENTION(SRAM2Pages));
1589
1590 /* Set RRSx bit(s) */
1591 SET_BIT(PWR->CR1, SRAM2Pages);
1592 }
1593
1594 /**
1595 * @brief Disable SRAM2 page(s) content retention in Stop 3 and Standby mode.
1596 * @note When RRSx bit is reset, SRAM2 is powered off in Stop 3 and Standby
1597 * mode and its content is lost.
1598 * @param SRAM2Pages : Specifies the SRAM2 pages.
1599 * This parameter can be one of the following values :
1600 * @arg PWR_SRAM2_PAGE1_STANDBY_RETENTION : SRAM2 page 1 retention.
1601 * @arg PWR_SRAM2_PAGE2_STANDBY_RETENTION : SRAM2 page 2 retention.
1602 * @arg PWR_SRAM2_FULL_STANDBY_RETENTION : SRAM2 page 1 and page 2 retention.
1603 * @retval None.
1604 */
HAL_PWREx_DisableSRAM2ContentStandbyRetention(uint32_t SRAM2Pages)1605 void HAL_PWREx_DisableSRAM2ContentStandbyRetention(uint32_t SRAM2Pages)
1606 {
1607 /* Check the parameters */
1608 assert_param(IS_PWR_SRAM2_STANDBY_RETENTION(SRAM2Pages));
1609
1610 /* Clear RRSx bit(s) */
1611 CLEAR_BIT(PWR->CR1, SRAM2Pages);
1612 }
1613
1614 /**
1615 * @brief Enable RAM page(s) content retention in Stop mode (Stop 0, 1, 2, 3).
1616 * @note When enabling content retention for a given RAM, memory kept powered
1617 * in Stop mode. (Not optimized power consumption)
1618 * @param RAMSelection: Specifies RAM page(s) to be retained in Stop mode.
1619 * This parameter can be one or a combination of the same
1620 * memory @ref PWREx_RAM_Contents_Stop_Retention.
1621 * @retval None.
1622 */
HAL_PWREx_EnableRAMsContentStopRetention(uint32_t RAMSelection)1623 void HAL_PWREx_EnableRAMsContentStopRetention(uint32_t RAMSelection)
1624 {
1625 uint32_t dummy;
1626
1627 /* Check RAM ID */
1628 switch (RAMSelection & SRAM_ID_MASK)
1629 {
1630 /* SRAM 1 Stop retention */
1631 case SRAM1_ID:
1632 {
1633 /* Check the parameters */
1634 assert_param(IS_PWR_SRAM1_STOP_RETENTION(RAMSelection));
1635
1636 /* Calculate pages mask */
1637 dummy = (RAMSelection & ~SRAM_ID_MASK) & (PAGE01_ID | PAGE02_ID | PAGE03_ID);
1638 CLEAR_BIT(PWR->CR2, dummy);
1639
1640 break;
1641 }
1642
1643 /* SRAM 2 Stop retention */
1644 case SRAM2_ID:
1645 {
1646 /* Check the parameters */
1647 assert_param(IS_PWR_SRAM2_STOP_RETENTION(RAMSelection));
1648
1649 /* Calculate pages mask */
1650 dummy = (RAMSelection & PWR_SRAM2_FULL_STOP_RETENTION) & ~SRAM_ID_MASK;
1651 CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_SRAM2PDS1_Pos));
1652
1653 break;
1654 }
1655
1656 /* SRAM 3 Stop retention */
1657 case SRAM3_ID:
1658 {
1659 /* Check the parameters */
1660 assert_param(IS_PWR_SRAM3_STOP_RETENTION(RAMSelection));
1661
1662 /* Calculate pages mask */
1663 dummy = (RAMSelection & ~SRAM_ID_MASK) & (PAGE01_ID | PAGE02_ID | PAGE03_ID | PAGE04_ID |
1664 PAGE05_ID | PAGE06_ID | PAGE07_ID | PAGE08_ID);
1665 CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_SRAM3PDS1_Pos));
1666
1667 break;
1668 }
1669
1670 /* SRAM 4 Stop retention */
1671 case SRAM4_ID:
1672 {
1673 /* Check the parameters */
1674 assert_param(IS_PWR_SRAM4_STOP_RETENTION(RAMSelection));
1675
1676 /* Calculate pages mask */
1677 dummy = (RAMSelection & PWR_SRAM4_FULL_STOP_RETENTION) & ~SRAM_ID_MASK;
1678 CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_SRAM4PDS_Pos));
1679
1680 break;
1681 }
1682
1683 /* ICACHE RAM Stop retention */
1684 case ICACHERAM_ID:
1685 {
1686 /* Check the parameters */
1687 assert_param(IS_PWR_ICACHE_STOP_RETENTION(RAMSelection));
1688
1689 /* Calculate pages mask */
1690 dummy = (RAMSelection & PWR_ICACHE_FULL_STOP_RETENTION) & ~SRAM_ID_MASK;
1691 CLEAR_BIT(PWR->CR2, dummy << PWR_CR2_ICRAMPDS_Pos);
1692
1693 break;
1694 }
1695
1696 /* DCACHE1 RAM Stop retention */
1697 case DCACHE1RAM_ID:
1698 {
1699 /* Check the parameters */
1700 assert_param(IS_PWR_DCACHE1_STOP_RETENTION(RAMSelection));
1701
1702 /* Calculate pages mask */
1703 dummy = (RAMSelection & PWR_DCACHE1_FULL_STOP_RETENTION) & ~SRAM_ID_MASK;
1704 CLEAR_BIT(PWR->CR2, dummy << PWR_CR2_DC1RAMPDS_Pos);
1705
1706 break;
1707 }
1708
1709 /* DMA2D RAM Stop retention */
1710 case DMA2DRAM_ID:
1711 {
1712 /* Check the parameters */
1713 assert_param(IS_PWR_DMA2DRAM_STOP_RETENTION(RAMSelection));
1714
1715 /* Calculate pages mask */
1716 dummy = (RAMSelection & PWR_DMA2DRAM_FULL_STOP_RETENTION) & ~SRAM_ID_MASK;
1717 CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_DMA2DRAMPDS_Pos));
1718
1719 break;
1720 }
1721
1722 /* FMAC, FDCAN and USB RAM Stop retention */
1723 case PERIPHRAM_ID:
1724 {
1725 /* Check the parameters */
1726 assert_param(IS_PWR_PERIPHRAM_STOP_RETENTION(RAMSelection));
1727
1728 /* Calculate pages mask */
1729 dummy = (RAMSelection & PWR_PERIPHRAM_FULL_STOP_RETENTION) & ~SRAM_ID_MASK;
1730 CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_PRAMPDS_Pos));
1731
1732 break;
1733 }
1734
1735 /* PKA32 RAM Stop retention */
1736 case PKARAM_ID:
1737 {
1738 /* Check the parameters */
1739 assert_param(IS_PWR_PKA32RAM_STOP_RETENTION(RAMSelection));
1740
1741 /* Calculate pages mask */
1742 dummy = (RAMSelection & PWR_PKA32RAM_FULL_STOP_RETENTION) & ~SRAM_ID_MASK;
1743 CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_PKARAMPDS_Pos));
1744
1745 break;
1746 }
1747
1748 default:
1749 {
1750 return;
1751 break;
1752 }
1753 }
1754 }
1755
1756 /**
1757 * @brief Disable RAM page(s) content lost in Stop mode (Stop 0, 1, 2, 3).
1758 * @note When disabling content lost for a given RAM, memory powered down
1759 * in Stop mode. (Optimized power consumption)
1760 * @param RAMSelection: Specifies RAM page(s) to be lost in Stop mode.
1761 * This parameter can be one or a combination of the same
1762 * memory @ref PWREx_RAM_Contents_Stop_Retention.
1763 * @retval None.
1764 */
HAL_PWREx_DisableRAMsContentStopRetention(uint32_t RAMSelection)1765 void HAL_PWREx_DisableRAMsContentStopRetention(uint32_t RAMSelection)
1766 {
1767 uint32_t dummy;
1768
1769 /* Check RAM ID */
1770 switch (RAMSelection & SRAM_ID_MASK)
1771 {
1772 /* SRAM 1 Stop retention */
1773 case SRAM1_ID:
1774 {
1775 /* Check the parameters */
1776 assert_param(IS_PWR_SRAM1_STOP_RETENTION(RAMSelection));
1777
1778 /* Calculate pages mask */
1779 dummy = (RAMSelection & ~SRAM_ID_MASK) & (PAGE01_ID | PAGE02_ID | PAGE03_ID);
1780 SET_BIT(PWR->CR2, dummy);
1781
1782 break;
1783 }
1784
1785 /* SRAM 2 Stop retention */
1786 case SRAM2_ID:
1787 {
1788 /* Check the parameters */
1789 assert_param(IS_PWR_SRAM2_STOP_RETENTION(RAMSelection));
1790
1791 /* Calculate pages mask */
1792 dummy = (RAMSelection & PWR_SRAM2_FULL_STOP_RETENTION) & ~SRAM_ID_MASK;
1793 SET_BIT(PWR->CR2, (dummy << PWR_CR2_SRAM2PDS1_Pos));
1794
1795 break;
1796 }
1797
1798 /* SRAM 3 Stop retention */
1799 case SRAM3_ID:
1800 {
1801 /* Check the parameters */
1802 assert_param(IS_PWR_SRAM3_STOP_RETENTION(RAMSelection));
1803
1804 /* Calculate pages mask */
1805 dummy = (RAMSelection & ~SRAM_ID_MASK) & (PAGE01_ID | PAGE02_ID | PAGE03_ID | PAGE04_ID |
1806 PAGE05_ID | PAGE06_ID | PAGE07_ID | PAGE08_ID);
1807 SET_BIT(PWR->CR2, (dummy << PWR_CR2_SRAM3PDS1_Pos));
1808
1809 break;
1810 }
1811
1812 /* SRAM 4 Stop retention */
1813 case SRAM4_ID:
1814 {
1815 /* Check the parameters */
1816 assert_param(IS_PWR_SRAM4_STOP_RETENTION(RAMSelection));
1817
1818 /* Calculate pages mask */
1819 dummy = (RAMSelection & PWR_SRAM4_FULL_STOP_RETENTION) & ~SRAM_ID_MASK;
1820 SET_BIT(PWR->CR2, (dummy << PWR_CR2_SRAM4PDS_Pos));
1821
1822 break;
1823 }
1824
1825 /* ICACHE RAM Stop retention */
1826 case ICACHERAM_ID:
1827 {
1828 /* Check the parameters */
1829 assert_param(IS_PWR_ICACHE_STOP_RETENTION(RAMSelection));
1830
1831 /* Calculate pages mask */
1832 dummy = (RAMSelection & PWR_ICACHE_FULL_STOP_RETENTION) & ~SRAM_ID_MASK;
1833 SET_BIT(PWR->CR2, (dummy << PWR_CR2_ICRAMPDS_Pos));
1834
1835 break;
1836 }
1837
1838 /* DCACHE1 RAM Stop retention */
1839 case DCACHE1RAM_ID:
1840 {
1841 /* Check the parameters */
1842 assert_param(IS_PWR_DCACHE1_STOP_RETENTION(RAMSelection));
1843
1844 /* Calculate pages mask */
1845 dummy = (RAMSelection & PWR_DCACHE1_FULL_STOP_RETENTION) & ~SRAM_ID_MASK;
1846 SET_BIT(PWR->CR2, (dummy << PWR_CR2_DC1RAMPDS_Pos));
1847
1848 break;
1849 }
1850
1851 /* DMA2D RAM Stop retention */
1852 case DMA2DRAM_ID:
1853 {
1854 /* Check the parameters */
1855 assert_param(IS_PWR_DMA2DRAM_STOP_RETENTION(RAMSelection));
1856
1857 /* Calculate pages mask */
1858 dummy = (RAMSelection & PWR_DMA2DRAM_FULL_STOP_RETENTION) & ~SRAM_ID_MASK;
1859 SET_BIT(PWR->CR2, (dummy << PWR_CR2_DMA2DRAMPDS_Pos));
1860
1861 break;
1862 }
1863
1864 /* FMAC, FDCAN and USB RAM Stop retention */
1865 case PERIPHRAM_ID:
1866 {
1867 /* Check the parameters */
1868 assert_param(IS_PWR_PERIPHRAM_STOP_RETENTION(RAMSelection));
1869
1870 /* Calculate pages mask */
1871 dummy = (RAMSelection & PWR_PERIPHRAM_FULL_STOP_RETENTION) & ~SRAM_ID_MASK;
1872 SET_BIT(PWR->CR2, (dummy << PWR_CR2_PRAMPDS_Pos));
1873
1874 break;
1875 }
1876
1877 /* PKA32 RAM Stop retention */
1878 case PKARAM_ID:
1879 {
1880 /* Check the parameters */
1881 assert_param(IS_PWR_PKA32RAM_STOP_RETENTION(RAMSelection));
1882
1883 /* Calculate pages mask */
1884 dummy = (RAMSelection & PWR_PKA32RAM_FULL_STOP_RETENTION) & ~SRAM_ID_MASK;
1885 SET_BIT(PWR->CR2, (dummy << PWR_CR2_PKARAMPDS_Pos));
1886
1887 break;
1888 }
1889
1890 default:
1891 {
1892 return;
1893 break;
1894 }
1895 }
1896 }
1897
1898 /**
1899 * @brief Enable RAMs full content retention in Run mode.
1900 * @param RAMSelection : Specifies the SRAM content to be retained in Run mode.
1901 * This parameter can be one or a combination of the following values :
1902 * @arg PWR_SRAM1_FULL_RUN_RETENTION : SRAM1 full content retention.
1903 * @arg PWR_SRAM2_FULL_RUN_RETENTION : SRAM2 full content retention.
1904 * @arg PWR_SRAM3_FULL_RUN_RETENTION : SRAM3 full content retention.
1905 * @arg PWR_SRAM4_FULL_RUN_RETENTION : SRAM4 full content retention.
1906 * @retval None.
1907 */
HAL_PWREx_EnableRAMsContentRunRetention(uint32_t RAMSelection)1908 void HAL_PWREx_EnableRAMsContentRunRetention(uint32_t RAMSelection)
1909 {
1910 /* Check the parameters */
1911 assert_param(IS_PWR_RAM_RUN_RETENTION(RAMSelection));
1912
1913 /* Enable RAM retention in Run mode */
1914 CLEAR_BIT(PWR->CR1, RAMSelection);
1915 }
1916
1917 /**
1918 * @brief Disable RAMs full content retention in Run mode.
1919 * @param RAMSelection : Specifies the SRAM content to be lost in Run mode.
1920 * This parameter can be one or a combination of the following values :
1921 * @arg PWR_SRAM1_FULL_RUN_RETENTION : SRAM1 full content lost.
1922 * @arg PWR_SRAM2_FULL_RUN_RETENTION : SRAM2 full content lost.
1923 * @arg PWR_SRAM3_FULL_RUN_RETENTION : SRAM3 full content lost.
1924 * @arg PWR_SRAM4_FULL_RUN_RETENTION : SRAM4 full content lost.
1925 * @retval None.
1926 */
HAL_PWREx_DisableRAMsContentRunRetention(uint32_t RAMSelection)1927 void HAL_PWREx_DisableRAMsContentRunRetention(uint32_t RAMSelection)
1928 {
1929 /* Check the parameters */
1930 assert_param(IS_PWR_RAM_RUN_RETENTION(RAMSelection));
1931
1932 /* Disable RAM retention in Run mode */
1933 SET_BIT(PWR->CR1, RAMSelection);
1934 }
1935
1936 /**
1937 * @brief Enable the Backup RAM retention in Standby, Shutdown and VBAT modes.
1938 * @note If BREN is reset, the backup RAM can still be used in Run, Sleep and
1939 * Stop modes. However, its content is lost in Standby, Shutdown and
1940 * VBAT modes.
1941 * @note This bit can be enabled only when LDO regulator is selected as
1942 * source supply.
1943 * @retval HAL Status.
1944 */
HAL_PWREx_EnableBkupRAMRetention(void)1945 HAL_StatusTypeDef HAL_PWREx_EnableBkupRAMRetention(void)
1946 {
1947 /*
1948 Backup RAM retention in Standby, Shutdown and VBAT should be enabled
1949 when the Vcore is alimented by the LDO regulator
1950 */
1951 if (HAL_PWREx_GetSupplyConfig() == PWR_LDO_SUPPLY)
1952 {
1953 SET_BIT(PWR->BDCR1, PWR_BDCR1_BREN);
1954 }
1955 /* SMPS regulator selected */
1956 else
1957 {
1958 return HAL_ERROR;
1959 }
1960
1961 return HAL_OK;
1962 }
1963
1964 /**
1965 * @brief Disable the Backup RAM retention in Standby, Shutdown and VBAT modes.
1966 * @note If BREN is reset, the backup RAM can still be used in Run, Sleep and
1967 * Stop modes. However, its content is lost in Standby, Shutdown and
1968 * VBAT modes. This bit can be writte
1969 * @retval None.
1970 */
HAL_PWREx_DisableBkupRAMRetention(void)1971 void HAL_PWREx_DisableBkupRAMRetention(void)
1972 {
1973 CLEAR_BIT(PWR->BDCR1, PWR_BDCR1_BREN);
1974 }
1975
1976 /**
1977 * @brief Enable the flash memory fast wakeup from Stop 0 and Stop 1 modes.
1978 * @note This feature is used to obtain the best trade-off between low-power
1979 * consumption and wakeup time when exiting the Stop 0 or Stop 1 modes.
1980 * When this feature is enabled, the Flash memory remains in normal
1981 * mode in Stop 0 and Stop 1 modes, which offers a faster startup time
1982 * with higher consumption.
1983 * @retval None.
1984 */
HAL_PWREx_EnableFlashFastWakeUp(void)1985 void HAL_PWREx_EnableFlashFastWakeUp(void)
1986 {
1987 SET_BIT(PWR->CR2, PWR_CR2_FLASHFWU);
1988 }
1989
1990 /**
1991 * @brief Disable the Flash Power Down in Stop mode.
1992 * @note This feature is used to obtain the best trade-off between low-power
1993 * consumption and wakeup time when exiting the Stop 0 or Stop 1 modes.
1994 * When this feature is disabled, the Flash memory enters low-power
1995 * mode in Stop 0 and Stop 1 modes, which causes a slower startup time
1996 * with lower consumption.
1997 * @retval None.
1998 */
HAL_PWREx_DisableFlashFastWakeUp(void)1999 void HAL_PWREx_DisableFlashFastWakeUp(void)
2000 {
2001 CLEAR_BIT(PWR->CR2, PWR_CR2_FLASHFWU);
2002 }
2003
2004 /**
2005 * @brief Enable the SRAM4 memory fast wakeup from Stop 0, Stop 1 and Stop 2 modes.
2006 * @note This bit is used to obtain the best trade-off between low-power consumption
2007 * and wakeup time. SRAM4 wakeup time increases the wakeup time when exiting
2008 * Stop 0, Stop 1 and Stop 2 modes, and also increases the LPDMA access time
2009 * to SRAM4 during Stop modes.
2010 * @retval None.
2011 */
HAL_PWREx_EnableSRAM4FastWakeUp(void)2012 void HAL_PWREx_EnableSRAM4FastWakeUp(void)
2013 {
2014 SET_BIT(PWR->CR2, PWR_CR2_SRAM4FWU);
2015 }
2016
2017 /**
2018 * @brief Disable the SRAM4 memory fast wakeup from Stop 0, Stop 1 and Stop 2 modes.
2019 * @note This bit is used to obtain the best trade-off between low-power consumption
2020 * and wakeup time. SRAM4 wakeup time increases the wakeup time when exiting
2021 * Stop 0, Stop 1 and Stop 2 modes, and also increases the LPDMA access time
2022 * to SRAM4 during Stop modes.
2023 * @retval None.
2024 */
HAL_PWREx_DisableSRAM4FastWakeUp(void)2025 void HAL_PWREx_DisableSRAM4FastWakeUp(void)
2026 {
2027 CLEAR_BIT(PWR->CR2, PWR_CR2_SRAM4FWU);
2028 }
2029 /**
2030 * @}
2031 */
2032
2033 /** @defgroup PWREx_Exported_Functions_Group5 I/O Pull-Up Pull-Down Configuration Functions
2034 * @brief I/O pull-up / pull-down configuration functions
2035 *
2036 @verbatim
2037 ===============================================================================
2038 ##### Voltage monitoring Functions #####
2039 ===============================================================================
2040 [..]
2041 In Standby and Shutdown mode, pull up and pull down can be configured to
2042 maintain an I/O in the selected state. If the APC bit in the PWR_APCR
2043 register is set, the I/Os can be configured either with a pull-up through
2044 PWR_PUCRx registers (x=A,B,C,D,E,F,G,H,I), or with a pull-down through
2045 PWR_PDCRx registers (x=A,B,C,D,E,F,G,H,I)), or can be kept in analog state
2046 if none of the PWR_PUCRx or PWR_PDCRx register is set.
2047
2048 [..]
2049 The pull-down configuration has highest priority over pull-up
2050 configuration in case both PWR_PUCRx and PWR_PDCRx are set for the same
2051 I/O.
2052 This configuration is lost when exiting the Shutdown but not from Standby
2053 mode.
2054
2055 @endverbatim
2056 * @{
2057 */
2058
2059 /**
2060 * @brief Enable pull-up and pull-down configuration.
2061 * @note When APC bit is set, the I/O pull-up and pull-down configurations
2062 * defined in PWR_PUCRx and PWR_PDCRx registers are applied in Standby
2063 * and Shutdown modes.
2064 * @note Pull-up set by PUy bit of PWR_PUCRx register is not activated if the
2065 * corresponding PDy bit of PWR_PDCRx register is also set (pull-down
2066 * configuration priority is higher). HAL_PWREx_EnableGPIOPullUp() and
2067 * HAL_PWREx_EnableGPIOPullDown() API's ensure there is no conflict
2068 * when setting PUy or PDy bit.
2069 * @retval None.
2070 */
HAL_PWREx_EnablePullUpPullDownConfig(void)2071 void HAL_PWREx_EnablePullUpPullDownConfig(void)
2072 {
2073 SET_BIT(PWR->APCR, PWR_APCR_APC);
2074 }
2075
2076 /**
2077 * @brief Disable pull-up and pull-down configuration.
2078 * @note When APC bit is cleared, the I/O pull-up and pull-down configurations
2079 * defined in PWR_PUCRx and PWR_PDCRx registers are not applied in
2080 * Standby and Shutdown modes.
2081 * @retval None.
2082 */
HAL_PWREx_DisablePullUpPullDownConfig(void)2083 void HAL_PWREx_DisablePullUpPullDownConfig(void)
2084 {
2085 CLEAR_BIT(PWR->APCR, PWR_APCR_APC);
2086 }
2087
2088 /**
2089 * @brief Enable GPIO pull-up state in Standby and Shutdown modes.
2090 * @note Set the relevant PUy bits of PWR_PUCRx register to configure the I/O
2091 * in pull-up state in Standby and Shutdown modes.
2092 * @note This state is effective in Standby and Shutdown modes only if APC
2093 * bit is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
2094 * @note The configuration is lost when exiting the Shutdown mode due to the
2095 * power-on reset, maintained when exiting the Standby mode.
2096 * @note To avoid any conflict at Standby and Shutdown modes exits, the
2097 * corresponding PDy bit of PWR_PDCRx register is cleared unless it is
2098 * reserved.
2099 * @note Even if a PUy bit to set is reserved, the other PUy bits entered as
2100 * input parameter at the same time are set.
2101 * @param GPIO_Port : Specify the IO port.
2102 * This parameter can be a value of
2103 * @ref PWREx_GPIO_Port.
2104 * @param GPIO_Pin : Specify the I/O pins numbers.
2105 * This parameter can be a value of
2106 * @ref PWREx_GPIO_Pin_Mask.
2107 * @retval HAL Status.
2108 */
HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO_Port,uint32_t GPIO_Pin)2109 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO_Port, uint32_t GPIO_Pin)
2110 {
2111 /* Check the parameters */
2112 assert_param(IS_PWR_GPIO_PORT(GPIO_Port));
2113 assert_param(IS_PWR_GPIO_PIN_MASK(GPIO_Pin));
2114
2115 /* Check GPIO port */
2116 switch (GPIO_Port)
2117 {
2118 case PWR_GPIO_A: /* Apply Pull Up to GPIO port A */
2119 SET_BIT(PWR->PUCRA, (GPIO_Pin & (~(PWR_GPIO_BIT_14))));
2120 CLEAR_BIT(PWR->PDCRA, (GPIO_Pin & (~(PWR_GPIO_BIT_13 | PWR_GPIO_BIT_15))));
2121 break;
2122
2123 case PWR_GPIO_B: /* Apply Pull Up to GPIO port B */
2124 SET_BIT(PWR->PUCRB, GPIO_Pin);
2125 CLEAR_BIT(PWR->PDCRB, (GPIO_Pin & (~(PWR_GPIO_BIT_4))));
2126 break;
2127
2128 case PWR_GPIO_C: /* Apply Pull Up to GPIO port C */
2129 SET_BIT(PWR->PUCRC, GPIO_Pin);
2130 CLEAR_BIT(PWR->PDCRC, GPIO_Pin);
2131 break;
2132
2133 case PWR_GPIO_D: /* Apply Pull Up to GPIO port D */
2134 SET_BIT(PWR->PUCRD, GPIO_Pin);
2135 CLEAR_BIT(PWR->PDCRD, GPIO_Pin);
2136 break;
2137
2138 case PWR_GPIO_E: /* Apply Pull Up to GPIO port E */
2139 SET_BIT(PWR->PUCRE, GPIO_Pin);
2140 CLEAR_BIT(PWR->PDCRE, GPIO_Pin);
2141 break;
2142
2143 case PWR_GPIO_F: /* Apply Pull Up to GPIO port F */
2144 SET_BIT(PWR->PUCRF, GPIO_Pin);
2145 CLEAR_BIT(PWR->PDCRF, GPIO_Pin);
2146 break;
2147
2148 case PWR_GPIO_G: /* Apply Pull Up to GPIO port G */
2149 SET_BIT(PWR->PUCRG, GPIO_Pin);
2150 CLEAR_BIT(PWR->PDCRG, GPIO_Pin);
2151 break;
2152
2153 case PWR_GPIO_H: /* Apply Pull Up to GPIO port H */
2154 SET_BIT(PWR->PUCRH, GPIO_Pin);
2155 CLEAR_BIT(PWR->PDCRH, GPIO_Pin);
2156 break;
2157
2158 case PWR_GPIO_I: /* Apply Pull Up to GPIO port I */
2159 SET_BIT(PWR->PUCRI, (GPIO_Pin & PWR_PORTI_AVAILABLE_PINS));
2160 CLEAR_BIT(PWR->PDCRI, (GPIO_Pin & PWR_PORTI_AVAILABLE_PINS));
2161 break;
2162
2163 default:
2164 return HAL_ERROR;
2165 break;
2166 }
2167
2168 return HAL_OK;
2169 }
2170
2171 /**
2172 * @brief Disable GPIO pull-up state in Standby mode and Shutdown modes.
2173 * @note Reset the relevant PUy bits of PWR_PUCRx register used to configure
2174 * the I/O in pull-up state in Standby and Shutdown modes.
2175 * @note Even if a PUy bit to reset is reserved, the other PUy bits entered as
2176 * input parameter at the same time are reset.
2177 * @param GPIO_Port : Specify the IO port.
2178 * This parameter can be a value of
2179 * @ref PWREx_GPIO_Port.
2180 * @param GPIO_Pin : Specify the I/O pins numbers.
2181 * This parameter can be a value of
2182 * @ref PWREx_GPIO_Pin_Mask.
2183 * @retval HAL Status.
2184 */
HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO_Port,uint32_t GPIO_Pin)2185 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO_Port, uint32_t GPIO_Pin)
2186 {
2187 /* Check the parameters */
2188 assert_param(IS_PWR_GPIO_PORT(GPIO_Port));
2189 assert_param(IS_PWR_GPIO_PIN_MASK(GPIO_Pin));
2190
2191 /* Check GPIO port */
2192 switch (GPIO_Port)
2193 {
2194 case PWR_GPIO_A: /* Disable Pull Up for GPIO port A */
2195 CLEAR_BIT(PWR->PUCRA, (GPIO_Pin & (~(PWR_GPIO_BIT_14))));
2196 break;
2197
2198 case PWR_GPIO_B: /* Disable Pull Up for GPIO port B */
2199 CLEAR_BIT(PWR->PUCRB, GPIO_Pin);
2200 break;
2201
2202 case PWR_GPIO_C: /* Disable Pull Up for GPIO port C */
2203 CLEAR_BIT(PWR->PUCRC, GPIO_Pin);
2204 break;
2205
2206 case PWR_GPIO_D: /* Disable Pull Up for GPIO port D */
2207 CLEAR_BIT(PWR->PUCRD, GPIO_Pin);
2208 break;
2209
2210 case PWR_GPIO_E: /* Disable Pull Up for GPIO port E */
2211 CLEAR_BIT(PWR->PUCRE, GPIO_Pin);
2212 break;
2213
2214 case PWR_GPIO_F: /* Disable Pull Up for GPIO port F */
2215 CLEAR_BIT(PWR->PUCRF, GPIO_Pin);
2216 break;
2217
2218 case PWR_GPIO_G: /* Disable Pull Up for GPIO port G */
2219 CLEAR_BIT(PWR->PUCRG, GPIO_Pin);
2220 break;
2221
2222 case PWR_GPIO_H: /* Disable Pull Up for GPIO port H */
2223 CLEAR_BIT(PWR->PUCRH, GPIO_Pin);
2224 break;
2225
2226 case PWR_GPIO_I: /* Disable Pull Up for GPIO port I */
2227 CLEAR_BIT(PWR->PUCRI, (GPIO_Pin & PWR_PORTI_AVAILABLE_PINS));
2228 break;
2229
2230 default:
2231 return HAL_ERROR;
2232 break;
2233 }
2234
2235 return HAL_OK;
2236 }
2237
2238 /**
2239 * @brief Enable GPIO pull-down state in Standby and Shutdown modes.
2240 * @note Set the relevant PDy bits of PWR_PDCRx register to configure the I/O
2241 * in pull-down state in Standby and Shutdown modes.
2242 * @note This state is effective in Standby and Shutdown modes only if APC bit
2243 * is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
2244 * @note The configuration is lost when exiting the Shutdown mode due to the
2245 * power-on reset, maintained when exiting the Standby mode.
2246 * @note To avoid any conflict at Standby and Shutdown modes exits, the
2247 * corresponding PUy bit of PWR_PUCRx register is cleared unless it is
2248 * reserved.
2249 * @note Even if a PDy bit to set is reserved, the other PDy bits entered as
2250 * input parameter at the same time are set.
2251 * @param GPIO_Port : Specify the IO port.
2252 * This parameter can be a value of
2253 * @ref PWREx_GPIO_Port.
2254 * @param GPIO_Pin : Specify the I/O pins numbers.
2255 * This parameter can be a value of
2256 * @ref PWREx_GPIO_Pin_Mask.
2257 * @retval HAL Status.
2258 */
HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO_Port,uint32_t GPIO_Pin)2259 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO_Port, uint32_t GPIO_Pin)
2260 {
2261 /* Check the parameters */
2262 assert_param(IS_PWR_GPIO_PORT(GPIO_Port));
2263 assert_param(IS_PWR_GPIO_PIN_MASK(GPIO_Pin));
2264
2265 /* Check GPIO port */
2266 switch (GPIO_Port)
2267 {
2268 case PWR_GPIO_A: /* Apply Pull Down to GPIO port A */
2269 SET_BIT(PWR->PDCRA, (GPIO_Pin & (~(PWR_GPIO_BIT_13 | PWR_GPIO_BIT_15))));
2270 CLEAR_BIT(PWR->PUCRA, (GPIO_Pin & (~(PWR_GPIO_BIT_14))));
2271 break;
2272
2273 case PWR_GPIO_B: /* Apply Pull Down to GPIO port B */
2274 SET_BIT(PWR->PDCRB, (GPIO_Pin & (~(PWR_GPIO_BIT_4))));
2275 CLEAR_BIT(PWR->PUCRB, GPIO_Pin);
2276 break;
2277
2278 case PWR_GPIO_C: /* Apply Pull Down to GPIO port C */
2279 SET_BIT(PWR->PDCRC, GPIO_Pin);
2280 CLEAR_BIT(PWR->PUCRC, GPIO_Pin);
2281 break;
2282
2283 case PWR_GPIO_D: /* Apply Pull Down to GPIO port D */
2284 SET_BIT(PWR->PDCRD, GPIO_Pin);
2285 CLEAR_BIT(PWR->PUCRD, GPIO_Pin);
2286 break;
2287
2288 case PWR_GPIO_E: /* Apply Pull Down to GPIO port E */
2289 SET_BIT(PWR->PDCRE, GPIO_Pin);
2290 CLEAR_BIT(PWR->PUCRE, GPIO_Pin);
2291 break;
2292
2293 case PWR_GPIO_F: /* Apply Pull Down to GPIO port F */
2294 SET_BIT(PWR->PDCRF, GPIO_Pin);
2295 CLEAR_BIT(PWR->PUCRF, GPIO_Pin);
2296 break;
2297
2298 case PWR_GPIO_G: /* Apply Pull Down to GPIO port G */
2299 SET_BIT(PWR->PDCRG, GPIO_Pin);
2300 CLEAR_BIT(PWR->PUCRG, GPIO_Pin);
2301 break;
2302
2303 case PWR_GPIO_H: /* Apply Pull Down to GPIO port H */
2304 SET_BIT(PWR->PDCRH, GPIO_Pin);
2305 CLEAR_BIT(PWR->PUCRH, GPIO_Pin);
2306 break;
2307
2308 case PWR_GPIO_I: /* Apply Pull Down to GPIO port I */
2309 SET_BIT(PWR->PDCRI, (GPIO_Pin & PWR_PORTI_AVAILABLE_PINS));
2310 CLEAR_BIT(PWR->PUCRI, (GPIO_Pin & PWR_PORTI_AVAILABLE_PINS));
2311 break;
2312
2313 default:
2314 return HAL_ERROR;
2315 break;
2316 }
2317
2318 return HAL_OK;
2319 }
2320
2321 /**
2322 * @brief Disable GPIO pull-down state in Standby and Shutdown modes.
2323 * @note Reset the relevant PDy bits of PWR_PDCRx register used to configure the I/O
2324 * in pull-down state in Standby and Shutdown modes.
2325 * @note Even if a PDy bit to reset is reserved, the other PDy bits entered as input
2326 * parameter at the same time are reset.
2327 * @param GPIO_Port : Specify the IO port.
2328 * This parameter can be a value of
2329 * @ref PWREx_GPIO_Port.
2330 * @param GPIO_Pin : Specify the I/O pins numbers.
2331 * This parameter can be a value of
2332 * @ref PWREx_GPIO_Pin_Mask.
2333 * @retval HAL Status.
2334 */
HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO_Port,uint32_t GPIO_Pin)2335 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO_Port, uint32_t GPIO_Pin)
2336 {
2337 /* Check the parameters */
2338 assert_param(IS_PWR_GPIO_PORT(GPIO_Port));
2339 assert_param(IS_PWR_GPIO_PIN_MASK(GPIO_Pin));
2340
2341 /* Check GPIO port */
2342 switch (GPIO_Port)
2343 {
2344 case PWR_GPIO_A: /* Disable Pull Down for GPIO port A */
2345 CLEAR_BIT(PWR->PDCRA, (GPIO_Pin & (~(PWR_GPIO_BIT_13 | PWR_GPIO_BIT_15))));
2346 break;
2347
2348 case PWR_GPIO_B: /* Disable Pull Down for GPIO port B */
2349 CLEAR_BIT(PWR->PDCRB, (GPIO_Pin & (~(PWR_GPIO_BIT_4))));
2350 break;
2351
2352 case PWR_GPIO_C: /* Disable Pull Down for GPIO port C */
2353 CLEAR_BIT(PWR->PDCRC, GPIO_Pin);
2354 break;
2355
2356 case PWR_GPIO_D: /* Disable Pull Down for GPIO port D */
2357 CLEAR_BIT(PWR->PDCRD, GPIO_Pin);
2358 break;
2359
2360 case PWR_GPIO_E: /* Disable Pull Down for GPIO port E */
2361 CLEAR_BIT(PWR->PDCRE, GPIO_Pin);
2362 break;
2363
2364 case PWR_GPIO_F: /* Disable Pull Down for GPIO port F */
2365 CLEAR_BIT(PWR->PDCRF, GPIO_Pin);
2366 break;
2367
2368 case PWR_GPIO_G: /* Disable Pull Down for GPIO port G */
2369 CLEAR_BIT(PWR->PDCRG, GPIO_Pin);
2370 break;
2371
2372 case PWR_GPIO_H: /* Disable Pull Down for GPIO port H */
2373 CLEAR_BIT(PWR->PDCRH, GPIO_Pin);
2374 break;
2375
2376 case PWR_GPIO_I: /* Disable Pull Down for GPIO port I */
2377 CLEAR_BIT(PWR->PDCRI, (GPIO_Pin & PWR_PORTI_AVAILABLE_PINS));
2378 break;
2379
2380 default:
2381 return HAL_ERROR;
2382 break;
2383 }
2384
2385 return HAL_OK;
2386 }
2387 /**
2388 * @}
2389 */
2390
2391 #endif /* defined (HAL_PWR_MODULE_ENABLED) */
2392
2393 /**
2394 * @}
2395 */
2396
2397 /**
2398 * @}
2399 */
2400
2401 /**
2402 * @}
2403 */
2404
