1 /**
2 ******************************************************************************
3 * @file stm32u5xx_hal_gtzc.c
4 * @author MCD Application Team
5 * @brief GTZC HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of GTZC peripheral:
8 * + TZSC Initialization and Configuration functions
9 * + TZSC-MPCWM Initialization and Configuration functions
10 * + MPCBB Initialization and Configuration functions
11 * + TZSC, TZSC-MPCWM and MPCBB Lock functions
12 * + TZIC Initialization and Configuration functions
13 *
14 ******************************************************************************
15 * @attention
16 *
17 * Copyright (c) 2021 STMicroelectronics.
18 * All rights reserved.
19 *
20 * This software component is licensed by ST under BSD 3-Clause license,
21 * the "License"; You may not use this file except in compliance with the
22 * License. You may obtain a copy of the License at:
23 * opensource.org/licenses/BSD-3-Clause
24 *
25 ******************************************************************************
26 @verbatim
27 ==============================================================================
28 ##### GTZC main features #####
29 ==============================================================================
30 [..]
31 (+) Global TrustZone Controller (GTZC) composed of three sub-blocks:
32 (++) TZSC: TrustZone security controller
33 This sub-block defines the secure/privileged state of master and slave
34 peripherals. It also controls the secure/privileged state of subregions
35 for the watermark memory peripheral controller (MPCWM).
36 (++) MPCBB: Block-Based memory protection controller
37 This sub-block defines the secure/privileged state of all blocks
38 (512-byte pages) of the associated SRAM.
39 (++) TZIC: TrustZone illegal access controller
40 This sub-block gathers all illegal access events in the system and
41 generates a secure interrupt towards NVIC.
42
43 (+) These sub-blocks are used to configure TrustZone system security in
44 a product having bus agents with programmable-security and privileged
45 attributes (securable) such as:
46 (++) on-chip RAM with programmable secure and/or privilege blocks (pages)
47 (++) AHB and APB peripherals with programmable security and/or privilege access
48 (++) AHB master granted as secure and/or privilege
49 (++) off-chip memories with secure and/or privilege areas
50
51 [..]
52 (+) TZIC accessible only with secure privileged transactions.
53 (+) Secure and non-secure access supported for privileged and unprivileged
54 part of TZSC and MPCBB
55 (+) Set of registers to define product security settings:
56 (++) Secure and privilege blocks for internal memories
57 (++) Secure and privilege regions for external memories
58 (++) Secure and privileged access mode for securable peripherals
59
60 ==============================================================================
61 ##### How to use this driver #####
62 ==============================================================================
63 [..]
64 The GTZC HAL driver can be used as follows:
65
66 (#) Configure or get back securable peripherals attributes using
67 HAL_GTZC_TZSC_ConfigPeriphAttributes() / HAL_GTZC_TZSC_GetConfigPeriphAttributes()
68
69 (#) Configure or get back MPCWM memories attributes using
70 HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes() / HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes()
71
72 (#) Lock TZSC sub-block or get lock status using HAL_GTZC_TZSC_Lock() /
73 HAL_GTZC_TZSC_GetLock()
74
75 (#) Configure or get back MPCBB memories complete configuration using
76 HAL_GTZC_MPCBB_ConfigMem() / HAL_GTZC_MPCBB_GetConfigMem()
77
78 (#) Configure or get back MPCBB memories attributes using
79 HAL_GTZC_MPCBB_ConfigMemAttributes() / HAL_GTZC_MPCBB_GetConfigMemAttributes()
80
81 (#) Lock MPCBB configuration or get lock status using HAL_GTZC_MPCBB_Lock() /
82 HAL_GTZC_MPCBB_GetLock()
83
84 (#) Lock MPCBB super-blocks or get lock status using HAL_GTZC_MPCBB_LockConfig() /
85 HAL_GTZC_MPCBB_GetLockConfig()
86
87 (#) Illegal access detection can be configured through TZIC sub-block using
88 following functions: HAL_GTZC_TZIC_DisableIT() / HAL_GTZC_TZIC_EnableIT()
89
90 (#) Illegal access flags can be retrieved through HAL_GTZC_TZIC_GetFlag() and
91 HAL_GTZC_TZIC_ClearFlag() functions
92
93 (#) Illegal access interrupt service routines are served by HAL_GTZC_IRQHandler()
94 and user can add his own code using HAL_GTZC_TZIC_Callback()
95
96 @endverbatim
97 ******************************************************************************
98 */
99
100 /* Includes ------------------------------------------------------------------*/
101 #include "stm32u5xx_hal.h"
102
103 /** @addtogroup STM32U5xx_HAL_Driver
104 * @{
105 */
106
107 /** @defgroup GTZC GTZC
108 * @brief GTZC HAL module driver
109 * @{
110 */
111
112 #ifdef HAL_GTZC_MODULE_ENABLED
113
114 /* Private typedef -----------------------------------------------------------*/
115 /* Private constants ---------------------------------------------------------*/
116
117 /** @defgroup GTZC_Private_Constants GTZC Private Constants
118 * @{
119 */
120
121 /* Definitions for TZSC_MPCWM */
122 #define TZSC_MPCWM1_MEM_SIZE 0x10000000U /* 256MB max size */
123 #define TZSC_MPCWM2_MEM_SIZE 0x10000000U /* 256MB max size */
124 #define TZSC_MPCWM3_MEM_SIZE 0x10000000U /* 256MB max size */
125 #define TZSC_MPCWM4_MEM_SIZE 0x00000800U /* 2KB max size */
126 #define TZSC_MPCWM5_MEM_SIZE 0x10000000U /* 256MB max size */
127
128 /* Definitions for GTZC TZSC & TZIC ALL register values */
129 /* TZSC1 / TZIC1 instances */
130 #define TZSC1_SECCFGR1_ALL (0x001FFFFFUL)
131 #define TZSC1_SECCFGR2_ALL (0x000001FFUL)
132 #define TZSC1_SECCFGR3_ALL (0x007FFFFFUL)
133
134 #define TZSC1_PRIVCFGR1_ALL (0x001FFFFFUL)
135 #define TZSC1_PRIVCFGR2_ALL (0x000001FFUL)
136 #define TZSC1_PRIVCFGR3_ALL (0x007FFFFFUL)
137
138 #define TZIC1_IER1_ALL (0x001FFFFFUL)
139 #define TZIC1_IER2_ALL (0x000001FFUL)
140 #define TZIC1_IER3_ALL (0x007FFFFFUL)
141 #define TZIC1_IER4_ALL (0x3F0FC01FUL)
142
143 #define TZIC1_FCR1_ALL (0x001FFFFFUL)
144 #define TZIC1_FCR2_ALL (0x000001FFUL)
145 #define TZIC1_FCR3_ALL (0x007FFFFFUL)
146 #define TZIC1_FCR4_ALL (0x3F0FC01FUL)
147
148 /* TZSC2 / TZIC2 instances */
149 #define TZSC2_SECCFGR1_ALL (0x00001BFFUL)
150
151 #define TZSC2_PRIVCFGR1_ALL (0x00001BFFUL)
152
153 #define TZIC2_IER1_ALL (0x00001BFFUL)
154 #define TZIC2_IER2_ALL (0x0300C07FUL)
155
156 #define TZIC2_FCR1_ALL (0x00001BFFUL)
157 #define TZIC2_FCR2_ALL (0x0300C07FUL)
158
159 /**
160 * @}
161 */
162
163 /* Private macros ------------------------------------------------------------*/
164
165 /** @defgroup GTZC_Private_Macros GTZC Private Macros
166 * @{
167 */
168
169 #define IS_ADDRESS_IN(mem, address)\
170 ( ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_NS(mem) ) \
171 && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_NS(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) ) \
172 || ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_S(mem) ) \
173 && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_S(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) ) )
174
175 #define IS_ADDRESS_IN_S(mem, address)\
176 ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_S(mem) ) \
177 && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_S(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) )
178
179 #define IS_ADDRESS_IN_NS(mem, address)\
180 ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_NS(mem) ) \
181 && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_NS(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) )
182
183 #define GTZC_BASE_ADDRESS(mem)\
184 ( mem ## _BASE )
185
186 /**
187 * @}
188 */
189
190 /* Private variables ---------------------------------------------------------*/
191 /* Private function prototypes -----------------------------------------------*/
192 /* Exported functions --------------------------------------------------------*/
193
194 /** @defgroup GTZC_Exported_Functions GTZC Exported Functions
195 * @{
196 */
197
198 /** @defgroup GTZC_Exported_Functions_Group1 TZSC Configuration functions
199 * @brief TZSC Configuration functions
200 *
201 @verbatim
202 ==============================================================================
203 ##### TZSC Configuration functions #####
204 ==============================================================================
205 [..]
206 This section provides functions allowing to configure TZSC
207 TZSC: TrustZone Security Controller
208 @endverbatim
209 * @{
210 */
211
212 /**
213 * @brief Configure TZSC on a single peripheral or on all peripherals.
214 * @note Secure and non-secure attributes can only be set from the secure
215 * state when the system implements the security (TZEN=1).
216 * @note Privilege and non-privilege attributes can only be set from the
217 * privilege state when TZEN=0 or TZEN=1
218 * @note Security and privilege attributes can be set independently.
219 * @note Default state is non-secure and unprivileged access allowed.
220 * @param PeriphId Peripheral identifier
221 * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId.
222 * Use GTZC_PERIPH_ALL to select all peripherals.
223 * @param PeriphAttributes Peripheral attributes, see @ref GTZC_TZSC_PeriphAttributes.
224 * @retval HAL status.
225 */
HAL_GTZC_TZSC_ConfigPeriphAttributes(uint32_t PeriphId,uint32_t PeriphAttributes)226 HAL_StatusTypeDef HAL_GTZC_TZSC_ConfigPeriphAttributes(uint32_t PeriphId,
227 uint32_t PeriphAttributes)
228 {
229 uint32_t register_address;
230
231 /* check entry parameters */
232 if ((PeriphAttributes > (GTZC_TZSC_PERIPH_SEC | GTZC_TZSC_PERIPH_PRIV))
233 || (HAL_GTZC_TZSC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZSC_PERIPH_NUMBER)
234 || (((PeriphId & GTZC_PERIPH_ALL) != 0U)
235 && (HAL_GTZC_TZSC_GET_ARRAY_INDEX(PeriphId) != 0U)))
236 {
237 return HAL_ERROR;
238 }
239
240 if ((PeriphId & GTZC_PERIPH_ALL) != 0U)
241 {
242 /* special case where same attributes are applied to all peripherals */
243
244 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
245 /* secure configuration */
246 if ((PeriphAttributes & GTZC_TZSC_PERIPH_SEC) == GTZC_TZSC_PERIPH_SEC)
247 {
248 SET_BIT(GTZC_TZSC1->SECCFGR1, TZSC1_SECCFGR1_ALL);
249 SET_BIT(GTZC_TZSC1->SECCFGR2, TZSC1_SECCFGR2_ALL);
250 SET_BIT(GTZC_TZSC1->SECCFGR3, TZSC1_SECCFGR3_ALL);
251 SET_BIT(GTZC_TZSC2->SECCFGR1, TZSC2_SECCFGR1_ALL);
252 }
253 else if ((PeriphAttributes & GTZC_TZSC_PERIPH_NSEC) == GTZC_TZSC_PERIPH_NSEC)
254 {
255 CLEAR_BIT(GTZC_TZSC1->SECCFGR1, TZSC1_SECCFGR1_ALL);
256 CLEAR_BIT(GTZC_TZSC1->SECCFGR2, TZSC1_SECCFGR2_ALL);
257 CLEAR_BIT(GTZC_TZSC1->SECCFGR3, TZSC1_SECCFGR3_ALL);
258 CLEAR_BIT(GTZC_TZSC2->SECCFGR1, TZSC2_SECCFGR1_ALL);
259 }
260 else
261 {
262 /* do nothing */
263 }
264 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
265
266 /* privilege configuration */
267 if ((PeriphAttributes & GTZC_TZSC_PERIPH_PRIV) == GTZC_TZSC_PERIPH_PRIV)
268 {
269 SET_BIT(GTZC_TZSC1->PRIVCFGR1, TZSC1_PRIVCFGR1_ALL);
270 SET_BIT(GTZC_TZSC1->PRIVCFGR2, TZSC1_PRIVCFGR2_ALL);
271 SET_BIT(GTZC_TZSC1->PRIVCFGR3, TZSC1_PRIVCFGR3_ALL);
272 SET_BIT(GTZC_TZSC2->PRIVCFGR1, TZSC2_PRIVCFGR1_ALL);
273 }
274 else if ((PeriphAttributes & GTZC_TZSC_PERIPH_NPRIV) == GTZC_TZSC_PERIPH_NPRIV)
275 {
276 CLEAR_BIT(GTZC_TZSC1->PRIVCFGR1, TZSC1_PRIVCFGR1_ALL);
277 CLEAR_BIT(GTZC_TZSC1->PRIVCFGR2, TZSC1_PRIVCFGR2_ALL);
278 CLEAR_BIT(GTZC_TZSC1->PRIVCFGR3, TZSC1_PRIVCFGR3_ALL);
279 CLEAR_BIT(GTZC_TZSC2->PRIVCFGR1, TZSC2_PRIVCFGR1_ALL);
280 }
281 else
282 {
283 /* do nothing */
284 }
285 }
286 else
287 {
288 /* common case where only one peripheral is configured */
289
290 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
291 /* secure configuration */
292 register_address = (uint32_t) &(HAL_GTZC_TZSC_GET_INSTANCE(PeriphId)->SECCFGR1)
293 + (4U * GTZC_GET_REG_INDEX_IN_INSTANCE(PeriphId));
294 if ((PeriphAttributes & GTZC_TZSC_PERIPH_SEC) == GTZC_TZSC_PERIPH_SEC)
295 {
296 SET_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
297 }
298 else if ((PeriphAttributes & GTZC_TZSC_PERIPH_NSEC) == GTZC_TZSC_PERIPH_NSEC)
299 {
300 CLEAR_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
301 }
302 else
303 {
304 /* do nothing */
305 }
306 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
307
308 /* privilege configuration */
309 register_address = (uint32_t) &(HAL_GTZC_TZSC_GET_INSTANCE(PeriphId)->PRIVCFGR1)
310 + (4U * GTZC_GET_REG_INDEX_IN_INSTANCE(PeriphId));
311 if ((PeriphAttributes & GTZC_TZSC_PERIPH_PRIV) == GTZC_TZSC_PERIPH_PRIV)
312 {
313 SET_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
314 }
315 else if ((PeriphAttributes & GTZC_TZSC_PERIPH_NPRIV) == GTZC_TZSC_PERIPH_NPRIV)
316 {
317 CLEAR_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
318 }
319 else
320 {
321 /* do nothing */
322 }
323 }
324 return HAL_OK;
325 }
326
327 /**
328 * @brief Get TZSC configuration on a single peripheral or on all peripherals.
329 * @param PeriphId Peripheral identifier.
330 * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId.
331 * Use GTZC_PERIPH_ALL to select all peripherals.
332 * @param PeriphAttributes Peripheral attribute pointer.
333 * This parameter can be a value of @ref GTZC_TZSC_PeriphAttributes.
334 * If PeriphId target a single peripheral, pointer on a single element.
335 * If all peripherals selected (GTZC_PERIPH_ALL), pointer to an array of
336 * GTZC_TZSC_PERIPH_NUMBER elements is to be provided.
337 * @retval HAL status.
338 */
HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId,uint32_t * PeriphAttributes)339 HAL_StatusTypeDef HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId,
340 uint32_t *PeriphAttributes)
341 {
342 uint32_t i;
343 uint32_t reg_value;
344 uint32_t register_address;
345
346 /* check entry parameters */
347 if ((PeriphAttributes == NULL)
348 || (HAL_GTZC_TZSC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZSC_PERIPH_NUMBER)
349 || (((PeriphId & GTZC_PERIPH_ALL) != 0U)
350 && (HAL_GTZC_TZSC_GET_ARRAY_INDEX(PeriphId) != 0U)))
351 {
352 return HAL_ERROR;
353 }
354
355 if ((PeriphId & GTZC_PERIPH_ALL) != 0U)
356 {
357 /* get secure configuration: read each register and deploy each bit value
358 * of corresponding index in the destination array
359 */
360 reg_value = READ_REG(GTZC_TZSC1->SECCFGR1);
361 for (i = 0U; i < 32U; i++)
362 {
363 if (((reg_value & (1UL << i)) >> i) != 0U)
364 {
365 PeriphAttributes[i] = GTZC_TZSC_PERIPH_SEC;
366 }
367 else
368 {
369 PeriphAttributes[i] = GTZC_TZSC_PERIPH_NSEC;
370 }
371 }
372
373 reg_value = READ_REG(GTZC_TZSC1->SECCFGR2);
374 for (i = 32U; i < 64U; i++)
375 {
376 if (((reg_value & (1UL << (i - 32U))) >> (i - 32U)) != 0U)
377 {
378 PeriphAttributes[i] = GTZC_TZSC_PERIPH_SEC;
379 }
380 else
381 {
382 PeriphAttributes[i] = GTZC_TZSC_PERIPH_NSEC;
383 }
384 }
385
386 reg_value = READ_REG(GTZC_TZSC1->SECCFGR3);
387 for (i = 64U; i < 96U; i++)
388 {
389 if (((reg_value & (1UL << (i - 64U))) >> (i - 64U)) != 0U)
390 {
391 PeriphAttributes[i] = GTZC_TZSC_PERIPH_SEC;
392 }
393 else
394 {
395 PeriphAttributes[i] = GTZC_TZSC_PERIPH_NSEC;
396 }
397 }
398
399 reg_value = READ_REG(GTZC_TZSC2->SECCFGR1);
400 for (i = 96U; i < GTZC_TZSC_PERIPH_NUMBER; i++)
401 {
402 if (((reg_value & (1UL << (i - 96U))) >> (i - 96U)) != 0U)
403 {
404 PeriphAttributes[i] = GTZC_TZSC_PERIPH_SEC;
405 }
406 else
407 {
408 PeriphAttributes[i] = GTZC_TZSC_PERIPH_NSEC;
409 }
410 }
411
412 /* get privilege configuration: read each register and deploy each bit value
413 * of corresponding index in the destination array
414 */
415 reg_value = READ_REG(GTZC_TZSC1->PRIVCFGR1);
416 for (i = 0U; i < 32U; i++)
417 {
418 if (((reg_value & (1UL << i)) >> i) != 0U)
419 {
420 PeriphAttributes[i] |= GTZC_TZSC_PERIPH_PRIV;
421 }
422 else
423 {
424 PeriphAttributes[i] |= GTZC_TZSC_PERIPH_NPRIV;
425 }
426 }
427
428 reg_value = READ_REG(GTZC_TZSC1->PRIVCFGR2);
429 for (i = 32U; i < 64U; i++)
430 {
431 if (((reg_value & (1UL << (i - 32U))) >> (i - 32U)) != 0U)
432 {
433 PeriphAttributes[i] |= GTZC_TZSC_PERIPH_PRIV;
434 }
435 else
436 {
437 PeriphAttributes[i] |= GTZC_TZSC_PERIPH_NPRIV;
438 }
439 }
440
441 reg_value = READ_REG(GTZC_TZSC1->PRIVCFGR3);
442 for (i = 64U; i < 96U; i++)
443 {
444 if (((reg_value & (1UL << (i - 64U))) >> (i - 64U)) != 0U)
445 {
446 PeriphAttributes[i] |= GTZC_TZSC_PERIPH_PRIV;
447 }
448 else
449 {
450 PeriphAttributes[i] |= GTZC_TZSC_PERIPH_NPRIV;
451 }
452 }
453
454 reg_value = READ_REG(GTZC_TZSC2->PRIVCFGR1);
455 for (i = 96U; i < GTZC_TZSC_PERIPH_NUMBER; i++)
456 {
457 if (((reg_value & (1UL << (i - 96U))) >> (i - 96U)) != 0U)
458 {
459 PeriphAttributes[i] |= GTZC_TZSC_PERIPH_PRIV;
460 }
461 else
462 {
463 PeriphAttributes[i] |= GTZC_TZSC_PERIPH_NPRIV;
464 }
465 }
466 }
467 else
468 {
469 /* common case where only one peripheral is configured */
470
471 /* secure configuration */
472 register_address = (uint32_t) &(HAL_GTZC_TZSC_GET_INSTANCE(PeriphId)->SECCFGR1)
473 + (4U * GTZC_GET_REG_INDEX_IN_INSTANCE(PeriphId));
474
475 if (((READ_BIT(*(__IO uint32_t *)register_address,
476 1UL << GTZC_GET_PERIPH_POS(PeriphId))) >> GTZC_GET_PERIPH_POS(PeriphId))
477 != 0U)
478 {
479 *PeriphAttributes = GTZC_TZSC_PERIPH_SEC;
480 }
481 else
482 {
483 *PeriphAttributes = GTZC_TZSC_PERIPH_NSEC;
484 }
485
486 /* privilege configuration */
487 register_address = (uint32_t) &(HAL_GTZC_TZSC_GET_INSTANCE(PeriphId)->PRIVCFGR1)
488 + (4U * GTZC_GET_REG_INDEX_IN_INSTANCE(PeriphId));
489 if (((READ_BIT(*(__IO uint32_t *)register_address,
490 1UL << GTZC_GET_PERIPH_POS(PeriphId))) >> GTZC_GET_PERIPH_POS(PeriphId))
491 != 0U)
492 {
493 *PeriphAttributes |= GTZC_TZSC_PERIPH_PRIV;
494 }
495 else
496 {
497 *PeriphAttributes |= GTZC_TZSC_PERIPH_NPRIV;
498 }
499 }
500 return HAL_OK;
501 }
502
503 /**
504 * @}
505 */
506
507 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
508
509 /** @defgroup GTZC_Exported_Functions_Group2 MPCWM Configuration functions
510 * @brief MPCWM Configuration functions
511 *
512 @verbatim
513 ==============================================================================
514 ##### MPCWM Configuration functions #####
515 ==============================================================================
516 [..]
517 This section provides functions allowing to configure MPCWM
518 MPCWM is Memory Protection Controller WaterMark
519 @endverbatim
520 * @{
521 */
522
523 /**
524 * @brief Configure a TZSC-MPCWM area.
525 * @param MemBaseAddress WM identifier.
526 * @param pMPCWM_Desc TZSC-MPCWM descriptor pointer.
527 * The structure description is available in @ref GTZC_Exported_Types.
528 * @retval HAL status.
529 */
HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes(uint32_t MemBaseAddress,MPCWM_ConfigTypeDef * pMPCWM_Desc)530 HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes(
531 uint32_t MemBaseAddress,
532 MPCWM_ConfigTypeDef *pMPCWM_Desc)
533 {
534 uint32_t register_address;
535 uint32_t reg_value;
536 uint32_t size;
537 /* granularity value depends on selected memory */
538 uint32_t granularity = (MemBaseAddress == BKPSRAM_BASE) ? \
539 GTZC_TZSC_MPCWM_GRANULARITY_2 : GTZC_TZSC_MPCWM_GRANULARITY_1;
540
541 /* check entry parameters */
542 if ((pMPCWM_Desc->AreaId > GTZC_TZSC_MPCWM_ID2)
543 || (((MemBaseAddress == FMC_BANK3) || (MemBaseAddress == BKPSRAM_BASE))
544 && (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID2))
545 || ((pMPCWM_Desc->Offset % granularity) != 0U)
546 || ((pMPCWM_Desc->Length % granularity) != 0U))
547 {
548 return HAL_ERROR;
549 }
550
551 /* check descriptor content vs. memory capacity */
552 switch (MemBaseAddress)
553 {
554 case OCTOSPI1_BASE:
555 size = TZSC_MPCWM1_MEM_SIZE;
556 if (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1)
557 {
558 register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM1AR);
559 }
560 else
561 {
562 /* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID2
563 * (Parameter already checked)
564 */
565 register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM1BR);
566 }
567 break;
568 case FMC_BANK1:
569 size = TZSC_MPCWM1_MEM_SIZE;
570 if (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1)
571 {
572 register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM2AR);
573 }
574 else
575 {
576 /* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID2
577 * (Parameter already checked)
578 */
579 register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM2BR);
580 }
581 break;
582 case FMC_BANK3:
583 /* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1
584 * (Parameter already checked)
585 */
586 size = TZSC_MPCWM3_MEM_SIZE;
587 register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM3AR);
588 break;
589 case BKPSRAM_BASE:
590 /* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1
591 * (Parameter already checked)
592 */
593 size = TZSC_MPCWM4_MEM_SIZE;
594 register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM4AR);
595 break;
596 case OCTOSPI2_BASE:
597 size = TZSC_MPCWM5_MEM_SIZE;
598 if (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1)
599 {
600 register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM5AR);
601 }
602 else
603 {
604 /* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID2
605 * (Parameter already checked)
606 */
607 register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM5BR);
608 }
609 break;
610 default:
611 return HAL_ERROR;
612 break;
613 }
614
615 if ((pMPCWM_Desc->Offset > size)
616 || ((pMPCWM_Desc->Offset
617 + pMPCWM_Desc->Length)
618 > size))
619 {
620 return HAL_ERROR;
621 }
622
623 /* Write watermark start and length value */
624 reg_value = ((pMPCWM_Desc->Offset / granularity)
625 << GTZC_TZSC_MPCWMR_SUBZ_START_Pos) & GTZC_TZSC_MPCWMR_SUBZ_START_Msk;
626 reg_value |= ((pMPCWM_Desc->Length / granularity)
627 << GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Pos) & GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk;
628 MODIFY_REG(*(__IO uint32_t *)register_address, GTZC_TZSC_MPCWMR_SUBZ_START_Msk | \
629 GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk, reg_value);
630
631 /* Write watermark configuration value */
632 reg_value = (pMPCWM_Desc->Attribute << GTZC_TZSC_MPCWM_CFGR_SEC_Pos) | \
633 pMPCWM_Desc->Lock | \
634 pMPCWM_Desc->AreaStatus;
635 MODIFY_REG(*(__IO uint32_t *)(register_address - 4U), (GTZC_TZSC_MPCWM_CFGR_PRIV | GTZC_TZSC_MPCWM_CFGR_SEC | \
636 GTZC_TZSC_MPCWM_CFGR_SRLOCK | GTZC_TZSC_MPCWM_CFGR_SREN), \
637 reg_value);
638
639 return HAL_OK;
640 }
641
642 /**
643 * @brief Get a TZSC-MPCWM area configuration.
644 * @param MemBaseAddress WM identifier.
645 * @param pMPCWM_Desc pointer to a TZSC-MPCWM descriptor.
646 * The structure description is available in @ref GTZC_Exported_Types.
647 * @retval HAL status.
648 */
HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes(uint32_t MemBaseAddress,MPCWM_ConfigTypeDef * pMPCWM_Desc)649 HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes(
650 uint32_t MemBaseAddress,
651 MPCWM_ConfigTypeDef *pMPCWM_Desc)
652 {
653 uint32_t register_address;
654 uint32_t reg_value;
655 uint32_t granularity = (MemBaseAddress == BKPSRAM_BASE) ? \
656 GTZC_TZSC_MPCWM_GRANULARITY_2 : GTZC_TZSC_MPCWM_GRANULARITY_1;
657
658 /* firstly take care of the first area, present on all MPCWM sub-blocks */
659 switch (MemBaseAddress)
660 {
661 case OCTOSPI1_BASE:
662 register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM1AR);
663 break;
664 case FMC_BANK1:
665 register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM2AR);
666 break;
667 case FMC_BANK3:
668 register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM3AR);
669 break;
670 case BKPSRAM_BASE:
671 register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM4AR);
672 break;
673 case OCTOSPI2_BASE:
674 register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM5AR);
675 break;
676 default:
677 return HAL_ERROR;
678 break;
679 }
680
681 /* read register and update the descriptor for first area*/
682 reg_value = READ_REG(*(__IO uint32_t *)register_address);
683 pMPCWM_Desc[0].AreaId = GTZC_TZSC_MPCWM_ID1;
684 pMPCWM_Desc[0].Offset = ((reg_value & GTZC_TZSC_MPCWMR_SUBZ_START_Msk)
685 >> GTZC_TZSC_MPCWMR_SUBZ_START_Pos) * granularity;
686 pMPCWM_Desc[0].Length = ((reg_value & GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk)
687 >> GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Pos) * granularity;
688
689 /* read configuration register and update the descriptor for first area*/
690 reg_value = READ_REG(*(__IO uint32_t *)(register_address - 4U));
691 pMPCWM_Desc[0].Attribute = (reg_value & (GTZC_TZSC_MPCWM_CFGR_PRIV | \
692 GTZC_TZSC_MPCWM_CFGR_SEC)) >> GTZC_TZSC_MPCWM_CFGR_SEC_Pos;
693 pMPCWM_Desc[0].Lock = reg_value & GTZC_TZSC_MPCWM_CFGR_SRLOCK;
694 pMPCWM_Desc[0].AreaStatus = reg_value & GTZC_TZSC_MPCWM_CFGR_SREN;
695
696 if ((MemBaseAddress != FMC_BANK3) && (MemBaseAddress != BKPSRAM_BASE))
697 {
698 /* Here MemBaseAddress = OCTOSPI1_BASE, OCTOSPI2_BASE
699 * or FMC_BANK1 (already checked)
700 * Now take care of the second area, present on these sub-blocks
701 */
702 switch (MemBaseAddress)
703 {
704 case OCTOSPI1_BASE:
705 register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM1BR);
706 break;
707 case FMC_BANK1:
708 register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM2BR);
709 break;
710 case OCTOSPI2_BASE:
711 register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM5BR);
712 break;
713 default:
714 return HAL_ERROR;
715 break;
716 }
717
718 /* read register and update the descriptor for second area*/
719 reg_value = READ_REG(*(__IO uint32_t *)register_address);
720 pMPCWM_Desc[1].AreaId = GTZC_TZSC_MPCWM_ID2;
721 pMPCWM_Desc[1].Offset = ((reg_value & GTZC_TZSC_MPCWMR_SUBZ_START_Msk)
722 >> GTZC_TZSC_MPCWMR_SUBZ_START_Pos) * granularity;
723 pMPCWM_Desc[1].Length = ((reg_value & GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk)
724 >> GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Pos) * granularity;
725
726 /* read configuration register and update the descriptor for second area*/
727 reg_value = READ_REG(*(__IO uint32_t *)(register_address - 4U));
728 pMPCWM_Desc[1].Attribute = reg_value & (GTZC_TZSC_MPCWM_CFGR_PRIV | \
729 GTZC_TZSC_MPCWM_CFGR_SEC);
730 pMPCWM_Desc[1].Lock = reg_value & GTZC_TZSC_MPCWM_CFGR_SRLOCK;
731 pMPCWM_Desc[1].AreaStatus = reg_value & GTZC_TZSC_MPCWM_CFGR_SREN;
732 }
733
734 return HAL_OK;
735 }
736
737 /**
738 * @}
739 */
740
741 /** @defgroup GTZC_Exported_Functions_Group3 TZSC Lock functions
742 * @brief TZSC Lock functions
743 *
744 @verbatim
745 ==============================================================================
746 ##### TZSC Lock functions #####
747 ==============================================================================
748 [..]
749 This section provides functions allowing to manage the TZSC (TrustZone
750 Security Controller) lock. It includes lock enable, and current value read.
751 @endverbatim
752 * @{
753 */
754
755 /**
756 * @brief Lock TZSC configuration.
757 * @note This function locks the configuration of TZSC_SECCFGRx and TZSC_PRIVCFGRx
758 * registers until next reset
759 * @param TZSC_Instance TZSC sub-block instance.
760 */
HAL_GTZC_TZSC_Lock(GTZC_TZSC_TypeDef * TZSC_Instance)761 void HAL_GTZC_TZSC_Lock(GTZC_TZSC_TypeDef *TZSC_Instance)
762 {
763 SET_BIT(TZSC_Instance->CR, GTZC_TZSC_CR_LCK_Msk);
764 }
765
766 /**
767 * @brief Get TZSC configuration lock state.
768 * @param TZSC_Instance TZSC sub-block instance.
769 * @retval Lock State (GTZC_TZSC_LOCK_OFF or GTZC_TZSC_LOCK_ON)
770 */
HAL_GTZC_TZSC_GetLock(GTZC_TZSC_TypeDef * TZSC_Instance)771 uint32_t HAL_GTZC_TZSC_GetLock(GTZC_TZSC_TypeDef *TZSC_Instance)
772 {
773 return READ_BIT(TZSC_Instance->CR, GTZC_TZSC_CR_LCK_Msk);
774 }
775
776 /**
777 * @}
778 */
779 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
780
781 /** @defgroup GTZC_Exported_Functions_Group4 MPCBB Configuration functions
782 * @brief MPCBB Configuration functions
783 *
784 @verbatim
785 ==============================================================================
786 ##### MPCBB Configuration functions #####
787 ==============================================================================
788 [..]
789 This section provides functions allowing to configure MPCBB
790 MPCBB is Memory Protection Controller Block Base
791 @endverbatim
792 * @{
793 */
794
795 /**
796 * @brief Set a complete MPCBB configuration on the SRAM passed as parameter.
797 * @param MemBaseAddress MPCBB identifier.
798 * @param pMPCBB_desc pointer to MPCBB descriptor.
799 * The structure description is available in @ref GTZC_Exported_Types.
800 * @retval HAL status.
801 */
HAL_GTZC_MPCBB_ConfigMem(uint32_t MemBaseAddress,MPCBB_ConfigTypeDef * pMPCBB_desc)802 HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMem(uint32_t MemBaseAddress,
803 MPCBB_ConfigTypeDef *pMPCBB_desc)
804 {
805 GTZC_MPCBB_TypeDef *mpcbb_ptr;
806 uint32_t reg_value;
807 uint32_t mem_size;
808 uint32_t size_in_superblocks;
809 uint32_t i;
810
811 /* check entry parameters */
812 if ((!(IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
813 && !(IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress))
814 && !(IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress))
815 && !(IS_GTZC_BASE_ADDRESS(SRAM4, MemBaseAddress)))
816 || ((pMPCBB_desc->SecureRWIllegalMode
817 != GTZC_MPCBB_SRWILADIS_ENABLE)
818 && (pMPCBB_desc->SecureRWIllegalMode
819 != GTZC_MPCBB_SRWILADIS_DISABLE))
820 || ((pMPCBB_desc->InvertSecureState
821 != GTZC_MPCBB_INVSECSTATE_NOT_INVERTED)
822 && (pMPCBB_desc->InvertSecureState
823 != GTZC_MPCBB_INVSECSTATE_INVERTED)))
824 {
825 return HAL_ERROR;
826 }
827
828 /* write InvertSecureState and SecureRWIllegalMode properties */
829 /* assume their Position/Mask is identical for all sub-blocks */
830 reg_value = pMPCBB_desc->InvertSecureState;
831 reg_value |= pMPCBB_desc->SecureRWIllegalMode;
832 if (IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
833 {
834 mpcbb_ptr = GTZC_MPCBB1;
835 mem_size = GTZC_MEM_SIZE(SRAM1);
836 }
837 else if (IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress))
838 {
839 mpcbb_ptr = GTZC_MPCBB2;
840 mem_size = GTZC_MEM_SIZE(SRAM2);
841 }
842 else if (IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress))
843 {
844 mpcbb_ptr = GTZC_MPCBB3;
845 mem_size = GTZC_MEM_SIZE(SRAM3);
846 }
847 else
848 {
849 /* Here MemBaseAddress is inside SRAM4 (parameter already checked) */
850 mpcbb_ptr = GTZC_MPCBB4;
851 mem_size = GTZC_MEM_SIZE(SRAM4);
852 }
853
854 /* translate mem_size in number of super-blocks */
855 size_in_superblocks = (mem_size / GTZC_MPCBB_SUPERBLOCK_SIZE);
856
857 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
858 uint32_t size_mask;
859
860 /* write configuration and lock register information */
861 MODIFY_REG(mpcbb_ptr->CR,
862 GTZC_MPCBB_CR_INVSECSTATE_Msk | GTZC_MPCBB_CR_SRWILADIS_Msk, reg_value);
863 if (size_in_superblocks == 32U)
864 {
865 size_mask = 0xFFFFFFFFU;
866 }
867 else
868 {
869 size_mask = (1UL << size_in_superblocks) - 1U;
870 }
871 /* limitation: code not portable with memory > 512K */
872 MODIFY_REG(mpcbb_ptr->CFGLOCKR1, size_mask, pMPCBB_desc->AttributeConfig.MPCBB_LockConfig_array[0]);
873
874 /* write SECCFGR register information */
875 for (i = 0U; i < size_in_superblocks; i++)
876 {
877 WRITE_REG(mpcbb_ptr->SECCFGR[i],
878 pMPCBB_desc->AttributeConfig.MPCBB_SecConfig_array[i]);
879 }
880 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
881
882 /* write PRIVCFGR register information */
883 for (i = 0U; i < size_in_superblocks; i++)
884 {
885 WRITE_REG(mpcbb_ptr->PRIVCFGR[i],
886 pMPCBB_desc->AttributeConfig.MPCBB_PrivConfig_array[i]);
887 }
888
889 return HAL_OK;
890 }
891
892 /**
893 * @brief Get a complete MPCBB configuration on the SRAM passed as parameter.
894 * @param MemBaseAddress MPCBB identifier.
895 * @param pMPCBB_desc pointer to a MPCBB descriptor.
896 * The structure description is available in @ref GTZC_Exported_Types.
897 * @retval HAL status.
898 */
HAL_GTZC_MPCBB_GetConfigMem(uint32_t MemBaseAddress,MPCBB_ConfigTypeDef * pMPCBB_desc)899 HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMem(uint32_t MemBaseAddress,
900 MPCBB_ConfigTypeDef *pMPCBB_desc)
901 {
902 GTZC_MPCBB_TypeDef *mpcbb_ptr;
903 uint32_t mem_size;
904 uint32_t size_in_superblocks;
905 uint32_t i;
906
907 /* check entry parameters */
908 if (!(IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
909 && !(IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress))
910 && !(IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress))
911 && !(IS_GTZC_BASE_ADDRESS(SRAM4, MemBaseAddress)))
912 {
913 return HAL_ERROR;
914 }
915
916 /* read InvertSecureState and SecureRWIllegalMode properties */
917 /* assume their Position/Mask is identical for all sub-blocks */
918 if (IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
919 {
920 mpcbb_ptr = GTZC_MPCBB1;
921 mem_size = GTZC_MEM_SIZE(SRAM1);
922 }
923 else if (IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress))
924 {
925 mpcbb_ptr = GTZC_MPCBB2;
926 mem_size = GTZC_MEM_SIZE(SRAM2);
927 }
928 else if (IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress))
929 {
930 mpcbb_ptr = GTZC_MPCBB3;
931 mem_size = GTZC_MEM_SIZE(SRAM3);
932 }
933 else
934 {
935 mpcbb_ptr = GTZC_MPCBB4;
936 mem_size = GTZC_MEM_SIZE(SRAM4);
937 }
938
939 /* translate mem_size in number of super-blocks */
940 size_in_superblocks = (mem_size / GTZC_MPCBB_SUPERBLOCK_SIZE);
941
942 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
943 uint32_t reg_value;
944 uint32_t size_mask;
945
946 /* read configuration and lock register information */
947 reg_value = READ_REG(mpcbb_ptr->CR);
948 pMPCBB_desc->InvertSecureState = (reg_value & GTZC_MPCBB_CR_INVSECSTATE_Msk);
949 pMPCBB_desc->SecureRWIllegalMode = (reg_value & GTZC_MPCBB_CR_SRWILADIS_Msk);
950 if (size_in_superblocks == 32U)
951 {
952 size_mask = 0xFFFFFFFFU;
953 }
954 else
955 {
956 size_mask = (1UL << size_in_superblocks) - 1U;
957 }
958 /* limitation: code not portable with memory > 512K */
959 pMPCBB_desc->AttributeConfig.MPCBB_LockConfig_array[0] = READ_REG(mpcbb_ptr->CFGLOCKR1)
960 & size_mask;
961 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
962
963 /* read SECCFGR / PRIVCFGR registers information */
964 for (i = 0U; i < size_in_superblocks; i++)
965 {
966 pMPCBB_desc->AttributeConfig.MPCBB_SecConfig_array[i] = mpcbb_ptr->SECCFGR[i];
967 pMPCBB_desc->AttributeConfig.MPCBB_PrivConfig_array[i] = mpcbb_ptr->PRIVCFGR[i];
968 }
969
970 return HAL_OK;
971 }
972
973 /**
974 * @brief Set a MPCBB attribute configuration on the SRAM passed as parameter
975 * for a number of blocks.
976 * @param MemAddress MPCBB identifier, and start block to configure
977 * (must be 512 Bytes aligned).
978 * @param NbBlocks Number of blocks to configure
979 * (Block size is 512 Bytes).
980 * @param pMemAttributes pointer to an array (containing "NbBlocks" elements),
981 * with each element must be GTZC_MCPBB_BLOCK_NSEC or GTZC_MCPBB_BLOCK_SEC,
982 * and GTZC_MCPBB_BLOCK_NPRIV or GTZC_MCPBB_BLOCK_PRIV.
983 * @retval HAL status.
984 */
HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress,uint32_t NbBlocks,uint32_t * pMemAttributes)985 HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress,
986 uint32_t NbBlocks,
987 uint32_t *pMemAttributes)
988 {
989 GTZC_MPCBB_TypeDef *mpcbb_ptr;
990 uint32_t base_address;
991 uint32_t end_address;
992 uint32_t block_start;
993 uint32_t offset_reg_start;
994 uint32_t offset_bit_start;
995 uint32_t i;
996 uint32_t do_attr_change;
997
998 /* firstly check that MemAddress is well 512 Bytes aligned */
999 if ((MemAddress % GTZC_MPCBB_BLOCK_SIZE) != 0U)
1000 {
1001 return HAL_ERROR;
1002 }
1003
1004 /* check entry parameters and deduce physical base address */
1005 end_address = MemAddress + (NbBlocks * GTZC_MPCBB_BLOCK_SIZE) - 1U;
1006 if (((IS_ADDRESS_IN_NS(SRAM1, MemAddress))
1007 && (IS_ADDRESS_IN_NS(SRAM1, end_address))) != 0U)
1008 {
1009 mpcbb_ptr = GTZC_MPCBB1;
1010 base_address = SRAM1_BASE_NS;
1011 }
1012 else if (((IS_ADDRESS_IN_S(SRAM1, MemAddress))
1013 && (IS_ADDRESS_IN_S(SRAM1, end_address))) != 0U)
1014 {
1015 mpcbb_ptr = GTZC_MPCBB1;
1016 base_address = SRAM1_BASE_S;
1017 }
1018 else if (((IS_ADDRESS_IN_NS(SRAM2, MemAddress))
1019 && (IS_ADDRESS_IN_NS(SRAM2, end_address))) != 0U)
1020 {
1021 mpcbb_ptr = GTZC_MPCBB2;
1022 base_address = SRAM2_BASE_NS;
1023 }
1024 else if (((IS_ADDRESS_IN_S(SRAM2, MemAddress))
1025 && (IS_ADDRESS_IN_S(SRAM2, end_address))) != 0U)
1026 {
1027 mpcbb_ptr = GTZC_MPCBB2;
1028 base_address = SRAM2_BASE_S;
1029 }
1030 else if (((IS_ADDRESS_IN_NS(SRAM3, MemAddress))
1031 && (IS_ADDRESS_IN_NS(SRAM3, end_address))) != 0U)
1032 {
1033 mpcbb_ptr = GTZC_MPCBB3;
1034 base_address = SRAM3_BASE_NS;
1035 }
1036 else if (((IS_ADDRESS_IN_S(SRAM3, MemAddress))
1037 && (IS_ADDRESS_IN_S(SRAM3, end_address))) != 0U)
1038 {
1039 mpcbb_ptr = GTZC_MPCBB3;
1040 base_address = SRAM3_BASE_S;
1041 }
1042 else if (((IS_ADDRESS_IN_NS(SRAM4, MemAddress))
1043 && (IS_ADDRESS_IN_NS(SRAM4, end_address))) != 0U)
1044 {
1045 mpcbb_ptr = GTZC_MPCBB4;
1046 base_address = SRAM4_BASE_NS;
1047 }
1048 else if (((IS_ADDRESS_IN_S(SRAM4, MemAddress))
1049 && (IS_ADDRESS_IN_S(SRAM4, end_address))) != 0U)
1050 {
1051 mpcbb_ptr = GTZC_MPCBB4;
1052 base_address = SRAM4_BASE_S;
1053 }
1054 else
1055 {
1056 return HAL_ERROR;
1057 }
1058
1059 /* get start coordinates of the configuration */
1060 block_start = (MemAddress - base_address) / GTZC_MPCBB_BLOCK_SIZE;
1061 offset_reg_start = block_start / 32U;
1062 offset_bit_start = block_start % 32U;
1063
1064 for (i = 0U; i < NbBlocks; i++)
1065 {
1066 /* Indicate change done for protection attributes */
1067 do_attr_change = 0U;
1068
1069 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1070 /* secure configuration */
1071 if ((pMemAttributes[i] & GTZC_MCPBB_BLOCK_SEC) == GTZC_MCPBB_BLOCK_SEC)
1072 {
1073 SET_BIT(mpcbb_ptr->SECCFGR[offset_reg_start],
1074 1UL << (offset_bit_start % 32U));
1075 do_attr_change = 1U;
1076 }
1077 else if ((pMemAttributes[i] & GTZC_MCPBB_BLOCK_NSEC) == GTZC_MCPBB_BLOCK_NSEC)
1078 {
1079 CLEAR_BIT(mpcbb_ptr->SECCFGR[offset_reg_start],
1080 1UL << (offset_bit_start % 32U));
1081 do_attr_change = 1U;
1082 }
1083 else
1084 {
1085 /* nothing to do */
1086 }
1087 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1088
1089 /* privilege configuration */
1090 if ((pMemAttributes[i] & GTZC_MCPBB_BLOCK_PRIV) == GTZC_MCPBB_BLOCK_PRIV)
1091 {
1092 SET_BIT(mpcbb_ptr->PRIVCFGR[offset_reg_start],
1093 1UL << (offset_bit_start % 32U));
1094 }
1095 else if ((pMemAttributes[i] & GTZC_MCPBB_BLOCK_NPRIV) == GTZC_MCPBB_BLOCK_NPRIV)
1096 {
1097 CLEAR_BIT(mpcbb_ptr->PRIVCFGR[offset_reg_start],
1098 1UL << (offset_bit_start % 32U));
1099 }
1100 else
1101 {
1102 /* if no change is done for security and privilege attributes: break the loop */
1103 if (do_attr_change == 0U)
1104 {
1105 break;
1106 }
1107 }
1108
1109 offset_bit_start++;
1110 if (offset_bit_start == 32U)
1111 {
1112 offset_bit_start = 0U;
1113 offset_reg_start++;
1114 }
1115 }
1116
1117 /* an unexpected value in pMemAttributes array leads to error status */
1118 if (i != NbBlocks)
1119 {
1120 return HAL_ERROR;
1121 }
1122
1123 return HAL_OK;
1124 }
1125
1126 /**
1127 * @brief Get a MPCBB attribute configuration on the SRAM passed as parameter
1128 * for a number of blocks.
1129 * @param MemAddress MPCBB identifier, and start block to get configuration
1130 * (must be 512 Bytes aligned).
1131 * @param NbBlocks Number of blocks to get configuration.
1132 * @param pMemAttributes pointer to an array (containing "NbBlocks" elements),
1133 * with each element will be GTZC_MCPBB_BLOCK_NSEC or GTZC_MCPBB_BLOCK_SEC,
1134 * and GTZC_MCPBB_BLOCK_NPRIV or GTZC_MCPBB_BLOCK_PRIV.
1135 * @retval HAL status.
1136 */
HAL_GTZC_MPCBB_GetConfigMemAttributes(uint32_t MemAddress,uint32_t NbBlocks,uint32_t * pMemAttributes)1137 HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMemAttributes(uint32_t MemAddress,
1138 uint32_t NbBlocks,
1139 uint32_t *pMemAttributes)
1140 {
1141 GTZC_MPCBB_TypeDef *mpcbb_ptr;
1142 uint32_t base_address;
1143 uint32_t end_address;
1144 uint32_t block_start;
1145 uint32_t offset_reg_start;
1146 uint32_t offset_bit_start;
1147 uint32_t i;
1148
1149 /* firstly check that MemAddress is well 512 Bytes aligned */
1150 if ((MemAddress % GTZC_MPCBB_BLOCK_SIZE) != 0U)
1151 {
1152 return HAL_ERROR;
1153 }
1154
1155 /* check entry parameters and deduce physical base address */
1156 end_address = MemAddress + (NbBlocks * GTZC_MPCBB_BLOCK_SIZE) - 1U;
1157 if ((IS_ADDRESS_IN_NS(SRAM1, MemAddress))
1158 && (IS_ADDRESS_IN_NS(SRAM1, end_address)))
1159 {
1160 mpcbb_ptr = GTZC_MPCBB1_NS;
1161 base_address = SRAM1_BASE_NS;
1162 }
1163 else if ((IS_ADDRESS_IN_S(SRAM1, MemAddress))
1164 && (IS_ADDRESS_IN_S(SRAM1, end_address)))
1165 {
1166 mpcbb_ptr = GTZC_MPCBB1_S;
1167 base_address = SRAM1_BASE_S;
1168 }
1169 else if ((IS_ADDRESS_IN_NS(SRAM2, MemAddress))
1170 && (IS_ADDRESS_IN_NS(SRAM2, end_address)))
1171 {
1172 mpcbb_ptr = GTZC_MPCBB2_NS;
1173 base_address = SRAM2_BASE_NS;
1174 }
1175 else if ((IS_ADDRESS_IN_S(SRAM2, MemAddress))
1176 && (IS_ADDRESS_IN_S(SRAM2, end_address)))
1177 {
1178 mpcbb_ptr = GTZC_MPCBB2_S;
1179 base_address = SRAM2_BASE_S;
1180 }
1181 else if ((IS_ADDRESS_IN_NS(SRAM3, MemAddress))
1182 && (IS_ADDRESS_IN_NS(SRAM3, end_address)))
1183 {
1184 mpcbb_ptr = GTZC_MPCBB3_NS;
1185 base_address = SRAM3_BASE_NS;
1186 }
1187 else if ((IS_ADDRESS_IN_S(SRAM3, MemAddress))
1188 && (IS_ADDRESS_IN_S(SRAM3, end_address)))
1189 {
1190 mpcbb_ptr = GTZC_MPCBB3_S;
1191 base_address = SRAM3_BASE_S;
1192 }
1193 else if ((IS_ADDRESS_IN_NS(SRAM4, MemAddress))
1194 && (IS_ADDRESS_IN_NS(SRAM4, end_address)))
1195 {
1196 mpcbb_ptr = GTZC_MPCBB4_NS;
1197 base_address = SRAM4_BASE_NS;
1198 }
1199 else if ((IS_ADDRESS_IN_S(SRAM4, MemAddress))
1200 && (IS_ADDRESS_IN_S(SRAM4, end_address)))
1201 {
1202 mpcbb_ptr = GTZC_MPCBB4_S;
1203 base_address = SRAM4_BASE_S;
1204 }
1205 else
1206 {
1207 return HAL_ERROR;
1208 }
1209
1210 /* get start coordinates of the configuration */
1211 block_start = (MemAddress - base_address) / GTZC_MPCBB_BLOCK_SIZE;
1212 offset_reg_start = block_start / 32U;
1213 offset_bit_start = block_start % 32U;
1214
1215 for (i = 0U; i < NbBlocks; i++)
1216 {
1217 pMemAttributes[i] = (READ_BIT(mpcbb_ptr->SECCFGR[offset_reg_start],
1218 1UL << (offset_bit_start % 32U))
1219 >> (offset_bit_start % 32U)) | GTZC_ATTR_SEC_MASK;
1220 pMemAttributes[i] |= (READ_BIT(mpcbb_ptr->PRIVCFGR[offset_reg_start],
1221 1UL << (offset_bit_start % 32U))
1222 >> (offset_bit_start % 32U)) | GTZC_ATTR_PRIV_MASK;
1223
1224 offset_bit_start++;
1225 if (offset_bit_start == 32U)
1226 {
1227 offset_bit_start = 0U;
1228 offset_reg_start++;
1229 }
1230 }
1231
1232 return HAL_OK;
1233 }
1234
1235 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1236 /**
1237 * @brief Lock MPCBB super-blocks on the SRAM passed as parameter.
1238 * @param MemAddress MPCBB start-address of super-block to configure
1239 * (must be 16KBytes aligned).
1240 * @param NbSuperBlocks Number of super-blocks to configure.
1241 * @param pLockAttributes pointer to an array (containing "NbSuperBlocks" elements),
1242 * with for each element:
1243 * value 0 super-block is unlocked, value 1 super-block is locked
1244 * (corresponds to GTZC_MCPBB_SUPERBLOCK_UNLOCKED and
1245 * GTZC_MCPBB_SUPERBLOCK_LOCKED values).
1246 * @retval HAL status.
1247 */
HAL_GTZC_MPCBB_LockConfig(uint32_t MemAddress,uint32_t NbSuperBlocks,uint32_t * pLockAttributes)1248 HAL_StatusTypeDef HAL_GTZC_MPCBB_LockConfig(uint32_t MemAddress,
1249 uint32_t NbSuperBlocks,
1250 uint32_t *pLockAttributes)
1251 {
1252 __IO uint32_t *reg_mpcbb;
1253 uint32_t base_address;
1254 uint32_t superblock_start;
1255 uint32_t offset_bit_start;
1256 uint32_t i;
1257
1258 /* firstly check that MemAddress is well 16KBytes aligned */
1259 if ((MemAddress % GTZC_MPCBB_SUPERBLOCK_SIZE) != 0U)
1260 {
1261 return HAL_ERROR;
1262 }
1263
1264 /* check entry parameters */
1265 if ((IS_ADDRESS_IN(SRAM1, MemAddress))
1266 && (IS_ADDRESS_IN(SRAM1, (MemAddress
1267 + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE)
1268 - 1U))))
1269 {
1270 base_address = GTZC_BASE_ADDRESS(SRAM1);
1271 /* limitation: code not portable with memory > 512K */
1272 reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB1_S->CFGLOCKR1;
1273 }
1274 else if ((IS_ADDRESS_IN(SRAM2, MemAddress))
1275 && (IS_ADDRESS_IN(SRAM2, (MemAddress
1276 + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE)
1277 - 1U))))
1278 {
1279 base_address = GTZC_BASE_ADDRESS(SRAM2);
1280 /* limitation: code not portable with memory > 512K */
1281 reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB2_S->CFGLOCKR1;
1282 }
1283 else if ((IS_ADDRESS_IN(SRAM3, MemAddress))
1284 && (IS_ADDRESS_IN(SRAM3, (MemAddress
1285 + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE)
1286 - 1U))))
1287 {
1288 base_address = GTZC_BASE_ADDRESS(SRAM3);
1289 /* limitation: code not portable with memory > 512K */
1290 reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB3_S->CFGLOCKR1;
1291 }
1292
1293 else if ((IS_ADDRESS_IN(SRAM4, MemAddress))
1294 && (IS_ADDRESS_IN(SRAM4, (MemAddress
1295 + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE)
1296 - 1U))))
1297 {
1298 base_address = GTZC_BASE_ADDRESS(SRAM4);
1299 /* limitation: code not portable with memory > 512K */
1300 reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB4_S->CFGLOCKR1;
1301 }
1302 else
1303 {
1304 return HAL_ERROR;
1305 }
1306
1307 /* get start coordinates of the configuration */
1308 superblock_start = (MemAddress - base_address) / GTZC_MPCBB_SUPERBLOCK_SIZE;
1309 offset_bit_start = superblock_start % 32U;
1310
1311 for (i = 0U; i < NbSuperBlocks; i++)
1312 {
1313 if (pLockAttributes[i] == GTZC_MCPBB_SUPERBLOCK_LOCKED)
1314 {
1315 SET_BIT(*reg_mpcbb, 1UL << (offset_bit_start % 32U));
1316 }
1317 else if (pLockAttributes[i] == GTZC_MCPBB_SUPERBLOCK_UNLOCKED)
1318 {
1319 CLEAR_BIT(*reg_mpcbb, 1UL << (offset_bit_start % 32U));
1320 }
1321 else
1322 {
1323 break;
1324 }
1325
1326 offset_bit_start++;
1327 }
1328
1329 /* an unexpected value in pLockAttributes array leads to an error status */
1330 if (i != NbSuperBlocks)
1331 {
1332 return HAL_ERROR;
1333 }
1334
1335 return HAL_OK;
1336 }
1337
1338 /**
1339 * @brief Get MPCBB super-blocks lock configuration on the SRAM passed as parameter.
1340 * @param MemAddress MPCBB start-address of super-block to get configuration
1341 * (must be 16KBytes aligned).
1342 * @param NbSuperBlocks Number of super-blocks to get configuration.
1343 * @param pLockAttributes pointer to an array (containing "NbSuperBlocks" elements),
1344 * with for each element:
1345 * value 0 super-block is unlocked, value 1 super-block is locked
1346 * (corresponds to GTZC_MCPBB_SUPERBLOCK_UNLOCKED and
1347 * GTZC_MCPBB_SUPERBLOCK_LOCKED values).
1348 * @retval HAL status.
1349 */
HAL_GTZC_MPCBB_GetLockConfig(uint32_t MemAddress,uint32_t NbSuperBlocks,uint32_t * pLockAttributes)1350 HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLockConfig(uint32_t MemAddress,
1351 uint32_t NbSuperBlocks,
1352 uint32_t *pLockAttributes)
1353 {
1354 uint32_t reg_mpcbb;
1355 uint32_t base_address;
1356 uint32_t superblock_start;
1357 uint32_t offset_bit_start;
1358 uint32_t i;
1359
1360 /* firstly check that MemAddress is well 16KBytes aligned */
1361 if ((MemAddress % GTZC_MPCBB_SUPERBLOCK_SIZE) != 0U)
1362 {
1363 return HAL_ERROR;
1364 }
1365
1366 /* check entry parameters */
1367 if ((IS_ADDRESS_IN(SRAM1, MemAddress))
1368 && (IS_ADDRESS_IN(SRAM1, (MemAddress
1369 + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE)
1370 - 1U))))
1371 {
1372 base_address = GTZC_BASE_ADDRESS(SRAM1);
1373 /* limitation: code not portable with memory > 512K */
1374 reg_mpcbb = GTZC_MPCBB1_S->CFGLOCKR1;
1375 }
1376 else if ((IS_ADDRESS_IN(SRAM2, MemAddress))
1377 && (IS_ADDRESS_IN(SRAM2, (MemAddress
1378 + (NbSuperBlocks
1379 * GTZC_MPCBB_SUPERBLOCK_SIZE)
1380 - 1U))))
1381 {
1382 base_address = GTZC_BASE_ADDRESS(SRAM2);
1383 /* limitation: code not portable with memory > 512K */
1384 reg_mpcbb = GTZC_MPCBB2_S->CFGLOCKR1;
1385 }
1386 else if ((IS_ADDRESS_IN(SRAM3, MemAddress))
1387 && (IS_ADDRESS_IN(SRAM3, (MemAddress
1388 + (NbSuperBlocks
1389 * GTZC_MPCBB_SUPERBLOCK_SIZE)
1390 - 1U))))
1391 {
1392 base_address = GTZC_BASE_ADDRESS(SRAM3);
1393 /* limitation: code not portable with memory > 512K */
1394 reg_mpcbb = GTZC_MPCBB3_S->CFGLOCKR1;
1395 }
1396 else if ((IS_ADDRESS_IN(SRAM4, MemAddress))
1397 && (IS_ADDRESS_IN(SRAM4, (MemAddress
1398 + (NbSuperBlocks
1399 * GTZC_MPCBB_SUPERBLOCK_SIZE)
1400 - 1U))))
1401 {
1402 base_address = GTZC_BASE_ADDRESS(SRAM4);
1403 /* limitation: code not portable with memory > 512K */
1404 reg_mpcbb = GTZC_MPCBB4_S->CFGLOCKR1;
1405 }
1406 else
1407 {
1408 return HAL_ERROR;
1409 }
1410
1411 /* get start coordinates of the configuration */
1412 superblock_start = (MemAddress - base_address) / GTZC_MPCBB_SUPERBLOCK_SIZE;
1413 offset_bit_start = superblock_start % 32U;
1414
1415 for (i = 0U; i < NbSuperBlocks; i++)
1416 {
1417 pLockAttributes[i] = (reg_mpcbb & (1UL << (offset_bit_start % 32U)))
1418 >> (offset_bit_start % 32U);
1419 offset_bit_start++;
1420 }
1421
1422 return HAL_OK;
1423 }
1424
1425 /**
1426 * @brief Lock a MPCBB configuration on the SRAM base address passed as parameter.
1427 * @note This functions locks the control register of the MPCBB until next reset.
1428 * @param MemBaseAddress MPCBB identifier.
1429 * @retval HAL status.
1430 */
HAL_GTZC_MPCBB_Lock(uint32_t MemBaseAddress)1431 HAL_StatusTypeDef HAL_GTZC_MPCBB_Lock(uint32_t MemBaseAddress)
1432 {
1433 /* check entry parameters */
1434 if (IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
1435 {
1436 SET_BIT(GTZC_MPCBB1_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
1437 }
1438 else if (IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress))
1439 {
1440 SET_BIT(GTZC_MPCBB2_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
1441 }
1442 else if (IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress))
1443 {
1444 SET_BIT(GTZC_MPCBB3_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
1445 }
1446 else if (IS_GTZC_BASE_ADDRESS(SRAM4, MemBaseAddress))
1447 {
1448 SET_BIT(GTZC_MPCBB4_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
1449 }
1450 else
1451 {
1452 return HAL_ERROR;
1453 }
1454
1455 return HAL_OK;
1456 }
1457
1458 /**
1459 * @brief Get MPCBB configuration lock state on the SRAM base address passed as parameter.
1460 * @param MemBaseAddress MPCBB identifier.
1461 * @param pLockState pointer to Lock State (GTZC_MCPBB_LOCK_OFF or GTZC_MCPBB_LOCK_ON).
1462 * @retval HAL status.
1463 */
HAL_GTZC_MPCBB_GetLock(uint32_t MemBaseAddress,uint32_t * pLockState)1464 HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLock(uint32_t MemBaseAddress,
1465 uint32_t *pLockState)
1466 {
1467 /* check entry parameters */
1468 if (IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
1469 {
1470 *pLockState = READ_BIT(GTZC_MPCBB1_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
1471 }
1472 else if (IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress))
1473 {
1474 *pLockState = READ_BIT(GTZC_MPCBB2_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
1475 }
1476 else if (IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress))
1477 {
1478 *pLockState = READ_BIT(GTZC_MPCBB3_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
1479 }
1480 else if (IS_GTZC_BASE_ADDRESS(SRAM4, MemBaseAddress))
1481 {
1482 *pLockState = READ_BIT(GTZC_MPCBB4_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
1483 }
1484 else
1485 {
1486 return HAL_ERROR;
1487 }
1488
1489 return HAL_OK;
1490 }
1491
1492 /**
1493 * @}
1494 */
1495
1496 /** @defgroup GTZC_Exported_Functions_Group5 TZIC Configuration and Control functions
1497 * @brief TZIC Configuration and Control functions
1498 *
1499 @verbatim
1500 ==============================================================================
1501 ##### TZIC Configuration and Control functions #####
1502 ==============================================================================
1503 [..]
1504 This section provides functions allowing to configure and control TZIC
1505 TZIC is Trust Zone Interrupt Controller
1506 @endverbatim
1507 * @{
1508 */
1509
1510 /**
1511 * @brief Disable the interrupt associated to a single TZIC peripheral or on all peripherals.
1512 * @param PeriphId Peripheral identifier.
1513 * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId.
1514 * Use GTZC_PERIPH_ALL to select all peripherals.
1515 * @retval HAL status.
1516 */
HAL_GTZC_TZIC_DisableIT(uint32_t PeriphId)1517 HAL_StatusTypeDef HAL_GTZC_TZIC_DisableIT(uint32_t PeriphId)
1518 {
1519 uint32_t register_address;
1520
1521 /* check entry parameters */
1522 if ((HAL_GTZC_TZIC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER)
1523 || (((PeriphId & GTZC_PERIPH_ALL) != 0U)
1524 && (HAL_GTZC_TZIC_GET_ARRAY_INDEX(PeriphId) != 0U)))
1525 {
1526 return HAL_ERROR;
1527 }
1528
1529 if ((PeriphId & GTZC_PERIPH_ALL) != 0U)
1530 {
1531 /* same configuration is applied to all peripherals */
1532 WRITE_REG(GTZC_TZIC1->IER1, 0U);
1533 WRITE_REG(GTZC_TZIC1->IER2, 0U);
1534 WRITE_REG(GTZC_TZIC1->IER3, 0U);
1535 WRITE_REG(GTZC_TZIC1->IER4, 0U);
1536 WRITE_REG(GTZC_TZIC2->IER1, 0U);
1537 WRITE_REG(GTZC_TZIC2->IER2, 0U);
1538 }
1539 else
1540 {
1541 /* common case where only one peripheral is configured */
1542 register_address = (uint32_t) &(HAL_GTZC_TZIC_GET_INSTANCE(PeriphId)->IER1)
1543 + (4U * GTZC_GET_REG_INDEX_IN_INSTANCE(PeriphId));
1544 CLEAR_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
1545 }
1546
1547 return HAL_OK;
1548 }
1549
1550 /**
1551 * @brief Enable the interrupt associated to a single TZIC peripheral or on all peripherals.
1552 * @param PeriphId Peripheral identifier.
1553 * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId.
1554 * Use GTZC_PERIPH_ALL to select all peripherals.
1555 * @retval HAL status.
1556 */
HAL_GTZC_TZIC_EnableIT(uint32_t PeriphId)1557 HAL_StatusTypeDef HAL_GTZC_TZIC_EnableIT(uint32_t PeriphId)
1558 {
1559 uint32_t register_address;
1560
1561 /* check entry parameters */
1562 if ((HAL_GTZC_TZIC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER)
1563 || (((PeriphId & GTZC_PERIPH_ALL) != 0U)
1564 && (HAL_GTZC_TZIC_GET_ARRAY_INDEX(PeriphId) != 0U)))
1565 {
1566 return HAL_ERROR;
1567 }
1568
1569 if ((PeriphId & GTZC_PERIPH_ALL) != 0U)
1570 {
1571 /* same configuration is applied to all peripherals */
1572 WRITE_REG(GTZC_TZIC1->IER1, TZIC1_IER1_ALL);
1573 WRITE_REG(GTZC_TZIC1->IER2, TZIC1_IER2_ALL);
1574 WRITE_REG(GTZC_TZIC1->IER3, TZIC1_IER3_ALL);
1575 WRITE_REG(GTZC_TZIC1->IER4, TZIC1_IER4_ALL);
1576 WRITE_REG(GTZC_TZIC2->IER1, TZIC2_IER1_ALL);
1577 WRITE_REG(GTZC_TZIC2->IER2, TZIC2_IER2_ALL);
1578 }
1579 else
1580 {
1581 /* common case where only one peripheral is configured */
1582 register_address = (uint32_t) &(HAL_GTZC_TZIC_GET_INSTANCE(PeriphId)->IER1)
1583 + (4U * GTZC_GET_REG_INDEX_IN_INSTANCE(PeriphId));
1584 SET_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
1585 }
1586
1587 return HAL_OK;
1588 }
1589
1590 /**
1591 * @brief Get TZIC flag on a single TZIC peripheral or on all peripherals.
1592 * @param PeriphId Peripheral identifier.
1593 * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId.
1594 * Use GTZC_PERIPH_ALL to select all peripherals.
1595 * @param pFlag Pointer to the flags.
1596 * If PeriphId target a single peripheral, pointer on a single element.
1597 * If all peripherals selected (GTZC_PERIPH_ALL), pointer to an array
1598 * of GTZC_TZIC_PERIPH_NUMBER elements.
1599 * Element content is either GTZC_TZIC_NO_ILA_EVENT
1600 * or GTZC_TZSC_ILA_EVENT_PENDING.
1601 * @retval HAL status
1602 */
HAL_GTZC_TZIC_GetFlag(uint32_t PeriphId,uint32_t * pFlag)1603 HAL_StatusTypeDef HAL_GTZC_TZIC_GetFlag(uint32_t PeriphId, uint32_t *pFlag)
1604 {
1605 uint32_t i;
1606 uint32_t reg_value;
1607 uint32_t register_address;
1608
1609 /* check entry parameters */
1610 if ((HAL_GTZC_TZIC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER)
1611 || (((PeriphId & GTZC_PERIPH_ALL) != 0U)
1612 && (HAL_GTZC_TZIC_GET_ARRAY_INDEX(PeriphId) != 0U)))
1613 {
1614 return HAL_ERROR;
1615 }
1616
1617 if ((PeriphId & GTZC_PERIPH_ALL) != 0U)
1618 {
1619 /* special case where it is applied to all peripherals */
1620 reg_value = READ_REG(GTZC_TZIC1->SR1);
1621 for (i = 0U; i < 32U; i++)
1622 {
1623 pFlag[i] = (reg_value & (1UL << i)) >> i;
1624 }
1625
1626 reg_value = READ_REG(GTZC_TZIC1->SR2);
1627 for (i = 32U; i < 64U; i++)
1628 {
1629 pFlag[i] = (reg_value & (1UL << (i - 32U))) >> (i - 32U);
1630 }
1631
1632 reg_value = READ_REG(GTZC_TZIC1->SR3);
1633 for (i = 64; i < 96U; i++)
1634 {
1635 pFlag[i] = (reg_value & (1UL << (i - 64U))) >> (i - 64U);
1636 }
1637
1638 reg_value = READ_REG(GTZC_TZIC1->SR4);
1639 for (i = 96U; i < 128U; i++)
1640 {
1641 pFlag[i] = (reg_value & (1UL << (i - 96U))) >> (i - 96U);
1642 }
1643
1644 reg_value = READ_REG(GTZC_TZIC2->SR1);
1645 for (i = 128U; i < 160U; i++)
1646 {
1647 pFlag[i] = (reg_value & (1UL << (i - 128U))) >> (i - 128U);
1648 }
1649
1650 reg_value = READ_REG(GTZC_TZIC2->SR2);
1651 for (i = 160U; i < GTZC_TZIC_PERIPH_NUMBER; i++)
1652 {
1653 pFlag[i] = (reg_value & (1UL << (i - 160U))) >> (i - 160U);
1654 }
1655 }
1656 else
1657 {
1658 /* common case where only one peripheral is concerned */
1659 register_address = (uint32_t) &(HAL_GTZC_TZIC_GET_INSTANCE(PeriphId)->SR1)
1660 + (4U * GTZC_GET_REG_INDEX_IN_INSTANCE(PeriphId));
1661 *pFlag = READ_BIT(*(__IO uint32_t *)register_address,
1662 1UL << GTZC_GET_PERIPH_POS(PeriphId)) >> GTZC_GET_PERIPH_POS(PeriphId);
1663 }
1664
1665 return HAL_OK;
1666 }
1667
1668 /**
1669 * @brief Clear TZIC flag on a single TZIC peripheral or on all peripherals.
1670 * @param PeriphId Peripheral identifier.
1671 * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId.
1672 * Use GTZC_PERIPH_ALL to select all peripherals.
1673 * @retval HAL status.
1674 */
HAL_GTZC_TZIC_ClearFlag(uint32_t PeriphId)1675 HAL_StatusTypeDef HAL_GTZC_TZIC_ClearFlag(uint32_t PeriphId)
1676 {
1677 uint32_t register_address;
1678
1679 /* check entry parameters */
1680 if ((HAL_GTZC_TZIC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER)
1681 || (((PeriphId & GTZC_PERIPH_ALL) != 0U)
1682 && (HAL_GTZC_TZIC_GET_ARRAY_INDEX(PeriphId) != 0U)))
1683 {
1684 return HAL_ERROR;
1685 }
1686
1687 if ((PeriphId & GTZC_PERIPH_ALL) != 0U)
1688 {
1689 /* same configuration is applied to all peripherals */
1690 WRITE_REG(GTZC_TZIC1->FCR1, TZIC1_FCR1_ALL);
1691 WRITE_REG(GTZC_TZIC1->FCR2, TZIC1_FCR2_ALL);
1692 WRITE_REG(GTZC_TZIC1->FCR3, TZIC1_FCR3_ALL);
1693 WRITE_REG(GTZC_TZIC1->FCR4, TZIC1_FCR4_ALL);
1694 WRITE_REG(GTZC_TZIC2->FCR1, TZIC2_FCR1_ALL);
1695 WRITE_REG(GTZC_TZIC2->FCR2, TZIC2_FCR2_ALL);
1696 }
1697 else
1698 {
1699 /* common case where only one peripheral is configured */
1700 register_address = (uint32_t) &(HAL_GTZC_TZIC_GET_INSTANCE(PeriphId)->FCR1)
1701 + (4U * GTZC_GET_REG_INDEX_IN_INSTANCE(PeriphId));
1702 SET_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
1703 }
1704
1705 return HAL_OK;
1706 }
1707
1708 /**
1709 * @}
1710 */
1711
1712 /** @defgroup GTZC_Exported_Functions_Group6 IRQ related functions
1713 * @brief IRQ related functions
1714 *
1715 @verbatim
1716 ==============================================================================
1717 ##### TZIC IRQ Handler and Callback functions #####
1718 ==============================================================================
1719 [..]
1720 This section provides functions allowing to treat ISR and provide user callback
1721 @endverbatim
1722 * @{
1723 */
1724
1725 /**
1726 * @brief This function handles GTZC TZIC interrupt request.
1727 * @retval None.
1728 */
HAL_GTZC_IRQHandler(void)1729 void HAL_GTZC_IRQHandler(void)
1730 {
1731 uint32_t position;
1732 uint32_t flag;
1733 uint32_t ier_itsources;
1734 uint32_t sr_flags;
1735
1736 /*********************************************************************/
1737 /****************************** TZIC1 ******************************/
1738 /*********************************************************************/
1739
1740 /* Get current IT Flags and IT sources value on 1st register of TZIC1 */
1741 ier_itsources = READ_REG(GTZC_TZIC1_S->IER1);
1742 sr_flags = READ_REG(GTZC_TZIC1_S->SR1);
1743
1744 /* Get Mask interrupt and then clear them */
1745 flag = ier_itsources & sr_flags;
1746 if (flag != 0U)
1747 {
1748 WRITE_REG(GTZC_TZIC1_S->FCR1, flag);
1749
1750 /* Loop on flag to check, which ones have been raised */
1751 position = 0U;
1752 while ((flag >> position) != 0U)
1753 {
1754 if ((flag & (1UL << position)) != 0U)
1755 {
1756 HAL_GTZC_TZIC_Callback(GTZC1_PERIPH_REG1 | position);
1757 }
1758
1759 /* Position bit to be updated */
1760 position++;
1761 }
1762 }
1763
1764 /* Get current IT Flags and IT sources value on 2nd register of TZIC1 */
1765 ier_itsources = READ_REG(GTZC_TZIC1_S->IER2);
1766 sr_flags = READ_REG(GTZC_TZIC1_S->SR2);
1767
1768 /* Get Mask interrupt and then clear them */
1769 flag = ier_itsources & sr_flags;
1770 if (flag != 0U)
1771 {
1772 WRITE_REG(GTZC_TZIC1_S->FCR2, flag);
1773
1774 /* Loop on flag to check, which ones have been raised */
1775 position = 0U;
1776 while ((flag >> position) != 0U)
1777 {
1778 if ((flag & (1UL << position)) != 0U)
1779 {
1780 HAL_GTZC_TZIC_Callback(GTZC1_PERIPH_REG2 | position);
1781 }
1782
1783 /* Position bit to be updated */
1784 position++;
1785 }
1786 }
1787
1788 /* Get current IT Flags and IT sources value on 3rd register of TZIC1 */
1789 ier_itsources = READ_REG(GTZC_TZIC1_S->IER3);
1790 sr_flags = READ_REG(GTZC_TZIC1_S->SR3);
1791
1792 /* Get Mask interrupt and then clear them */
1793 flag = ier_itsources & sr_flags;
1794 if (flag != 0U)
1795 {
1796 WRITE_REG(GTZC_TZIC1_S->FCR3, flag);
1797
1798 /* Loop on flag to check, which ones have been raised */
1799 position = 0U;
1800 while ((flag >> position) != 0U)
1801 {
1802 if ((flag & (1UL << position)) != 0U)
1803 {
1804 HAL_GTZC_TZIC_Callback(GTZC1_PERIPH_REG3 | position);
1805 }
1806
1807 /* Position bit to be updated */
1808 position++;
1809 }
1810 }
1811
1812 /* Get current IT Flags and IT sources value on 4th register of TZIC1 */
1813 ier_itsources = READ_REG(GTZC_TZIC1_S->IER4);
1814 sr_flags = READ_REG(GTZC_TZIC1_S->SR4);
1815
1816 /* Get Mask interrupt and then clear them */
1817 flag = ier_itsources & sr_flags;
1818 if (flag != 0U)
1819 {
1820 WRITE_REG(GTZC_TZIC1_S->FCR4, flag);
1821
1822 /* Loop on flag to check, which ones have been raised */
1823 position = 0U;
1824 while ((flag >> position) != 0U)
1825 {
1826 if ((flag & (1UL << position)) != 0U)
1827 {
1828 HAL_GTZC_TZIC_Callback(GTZC1_PERIPH_REG4 | position);
1829 }
1830
1831 /* Position bit to be updated */
1832 position++;
1833 }
1834 }
1835
1836 /*********************************************************************/
1837 /****************************** TZIC2 ******************************/
1838 /*********************************************************************/
1839
1840 /* Get current IT Flags and IT sources value on 1st register of TZIC2 */
1841 ier_itsources = READ_REG(GTZC_TZIC2_S->IER1);
1842 sr_flags = READ_REG(GTZC_TZIC2_S->SR1);
1843
1844 /* Get Mask interrupt and then clear them */
1845 flag = ier_itsources & sr_flags;
1846 if (flag != 0U)
1847 {
1848 WRITE_REG(GTZC_TZIC2_S->FCR1, flag);
1849
1850 /* Loop on flag to check, which ones have been raised */
1851 position = 0U;
1852 while ((flag >> position) != 0U)
1853 {
1854 if ((flag & (1UL << position)) != 0U)
1855 {
1856 HAL_GTZC_TZIC_Callback(GTZC2_PERIPH_REG1 | position);
1857 }
1858
1859 /* Position bit to be updated */
1860 position++;
1861 }
1862 }
1863
1864 /* Get current IT Flags and IT sources value on 2nd register of TZIC2 */
1865 ier_itsources = READ_REG(GTZC_TZIC2_S->IER2);
1866 sr_flags = READ_REG(GTZC_TZIC2_S->SR2);
1867
1868 /* Get Mask interrupt and then clear them */
1869 flag = ier_itsources & sr_flags;
1870 if (flag != 0U)
1871 {
1872 WRITE_REG(GTZC_TZIC2_S->FCR2, flag);
1873
1874 /* Loop on flag to check, which ones have been raised */
1875 position = 0U;
1876 while ((flag >> position) != 0U)
1877 {
1878 if ((flag & (1UL << position)) != 0U)
1879 {
1880 HAL_GTZC_TZIC_Callback(GTZC2_PERIPH_REG2 | position);
1881 }
1882
1883 /* Position bit to be updated */
1884 position++;
1885 }
1886 }
1887 }
1888
1889 /**
1890 * @brief GTZC TZIC sub-block interrupt callback.
1891 * @param PeriphId Peripheral identifier triggering the illegal access.
1892 * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId
1893 * @retval None.
1894 */
HAL_GTZC_TZIC_Callback(uint32_t PeriphId)1895 __weak void HAL_GTZC_TZIC_Callback(uint32_t PeriphId)
1896 {
1897 /* Prevent unused argument(s) compilation warning */
1898 UNUSED(PeriphId);
1899
1900 /* NOTE: This function should not be modified. When the callback is needed,
1901 * the HAL_GTZC_TZIC_Callback is to be implemented in the user file
1902 */
1903 }
1904
1905 /**
1906 * @}
1907 */
1908
1909 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1910
1911 /**
1912 * @}
1913 */
1914
1915 #endif /*HAL_GTZC_MODULE_ENABLED*/
1916
1917 /**
1918 * @}
1919 */
1920
1921 /**
1922 * @}
1923 */
1924
1925
