1 /**
2 ******************************************************************************
3 * @file stm32l5xx_hal_gtzc.c
4 * @author MCD Application Team
5 * @brief GTZC HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of GTZC peripheral:
8 * + TZSC Initialization and Configuration functions
9 * + TZSC-MPCWM Initialization and Configuration functions
10 * + MPCBB Initialization and Configuration functions
11 * + TZSC, TZSC-MPCWM and MPCBB Lock functions
12 * + TZIC Initialization and Configuration functions
13 *
14 @verbatim
15 ==============================================================================
16 ##### GTZC main features #####
17 ==============================================================================
18 [..]
19 (+) Global TrustZone Controller (GTZC) composed of three sub-blocks:
20 (++) TZSC: TrustZone security controller
21 This sub-block defines the secure/privileged state of master and slave
22 peripherals. It also controls the secure state of subregions
23 for the watermark memory peripheral controller (MPCWM).
24 (++) MPCBB: Block-Based memory protection controller
25 This sub-block defines the secure state of all blocks
26 (256-byte pages) of the associated SRAM.
27 (++) TZIC: TrustZone illegal access controller
28 This sub-block gathers all illegal access events in the system and
29 generates a secure interrupt towards NVIC.
30
31 (+) These sub-blocks are used to configure TrustZone system security in
32 a product having bus agents with programmable-security and privileged
33 attributes (securable) such as:
34 (++) on-chip RAM with programmable secure blocks (pages)
35 (++) AHB and APB peripherals with programmable security and/or privilege access
36 (++) AHB master granted as secure and/or privilege
37 (++) off-chip memories with secure areas
38
39 [..]
40 (+) TZIC accessible only with secure privileged transactions.
41 (+) Secure and non-secure access supported for privileged and unprivileged
42 part of TZSC and MPCBB
43
44 ==============================================================================
45 ##### How to use this driver #####
46 ==============================================================================
47 [..]
48 The GTZC HAL driver can be used as follows:
49
50 (#) Configure or get back securable peripherals attributes using
51 HAL_GTZC_TZSC_ConfigPeriphAttributes() / HAL_GTZC_TZSC_GetConfigPeriphAttributes()
52
53 (#) Configure or get back MPCWM memories attributes using
54 HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes() / HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes()
55
56 (#) Lock TZSC sub-block or get lock status using HAL_GTZC_TZSC_Lock() /
57 HAL_GTZC_TZSC_GetLock()
58
59 (#) Configure or get back MPCBB memories complete configuration using
60 HAL_GTZC_MPCBB_ConfigMem() / HAL_GTZC_MPCBB_GetConfigMem()
61
62 (#) Configure or get back MPCBB memories attributes using
63 HAL_GTZC_MPCBB_ConfigMemAttributes() / HAL_GTZC_MPCBB_GetConfigMemAttributes()
64
65 (#) Lock MPCBB configuration or get lock status using HAL_GTZC_MPCBB_Lock() /
66 HAL_GTZC_MPCBB_GetLock()
67
68 (#) Lock MPCBB super-blocks or get lock status using HAL_GTZC_MPCBB_LockConfig() /
69 HAL_GTZC_MPCBB_GetLockConfig()
70
71 (#) Illegal access detection can be configured through TZIC sub-block using
72 following functions: HAL_GTZC_TZIC_DisableIT() / HAL_GTZC_TZIC_EnableIT()
73
74 (#) Illegal access flags can be retrieved through HAL_GTZC_TZIC_GetFlag() and
75 HAL_GTZC_TZIC_ClearFlag() functions
76
77 (#) Illegal access interrupt service routines are served by HAL_GTZC_IRQHandler()
78 and user can add his own code using HAL_GTZC_TZIC_Callback()
79
80 @endverbatim
81 ******************************************************************************
82 * @attention
83 *
84 * <h2><center>© Copyright (c) 2019 STMicroelectronics.
85 * All rights reserved.</center></h2>
86 *
87 * This software component is licensed by ST under BSD 3-Clause license,
88 * the "License"; You may not use this file except in compliance with the
89 * License. You may obtain a copy of the License at:
90 * opensource.org/licenses/BSD-3-Clause
91 *
92 ******************************************************************************
93 */
94
95 /* Includes ------------------------------------------------------------------*/
96 #include "stm32l5xx_hal.h"
97
98 /** @addtogroup STM32L5xx_HAL_Driver
99 * @{
100 */
101
102 /** @defgroup GTZC GTZC
103 * @brief GTZC HAL module driver
104 * @{
105 */
106
107 #ifdef HAL_GTZC_MODULE_ENABLED
108
109 /* Private typedef -----------------------------------------------------------*/
110 /* Private constants ---------------------------------------------------------*/
111
112 /** @defgroup GTZC_Private_Constants GTZC Private Constants
113 * @{
114 */
115
116 /* Definitions for GTZC_TZSC_MPCWM */
117 #define GTZC_TZSC_MPCWM1_MEM_SIZE 0x10000000U /* 256MB max size */
118 #define GTZC_TZSC_MPCWM2_MEM_SIZE 0x10000000U /* 256MB max size */
119 #define GTZC_TZSC_MPCWM3_MEM_SIZE 0x10000000U /* 256MB max size */
120
121 /* Definitions for GTZC TZSC & TZIC ALL register values */
122 #define TZSC_SECCFGR1_ALL (0xFFFFFFFFUL)
123 #if defined (STM32L562xx)
124 #define TZSC_SECCFGR2_ALL (0x0007FFFFUL)
125 #else
126 #define TZSC_SECCFGR2_ALL (0x00076FFFUL)
127 #endif /* STM32L562xx */
128 #define TZSC_PRIVCFGR1_ALL (0xFFFFFFFFUL)
129 #if defined (STM32L562xx)
130 #define TZSC_PRIVCFGR2_ALL (0x0007FFFFUL)
131 #else
132 #define TZSC_PRIVCFGR2_ALL (0x00076FFFUL)
133 #endif /* STM32L562xx */
134 #define TZIC_IER1_ALL (0xFFFFFFFFUL)
135 #if defined (STM32L562xx)
136 #define TZIC_IER2_ALL (0x3FFFFFFFUL)
137 #else
138 #define TZIC_IER2_ALL (0x3FFF6FFFUL)
139 #endif /* STM32L562xx */
140 #define TZIC_IER3_ALL (0x000000FFUL)
141 #define TZIC_FCR1_ALL (0xFFFFFFFFUL)
142 #if defined (STM32L562xx)
143 #define TZIC_FCR2_ALL (0x3FFFFFFFUL)
144 #else
145 #define TZIC_FCR2_ALL (0x3FFF6FFFUL)
146 #endif /* STM32L562xx */
147 #define TZIC_FCR3_ALL (0x000000FFUL)
148
149 /**
150 * @}
151 */
152
153 /* Private macros ------------------------------------------------------------*/
154
155 /** @defgroup GTZC_Private_Macros GTZC Private Macros
156 * @{
157 */
158
159 #define IS_ADDRESS_IN(mem, address)\
160 ( ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_NS(mem) ) \
161 && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_NS(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) ) \
162 || ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_S(mem) ) \
163 && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_S(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) ) )
164
165 #define IS_ADDRESS_IN_S(mem, address)\
166 ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_S(mem) ) \
167 && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_S(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) )
168
169 #define IS_ADDRESS_IN_NS(mem, address)\
170 ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_NS(mem) ) \
171 && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_NS(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) )
172
173 #define GTZC_BASE_ADDRESS(mem)\
174 ( mem ## _BASE )
175
176 /**
177 * @}
178 */
179
180 /* Private variables ---------------------------------------------------------*/
181 /* Private function prototypes -----------------------------------------------*/
182 /* Exported functions --------------------------------------------------------*/
183
184 /** @defgroup GTZC_Exported_Functions GTZC Exported Functions
185 * @{
186 */
187
188 /** @defgroup GTZC_Exported_Functions_Group1 TZSC Configuration functions
189 * @brief TZSC Configuration functions
190 *
191 @verbatim
192 ==============================================================================
193 ##### TZSC Configuration functions #####
194 ==============================================================================
195 [..]
196 This section provides functions allowing to configure TZSC
197 TZSC is TrustZone Security Controller
198 @endverbatim
199 * @{
200 */
201
202 /**
203 * @brief Configure TZSC on a single peripheral or on all peripherals.
204 * @note Secure and non-secure attributes can only be set from the secure
205 * state when the system implements the security (TZEN=1).
206 * @note Privilege and non-privilege attributes can only be set from the
207 * privilege state when TZEN=0 or TZEN=1
208 * @note Security and privilege attributes can be set independently.
209 * @note Default state is non-secure and unprivileged access allowed.
210 * @param PeriphId Peripheral identifier
211 * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId.
212 * Use GTZC_PERIPH_ALL to select all peripherals.
213 * @param PeriphAttributes Peripheral attributes, see @ref GTZC_TZSC_PeriphAttributes.
214 * @retval HAL status.
215 */
HAL_GTZC_TZSC_ConfigPeriphAttributes(uint32_t PeriphId,uint32_t PeriphAttributes)216 HAL_StatusTypeDef HAL_GTZC_TZSC_ConfigPeriphAttributes(uint32_t PeriphId,
217 uint32_t PeriphAttributes)
218 {
219 uint32_t register_address;
220
221 /* check entry parameters */
222 if ((PeriphAttributes > (GTZC_TZSC_PERIPH_SEC | GTZC_TZSC_PERIPH_PRIV))
223 || (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZSC_PERIPH_NUMBER)
224 || (((PeriphId & GTZC_PERIPH_ALL) != 0U) && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U)))
225 {
226 return HAL_ERROR;
227 }
228
229 if ((PeriphId & GTZC_PERIPH_ALL) != 0U)
230 {
231 /* special case where same attributes are applied to all peripherals */
232
233 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
234 /* secure configuration */
235 if ((PeriphAttributes & GTZC_TZSC_PERIPH_SEC) == GTZC_TZSC_PERIPH_SEC)
236 {
237 SET_BIT(GTZC_TZSC->SECCFGR1, TZSC_SECCFGR1_ALL);
238 SET_BIT(GTZC_TZSC->SECCFGR2, TZSC_SECCFGR2_ALL);
239 }
240 else if ((PeriphAttributes & GTZC_TZSC_PERIPH_NSEC) == GTZC_TZSC_PERIPH_NSEC)
241 {
242 CLEAR_BIT(GTZC_TZSC->SECCFGR1, TZSC_SECCFGR1_ALL);
243 CLEAR_BIT(GTZC_TZSC->SECCFGR2, TZSC_SECCFGR2_ALL);
244 }
245 else
246 {
247 /* do nothing */
248 }
249 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
250
251 /* privilege configuration */
252 if ((PeriphAttributes & GTZC_TZSC_PERIPH_PRIV) == GTZC_TZSC_PERIPH_PRIV)
253 {
254 SET_BIT(GTZC_TZSC->PRIVCFGR1, TZSC_PRIVCFGR1_ALL);
255 SET_BIT(GTZC_TZSC->PRIVCFGR2, TZSC_PRIVCFGR2_ALL);
256 }
257 else if ((PeriphAttributes & GTZC_TZSC_PERIPH_NPRIV) == GTZC_TZSC_PERIPH_NPRIV)
258 {
259 CLEAR_BIT(GTZC_TZSC->PRIVCFGR1, TZSC_PRIVCFGR1_ALL);
260 CLEAR_BIT(GTZC_TZSC->PRIVCFGR2, TZSC_PRIVCFGR2_ALL);
261 }
262 else
263 {
264 /* do nothing */
265 }
266 }
267 else
268 {
269 /* common case where only one peripheral is configured */
270
271 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
272 /* secure configuration */
273 register_address = (uint32_t) &(GTZC_TZSC->SECCFGR1) + (4U * GTZC_GET_REG_INDEX(PeriphId));
274 if ((PeriphAttributes & GTZC_TZSC_PERIPH_SEC) == GTZC_TZSC_PERIPH_SEC)
275 {
276 SET_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
277 }
278 else if ((PeriphAttributes & GTZC_TZSC_PERIPH_NSEC) == GTZC_TZSC_PERIPH_NSEC)
279 {
280 CLEAR_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
281 }
282 else
283 {
284 /* do nothing */
285 }
286 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
287
288 /* privilege configuration */
289 register_address = (uint32_t) &(GTZC_TZSC->PRIVCFGR1) + (4U * GTZC_GET_REG_INDEX(PeriphId));
290 if ((PeriphAttributes & GTZC_TZSC_PERIPH_PRIV) == GTZC_TZSC_PERIPH_PRIV)
291 {
292 SET_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
293 }
294 else if ((PeriphAttributes & GTZC_TZSC_PERIPH_NPRIV) == GTZC_TZSC_PERIPH_NPRIV)
295 {
296 CLEAR_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
297 }
298 else
299 {
300 /* do nothing */
301 }
302 }
303 return HAL_OK;
304 }
305
306 /**
307 * @brief Get TZSC configuration on a single peripheral or on all peripherals.
308 * @param PeriphId Peripheral identifier.
309 * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId.
310 * Use GTZC_PERIPH_ALL to select all peripherals.
311 * @param PeriphAttributes Peripheral attribute pointer.
312 * This parameter can be a value of @ref GTZC_TZSC_PeriphAttributes.
313 * If PeriphId target a single peripheral, pointer on a single element.
314 * If all peripherals selected (GTZC_PERIPH_ALL), pointer to an array of
315 * GTZC_TZSC_PERIPH_NUMBER elements is to be provided.
316 * @retval HAL status.
317 */
HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId,uint32_t * PeriphAttributes)318 HAL_StatusTypeDef HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId,
319 uint32_t *PeriphAttributes)
320 {
321 uint32_t i;
322 uint32_t reg_value;
323 uint32_t register_address;
324
325 /* check entry parameters */
326 if ((PeriphAttributes == NULL)
327 || (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZSC_PERIPH_NUMBER)
328 || (((PeriphId & GTZC_PERIPH_ALL) != 0U) && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U)))
329 {
330 return HAL_ERROR;
331 }
332
333 if ((PeriphId & GTZC_PERIPH_ALL) != 0U)
334 {
335 /* get secure configuration: read each register and deploy each bit value
336 * of corresponding index in the destination array
337 */
338 reg_value = READ_REG(GTZC_TZSC->SECCFGR1);
339 for (i = 0U; i < 32U; i++)
340 {
341 if (((reg_value & (1UL << i)) >> i) != 0U)
342 {
343 PeriphAttributes[i] = GTZC_TZSC_PERIPH_SEC;
344 }
345 else
346 {
347 PeriphAttributes[i] = GTZC_TZSC_PERIPH_NSEC;
348 }
349 }
350
351 reg_value = READ_REG(GTZC_TZSC->SECCFGR2);
352 for (/*i = 32U*/; i < GTZC_TZSC_PERIPH_NUMBER; i++)
353 {
354 if (((reg_value & (1UL << (i - 32U))) >> (i - 32U)) != 0U)
355 {
356 PeriphAttributes[i] = GTZC_TZSC_PERIPH_SEC;
357 }
358 else
359 {
360 PeriphAttributes[i] = GTZC_TZSC_PERIPH_NSEC;
361 }
362 }
363
364 /* get privilege configuration: read each register and deploy each bit value
365 * of corresponding index in the destination array
366 */
367 reg_value = READ_REG(GTZC_TZSC->PRIVCFGR1);
368 for (i = 0U; i < 32U; i++)
369 {
370 if (((reg_value & (1UL << i)) >> i) != 0U)
371 {
372 PeriphAttributes[i] |= GTZC_TZSC_PERIPH_PRIV;
373 }
374 else
375 {
376 PeriphAttributes[i] |= GTZC_TZSC_PERIPH_NPRIV;
377 }
378 }
379
380 reg_value = READ_REG(GTZC_TZSC->PRIVCFGR2);
381 for (/*i = 32U*/; i < GTZC_TZSC_PERIPH_NUMBER; i++)
382 {
383 if (((reg_value & (1UL << (i - 32U))) >> (i - 32U)) != 0U)
384 {
385 PeriphAttributes[i] |= GTZC_TZSC_PERIPH_PRIV;
386 }
387 else
388 {
389 PeriphAttributes[i] |= GTZC_TZSC_PERIPH_NPRIV;
390 }
391 }
392
393 }
394 else
395 {
396 /* common case where only one peripheral is configured */
397
398 /* secure configuration */
399 register_address = (uint32_t) &(GTZC_TZSC->SECCFGR1) + (4U * GTZC_GET_REG_INDEX(PeriphId));
400
401 if (((READ_BIT(*(__IO uint32_t *)register_address,
402 1UL << GTZC_GET_PERIPH_POS(PeriphId))) >> GTZC_GET_PERIPH_POS(PeriphId))
403 != 0U)
404 {
405 *PeriphAttributes = GTZC_TZSC_PERIPH_SEC;
406 }
407 else
408 {
409 *PeriphAttributes = GTZC_TZSC_PERIPH_NSEC;
410 }
411
412 /* privilege configuration */
413 register_address = (uint32_t) &(GTZC_TZSC->PRIVCFGR1) + (4U * GTZC_GET_REG_INDEX(PeriphId));
414
415 if (((READ_BIT(*(__IO uint32_t *)register_address,
416 1UL << GTZC_GET_PERIPH_POS(PeriphId))) >> GTZC_GET_PERIPH_POS(PeriphId))
417 != 0U)
418 {
419 *PeriphAttributes |= GTZC_TZSC_PERIPH_PRIV;
420 }
421 else
422 {
423 *PeriphAttributes |= GTZC_TZSC_PERIPH_NPRIV;
424 }
425 }
426 return HAL_OK;
427 }
428
429 /**
430 * @}
431 */
432
433 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
434
435 /** @defgroup GTZC_Exported_Functions_Group2 MPCWM Configuration functions
436 * @brief MPCWM Configuration functions
437 *
438 @verbatim
439 ==============================================================================
440 ##### MPCWM Configuration functions #####
441 ==============================================================================
442 [..]
443 This section provides functions allowing to configure MPCWM
444 MPCWM is Memory Protection Controller WaterMark
445 @endverbatim
446 * @{
447 */
448
449 /**
450 * @brief Configure a TZSC-MPCWM area.
451 * @param MemBaseAddress WM identifier.
452 * @param pMPCWM_Desc TZSC-MPCWM descriptor pointer.
453 * The structure description is available in @ref GTZC_Exported_Types.
454 * @retval HAL status.
455 */
HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes(uint32_t MemBaseAddress,MPCWM_ConfigTypeDef * pMPCWM_Desc)456 HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes(uint32_t MemBaseAddress,
457 MPCWM_ConfigTypeDef *pMPCWM_Desc)
458 {
459 uint32_t register_address;
460 uint32_t reg_value;
461 uint32_t size;
462 uint32_t start_pos, start_msk;
463 uint32_t length_pos, length_msk;
464
465 /* check entry parameters */
466 if ((pMPCWM_Desc->AreaId > GTZC_TZSC_MPCWM_ID2)
467 || ((MemBaseAddress == FMC_BANK3) && (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID2))
468 || ((pMPCWM_Desc->Offset % GTZC_TZSC_MPCWM_GRANULARITY) != 0U)
469 || ((pMPCWM_Desc->Length % GTZC_TZSC_MPCWM_GRANULARITY) != 0U))
470 {
471 return HAL_ERROR;
472 }
473
474 /* check descriptor content vs. memory capacity */
475 switch (MemBaseAddress)
476 {
477 case OCTOSPI1_BASE:
478 size = GTZC_TZSC_MPCWM1_MEM_SIZE;
479 if (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1)
480 {
481 register_address = (uint32_t) &(GTZC_TZSC_S->MPCWM1_NSWMR1);
482 start_pos = GTZC_TZSC_MPCWM1_NSWMR1_NSWM1STRT_Pos;
483 start_msk = GTZC_TZSC_MPCWM1_NSWMR1_NSWM1STRT_Msk;
484 length_pos = GTZC_TZSC_MPCWM1_NSWMR1_NSWM1LGTH_Pos;
485 length_msk = GTZC_TZSC_MPCWM1_NSWMR1_NSWM1LGTH_Msk;
486 }
487 else
488 {
489 /* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID2
490 * (Parameter already checked)
491 */
492 register_address = (uint32_t) &(GTZC_TZSC_S->MPCWM1_NSWMR2);
493 start_pos = GTZC_TZSC_MPCWM1_NSWMR2_NSWM2STRT_Pos;
494 start_msk = GTZC_TZSC_MPCWM1_NSWMR2_NSWM2STRT_Msk;
495 length_pos = GTZC_TZSC_MPCWM1_NSWMR2_NSWM2LGTH_Pos;
496 length_msk = GTZC_TZSC_MPCWM1_NSWMR2_NSWM2LGTH_Msk;
497 }
498 break;
499 case FMC_BANK1:
500 size = GTZC_TZSC_MPCWM1_MEM_SIZE;
501 if (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1)
502 {
503 register_address = (uint32_t) &(GTZC_TZSC_S->MPCWM2_NSWMR1);
504 start_pos = GTZC_TZSC_MPCWM2_NSWMR1_NSWM1STRT_Pos;
505 start_msk = GTZC_TZSC_MPCWM2_NSWMR1_NSWM1STRT_Msk;
506 length_pos = GTZC_TZSC_MPCWM2_NSWMR1_NSWM1LGTH_Pos;
507 length_msk = GTZC_TZSC_MPCWM2_NSWMR1_NSWM1LGTH_Msk;
508 }
509 else
510 {
511 /* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID2
512 * (Parameter already checked)
513 */
514 register_address = (uint32_t) &(GTZC_TZSC_S->MPCWM2_NSWMR2);
515 start_pos = GTZC_TZSC_MPCWM2_NSWMR2_NSWM2STRT_Pos;
516 start_msk = GTZC_TZSC_MPCWM2_NSWMR2_NSWM2STRT_Msk;
517 length_pos = GTZC_TZSC_MPCWM2_NSWMR2_NSWM2LGTH_Pos;
518 length_msk = GTZC_TZSC_MPCWM2_NSWMR2_NSWM2LGTH_Msk;
519 }
520 break;
521 case FMC_BANK3:
522 /* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1
523 * (Parameter already checked)
524 */
525 size = GTZC_TZSC_MPCWM3_MEM_SIZE;
526 register_address = (uint32_t) &(GTZC_TZSC_S->MPCWM3_NSWMR1);
527 start_pos = GTZC_TZSC_MPCWM3_NSWMR1_NSWM1STRT_Pos;
528 start_msk = GTZC_TZSC_MPCWM3_NSWMR1_NSWM1STRT_Msk;
529 length_pos = GTZC_TZSC_MPCWM3_NSWMR1_NSWM1LGTH_Pos;
530 length_msk = GTZC_TZSC_MPCWM3_NSWMR1_NSWM1LGTH_Msk;
531 break;
532 default:
533 return HAL_ERROR;
534 break;
535 }
536
537 if ((pMPCWM_Desc->Offset > size)
538 || ((pMPCWM_Desc->Offset + pMPCWM_Desc->Length) > size))
539 {
540 return HAL_ERROR;
541 }
542
543 /* write descriptor value */
544 reg_value = ((pMPCWM_Desc->Offset / GTZC_TZSC_MPCWM_GRANULARITY) << start_pos) & start_msk;
545 reg_value |= ((pMPCWM_Desc->Length / GTZC_TZSC_MPCWM_GRANULARITY) << length_pos) & length_msk;
546 MODIFY_REG(*(__IO uint32_t *)register_address, start_msk | length_msk, reg_value);
547
548 return HAL_OK;
549 }
550
551 /**
552 * @brief Get a TZSC-MPCWM area configuration.
553 * @param MemBaseAddress WM identifier.
554 * @param pMPCWM_Desc pointer to a TZSC-MPCWM descriptor.
555 * The structure description is available in @ref GTZC_Exported_Types.
556 * @retval HAL status.
557 */
HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes(uint32_t MemBaseAddress,MPCWM_ConfigTypeDef * pMPCWM_Desc)558 HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes(uint32_t MemBaseAddress,
559 MPCWM_ConfigTypeDef *pMPCWM_Desc)
560 {
561 uint32_t register_address;
562 uint32_t reg_value;
563 uint32_t start_pos, start_msk;
564 uint32_t length_pos, length_msk;
565
566 /* firstly take care of the first area, present on all MPCWM sub-blocks */
567 switch (MemBaseAddress)
568 {
569 case OCTOSPI1_BASE:
570 register_address = (uint32_t) &(GTZC_TZSC_S->MPCWM1_NSWMR1);
571 start_pos = GTZC_TZSC_MPCWM1_NSWMR1_NSWM1STRT_Pos;
572 start_msk = GTZC_TZSC_MPCWM1_NSWMR1_NSWM1STRT_Msk;
573 length_pos = GTZC_TZSC_MPCWM1_NSWMR1_NSWM1LGTH_Pos;
574 length_msk = GTZC_TZSC_MPCWM1_NSWMR1_NSWM1LGTH_Msk;
575 break;
576 case FMC_BANK1:
577 register_address = (uint32_t) &(GTZC_TZSC_S->MPCWM2_NSWMR1);
578 start_pos = GTZC_TZSC_MPCWM2_NSWMR1_NSWM1STRT_Pos;
579 start_msk = GTZC_TZSC_MPCWM2_NSWMR1_NSWM1STRT_Msk;
580 length_pos = GTZC_TZSC_MPCWM2_NSWMR1_NSWM1LGTH_Pos;
581 length_msk = GTZC_TZSC_MPCWM2_NSWMR1_NSWM1LGTH_Msk;
582 break;
583 case FMC_BANK3:
584 register_address = (uint32_t) &(GTZC_TZSC_S->MPCWM3_NSWMR1);
585 start_pos = GTZC_TZSC_MPCWM3_NSWMR1_NSWM1STRT_Pos;
586 start_msk = GTZC_TZSC_MPCWM3_NSWMR1_NSWM1STRT_Msk;
587 length_pos = GTZC_TZSC_MPCWM3_NSWMR1_NSWM1LGTH_Pos;
588 length_msk = GTZC_TZSC_MPCWM3_NSWMR1_NSWM1LGTH_Msk;
589 break;
590 default:
591 return HAL_ERROR;
592 break;
593 }
594
595 /* read register and update the descriptor for first area*/
596 reg_value = READ_REG(*(__IO uint32_t *)register_address);
597 pMPCWM_Desc[0].AreaId = GTZC_TZSC_MPCWM_ID1;
598 pMPCWM_Desc[0].Offset = ((reg_value & start_msk) >> start_pos) * GTZC_TZSC_MPCWM_GRANULARITY;
599 pMPCWM_Desc[0].Length = ((reg_value & length_msk) >> length_pos) * GTZC_TZSC_MPCWM_GRANULARITY;
600
601 if (MemBaseAddress != FMC_BANK3)
602 {
603 /* Here MemBaseAddress = OCTOSPI1_BASE
604 * or FMC_BANK1 (already tested)
605 * Now take care of the second area, present on these sub-blocks
606 */
607 switch (MemBaseAddress)
608 {
609 case OCTOSPI1_BASE:
610 register_address = (uint32_t) &(GTZC_TZSC_S->MPCWM1_NSWMR2);
611 start_pos = GTZC_TZSC_MPCWM1_NSWMR2_NSWM2STRT_Pos;
612 start_msk = GTZC_TZSC_MPCWM1_NSWMR2_NSWM2STRT_Msk;
613 length_pos = GTZC_TZSC_MPCWM1_NSWMR2_NSWM2LGTH_Pos;
614 length_msk = GTZC_TZSC_MPCWM1_NSWMR2_NSWM2LGTH_Msk;
615 break;
616 case FMC_BANK1:
617 register_address = (uint32_t) &(GTZC_TZSC_S->MPCWM2_NSWMR2);
618 start_pos = GTZC_TZSC_MPCWM2_NSWMR2_NSWM2STRT_Pos;
619 start_msk = GTZC_TZSC_MPCWM2_NSWMR2_NSWM2STRT_Msk;
620 length_pos = GTZC_TZSC_MPCWM2_NSWMR2_NSWM2LGTH_Pos;
621 length_msk = GTZC_TZSC_MPCWM2_NSWMR2_NSWM2LGTH_Msk;
622 break;
623 default:
624 return HAL_ERROR;
625 break;
626 }
627
628 /* read register and update the descriptor for second area*/
629 reg_value = READ_REG(*(__IO uint32_t *)register_address);
630 pMPCWM_Desc[1].AreaId = GTZC_TZSC_MPCWM_ID2;
631 pMPCWM_Desc[1].Offset = ((reg_value & start_msk) >> start_pos) * GTZC_TZSC_MPCWM_GRANULARITY;
632 pMPCWM_Desc[1].Length = ((reg_value & length_msk) >> length_pos) * GTZC_TZSC_MPCWM_GRANULARITY;
633 }
634
635 return HAL_OK;
636 }
637
638 /**
639 * @}
640 */
641
642 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
643
644 /** @defgroup GTZC_Exported_Functions_Group3 TZSC and TZSC-MPCWM Lock functions
645 * @brief TZSC and TZSC-MPCWM Lock functions
646 *
647 @verbatim
648 ==============================================================================
649 ##### TZSC and TZSC-MPCWM Lock functions #####
650 ==============================================================================
651 [..]
652 This section provides functions allowing to manage the common TZSC and
653 TZSC-MPCWM lock. It includes lock enable, and current value read.
654 TZSC is TrustZone Security Controller
655 MPCWM is Memory Protection Controller WaterMark
656 @endverbatim
657 * @{
658 */
659
660 /**
661 * @brief Lock TZSC and TZSC-MPCWM configuration.
662 * @param TZSC_Instance TZSC sub-block instance.
663 */
664 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
665
HAL_GTZC_TZSC_Lock(GTZC_TZSC_TypeDef * TZSC_Instance)666 void HAL_GTZC_TZSC_Lock(GTZC_TZSC_TypeDef *TZSC_Instance)
667 {
668 SET_BIT(TZSC_Instance->CR, GTZC_TZSC_CR_LCK_Msk);
669 }
670
671 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
672
673 /**
674 * @brief Get TZSC and TZSC-MPCWM configuration lock state.
675 * @param TZSC_Instance TZSC sub-block instance.
676 * @retval Lock State (GTZC_TZSC_LOCK_OFF or GTZC_TZSC_LOCK_ON)
677 */
HAL_GTZC_TZSC_GetLock(GTZC_TZSC_TypeDef * TZSC_Instance)678 uint32_t HAL_GTZC_TZSC_GetLock(GTZC_TZSC_TypeDef *TZSC_Instance)
679 {
680 return READ_BIT(TZSC_Instance->CR, GTZC_TZSC_CR_LCK_Msk);
681 }
682
683 /**
684 * @}
685 */
686
687 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
688
689 /** @defgroup GTZC_Exported_Functions_Group4 MPCBB Configuration functions
690 * @brief MPCBB Configuration functions
691 *
692 @verbatim
693 ==============================================================================
694 ##### MPCBB Configuration functions #####
695 ==============================================================================
696 [..]
697 This section provides functions allowing to configure MPCBB
698 MPCBB is Memory Protection Controller Block Base
699 @endverbatim
700 * @{
701 */
702
703 /**
704 * @brief Set a complete MPCBB configuration on the SRAM passed as parameter.
705 * @param MemBaseAddress MPCBB identifier.
706 * @param pMPCBB_desc pointer to MPCBB descriptor.
707 * The structure description is available in @ref GTZC_Exported_Types.
708 * @retval HAL status.
709 */
HAL_GTZC_MPCBB_ConfigMem(uint32_t MemBaseAddress,MPCBB_ConfigTypeDef * pMPCBB_desc)710 HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMem(uint32_t MemBaseAddress,
711 MPCBB_ConfigTypeDef *pMPCBB_desc)
712 {
713 GTZC_MPCBB_TypeDef *mpcbb_ptr;
714 uint32_t reg_value;
715 uint32_t mem_size;
716 uint32_t size_mask;
717 uint32_t size_in_superblocks;
718 uint32_t i;
719
720 /* check entry parameters */
721 if ((!(IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
722 && !(IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress)))
723 || ((pMPCBB_desc->SecureRWIllegalMode != GTZC_MPCBB_SRWILADIS_ENABLE)
724 && (pMPCBB_desc->SecureRWIllegalMode != GTZC_MPCBB_SRWILADIS_DISABLE))
725 || ((pMPCBB_desc->InvertSecureState != GTZC_MPCBB_INVSECSTATE_NOT_INVERTED)
726 && (pMPCBB_desc->InvertSecureState != GTZC_MPCBB_INVSECSTATE_INVERTED)))
727 {
728 return HAL_ERROR;
729 }
730
731 /* write InvertSecureState and SecureRWIllegalMode properties */
732 /* assume their Position/Mask is identical for all sub-blocks */
733 reg_value = pMPCBB_desc->InvertSecureState;
734 reg_value |= pMPCBB_desc->SecureRWIllegalMode;
735 if (IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
736 {
737 mpcbb_ptr = GTZC_MPCBB1_S;
738 mem_size = GTZC_MEM_SIZE(SRAM1);
739 }
740 else
741 {
742 /* Here MemBaseAddress is inside SRAM2 (already tested) */
743 mpcbb_ptr = GTZC_MPCBB2_S;
744 mem_size = GTZC_MEM_SIZE(SRAM2);
745 }
746
747 /* write configuration and lock register information */
748 MODIFY_REG(mpcbb_ptr->CR,
749 GTZC_MPCBB_CR_INVSECSTATE_Msk | GTZC_MPCBB_CR_SRWILADIS_Msk, reg_value);
750 size_mask = (1UL << (mem_size / GTZC_MPCBB_SUPERBLOCK_SIZE)) - 1U;
751 /* limitation: code not portable with memory > 256K */
752 MODIFY_REG(mpcbb_ptr->LCKVTR1, size_mask, pMPCBB_desc->AttributeConfig.MPCBB_LockConfig_array[0]);
753
754 /* write vector register information */
755 size_in_superblocks = (mem_size / GTZC_MPCBB_SUPERBLOCK_SIZE);
756 for (i = 0U; i < size_in_superblocks; i++)
757 {
758 WRITE_REG(mpcbb_ptr->VCTR[i],
759 pMPCBB_desc->AttributeConfig.MPCBB_SecConfig_array[i]);
760 }
761
762 return HAL_OK;
763 }
764
765 /**
766 * @brief Get a complete MPCBB configuration on the SRAM passed as parameter.
767 * @param MemBaseAddress MPCBB identifier.
768 * @param pMPCBB_desc pointer to a MPCBB descriptor.
769 * The structure description is available in @ref GTZC_Exported_Types.
770 * @retval HAL status.
771 */
HAL_GTZC_MPCBB_GetConfigMem(uint32_t MemBaseAddress,MPCBB_ConfigTypeDef * pMPCBB_desc)772 HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMem(uint32_t MemBaseAddress,
773 MPCBB_ConfigTypeDef *pMPCBB_desc)
774 {
775 GTZC_MPCBB_TypeDef *mpcbb_ptr;
776 uint32_t reg_value;
777 uint32_t mem_size;
778 uint32_t size_mask;
779 uint32_t size_in_superblocks;
780 uint32_t i;
781
782 /* check entry parameters */
783 if (!(IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
784 && !(IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress)))
785 {
786 return HAL_ERROR;
787 }
788
789 /* read InvertSecureState and SecureRWIllegalMode properties */
790 /* assume their Position/Mask is identical for all sub-blocks */
791 if (IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
792 {
793 mpcbb_ptr = GTZC_MPCBB1_S;
794 mem_size = GTZC_MEM_SIZE(SRAM1);
795 }
796 else
797 {
798 mpcbb_ptr = GTZC_MPCBB2_S;
799 mem_size = GTZC_MEM_SIZE(SRAM2);
800 }
801
802 /* read configuration and lock register information */
803 reg_value = READ_REG(mpcbb_ptr->CR);
804 pMPCBB_desc->InvertSecureState = (reg_value & GTZC_MPCBB_CR_INVSECSTATE_Msk);
805 pMPCBB_desc->SecureRWIllegalMode = (reg_value & GTZC_MPCBB_CR_SRWILADIS_Msk);
806 size_mask = (1UL << (mem_size / GTZC_MPCBB_SUPERBLOCK_SIZE)) - 1U;
807 /* limitation: code not portable with memory > 256K */
808 pMPCBB_desc->AttributeConfig.MPCBB_LockConfig_array[0] = READ_REG(mpcbb_ptr->LCKVTR1)& size_mask;
809
810 /* read vector register information */
811 size_in_superblocks = (mem_size / GTZC_MPCBB_SUPERBLOCK_SIZE);
812 for (i = 0U; i < size_in_superblocks; i++)
813 {
814 pMPCBB_desc->AttributeConfig.MPCBB_SecConfig_array[i] = mpcbb_ptr->VCTR[i];
815 }
816
817 return HAL_OK;
818 }
819
820 /**
821 * @brief Set a MPCBB attribute configuration on the SRAM passed as parameter
822 * for a number of blocks.
823 * @param MemAddress MPCBB identifier, and start block to configure
824 * (must be 256 Bytes aligned).
825 * @param NbBlocks Number of blocks to configure.
826 * @param pMemAttributes pointer to an array (containing "NbBlocks" elements),
827 * with each element must be GTZC_MCPBB_BLOCK_NSEC or GTZC_MCPBB_BLOCK_SEC.
828 * @retval HAL status.
829 */
HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress,uint32_t NbBlocks,uint32_t * pMemAttributes)830 HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress,
831 uint32_t NbBlocks,
832 uint32_t *pMemAttributes)
833 {
834 GTZC_MPCBB_TypeDef *mpcbb_ptr;
835 uint32_t base_address, end_address;
836 uint32_t block_start, offset_reg_start, offset_bit_start;
837 uint32_t i;
838
839 /* firstly check that MemAddress is well 256 Bytes aligned */
840 if ((MemAddress % GTZC_MPCBB_BLOCK_SIZE) != 0U)
841 {
842 return HAL_ERROR;
843 }
844
845 /* check entry parameters and deduce physical base address */
846 end_address = MemAddress + (NbBlocks * GTZC_MPCBB_BLOCK_SIZE) - 1U;
847 if (((IS_ADDRESS_IN_NS(SRAM1, MemAddress))
848 && (IS_ADDRESS_IN_NS(SRAM1, end_address))) != 0U)
849 {
850 mpcbb_ptr = GTZC_MPCBB1_S;
851 base_address = SRAM1_BASE_NS;
852 }
853 else if (((IS_ADDRESS_IN_S(SRAM1, MemAddress))
854 && (IS_ADDRESS_IN_S(SRAM1, end_address))) != 0U)
855 {
856 mpcbb_ptr = GTZC_MPCBB1_S;
857 base_address = SRAM1_BASE_S;
858 }
859 else if (((IS_ADDRESS_IN_NS(SRAM2, MemAddress))
860 && (IS_ADDRESS_IN_NS(SRAM2, end_address))) != 0U)
861 {
862 mpcbb_ptr = GTZC_MPCBB2_S;
863 base_address = SRAM2_BASE_NS;
864 }
865 else if (((IS_ADDRESS_IN_S(SRAM2, MemAddress))
866 && (IS_ADDRESS_IN_S(SRAM2, end_address))) != 0U)
867 {
868 mpcbb_ptr = GTZC_MPCBB2_S;
869 base_address = SRAM2_BASE_S;
870 }
871 else
872 {
873 return HAL_ERROR;
874 }
875
876 /* get start coordinates of the configuration */
877 block_start = (MemAddress - base_address) / GTZC_MPCBB_BLOCK_SIZE;
878 offset_reg_start = block_start / 32U;
879 offset_bit_start = block_start % 32U;
880
881 for (i = 0U; i < NbBlocks; i++)
882 {
883 if (pMemAttributes[i] == GTZC_MCPBB_BLOCK_SEC)
884 {
885 SET_BIT(mpcbb_ptr->VCTR[offset_reg_start],
886 1UL << (offset_bit_start % 32U));
887 }
888 else if (pMemAttributes[i] == GTZC_MCPBB_BLOCK_NSEC)
889 {
890 CLEAR_BIT(mpcbb_ptr->VCTR[offset_reg_start],
891 1UL << (offset_bit_start % 32U));
892 }
893 else
894 {
895 break;
896 }
897
898 offset_bit_start++;
899 if (offset_bit_start == 32U)
900 {
901 offset_bit_start = 0U;
902 offset_reg_start++;
903 }
904 }
905
906 /* an unexpected value in pMemAttributes array leads to error status */
907 if (i != NbBlocks)
908 {
909 return HAL_ERROR;
910 }
911
912 return HAL_OK;
913 }
914
915 /**
916 * @brief Get a MPCBB attribute configuration on the SRAM passed as parameter
917 * for a number of blocks.
918 * @param MemAddress MPCBB identifier, and start block to get configuration
919 * (must be 256 Bytes aligned).
920 * @param NbBlocks Number of blocks to get configuration.
921 * @param pMemAttributes pointer to an array (containing "NbBlocks" elements),
922 * with each element will be GTZC_MCPBB_BLOCK_NSEC or GTZC_MCPBB_BLOCK_SEC.
923 * @retval HAL status.
924 */
HAL_GTZC_MPCBB_GetConfigMemAttributes(uint32_t MemAddress,uint32_t NbBlocks,uint32_t * pMemAttributes)925 HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMemAttributes(uint32_t MemAddress,
926 uint32_t NbBlocks,
927 uint32_t *pMemAttributes)
928 {
929 GTZC_MPCBB_TypeDef *mpcbb_ptr;
930 uint32_t base_address, end_address;
931 uint32_t block_start, offset_reg_start, offset_bit_start;
932 uint32_t i;
933
934 /* firstly check that MemAddress is well 256 Bytes aligned */
935 if ((MemAddress % GTZC_MPCBB_BLOCK_SIZE) != 0U)
936 {
937 return HAL_ERROR;
938 }
939
940 /* check entry parameters and deduce physical base address */
941 end_address = MemAddress + (NbBlocks * GTZC_MPCBB_BLOCK_SIZE) - 1U;
942 if ((IS_ADDRESS_IN_NS(SRAM1, MemAddress))
943 && (IS_ADDRESS_IN_NS(SRAM1, end_address)))
944 {
945 mpcbb_ptr = GTZC_MPCBB1_S;
946 base_address = SRAM1_BASE_NS;
947 }
948 else if ((IS_ADDRESS_IN_S(SRAM1, MemAddress))
949 && (IS_ADDRESS_IN_S(SRAM1, end_address)))
950 {
951 mpcbb_ptr = GTZC_MPCBB1_S;
952 base_address = SRAM1_BASE_S;
953 }
954 else if ((IS_ADDRESS_IN_NS(SRAM2, MemAddress))
955 && (IS_ADDRESS_IN_NS(SRAM2, end_address)))
956 {
957 mpcbb_ptr = GTZC_MPCBB2_S;
958 base_address = SRAM2_BASE_NS;
959 }
960 else if ((IS_ADDRESS_IN_S(SRAM2, MemAddress))
961 && (IS_ADDRESS_IN_S(SRAM2, end_address)))
962 {
963 mpcbb_ptr = GTZC_MPCBB2_S;
964 base_address = SRAM2_BASE_S;
965 }
966 else
967 {
968 return HAL_ERROR;
969 }
970
971 /* get start coordinates of the configuration */
972 block_start = (MemAddress - base_address) / GTZC_MPCBB_BLOCK_SIZE;
973 offset_reg_start = block_start / 32U;
974 offset_bit_start = block_start % 32U;
975
976 for (i = 0U; i < NbBlocks; i++)
977 {
978 pMemAttributes[i] = READ_BIT(mpcbb_ptr->VCTR[offset_reg_start],
979 1UL << (offset_bit_start % 32U))
980 >> (offset_bit_start % 32U);
981
982 offset_bit_start++;
983 if (offset_bit_start == 32U)
984 {
985 offset_bit_start = 0U;
986 offset_reg_start++;
987 }
988 }
989
990 return HAL_OK;
991 }
992
993 /**
994 * @brief Lock MPCBB super-blocks on the SRAM passed as parameter.
995 * @param MemAddress MPCBB identifier, and start super-block to configure
996 * (must be 8KBytes aligned).
997 * @param NbSuperBlocks Number of super-blocks to configure.
998 * @param pLockAttributes pointer to an array (containing "NbSuperBlocks" elements),
999 * with for each element:
1000 * value 0 super-block is unlocked, value 1 super-block is locked
1001 * (corresponds to GTZC_MCPBB_SUPERBLOCK_UNLOCKED and
1002 * GTZC_MCPBB_SUPERBLOCK_LOCKED values).
1003 * @retval HAL status.
1004 */
HAL_GTZC_MPCBB_LockConfig(uint32_t MemAddress,uint32_t NbSuperBlocks,uint32_t * pLockAttributes)1005 HAL_StatusTypeDef HAL_GTZC_MPCBB_LockConfig(uint32_t MemAddress,
1006 uint32_t NbSuperBlocks,
1007 uint32_t *pLockAttributes)
1008 {
1009 __IO uint32_t *reg_mpcbb;
1010 uint32_t base_address;
1011 uint32_t superblock_start, offset_bit_start;
1012 uint32_t i;
1013
1014 /* firstly check that MemAddress is well 8KBytes aligned */
1015 if ((MemAddress % GTZC_MPCBB_SUPERBLOCK_SIZE) != 0U)
1016 {
1017 return HAL_ERROR;
1018 }
1019
1020 /* check entry parameters */
1021 if ((IS_ADDRESS_IN(SRAM1, MemAddress))
1022 && (IS_ADDRESS_IN(SRAM1, (MemAddress
1023 + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE)
1024 - 1U))))
1025 {
1026 base_address = GTZC_BASE_ADDRESS(SRAM1);
1027 /* limitation: code not portable with memory > 256K */
1028 reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB1_S->LCKVTR1;
1029 }
1030 else if ((IS_ADDRESS_IN(SRAM2, MemAddress))
1031 && (IS_ADDRESS_IN(SRAM2, (MemAddress
1032 + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE)
1033 - 1U))))
1034 {
1035 base_address = GTZC_BASE_ADDRESS(SRAM2);
1036 /* limitation: code not portable with memory > 256K */
1037 reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB2_S->LCKVTR1;
1038 }
1039 else
1040 {
1041 return HAL_ERROR;
1042 }
1043
1044 /* get start coordinates of the configuration */
1045 superblock_start = (MemAddress - base_address) / GTZC_MPCBB_SUPERBLOCK_SIZE;
1046 offset_bit_start = superblock_start % 32U;
1047
1048 for (i = 0U; i < NbSuperBlocks; i++)
1049 {
1050 if (pLockAttributes[i] == GTZC_MCPBB_SUPERBLOCK_LOCKED)
1051 {
1052 SET_BIT(*reg_mpcbb, 1UL << (offset_bit_start % 32U));
1053 }
1054 else if (pLockAttributes[i] == GTZC_MCPBB_SUPERBLOCK_UNLOCKED)
1055 {
1056 CLEAR_BIT(*reg_mpcbb, 1UL << (offset_bit_start % 32U));
1057 }
1058 else
1059 {
1060 break;
1061 }
1062
1063 offset_bit_start++;
1064 }
1065
1066 /* an unexpected value in pLockAttributes array leads to an error status */
1067 if (i != NbSuperBlocks)
1068 {
1069 return HAL_ERROR;
1070 }
1071
1072 return HAL_OK;
1073 }
1074
1075 /**
1076 * @brief Get MPCBB super-blocks lock configuration on the SRAM passed as parameter.
1077 * @param MemAddress MPCBB identifier, and start super-block to get
1078 * configuration (must be 8KBytes aligned).
1079 * @param NbSuperBlocks Number of super-blocks to get configuration.
1080 * @param pLockAttributes pointer to an array (size is NbSuperBlocks),
1081 * with for each element:
1082 * value 0 super-block is unlocked, value 1 super-block is locked
1083 * (corresponds to GTZC_MCPBB_SUPERBLOCK_UNLOCKED and
1084 * GTZC_MCPBB_SUPERBLOCK_LOCKED values).
1085 * @retval HAL status.
1086 */
HAL_GTZC_MPCBB_GetLockConfig(uint32_t MemAddress,uint32_t NbSuperBlocks,uint32_t * pLockAttributes)1087 HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLockConfig(uint32_t MemAddress,
1088 uint32_t NbSuperBlocks,
1089 uint32_t *pLockAttributes)
1090 {
1091 uint32_t reg_mpcbb;
1092 uint32_t base_address;
1093 uint32_t superblock_start, offset_bit_start;
1094 uint32_t i;
1095
1096 /* firstly check that MemAddress is well 8KBytes aligned */
1097 if ((MemAddress % GTZC_MPCBB_SUPERBLOCK_SIZE) != 0U)
1098 {
1099 return HAL_ERROR;
1100 }
1101
1102 /* check entry parameters */
1103 if ((IS_ADDRESS_IN(SRAM1, MemAddress))
1104 && (IS_ADDRESS_IN(SRAM1, (MemAddress
1105 + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE)
1106 - 1U))))
1107 {
1108 base_address = GTZC_BASE_ADDRESS(SRAM1);
1109 /* limitation: code not portable with memory > 256K */
1110 reg_mpcbb = GTZC_MPCBB1_S->LCKVTR1;
1111 }
1112 else if ((IS_ADDRESS_IN(SRAM2, MemAddress))
1113 && (IS_ADDRESS_IN(SRAM2, (MemAddress
1114 + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE)
1115 - 1U))))
1116 {
1117 base_address = GTZC_BASE_ADDRESS(SRAM2);
1118 /* limitation: code not portable with memory > 256K */
1119 reg_mpcbb = GTZC_MPCBB2_S->LCKVTR1;
1120 }
1121 else
1122 {
1123 return HAL_ERROR;
1124 }
1125
1126 /* get start coordinates of the configuration */
1127 superblock_start = (MemAddress - base_address) / GTZC_MPCBB_SUPERBLOCK_SIZE;
1128 offset_bit_start = superblock_start % 32U;
1129
1130 for (i = 0U; i < NbSuperBlocks; i++)
1131 {
1132 pLockAttributes[i] = (reg_mpcbb & (1UL << (offset_bit_start % 32U)))
1133 >> (offset_bit_start % 32U);
1134 offset_bit_start++;
1135 }
1136
1137 return HAL_OK;
1138 }
1139
1140 /**
1141 * @brief Lock a MPCBB configuration on the SRAM base address passed as parameter.
1142 * @param MemBaseAddress MPCBB identifier.
1143 * @retval HAL status.
1144 */
HAL_GTZC_MPCBB_Lock(uint32_t MemBaseAddress)1145 HAL_StatusTypeDef HAL_GTZC_MPCBB_Lock(uint32_t MemBaseAddress)
1146 {
1147 /* check entry parameters */
1148 if (IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
1149 {
1150 SET_BIT(GTZC_MPCBB1_S->CR, GTZC_MPCBB_CR_LCK_Msk);
1151 }
1152 else if (IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress))
1153 {
1154 SET_BIT(GTZC_MPCBB2_S->CR, GTZC_MPCBB_CR_LCK_Msk);
1155 }
1156 else
1157 {
1158 return HAL_ERROR;
1159 }
1160
1161 return HAL_OK;
1162 }
1163
1164 /**
1165 * @brief Get MPCBB configuration lock state on the SRAM base address passed as parameter.
1166 * @param MemBaseAddress MPCBB identifier.
1167 * @param pLockState pointer to Lock State (GTZC_MCPBB_LOCK_OFF or GTZC_MCPBB_LOCK_ON).
1168 * @retval HAL status.
1169 */
HAL_GTZC_MPCBB_GetLock(uint32_t MemBaseAddress,uint32_t * pLockState)1170 HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLock(uint32_t MemBaseAddress,
1171 uint32_t *pLockState)
1172 {
1173 /* check entry parameters */
1174 if (IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
1175 {
1176 *pLockState = READ_BIT(GTZC_MPCBB1_S->CR, GTZC_MPCBB_CR_LCK_Msk);
1177 }
1178 else if (IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress))
1179 {
1180 *pLockState = READ_BIT(GTZC_MPCBB2_S->CR, GTZC_MPCBB_CR_LCK_Msk);
1181 }
1182 else
1183 {
1184 return HAL_ERROR;
1185 }
1186
1187 return HAL_OK;
1188 }
1189
1190 /**
1191 * @}
1192 */
1193
1194 /** @defgroup GTZC_Exported_Functions_Group5 TZIC Configuration and Control functions
1195 * @brief TZIC Configuration and Control functions
1196 *
1197 @verbatim
1198 ==============================================================================
1199 ##### TZIC Configuration and Control functions #####
1200 ==============================================================================
1201 [..]
1202 This section provides functions allowing to configure and control TZIC
1203 TZIC is Trust Zone Interrupt Controller
1204 @endverbatim
1205 * @{
1206 */
1207
1208 /**
1209 * @brief Disable the interrupt associated to a single TZIC peripheral or on all peripherals.
1210 * @param PeriphId Peripheral identifier.
1211 * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId.
1212 * Use GTZC_PERIPH_ALL to select all peripherals.
1213 * @retval HAL status.
1214 */
HAL_GTZC_TZIC_DisableIT(uint32_t PeriphId)1215 HAL_StatusTypeDef HAL_GTZC_TZIC_DisableIT(uint32_t PeriphId)
1216 {
1217 uint32_t register_address;
1218
1219 /* check entry parameters */
1220 if ((HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER)
1221 || (((PeriphId & GTZC_PERIPH_ALL) != 0U) && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U)))
1222 {
1223 return HAL_ERROR;
1224 }
1225
1226 if ((PeriphId & GTZC_PERIPH_ALL) != 0U)
1227 {
1228 /* same configuration is applied to all peripherals */
1229 WRITE_REG(GTZC_TZIC->IER1, 0U);
1230 WRITE_REG(GTZC_TZIC->IER2, 0U);
1231 WRITE_REG(GTZC_TZIC->IER3, 0U);
1232 }
1233 else
1234 {
1235 /* common case where only one peripheral is configured */
1236 register_address = (uint32_t) &(GTZC_TZIC->IER1) + (4U * GTZC_GET_REG_INDEX(PeriphId));
1237 CLEAR_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
1238 }
1239
1240 return HAL_OK;
1241 }
1242
1243 /**
1244 * @brief Enable the interrupt associated to a single TZIC peripheral or on all peripherals.
1245 * @param PeriphId Peripheral identifier.
1246 * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId.
1247 * Use GTZC_PERIPH_ALL to select all peripherals.
1248 * @retval HAL status.
1249 */
HAL_GTZC_TZIC_EnableIT(uint32_t PeriphId)1250 HAL_StatusTypeDef HAL_GTZC_TZIC_EnableIT(uint32_t PeriphId)
1251 {
1252 uint32_t register_address;
1253
1254 /* check entry parameters */
1255 if ((HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER)
1256 || (((PeriphId & GTZC_PERIPH_ALL) != 0U) && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U)))
1257 {
1258 return HAL_ERROR;
1259 }
1260
1261 if ((PeriphId & GTZC_PERIPH_ALL) != 0U)
1262 {
1263 /* same configuration is applied to all peripherals */
1264 WRITE_REG(GTZC_TZIC->IER1, TZIC_IER1_ALL);
1265 WRITE_REG(GTZC_TZIC->IER2, TZIC_IER2_ALL);
1266 WRITE_REG(GTZC_TZIC->IER3, TZIC_IER3_ALL);
1267 }
1268 else
1269 {
1270 /* common case where only one peripheral is configured */
1271 register_address = (uint32_t) &(GTZC_TZIC->IER1) + (4U * GTZC_GET_REG_INDEX(PeriphId));
1272 SET_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
1273 }
1274
1275 return HAL_OK;
1276 }
1277
1278 /**
1279 * @brief Get TZIC flag on a single TZIC peripheral or on all peripherals.
1280 * @param PeriphId Peripheral identifier.
1281 * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId.
1282 * Use GTZC_PERIPH_ALL to select all peripherals.
1283 * @param pFlag Pointer to the flags.
1284 * If PeriphId target a single peripheral, pointer on a single element.
1285 * If all peripherals selected (GTZC_PERIPH_ALL), pointer to an array
1286 * of GTZC_TZIC_PERIPH_NUMBER elements.
1287 * Element content is either GTZC_TZIC_NO_ILA_EVENT
1288 * or GTZC_TZSC_ILA_EVENT_PENDING.
1289 * @retval HAL status
1290 */
HAL_GTZC_TZIC_GetFlag(uint32_t PeriphId,uint32_t * pFlag)1291 HAL_StatusTypeDef HAL_GTZC_TZIC_GetFlag(uint32_t PeriphId, uint32_t *pFlag)
1292 {
1293 uint32_t i;
1294 uint32_t reg_value;
1295 uint32_t register_address;
1296
1297 /* check entry parameters */
1298 if ((HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER)
1299 || (((PeriphId & GTZC_PERIPH_ALL) != 0U) && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U)))
1300 {
1301 return HAL_ERROR;
1302 }
1303
1304 if ((PeriphId & GTZC_PERIPH_ALL) != 0U)
1305 {
1306 /* special case where it is applied to all peripherals */
1307 reg_value = READ_REG(GTZC_TZIC->SR1);
1308 for (i = 0U; i < 32U; i++)
1309 {
1310 pFlag[i] = (reg_value & (1UL << i)) >> i;
1311 }
1312
1313 reg_value = READ_REG(GTZC_TZIC->SR2);
1314 for (/*i = 32U*/; i < 64U; i++)
1315 {
1316 pFlag[i] = (reg_value & (1UL << (i - 32U))) >> (i - 32U);
1317 }
1318
1319 reg_value = READ_REG(GTZC_TZIC->SR3);
1320 for (/*i = 64U*/; i < GTZC_TZIC_PERIPH_NUMBER; i++)
1321 {
1322 pFlag[i] = (reg_value & (1UL << (i - 64U))) >> (i - 64U);
1323 }
1324 }
1325 else
1326 {
1327 /* common case where only one peripheral is concerned */
1328 register_address = (uint32_t) &(GTZC_TZIC->SR1) + (4U * GTZC_GET_REG_INDEX(PeriphId));
1329 *pFlag = READ_BIT(*(__IO uint32_t *)register_address,
1330 1UL << GTZC_GET_PERIPH_POS(PeriphId)) >> GTZC_GET_PERIPH_POS(PeriphId);
1331 }
1332
1333 return HAL_OK;
1334 }
1335
1336 /**
1337 * @brief Clear TZIC flag on a single TZIC peripheral or on all peripherals.
1338 * @param PeriphId Peripheral identifier.
1339 * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId.
1340 * Use GTZC_PERIPH_ALL to select all peripherals.
1341 * @retval HAL status.
1342 */
HAL_GTZC_TZIC_ClearFlag(uint32_t PeriphId)1343 HAL_StatusTypeDef HAL_GTZC_TZIC_ClearFlag(uint32_t PeriphId)
1344 {
1345 uint32_t register_address;
1346
1347 /* check entry parameters */
1348 if ((HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER)
1349 || (((PeriphId & GTZC_PERIPH_ALL) != 0U) && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U)))
1350 {
1351 return HAL_ERROR;
1352 }
1353
1354 if ((PeriphId & GTZC_PERIPH_ALL) != 0U)
1355 {
1356 /* same configuration is applied to all peripherals */
1357 WRITE_REG(GTZC_TZIC->FCR1, TZIC_FCR1_ALL);
1358 WRITE_REG(GTZC_TZIC->FCR2, TZIC_FCR2_ALL);
1359 WRITE_REG(GTZC_TZIC->FCR3, TZIC_FCR3_ALL);
1360 }
1361 else
1362 {
1363 /* common case where only one peripheral is configured */
1364 register_address = (uint32_t) &(GTZC_TZIC->FCR1) + (4U * GTZC_GET_REG_INDEX(PeriphId));
1365 SET_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
1366 }
1367
1368 return HAL_OK;
1369 }
1370
1371 /**
1372 * @}
1373 */
1374
1375 /** @defgroup GTZC_Exported_Functions_Group6 IRQ related functions
1376 * @brief IRQ related functions
1377 *
1378 @verbatim
1379 ==============================================================================
1380 ##### TZIC IRQ Handler and Callback functions #####
1381 ==============================================================================
1382 [..]
1383 This section provides functions allowing to treat ISR and provide user callback
1384 @endverbatim
1385 * @{
1386 */
1387
1388 /**
1389 * @brief This function handles GTZC interrupt request.
1390 * @retval None.
1391 */
HAL_GTZC_IRQHandler(void)1392 void HAL_GTZC_IRQHandler(void)
1393 {
1394 uint32_t position;
1395 uint32_t flag;
1396 uint32_t ier_itsources;
1397 uint32_t sr_flags;
1398
1399 /* Get current IT Flags and IT sources value on 1st register */
1400 ier_itsources = READ_REG(GTZC_TZIC->IER1);
1401 sr_flags = READ_REG(GTZC_TZIC->SR1);
1402
1403 /* Get Mask interrupt and then clear them */
1404 flag = ier_itsources & sr_flags;
1405 if (flag != 0U)
1406 {
1407 WRITE_REG(GTZC_TZIC->FCR1, flag);
1408
1409 /* Loop on flag to check, which ones have been raised */
1410 position = 0U;
1411 while ((flag >> position) != 0U)
1412 {
1413 if ((flag & (1UL << position)) != 0U)
1414 {
1415 HAL_GTZC_TZIC_Callback(GTZC_PERIPH_REG1 | position);
1416 }
1417
1418 /* Position bit to be updated */
1419 position++;
1420 }
1421 }
1422
1423 /* Get current IT Flags and IT sources value on 2nd register */
1424 ier_itsources = READ_REG(GTZC_TZIC->IER2);
1425 sr_flags = READ_REG(GTZC_TZIC->SR2);
1426
1427 /* Get Mask interrupt and then clear them */
1428 flag = ier_itsources & sr_flags;
1429 if (flag != 0U)
1430 {
1431 WRITE_REG(GTZC_TZIC->FCR2, flag);
1432
1433 /* Loop on flag to check, which ones have been raised */
1434 position = 0U;
1435 while ((flag >> position) != 0U)
1436 {
1437 if ((flag & (1UL << position)) != 0U)
1438 {
1439 HAL_GTZC_TZIC_Callback(GTZC_PERIPH_REG2 | position);
1440 }
1441
1442 /* Position bit to be updated */
1443 position++;
1444 }
1445 }
1446
1447 /* Get current IT Flags and IT sources value on 3rd register */
1448 ier_itsources = READ_REG(GTZC_TZIC->IER3);
1449 sr_flags = READ_REG(GTZC_TZIC->SR3);
1450
1451 /* Get Mask interrupt and then clear them */
1452 flag = ier_itsources & sr_flags;
1453 if (flag != 0U)
1454 {
1455 WRITE_REG(GTZC_TZIC->FCR3, flag);
1456
1457 /* Loop on flag to check, which ones have been raised */
1458 position = 0U;
1459 while ((flag >> position) != 0U)
1460 {
1461 if ((flag & (1UL << position)) != 0U)
1462 {
1463 HAL_GTZC_TZIC_Callback(GTZC_PERIPH_REG3 | position);
1464 }
1465
1466 /* Position bit to be updated */
1467 position++;
1468 }
1469 }
1470 }
1471
1472 /**
1473 * @brief GTZC TZIC sub-block interrupt callback.
1474 * @param PeriphId Peripheral identifier triggering the illegal access.
1475 * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId
1476 * @retval None.
1477 */
HAL_GTZC_TZIC_Callback(uint32_t PeriphId)1478 __weak void HAL_GTZC_TZIC_Callback(uint32_t PeriphId)
1479 {
1480 /* Prevent unused argument(s) compilation warning */
1481 UNUSED(PeriphId);
1482
1483 /* NOTE: This function should not be modified. When the callback is needed,
1484 * the HAL_GTZC_TZIC_Callback is to be implemented in the user file
1485 */
1486 }
1487
1488 /**
1489 * @}
1490 */
1491
1492 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1493
1494 /**
1495 * @}
1496 */
1497
1498 #endif /*HAL_GTZC_MODULE_ENABLED*/
1499
1500 /**
1501 * @}
1502 */
1503
1504 /**
1505 * @}
1506 */
1507
1508 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1509
