1 /**
2 ******************************************************************************
3 * @file stm32h5xx_hal_rcc_ex.c
4 * @author MCD Application Team
5 * @brief Extended RCC HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities RCC extended peripheral:
8 * + Extended Peripheral Control functions
9 * + Extended Clock management functions
10 * + Extended Clock Recovery System Control functions
11 *
12 ******************************************************************************
13 * @attention
14 *
15 * Copyright (c) 2022 STMicroelectronics.
16 * All rights reserved.
17 *
18 * This software is licensed under terms that can be found in the LICENSE file
19 * in the root directory of this software component.
20 * If no LICENSE file comes with this software, it is provided AS-IS.
21 *
22 ******************************************************************************
23 */
24
25 /* Includes ------------------------------------------------------------------*/
26 #include "stm32h5xx_hal.h"
27
28 /** @addtogroup STM32H5xx_HAL_Driver
29 * @{
30 */
31
32 /** @defgroup RCCEx RCCEx
33 * @brief RCC Extended HAL module driver
34 * @{
35 */
36
37 #ifdef HAL_RCC_MODULE_ENABLED
38
39 /* Private typedef -----------------------------------------------------------*/
40 /* Private defines -----------------------------------------------------------*/
41 /** @defgroup RCCEx_Private_Constants RCCEx Private Constants
42 * @{
43 */
44 #define PLL1_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */
45 #define PLL2_TIMEOUT_VALUE ((uint32_t)/*8U*/2U) /* 2 ms (minimum Tick + 1) */
46 #if defined(RCC_CR_PLL3ON)
47 #define PLL3_TIMEOUT_VALUE ((uint32_t)/*8U*/2U) /* 2 ms (minimum Tick + 1) */
48 #endif /* RCC_CR_PLL3ON */
49
50 #define __LSCO_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE()
51
52 #define LSCO_GPIO_PORT GPIOB
53
54 #define LSCO_PIN GPIO_PIN_2
55
56 /**
57 * @}
58 */
59
60 /* Private macros ------------------------------------------------------------*/
61 /* Private variables ---------------------------------------------------------*/
62 /* Private function prototypes -----------------------------------------------*/
63 /** @defgroup RCCEx_Private_Functions RCCEx Private Functions
64 * @{
65 */
66 static HAL_StatusTypeDef RCCEx_PLLSource_Enable(uint32_t PllSource);
67 static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *Pll2);
68 #if defined(RCC_CR_PLL3ON)
69 static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *Pll3);
70 #endif /* RCC_CR_PLL3ON */
71 /**
72 * @}
73 */
74
75 /* Exported functions --------------------------------------------------------*/
76
77 /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
78 * @{
79 */
80
81 /** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
82 * @brief Extended Peripheral Control functions
83 *
84 @verbatim
85 ===============================================================================
86 ##### Extended Peripheral Control functions #####
87 ===============================================================================
88 [..]
89 This subsection provides a set of functions allowing to control the RCC Clocks
90 frequencies.
91 [..]
92 (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
93 select the RTC clock source; in this case the Backup domain will be reset in
94 order to modify the RTC Clock source, as consequence RTC registers (including
95 the backup registers) are set to their reset values.
96
97 @endverbatim
98 * @{
99 */
100 /**
101 * @brief Initialize the RCC extended peripherals clocks according to the specified
102 * parameters in the RCC_PeriphCLKInitTypeDef.
103 * @param pPeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
104 * contains a field PeriphClockSelection which can be a combination of the following values:
105 * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock
106 * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
107 * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock
108 * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock (*)
109 * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock (*)
110 * @arg @ref RCC_PERIPHCLK_USART6 USART6 peripheral clock (*)
111 * @arg @ref RCC_PERIPHCLK_UART7 UART7 peripheral clock (*)
112 * @arg @ref RCC_PERIPHCLK_UART8 UART8 peripheral clock (*)
113 * @arg @ref RCC_PERIPHCLK_UART9 UART9 peripheral clock (*)
114 * @arg @ref RCC_PERIPHCLK_USART10 USART10 peripheral clock (*)
115 * @arg @ref RCC_PERIPHCLK_USART11 USART11 peripheral clock (*)
116 * @arg @ref RCC_PERIPHCLK_UART12 UART12 peripheral clock (*)
117 * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock
118 * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock
119 * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
120 * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock (*)
121 * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock (*)
122 * @arg @ref RCC_PERIPHCLK_I3C1 I3C1 peripheral clock
123 * @arg @ref RCC_PERIPHCLK_I3C2 I3C2 peripheral clock (***)
124 * @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock
125 * @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock
126 * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock (*)
127 * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock (*)
128 * @arg @ref RCC_PERIPHCLK_ADCDAC ADCDAC peripheral clock
129 * @arg @ref RCC_PERIPHCLK_ADC1 ADC1 peripheral clock
130 * @arg @ref RCC_PERIPHCLK_ADC2 ADC2 peripheral clock
131 * @arg @ref RCC_PERIPHCLK_SDMMC1 SDMMC1 peripheral clock (*)
132 * @arg @ref RCC_PERIPHCLK_SDMMC2 SDMMC2 peripheral clock (**)
133 * @arg @ref RCC_PERIPHCLK_CKPER CKPER peripheral clock
134 * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
135 * @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock
136 * @arg @ref RCC_PERIPHCLK_SPI1 SPI1 peripheral clock
137 * @arg @ref RCC_PERIPHCLK_SPI2 SPI2 peripheral clock
138 * @arg @ref RCC_PERIPHCLK_SPI3 SPI3 peripheral clock
139 * @arg @ref RCC_PERIPHCLK_SPI4 SPI4 peripheral clock (*)
140 * @arg @ref RCC_PERIPHCLK_SPI5 SPI5 peripheral clock (*)
141 * @arg @ref RCC_PERIPHCLK_SPI6 SPI6 peripheral clock (*)
142 * @arg @ref RCC_PERIPHCLK_OSPI OCTOSPI peripheral clock (*)
143 * @arg @ref RCC_PERIPHCLK_FDCAN12 FDCAN12 peripheral clock (**)
144 * @arg @ref RCC_PERIPHCLK_FDCAN1 FDCAN1 peripheral clock (*)
145 * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock (*)
146 * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
147 * @arg @ref RCC_PERIPHCLK_LPTIM3 LPTIM3 peripheral clock (*)
148 * @arg @ref RCC_PERIPHCLK_LPTIM4 LPTIM4 peripheral clock (*)
149 * @arg @ref RCC_PERIPHCLK_LPTIM5 LPTIM5 peripheral clock (*)
150 * @arg @ref RCC_PERIPHCLK_LPTIM6 LPTIM6 peripheral clock (*)
151 * @arg @ref RCC_PERIPHCLK_DAC_LP DAC peripheral low-power clock
152 * @arg @ref RCC_PERIPHCLK_TIM TIM peripheral clock
153 *
154 * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
155 * the RTC clock source: in this case the access to Backup domain is enabled.
156 *
157 * @retval HAL status
158 *
159 * (*) : For stm32h56xxx and stm32h57xxx family lines only.
160 * (**) : For stm32h563xx and stm32h57xxx family lines only.
161 * (***) : For stm32h503xx family line only.
162 */
HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef * pPeriphClkInit)163 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphClkInit)
164 {
165 uint32_t tmpregister;
166 uint32_t tickstart;
167 HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */
168 HAL_StatusTypeDef status = HAL_OK; /* Final status */
169
170 /* Check the parameters */
171 assert_param(IS_RCC_PERIPHCLOCK(pPeriphClkInit->PeriphClockSelection));
172
173 /*------------------------------------ CKPER configuration --------------------------------------*/
174 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CKPER) == RCC_PERIPHCLK_CKPER)
175 {
176 /* Check the parameters */
177 assert_param(IS_RCC_CLKPSOURCE(pPeriphClkInit->CkperClockSelection));
178
179 /* Configure the CKPER clock source */
180 __HAL_RCC_CLKP_CONFIG(pPeriphClkInit->CkperClockSelection);
181 }
182
183 /*-------------------------- USART1 clock source configuration -------------------*/
184 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
185 {
186 /* Check the parameters */
187 assert_param(IS_RCC_USART1CLKSOURCE(pPeriphClkInit->Usart1ClockSelection));
188
189 switch (pPeriphClkInit->Usart1ClockSelection)
190 {
191 case RCC_USART1CLKSOURCE_PCLK2: /* PCLK2 is used as clock source for USART1*/
192
193 /* USART1 clock source config set later after clock selection check */
194 break;
195
196 case RCC_USART1CLKSOURCE_PLL2Q: /* PLL2 is used as clock source for USART1*/
197 /* PLL2 input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */
198 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
199 /* USART1 clock source config set later after clock selection check */
200 break;
201 #if defined(RCC_USART1CLKSOURCE_PLL3Q)
202 case RCC_USART1CLKSOURCE_PLL3Q: /* PLL3 is used as clock source for USART1*/
203 /* PLL3 input clock, parameters M, N & Q configuration clock output (PLL3ClockOut) */
204 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
205 /* USART1 clock source config set later after clock selection check */
206 break;
207 #endif /* RCC_CR_PLL3ON */
208
209 case RCC_USART1CLKSOURCE_HSI: /* HSI clock is used as source of USART1 clock*/
210 /* USART1 clock source config set later after clock selection check */
211 break;
212
213 case RCC_USART1CLKSOURCE_CSI: /* CSI clock is used as source of USART1 clock*/
214 /* USART1 clock source config set later after clock selection check */
215 break;
216
217 case RCC_USART1CLKSOURCE_LSE: /* LSE clock is used as source of USART1 clock*/
218 /* USART1 clock source config set later after clock selection check */
219 break;
220
221 default:
222 ret = HAL_ERROR;
223 break;
224 }
225
226 if (ret == HAL_OK)
227 {
228 /* Set the source of USART1 clock*/
229 __HAL_RCC_USART1_CONFIG(pPeriphClkInit->Usart1ClockSelection);
230 }
231 else
232 {
233 /* set overall return value */
234 status = ret;
235 }
236 }
237
238 /*-------------------------- USART2 clock source configuration -------------------*/
239 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
240 {
241 /* Check the parameters */
242 assert_param(IS_RCC_USART2CLKSOURCE(pPeriphClkInit->Usart2ClockSelection));
243
244 switch (pPeriphClkInit->Usart2ClockSelection)
245 {
246 case RCC_USART2CLKSOURCE_PCLK1: /* PCLK1 is used as clock source for USART2*/
247
248 /* USART2 clock source config set later after clock selection check */
249 break;
250
251 case RCC_USART2CLKSOURCE_PLL2Q: /* PLL2 is used as clock source for USART2*/
252 /* PLL2 input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */
253 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
254 /* USART2 clock source config set later after clock selection check */
255 break;
256
257 #if defined(RCC_USART2CLKSOURCE_PLL3Q)
258 case RCC_USART2CLKSOURCE_PLL3Q: /* PLL3 is used as clock source for USART2*/
259 /* PLL3 input clock, parameters M, N & Q configuration clock output (PLL3ClockOut) */
260 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
261 /* USART2 clock source config set later after clock selection check */
262 break;
263 #endif /* RCC_USART2CLKSOURCE_PLL3 */
264
265 case RCC_USART2CLKSOURCE_HSI: /* HSI clock is used as source of USART2 clock*/
266 /* USART2 clock source config set later after clock selection check */
267 break;
268
269 case RCC_USART2CLKSOURCE_CSI: /* CSI clock is used as source of USART2 clock*/
270 /* USART2 clock source config set later after clock selection check */
271 break;
272
273 case RCC_USART2CLKSOURCE_LSE: /* LSE clock is used as source of USART2 clock*/
274 /* USART2 clock source config set later after clock selection check */
275 break;
276
277 default:
278 ret = HAL_ERROR;
279 break;
280 }
281
282 if (ret == HAL_OK)
283 {
284 /* Set the source of USART2 clock*/
285 __HAL_RCC_USART2_CONFIG(pPeriphClkInit->Usart2ClockSelection);
286 }
287 else
288 {
289 /* set overall return value */
290 status = ret;
291 }
292 }
293
294 /*-------------------------- USART3 clock source configuration -------------------*/
295 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
296 {
297 /* Check the parameters */
298 assert_param(IS_RCC_USART3CLKSOURCE(pPeriphClkInit->Usart3ClockSelection));
299
300 switch (pPeriphClkInit->Usart3ClockSelection)
301 {
302 case RCC_USART3CLKSOURCE_PCLK1: /* PCLK1 is used as clock source for USART3*/
303
304 /* USART3 clock source config set later after clock selection check */
305 break;
306
307 case RCC_USART3CLKSOURCE_PLL2Q: /* PLL2 is used as clock source for USART3*/
308 /* PLL2 input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */
309 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
310 /* USART3 clock source config set later after clock selection check */
311 break;
312
313 #if defined(RCC_USART3CLKSOURCE_PLL3Q)
314 case RCC_USART3CLKSOURCE_PLL3Q: /* PLL3 is used as clock source for USART3*/
315 /* PLL3 input clock, parameters M, N & Q configuration clock output (PLL3ClockOut) */
316 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
317 /* USART3 clock source config set later after clock selection check */
318 break;
319 #endif /* RCC_USART3CLKSOURCE_PLL3 */
320
321 case RCC_USART3CLKSOURCE_HSI: /* HSI clock is used as source of USART3 clock*/
322 /* USART3 clock source config set later after clock selection check */
323 break;
324
325 case RCC_USART3CLKSOURCE_CSI: /* CSI clock is used as source of USART3 clock*/
326 /* USART3 clock source config set later after clock selection check */
327 break;
328
329 case RCC_USART3CLKSOURCE_LSE: /* LSE clock is used as source of USART3 clock*/
330 /* USART3 clock source config set later after clock selection check */
331 break;
332
333 default:
334 ret = HAL_ERROR;
335 break;
336 }
337
338 if (ret == HAL_OK)
339 {
340 /* Set the source of USART3 clock*/
341 __HAL_RCC_USART3_CONFIG(pPeriphClkInit->Usart3ClockSelection);
342 }
343 else
344 {
345 /* set overall return value */
346 status = ret;
347 }
348 }
349
350 #if defined(UART4)
351 /*-------------------------- UART4 clock source configuration --------------------*/
352 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
353 {
354 /* Check the parameters */
355 assert_param(IS_RCC_UART4CLKSOURCE(pPeriphClkInit->Uart4ClockSelection));
356
357 switch (pPeriphClkInit->Uart4ClockSelection)
358 {
359 case RCC_UART4CLKSOURCE_PCLK1: /* PCLK1 is used as clock source for UART4*/
360
361 /* UART4 clock source config set later after clock selection check */
362 break;
363
364 case RCC_UART4CLKSOURCE_PLL2Q: /* PLL2 is used as clock source for UART4*/
365 /* PLL2 input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */
366 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
367 /* UART4 clock source config set later after clock selection check */
368 break;
369
370 case RCC_UART4CLKSOURCE_PLL3Q: /* PLL3 is used as clock source for UART4*/
371 /* PLL3 input clock, parameters M, N & Q configuration clock output (PLL3ClockOut) */
372 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
373 /* UART4 clock source config set later after clock selection check */
374 break;
375
376 case RCC_UART4CLKSOURCE_HSI: /* HSI clock is used as source of UART4 clock*/
377 /* UART4 clock source config set later after clock selection check */
378 break;
379
380 case RCC_UART4CLKSOURCE_CSI: /* CSI clock is used as source of UART4 clock*/
381 /* UART4 clock source config set later after clock selection check */
382 break;
383
384 case RCC_UART4CLKSOURCE_LSE: /* LSE clock is used as source of UART4 clock*/
385 /* UART4 clock source config set later after clock selection check */
386 break;
387
388 default:
389 ret = HAL_ERROR;
390 break;
391 }
392
393 if (ret == HAL_OK)
394 {
395 /* Set the source of UART4 clock*/
396 __HAL_RCC_UART4_CONFIG(pPeriphClkInit->Uart4ClockSelection);
397 }
398 else
399 {
400 /* set overall return value */
401 status = ret;
402 }
403 }
404 #endif /* UART4 */
405
406 #if defined(UART5)
407 /*-------------------------- UART5 clock source configuration --------------------*/
408 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
409 {
410 /* Check the parameters */
411 assert_param(IS_RCC_UART5CLKSOURCE(pPeriphClkInit->Uart5ClockSelection));
412
413 switch (pPeriphClkInit->Uart5ClockSelection)
414 {
415 case RCC_UART5CLKSOURCE_PCLK1: /* PCLK1 is used as clock source for UART5*/
416
417 /* UART5 clock source config set later after clock selection check */
418 break;
419
420 case RCC_UART5CLKSOURCE_PLL2Q: /* PLL2 is used as clock source for UART5*/
421 /* PLL2 input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */
422 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
423 /* UART5 clock source config set later after clock selection check */
424 break;
425
426 case RCC_UART5CLKSOURCE_PLL3Q: /* PLL3 is used as clock source for UART5*/
427 /* PLL3 input clock, parameters M, N & Q configuration clock output (PLL3ClockOut) */
428 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
429 /* UART5 clock source config set later after clock selection check */
430 break;
431
432 case RCC_UART5CLKSOURCE_HSI: /* HSI clock is used as source of UART5 clock*/
433 /* UART5 clock source config set later after clock selection check */
434 break;
435
436 case RCC_UART5CLKSOURCE_CSI: /* CSI clock is used as source of UART5 clock*/
437 /* UART5 clock source config set later after clock selection check */
438 break;
439
440 case RCC_UART5CLKSOURCE_LSE: /* LSE clock is used as source of UART5 clock*/
441 /* UART5 clock source config set later after clock selection check */
442 break;
443
444 default:
445 ret = HAL_ERROR;
446 break;
447 }
448
449 if (ret == HAL_OK)
450 {
451 /* Set the source of UART5 clock*/
452 __HAL_RCC_UART5_CONFIG(pPeriphClkInit->Uart5ClockSelection);
453 }
454 else
455 {
456 /* set overall return value */
457 status = ret;
458 }
459 }
460 #endif /* UART5 */
461
462 #if defined(USART6)
463 /*-------------------------- USART6 clock source configuration -------------------*/
464 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6)
465 {
466 /* Check the parameters */
467 assert_param(IS_RCC_USART6CLKSOURCE(pPeriphClkInit->Usart6ClockSelection));
468
469 switch (pPeriphClkInit->Usart6ClockSelection)
470 {
471 case RCC_USART6CLKSOURCE_PCLK1: /* PCLK1 is used as clock source for USART6*/
472
473 /* USART6 clock source config set later after clock selection check */
474 break;
475
476 case RCC_USART6CLKSOURCE_PLL2Q: /* PLL2 is used as clock source for USART6*/
477 /* PLL2 input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */
478 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
479 /* USART6 clock source config set later after clock selection check */
480 break;
481
482 case RCC_USART6CLKSOURCE_PLL3Q: /* PLL3 is used as clock source for USART6*/
483 /* PLL3 input clock, parameters M, N & Q configuration clock output (PLL3ClockOut) */
484 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
485 /* USART6 clock source config set later after clock selection check */
486 break;
487
488 case RCC_USART6CLKSOURCE_HSI: /* HSI clock is used as source of USART6 clock*/
489 /* USART6 clock source config set later after clock selection check */
490 break;
491
492 case RCC_USART6CLKSOURCE_CSI: /* CSI clock is used as source of USART6 clock*/
493 /* USART6 clock source config set later after clock selection check */
494 break;
495
496 case RCC_USART6CLKSOURCE_LSE: /* LSE clock is used as source of USART6 clock*/
497 /* USART6 clock source config set later after clock selection check */
498 break;
499
500 default:
501 ret = HAL_ERROR;
502 break;
503 }
504
505 if (ret == HAL_OK)
506 {
507 /* Set the source of USART6 clock*/
508 __HAL_RCC_USART6_CONFIG(pPeriphClkInit->Usart6ClockSelection);
509 }
510 else
511 {
512 /* set overall return value */
513 status = ret;
514 }
515 }
516 #endif /* USART6 */
517
518 #if defined(UART7)
519 /*-------------------------- UART7 clock source configuration -------------------*/
520 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7)
521 {
522 /* Check the parameters */
523 assert_param(IS_RCC_UART7CLKSOURCE(pPeriphClkInit->Uart7ClockSelection));
524
525 switch (pPeriphClkInit->Uart7ClockSelection)
526 {
527 case RCC_UART7CLKSOURCE_PCLK1: /* PCLK1 is used as clock source for UART7*/
528
529 /* UART7 clock source config set later after clock selection check */
530 break;
531
532 case RCC_UART7CLKSOURCE_PLL2Q: /* PLL2 is used as clock source for UART7*/
533 /* PLL2 input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */
534 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
535 /* UART7 clock source config set later after clock selection check */
536 break;
537
538 case RCC_UART7CLKSOURCE_PLL3Q: /* PLL3 is used as clock source for UART7*/
539 /* PLL3 input clock, parameters M, N & Q configuration clock output (PLL3ClockOut) */
540 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
541 /* UART7 clock source config set later after clock selection check */
542 break;
543
544 case RCC_UART7CLKSOURCE_HSI: /* HSI clock is used as source of UART7 clock*/
545 /* UART7 clock source config set later after clock selection check */
546 break;
547
548 case RCC_UART7CLKSOURCE_CSI: /* CSI clock is used as source of UART7 clock*/
549 /* UART7 clock source config set later after clock selection check */
550 break;
551
552 case RCC_UART7CLKSOURCE_LSE: /* LSE clock is used as source of UART7 clock*/
553 /* UART7 clock source config set later after clock selection check */
554 break;
555
556 default:
557 ret = HAL_ERROR;
558 break;
559 }
560
561 if (ret == HAL_OK)
562 {
563 /* Set the source of UART7 clock*/
564 __HAL_RCC_UART7_CONFIG(pPeriphClkInit->Uart7ClockSelection);
565 }
566 else
567 {
568 /* set overall return value */
569 status = ret;
570 }
571 }
572 #endif /* UART7 */
573
574 #if defined(UART8)
575 /*-------------------------- UART8 clock source configuration -------------------*/
576 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8)
577 {
578 /* Check the parameters */
579 assert_param(IS_RCC_UART8CLKSOURCE(pPeriphClkInit->Uart8ClockSelection));
580
581 switch (pPeriphClkInit->Uart8ClockSelection)
582 {
583 case RCC_UART8CLKSOURCE_PCLK1: /* PCLK1 is used as clock source for UART8*/
584
585 /* UART8 clock source config set later after clock selection check */
586 break;
587
588 case RCC_UART8CLKSOURCE_PLL2Q: /* PLL2 is used as clock source for UART8*/
589 /* PLL2 input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */
590 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
591 /* UART8 clock source config set later after clock selection check */
592 break;
593
594 case RCC_UART8CLKSOURCE_PLL3Q: /* PLL3 is used as clock source for UART8*/
595 /* PLL3 input clock, parameters M, N & Q configuration clock output (PLL3ClockOut) */
596 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
597 /* UART8 clock source config set later after clock selection check */
598 break;
599
600 case RCC_UART8CLKSOURCE_HSI: /* HSI clock is used as source of UART8 clock*/
601 /* UART8 clock source config set later after clock selection check */
602 break;
603
604 case RCC_UART8CLKSOURCE_CSI: /* CSI clock is used as source of UART8 clock*/
605 /* UART8 clock source config set later after clock selection check */
606 break;
607
608 case RCC_UART8CLKSOURCE_LSE: /* LSE clock is used as source of UART8 clock*/
609 /* UART8 clock source config set later after clock selection check */
610 break;
611
612 default:
613 ret = HAL_ERROR;
614 break;
615 }
616
617 if (ret == HAL_OK)
618 {
619 /* Set the source of UART8 clock*/
620 __HAL_RCC_UART8_CONFIG(pPeriphClkInit->Uart8ClockSelection);
621 }
622 else
623 {
624 /* set overall return value */
625 status = ret;
626 }
627 }
628 #endif /* UART9 */
629
630 #if defined(UART9)
631 /*-------------------------- UART9 clock source configuration -------------------*/
632 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART9) == RCC_PERIPHCLK_UART9)
633 {
634 /* Check the parameters */
635 assert_param(IS_RCC_UART9CLKSOURCE(pPeriphClkInit->Uart9ClockSelection));
636
637 switch (pPeriphClkInit->Uart9ClockSelection)
638 {
639 case RCC_UART9CLKSOURCE_PCLK1: /* PCLK1 is used as clock source for UART9*/
640
641 /* UART9 clock source config set later after clock selection check */
642 break;
643
644 case RCC_UART9CLKSOURCE_PLL2Q: /* PLL2 is used as clock source for UART9*/
645 /* PLL2 input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */
646 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
647 /* UART9 clock source config set later after clock selection check */
648 break;
649
650 case RCC_UART9CLKSOURCE_PLL3Q: /* PLL3 is used as clock source for UART9*/
651 /* PLL3 input clock, parameters M, N & Q configuration clock output (PLL3ClockOut) */
652 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
653 /* UART9 clock source config set later after clock selection check */
654 break;
655
656 case RCC_UART9CLKSOURCE_HSI: /* HSI clock is used as source of UART9 clock*/
657 /* UART9 clock source config set later after clock selection check */
658 break;
659
660 case RCC_UART9CLKSOURCE_CSI: /* CSI clock is used as source of UART9 clock*/
661 /* UART9 clock source config set later after clock selection check */
662 break;
663
664 case RCC_UART9CLKSOURCE_LSE: /* LSE clock is used as source of UART9 clock*/
665 /* UART9 clock source config set later after clock selection check */
666 break;
667
668 default:
669 ret = HAL_ERROR;
670 break;
671 }
672
673 if (ret == HAL_OK)
674 {
675 /* Set the source of UART9 clock*/
676 __HAL_RCC_UART9_CONFIG(pPeriphClkInit->Uart9ClockSelection);
677 }
678 else
679 {
680 /* set overall return value */
681 status = ret;
682 }
683 }
684 #endif /* UART9 */
685
686 #if defined(USART10)
687 /*-------------------------- USART10 clock source configuration -------------------*/
688 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART10) == RCC_PERIPHCLK_USART10)
689 {
690 /* Check the parameters */
691 assert_param(IS_RCC_USART10CLKSOURCE(pPeriphClkInit->Usart10ClockSelection));
692
693 switch (pPeriphClkInit->Usart10ClockSelection)
694 {
695 case RCC_USART10CLKSOURCE_PCLK1: /* PCLK1 is used as clock source for USART10*/
696
697 /* USART10 clock source config set later after clock selection check */
698 break;
699
700 case RCC_USART10CLKSOURCE_PLL2Q: /* PLL2 is used as clock source for USART10*/
701 /* PLL2 input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */
702 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
703 /* USART10 clock source config set later after clock selection check */
704 break;
705
706 case RCC_USART10CLKSOURCE_PLL3Q: /* PLL3 is used as clock source for USART10*/
707 /* PLL3 input clock, parameters M, N & Q configuration clock output (PLL3ClockOut) */
708 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
709 /* USART10 clock source config set later after clock selection check */
710 break;
711
712 case RCC_USART10CLKSOURCE_HSI: /* HSI clock is used as source of USART10 clock*/
713 /* USART10 clock source config set later after clock selection check */
714 break;
715
716 case RCC_USART10CLKSOURCE_CSI: /* CSI clock is used as source of USART10 clock*/
717 /* USART10 clock source config set later after clock selection check */
718 break;
719
720 case RCC_USART10CLKSOURCE_LSE: /* LSE clock is used as source of USART10 clock*/
721 /* USART10 clock source config set later after clock selection check */
722 break;
723
724 default:
725 ret = HAL_ERROR;
726 break;
727 }
728
729 if (ret == HAL_OK)
730 {
731 /* Set the source of USART10 clock*/
732 __HAL_RCC_USART10_CONFIG(pPeriphClkInit->Usart10ClockSelection);
733 }
734 else
735 {
736 /* set overall return value */
737 status = ret;
738 }
739 }
740 #endif /* USART10 */
741
742 #if defined(USART11)
743 /*-------------------------- USART11 clock source configuration -------------------*/
744 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART11) == RCC_PERIPHCLK_USART11)
745 {
746 /* Check the parameters */
747 assert_param(IS_RCC_USART11CLKSOURCE(pPeriphClkInit->Usart11ClockSelection));
748
749 switch (pPeriphClkInit->Usart11ClockSelection)
750 {
751 case RCC_USART11CLKSOURCE_PCLK1: /* PCLK1 is used as clock source for USART11*/
752
753 /* USART11 clock source config set later after clock selection check */
754 break;
755
756 case RCC_USART11CLKSOURCE_PLL2Q: /* PLL2 is used as clock source for USART11*/
757 /* PLL2 input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */
758 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
759 /* USART11 clock source config set later after clock selection check */
760 break;
761
762 case RCC_USART11CLKSOURCE_PLL3Q: /* PLL3 is used as clock source for USART11*/
763 /* PLL3 input clock, parameters M, N & Q configuration clock output (PLL3ClockOut) */
764 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
765 /* USART11 clock source config set later after clock selection check */
766 break;
767
768 case RCC_USART11CLKSOURCE_HSI: /* HSI clock is used as source of USART11 clock*/
769 /* USART11 clock source config set later after clock selection check */
770 break;
771
772 case RCC_USART11CLKSOURCE_CSI: /* CSI clock is used as source of USART11 clock*/
773 /* USART11 clock source config set later after clock selection check */
774 break;
775
776 case RCC_USART11CLKSOURCE_LSE: /* LSE clock is used as source of USART11 clock*/
777 /* USART11 clock source config set later after clock selection check */
778 break;
779
780 default:
781 ret = HAL_ERROR;
782 break;
783 }
784
785 if (ret == HAL_OK)
786 {
787 /* Set the source of USART11 clock*/
788 __HAL_RCC_USART11_CONFIG(pPeriphClkInit->Usart11ClockSelection);
789 }
790 else
791 {
792 /* set overall return value */
793 status = ret;
794 }
795 }
796 #endif /*USART11*/
797
798 #if defined(UART12)
799 /*-------------------------- UART12 clock source configuration -------------------*/
800 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART12) == RCC_PERIPHCLK_UART12)
801 {
802 /* Check the parameters */
803 assert_param(IS_RCC_UART12CLKSOURCE(pPeriphClkInit->Uart12ClockSelection));
804
805 switch (pPeriphClkInit->Uart12ClockSelection)
806 {
807 case RCC_UART12CLKSOURCE_PCLK1: /* PCLK1 is used as clock source for UART12*/
808
809 /* UART12 clock source config set later after clock selection check */
810 break;
811
812 case RCC_UART12CLKSOURCE_PLL2Q: /* PLL2 is used as clock source for UART12*/
813 /* PLL2 input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */
814 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
815 /* UART12 clock source config set later after clock selection check */
816 break;
817
818 case RCC_UART12CLKSOURCE_PLL3Q: /* PLL3 is used as clock source for UART12*/
819 /* PLL3 input clock, parameters M, N & Q configuration clock output (PLL3ClockOut) */
820 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
821 /* UART12 clock source config set later after clock selection check */
822 break;
823
824 case RCC_UART12CLKSOURCE_HSI: /* HSI clock is used as source of UART12 clock*/
825 /* UART12 clock source config set later after clock selection check */
826 break;
827
828 case RCC_UART12CLKSOURCE_CSI: /* CSI clock is used as source of UART12 clock*/
829 /* UART12 clock source config set later after clock selection check */
830 break;
831
832 case RCC_UART12CLKSOURCE_LSE: /* LSE clock is used as source of UART12 clock*/
833 /* UART12 clock source config set later after clock selection check */
834 break;
835
836 default:
837 ret = HAL_ERROR;
838 break;
839 }
840
841 if (ret == HAL_OK)
842 {
843 /* Set the source of UART12 clock*/
844 __HAL_RCC_UART12_CONFIG(pPeriphClkInit->Uart12ClockSelection);
845 }
846 else
847 {
848 /* set overall return value */
849 status = ret;
850 }
851 }
852 #endif /* UART12 */
853
854 /*-------------------------- LPUART1 clock source configuration ------------------*/
855 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
856 {
857 /* Check the parameters */
858 assert_param(IS_RCC_LPUART1CLKSOURCE(pPeriphClkInit->Lpuart1ClockSelection));
859
860 switch (pPeriphClkInit->Lpuart1ClockSelection)
861 {
862 case RCC_LPUART1CLKSOURCE_PCLK3: /* PCLK3 is used as clock source for LPUART1*/
863
864 /* LPUART1 clock source config set later after clock selection check */
865 break;
866
867 case RCC_LPUART1CLKSOURCE_PLL2Q: /* PLL2 is used as clock source for LPUART1*/
868 /* PLL2 input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */
869 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
870 /* LPUART1 clock source config set later after clock selection check */
871 break;
872
873 #if defined(RCC_LPUART1CLKSOURCE_PLL3Q)
874 case RCC_LPUART1CLKSOURCE_PLL3Q: /* PLL3 is used as clock source for LPUART1*/
875 /* PLL3 input clock, parameters M, N & Q configuration clock output (PLL3ClockOut) */
876 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
877 /* LPUART1 clock source config set later after clock selection check */
878 break;
879 #endif /* RCC_LPUART1CLKSOURCE_PLL3Q */
880
881 case RCC_LPUART1CLKSOURCE_HSI: /* HSI clock is used as source of LPUART1 clock*/
882 /* LPUART1 clock source config set later after clock selection check */
883 break;
884
885 case RCC_LPUART1CLKSOURCE_CSI: /* CSI clock is used as source of LPUART1 clock*/
886 /* LPUART1 clock source config set later after clock selection check */
887 break;
888
889 case RCC_LPUART1CLKSOURCE_LSE: /* LSE clock is used as source of LPUART1 clock*/
890 /* LPUART1 clock source config set later after clock selection check */
891 break;
892
893 default:
894 ret = HAL_ERROR;
895 break;
896 }
897
898 if (ret == HAL_OK)
899 {
900 /* Set the source of LPUART1 clock*/
901 __HAL_RCC_LPUART1_CONFIG(pPeriphClkInit->Lpuart1ClockSelection);
902 }
903 else
904 {
905 /* set overall return value */
906 status = ret;
907 }
908 }
909
910 /*-------------------------- I2C1 clock source configuration ---------------------*/
911 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
912 {
913 /* Check the parameters */
914 assert_param(IS_RCC_I2C1CLKSOURCE(pPeriphClkInit->I2c1ClockSelection));
915
916 switch (pPeriphClkInit->I2c1ClockSelection)
917 {
918 case RCC_I2C1CLKSOURCE_PCLK1: /* PCLK1 is used as clock source for I2C1*/
919
920 /* I2C1 clock source config set later after clock selection check */
921 break;
922
923 #if defined(RCC_I2C1CLKSOURCE_PLL3R)
924 case RCC_I2C1CLKSOURCE_PLL3R: /* PLL3 is used as clock source for I2C1*/
925 /* PLL3 input clock, parameters M, N & R configuration clock output (PLL3ClockOut) */
926 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
927 #else
928 case RCC_I2C1CLKSOURCE_PLL2R: /* PLL2 is used as clock source for I2C1*/
929 /* PLL2 input clock, parameters M, N & R configuration clock output (PLL2ClockOut) */
930 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
931 #endif /* RCC_I2C1CLKSOURCE_PLL3R */
932 /* I2C1 clock source config set later after clock selection check */
933 break;
934
935
936 case RCC_I2C1CLKSOURCE_HSI: /* HSI clock is used as source of I2C1 clock*/
937 /* I2C1 clock source config set later after clock selection check */
938 break;
939
940 case RCC_I2C1CLKSOURCE_CSI: /* CSI clock is used as source of I2C1 clock*/
941 /* I2C1 clock source config set later after clock selection check */
942 break;
943
944 default:
945 ret = HAL_ERROR;
946 break;
947 }
948
949 if (ret == HAL_OK)
950 {
951 /* Set the source of I2C1 clock*/
952 __HAL_RCC_I2C1_CONFIG(pPeriphClkInit->I2c1ClockSelection);
953 }
954 else
955 {
956 /* set overall return value */
957 status = ret;
958 }
959 }
960
961 /*-------------------------- I2C2 clock source configuration ---------------------*/
962 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
963 {
964 /* Check the parameters */
965 assert_param(IS_RCC_I2C2CLKSOURCE(pPeriphClkInit->I2c2ClockSelection));
966
967 switch (pPeriphClkInit->I2c2ClockSelection)
968 {
969 case RCC_I2C2CLKSOURCE_PCLK1: /* PCLK1 is used as clock source for I2C2*/
970
971 /* I2C2 clock source config set later after clock selection check */
972 break;
973
974 #if defined(RCC_I2C2CLKSOURCE_PLL3R)
975 case RCC_I2C2CLKSOURCE_PLL3R: /* PLL3 is used as clock source for I2C2*/
976 /* PLL3 input clock, parameters M, N & R configuration clock output (PLL3ClockOut) */
977 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
978 #else
979 case RCC_I2C2CLKSOURCE_PLL2R: /* PLL32 is used as clock source for I2C2*/
980 /* PLL2 input clock, parameters M, N & R configuration clock output (PLL2ClockOut) */
981 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
982 #endif /* RCC_I2C2CLKSOURCE_PLL3R */
983 /* I2C2 clock source config set later after clock selection check */
984 break;
985
986 case RCC_I2C2CLKSOURCE_HSI: /* HSI clock is used as source of I2C2 clock*/
987 /* I2C2 clock source config set later after clock selection check */
988 break;
989
990 case RCC_I2C2CLKSOURCE_CSI: /* CSI clock is used as source of I2C2 clock*/
991 /* I2C2 clock source config set later after clock selection check */
992 break;
993
994 default:
995 ret = HAL_ERROR;
996 break;
997 }
998
999 if (ret == HAL_OK)
1000 {
1001 /* Set the source of I2C2 clock*/
1002 __HAL_RCC_I2C2_CONFIG(pPeriphClkInit->I2c2ClockSelection);
1003 }
1004 else
1005 {
1006 /* set overall return value */
1007 status = ret;
1008 }
1009 }
1010
1011 #if defined(I2C3)
1012 /*-------------------------- I2C3 clock source configuration ---------------------*/
1013 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
1014 {
1015 /* Check the parameters */
1016 assert_param(IS_RCC_I2C3CLKSOURCE(pPeriphClkInit->I2c3ClockSelection));
1017
1018 switch (pPeriphClkInit->I2c3ClockSelection)
1019 {
1020 case RCC_I2C3CLKSOURCE_PCLK3: /* PCLK3 is used as clock source for I2C3*/
1021
1022 /* I2C3 clock source config set later after clock selection check */
1023 break;
1024
1025 case RCC_I2C3CLKSOURCE_PLL3R: /* PLL3 is used as clock source for I2C3*/
1026 /* PLL3 input clock, parameters M, N & R configuration clock output (PLL3ClockOut) */
1027 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
1028 /* I2C3 clock source config set later after clock selection check */
1029 break;
1030
1031 case RCC_I2C3CLKSOURCE_HSI: /* HSI clock is used as source of I2C3 clock*/
1032 /* I2C3 clock source config set later after clock selection check */
1033 break;
1034
1035 case RCC_I2C3CLKSOURCE_CSI: /* CSI clock is used as source of I2C3 clock*/
1036 /* I2C3 clock source config set later after clock selection check */
1037 break;
1038
1039 default:
1040 ret = HAL_ERROR;
1041 break;
1042 }
1043
1044 if (ret == HAL_OK)
1045 {
1046 /* Set the source of I2C3 clock*/
1047 __HAL_RCC_I2C3_CONFIG(pPeriphClkInit->I2c3ClockSelection);
1048 }
1049 else
1050 {
1051 /* set overall return value */
1052 status = ret;
1053 }
1054 }
1055 #endif /* I2C3 */
1056
1057 #if defined(I2C4)
1058 /*-------------------------- I2C4 clock source configuration ---------------------*/
1059 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
1060 {
1061 /* Check the parameters */
1062 assert_param(IS_RCC_I2C4CLKSOURCE(pPeriphClkInit->I2c4ClockSelection));
1063
1064 switch (pPeriphClkInit->I2c4ClockSelection)
1065 {
1066 case RCC_I2C4CLKSOURCE_PCLK3: /* PCLK3 is used as clock source for I2C4*/
1067
1068 /* I2C4 clock source config set later after clock selection check */
1069 break;
1070
1071 case RCC_I2C4CLKSOURCE_PLL3R: /* PLL3 is used as clock source for I2C4*/
1072 /* PLL3 input clock, parameters M, N & R configuration clock output (PLL3ClockOut) */
1073 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
1074 /* I2C4 clock source config set later after clock selection check */
1075 break;
1076
1077 case RCC_I2C4CLKSOURCE_HSI: /* HSI clock is used as source of I2C4 clock*/
1078 /* I2C4 clock source config set later after clock selection check */
1079 break;
1080
1081 case RCC_I2C4CLKSOURCE_CSI: /* CSI clock is used as source of I2C4 clock*/
1082 /* I2C4 clock source config set later after clock selection check */
1083 break;
1084
1085 default:
1086 ret = HAL_ERROR;
1087 break;
1088 }
1089
1090 if (ret == HAL_OK)
1091 {
1092 /* Set the source of I2C4 clock*/
1093 __HAL_RCC_I2C4_CONFIG(pPeriphClkInit->I2c4ClockSelection);
1094 }
1095 else
1096 {
1097 /* set overall return value */
1098 status = ret;
1099 }
1100 }
1101 #endif /* I2C4 */
1102
1103 /*-------------------------- I3C1 clock source configuration ---------------------*/
1104 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I3C1) == RCC_PERIPHCLK_I3C1)
1105 {
1106 /* Check the parameters */
1107 assert_param(IS_RCC_I3C1CLKSOURCE(pPeriphClkInit->I3c1ClockSelection));
1108
1109 switch (pPeriphClkInit->I3c1ClockSelection)
1110 {
1111 case RCC_I3C1CLKSOURCE_PCLK1: /* PCLK1 is used as clock source for I3C1*/
1112
1113 /* I3C1 clock source config set later after clock selection check */
1114 break;
1115
1116 #if defined(RCC_I3C1CLKSOURCE_PLL3R)
1117 case RCC_I3C1CLKSOURCE_PLL3R: /* PLL3 is used as clock source for I3C1*/
1118 /* PLL3 input clock, parameters M, N & R configuration clock output (PLL3ClockOut) */
1119 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
1120 #else
1121 case RCC_I3C1CLKSOURCE_PLL2R: /* PLL2 is used as clock source for I3C1*/
1122 /* PLL2 input clock, parameters M, N & R configuration clock output (PLL2ClockOut) */
1123 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
1124 #endif /* RCC_I3C1CLKSOURCE_PLL3R */
1125 /* I3C1 clock source config set later after clock selection check */
1126 break;
1127
1128 case RCC_I3C1CLKSOURCE_HSI: /* HSI clock is used as source of I3C1 clock*/
1129 /* I3C1 clock source config set later after clock selection check */
1130 break;
1131
1132 default:
1133 ret = HAL_ERROR;
1134 break;
1135 }
1136
1137 if (ret == HAL_OK)
1138 {
1139 /* Set the source of I3C1 clock*/
1140 __HAL_RCC_I3C1_CONFIG(pPeriphClkInit->I3c1ClockSelection);
1141 }
1142 else
1143 {
1144 /* set overall return value */
1145 status = ret;
1146 }
1147 }
1148
1149 #if defined (I3C2)
1150 /*-------------------------- I3C2 clock source configuration ---------------------*/
1151 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I3C2) == RCC_PERIPHCLK_I3C2)
1152 {
1153 /* Check the parameters */
1154 assert_param(IS_RCC_I3C2CLKSOURCE(pPeriphClkInit->I3c2ClockSelection));
1155
1156 switch (pPeriphClkInit->I3c2ClockSelection)
1157 {
1158 case RCC_I3C2CLKSOURCE_PCLK3: /* PCLK1 is used as clock source for I3C2*/
1159
1160 /* I3C2 clock source config set later after clock selection check */
1161 break;
1162
1163 case RCC_I3C2CLKSOURCE_PLL2R: /* PLL2 is used as clock source for I3C2*/
1164 /* PLL2 input clock, parameters M, N & R configuration clock output (PLL2ClockOut) */
1165 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
1166 /* I3C2 clock source config set later after clock selection check */
1167 break;
1168
1169 case RCC_I3C2CLKSOURCE_HSI: /* HSI clock is used as source of I3C2 clock*/
1170 /* I3C2 clock source config set later after clock selection check */
1171 break;
1172
1173 default:
1174 ret = HAL_ERROR;
1175 break;
1176 }
1177
1178 if (ret == HAL_OK)
1179 {
1180 /* Set the source of I3C2 clock*/
1181 __HAL_RCC_I3C2_CONFIG(pPeriphClkInit->I3c2ClockSelection);
1182 }
1183 else
1184 {
1185 /* set overall return value */
1186 status = ret;
1187 }
1188 }
1189 #endif /* I3C2 */
1190
1191 /*------------------------------------ TIM configuration --------------------------------------*/
1192 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM)
1193 {
1194 /* Check the parameters */
1195 assert_param(IS_RCC_TIMPRES(pPeriphClkInit->TimPresSelection));
1196
1197 /* Configure Timer Prescaler */
1198 __HAL_RCC_TIMCLKPRESCALER(pPeriphClkInit->TimPresSelection);
1199 }
1200
1201 /*-------------------------- LPTIM1 clock source configuration ---------------------*/
1202 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
1203 {
1204 /* Check the parameters */
1205 assert_param(IS_RCC_LPTIM1CLK(pPeriphClkInit->Lptim1ClockSelection));
1206
1207 switch (pPeriphClkInit->Lptim1ClockSelection)
1208 {
1209 case RCC_LPTIM1CLKSOURCE_PCLK3: /* PCLK3 is used as clock source for LPTIM1*/
1210
1211 /* LPTIM1 clock source config set later after clock selection check */
1212 break;
1213
1214 case RCC_LPTIM1CLKSOURCE_PLL2P: /* PLL2 is used as clock source for LPTIM1*/
1215 /* PLL2 P input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */
1216 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
1217 /* LPTIM1 clock source config set later after clock selection check */
1218 break;
1219
1220 #if defined(RCC_LPTIM1CLKSOURCE_PLL3R)
1221 case RCC_LPTIM1CLKSOURCE_PLL3R: /* PLL3 is used as clock source for LPTIM1*/
1222 /* PLL3 R input clock, parameters M, N & R configuration clock output (PLL3ClockOut) */
1223 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
1224 /* LPTIM1 clock source config set later after clock selection check */
1225 break;
1226 #endif /* RCC_LPTIM1CLKSOURCE_PLL3R */
1227
1228 case RCC_LPTIM1CLKSOURCE_LSE: /* LSE clock is used as source of LPTIM1 clock*/
1229 /* LPTIM1 clock source config set later after clock selection check */
1230 break;
1231
1232 case RCC_LPTIM1CLKSOURCE_LSI: /* LSI clock is used as source of LPTIM1 clock*/
1233 /* LPTIM1 clock source config set later after clock selection check */
1234 break;
1235
1236 case RCC_LPTIM1CLKSOURCE_CLKP: /* CLKP is used as source of LPTIM1 clock*/
1237 /* LPTIM1 clock source config set later after clock selection check */
1238 break;
1239
1240 default:
1241 ret = HAL_ERROR;
1242 break;
1243 }
1244
1245 if (ret == HAL_OK)
1246 {
1247 /* Set the source of LPTIM1 clock*/
1248 __HAL_RCC_LPTIM1_CONFIG(pPeriphClkInit->Lptim1ClockSelection);
1249 }
1250 else
1251 {
1252 /* set overall return value */
1253 status = ret;
1254 }
1255 }
1256
1257 /*-------------------------- LPTIM2 clock source configuration ---------------------*/
1258 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2)
1259 {
1260 /* Check the parameters */
1261 assert_param(IS_RCC_LPTIM2CLK(pPeriphClkInit->Lptim2ClockSelection));
1262
1263 switch (pPeriphClkInit->Lptim2ClockSelection)
1264 {
1265 case RCC_LPTIM2CLKSOURCE_PCLK1: /* PCLK1 is used as clock source for LPTIM2*/
1266
1267 /* LPTIM2 clock source config set later after clock selection check */
1268 break;
1269
1270 case RCC_LPTIM2CLKSOURCE_PLL2P: /* PLL2 is used as clock source for LPTIM2*/
1271 /* PLL2 P input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */
1272 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
1273 /* LPTIM2 clock source config set later after clock selection check */
1274 break;
1275
1276 #if defined(RCC_LPTIM2CLKSOURCE_PLL3R)
1277 case RCC_LPTIM2CLKSOURCE_PLL3R: /* PLL3 is used as clock source for LPTIM2*/
1278 /* PLL3 R input clock, parameters M, N & R configuration clock output (PLL3ClockOut) */
1279 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
1280 /* LPTIM2 clock source config set later after clock selection check */
1281 break;
1282 #endif /* RCC_LPTIM2CLKSOURCE_PLL3R */
1283
1284 case RCC_LPTIM2CLKSOURCE_LSE: /* LSE clock is used as source of LPTIM2 clock*/
1285 /* LPTIM2 clock source config set later after clock selection check */
1286 break;
1287
1288 case RCC_LPTIM2CLKSOURCE_LSI: /* LSI clock is used as source of LPTIM2 clock*/
1289 /* LPTIM2 clock source config set later after clock selection check */
1290 break;
1291
1292 case RCC_LPTIM2CLKSOURCE_CLKP: /* CLKP is used as source of LPTIM2 clock*/
1293 /* LPTIM2 clock source config set later after clock selection check */
1294 break;
1295
1296 default:
1297 ret = HAL_ERROR;
1298 break;
1299 }
1300
1301 if (ret == HAL_OK)
1302 {
1303 /* Set the source of LPTIM2 clock*/
1304 __HAL_RCC_LPTIM2_CONFIG(pPeriphClkInit->Lptim2ClockSelection);
1305 }
1306 else
1307 {
1308 /* set overall return value */
1309 status = ret;
1310 }
1311 }
1312
1313 #if defined(LPTIM3)
1314 /*-------------------------- LPTIM3 clock source configuration ---------------------*/
1315 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM3) == RCC_PERIPHCLK_LPTIM3)
1316 {
1317 /* Check the parameters */
1318 assert_param(IS_RCC_LPTIM3CLK(pPeriphClkInit->Lptim3ClockSelection));
1319
1320 switch (pPeriphClkInit->Lptim3ClockSelection)
1321 {
1322 case RCC_LPTIM3CLKSOURCE_PCLK3: /* PCLK3 is used as clock source for LPTIM3*/
1323
1324 /* LPTIM3 clock source config set later after clock selection check */
1325 break;
1326
1327 case RCC_LPTIM3CLKSOURCE_PLL2P: /* PLL2 is used as clock source for LPTIM3*/
1328 /* PLL2 P input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */
1329 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
1330 /* LPTIM3 clock source config set later after clock selection check */
1331 break;
1332
1333 case RCC_LPTIM3CLKSOURCE_PLL3R: /* PLL3 is used as clock source for LPTIM3*/
1334 /* PLL3 R input clock, parameters M, N & R configuration clock output (PLL3ClockOut) */
1335 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
1336 /* LPTIM3 clock source config set later after clock selection check */
1337 break;
1338
1339 case RCC_LPTIM3CLKSOURCE_LSE: /* LSE clock is used as source of LPTIM3 clock*/
1340 /* LPTIM3 clock source config set later after clock selection check */
1341 break;
1342
1343 case RCC_LPTIM3CLKSOURCE_LSI: /* LSI clock is used as source of LPTIM3 clock*/
1344 /* LPTIM3 clock source config set later after clock selection check */
1345 break;
1346
1347 case RCC_LPTIM3CLKSOURCE_CLKP: /* CLKP is used as source of LPTIM3 clock*/
1348 /* LPTIM3 clock source config set later after clock selection check */
1349 break;
1350
1351 default:
1352 ret = HAL_ERROR;
1353 break;
1354 }
1355
1356 if (ret == HAL_OK)
1357 {
1358 /* Set the source of LPTIM3 clock*/
1359 __HAL_RCC_LPTIM3_CONFIG(pPeriphClkInit->Lptim3ClockSelection);
1360 }
1361 else
1362 {
1363 /* set overall return value */
1364 status = ret;
1365 }
1366 }
1367 #endif /* LPTIM3 */
1368
1369 #if defined(LPTIM4)
1370 /*-------------------------- LPTIM4 clock source configuration ---------------------*/
1371 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM4) == RCC_PERIPHCLK_LPTIM4)
1372 {
1373 /* Check the parameters */
1374 assert_param(IS_RCC_LPTIM4CLK(pPeriphClkInit->Lptim4ClockSelection));
1375
1376 switch (pPeriphClkInit->Lptim4ClockSelection)
1377 {
1378 case RCC_LPTIM4CLKSOURCE_PCLK3: /* PCLK3 is used as clock source for LPTIM4*/
1379
1380 /* LPTIM4 clock source config set later after clock selection check */
1381 break;
1382
1383 case RCC_LPTIM4CLKSOURCE_PLL2P: /* PLL2 is used as clock source for LPTIM4*/
1384 /* PLL2 P input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */
1385 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
1386 /* LPTIM4 clock source config set later after clock selection check */
1387 break;
1388
1389 case RCC_LPTIM4CLKSOURCE_PLL3R: /* PLL3 is used as clock source for LPTIM4*/
1390 /* PLL3 R input clock, parameters M, N & R configuration clock output (PLL3ClockOut) */
1391 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
1392 /* LPTIM4 clock source config set later after clock selection check */
1393 break;
1394
1395 case RCC_LPTIM4CLKSOURCE_LSE: /* LSE clock is used as source of LPTIM4 clock*/
1396 /* LPTIM4 clock source config set later after clock selection check */
1397 break;
1398
1399 case RCC_LPTIM4CLKSOURCE_LSI: /* LSI clock is used as source of LPTIM4 clock*/
1400 /* LPTIM4 clock source config set later after clock selection check */
1401 break;
1402
1403 case RCC_LPTIM4CLKSOURCE_CLKP: /* CLKP is used as source of LPTIM4 clock*/
1404 /* LPTIM4 clock source config set later after clock selection check */
1405 break;
1406
1407 default:
1408 ret = HAL_ERROR;
1409 break;
1410 }
1411
1412 if (ret == HAL_OK)
1413 {
1414 /* Set the source of LPTIM4 clock*/
1415 __HAL_RCC_LPTIM4_CONFIG(pPeriphClkInit->Lptim4ClockSelection);
1416 }
1417 else
1418 {
1419 /* set overall return value */
1420 status = ret;
1421 }
1422 }
1423 #endif /* LPTIM4 */
1424
1425 #if defined(LPTIM5)
1426 /*-------------------------- LPTIM5 clock source configuration ---------------------*/
1427 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM5) == RCC_PERIPHCLK_LPTIM5)
1428 {
1429 /* Check the parameters */
1430 assert_param(IS_RCC_LPTIM5CLK(pPeriphClkInit->Lptim5ClockSelection));
1431
1432 switch (pPeriphClkInit->Lptim5ClockSelection)
1433 {
1434 case RCC_LPTIM5CLKSOURCE_PCLK3: /* PCLK3 is used as clock source for LPTIM5*/
1435
1436 /* LPTIM5 clock source config set later after clock selection check */
1437 break;
1438
1439 case RCC_LPTIM5CLKSOURCE_PLL2P: /* PLL2 is used as clock source for LPTIM5*/
1440 /* PLL2 P input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */
1441 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
1442 /* LPTIM5 clock source config set later after clock selection check */
1443 break;
1444
1445 case RCC_LPTIM5CLKSOURCE_PLL3R: /* PLL3 is used as clock source for LPTIM5*/
1446 /* PLL3 R input clock, parameters M, N & R configuration clock output (PLL3ClockOut) */
1447 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
1448 /* LPTIM5 clock source config set later after clock selection check */
1449 break;
1450
1451 case RCC_LPTIM5CLKSOURCE_LSE: /* LSE clock is used as source of LPTIM5 clock*/
1452 /* LPTIM5 clock source config set later after clock selection check */
1453 break;
1454
1455 case RCC_LPTIM5CLKSOURCE_LSI: /* LSI clock is used as source of LPTIM5 clock*/
1456 /* LPTIM5 clock source config set later after clock selection check */
1457 break;
1458
1459 case RCC_LPTIM5CLKSOURCE_CLKP: /* CLKP is used as source of LPTIM5 clock*/
1460 /* LPTIM5 clock source config set later after clock selection check */
1461 break;
1462
1463 default:
1464 ret = HAL_ERROR;
1465 break;
1466 }
1467
1468 if (ret == HAL_OK)
1469 {
1470 /* Set the source of LPTIM5 clock*/
1471 __HAL_RCC_LPTIM5_CONFIG(pPeriphClkInit->Lptim5ClockSelection);
1472 }
1473 else
1474 {
1475 /* set overall return value */
1476 status = ret;
1477 }
1478 }
1479 #endif /* LPTIM5 */
1480
1481 #if defined(LPTIM6)
1482 /*-------------------------- LPTIM6 clock source configuration ---------------------*/
1483 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM6) == RCC_PERIPHCLK_LPTIM6)
1484 {
1485 /* Check the parameters */
1486 assert_param(IS_RCC_LPTIM6CLK(pPeriphClkInit->Lptim6ClockSelection));
1487
1488 switch (pPeriphClkInit->Lptim6ClockSelection)
1489 {
1490 case RCC_LPTIM6CLKSOURCE_PCLK3: /* PCLK3 is used as clock source for LPTIM6*/
1491
1492 /* LPTIM6 clock source config set later after clock selection check */
1493 break;
1494
1495 case RCC_LPTIM6CLKSOURCE_PLL2P: /* PLL2 is used as clock source for LPTIM6*/
1496 /* PLL2 P input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */
1497 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
1498 /* LPTIM6 clock source config set later after clock selection check */
1499 break;
1500
1501 case RCC_LPTIM6CLKSOURCE_PLL3R: /* PLL3 is used as clock source for LPTIM6*/
1502 /* PLL3 R input clock, parameters M, N & R configuration clock output (PLL3ClockOut) */
1503 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
1504 /* LPTIM6 clock source config set later after clock selection check */
1505 break;
1506
1507 case RCC_LPTIM6CLKSOURCE_LSE: /* LSE clock is used as source of LPTIM6 clock*/
1508 /* LPTIM6 clock source config set later after clock selection check */
1509 break;
1510
1511 case RCC_LPTIM6CLKSOURCE_LSI: /* LSI clock is used as source of LPTIM6 clock*/
1512 /* LPTIM6 clock source config set later after clock selection check */
1513 break;
1514
1515 case RCC_LPTIM6CLKSOURCE_CLKP: /* CLKP is used as source of LPTIM6 clock*/
1516 /* LPTIM6 clock source config set later after clock selection check */
1517 break;
1518
1519 default:
1520 ret = HAL_ERROR;
1521 break;
1522 }
1523
1524 if (ret == HAL_OK)
1525 {
1526 /* Set the source of LPTIM6 clock*/
1527 __HAL_RCC_LPTIM6_CONFIG(pPeriphClkInit->Lptim6ClockSelection);
1528 }
1529 else
1530 {
1531 /* set overall return value */
1532 status = ret;
1533 }
1534 }
1535 #endif /* LPTIM6 */
1536
1537 #if defined(SAI1)
1538 /*-------------------------- SAI1 clock source configuration ---------------------*/
1539 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)
1540 {
1541 /* Check the parameters */
1542 assert_param(IS_RCC_SAI1CLK(pPeriphClkInit->Sai1ClockSelection));
1543
1544 switch (pPeriphClkInit->Sai1ClockSelection)
1545 {
1546 case RCC_SAI1CLKSOURCE_PLL1Q: /* PLL is used as clock source for SAI1*/
1547 /* Enable SAI Clock output generated from System PLL . */
1548 __HAL_RCC_PLL1_CLKOUT_ENABLE(RCC_PLL1_DIVQ);
1549 /* SAI1 clock source config set later after clock selection check */
1550 break;
1551
1552 case RCC_SAI1CLKSOURCE_PLL2P: /* PLL2 is used as clock source for SAI1*/
1553 /* PLL2 P input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */
1554 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
1555 /* SAI1 clock source config set later after clock selection check */
1556 break;
1557
1558 case RCC_SAI1CLKSOURCE_PLL3P: /* PLL3 is used as clock source for SAI1*/
1559 /* PLL3 P input clock, parameters M, N & P configuration clock output (PLL3ClockOut) */
1560 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
1561 /* SAI1 clock source config set later after clock selection check */
1562 break;
1563
1564 case RCC_SAI1CLKSOURCE_PIN: /* External clock is used as source of SAI1 clock*/
1565 break;
1566
1567 case RCC_SAI1CLKSOURCE_CLKP: /* CLKP is used as source of SAI1 clock*/
1568 /* SAI1 clock source config set later after clock selection check */
1569 break;
1570
1571 default:
1572 ret = HAL_ERROR;
1573 break;
1574 }
1575
1576 if (ret == HAL_OK)
1577 {
1578 /* Set the source of SAI1 clock*/
1579 __HAL_RCC_SAI1_CONFIG(pPeriphClkInit->Sai1ClockSelection);
1580 }
1581 else
1582 {
1583 /* set overall return value */
1584 status = ret;
1585 }
1586 }
1587 #endif /* SAI1*/
1588
1589 #if defined(SAI2)
1590 /*-------------------------- SAI2 clock source configuration ---------------------*/
1591 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2)
1592 {
1593 /* Check the parameters */
1594 assert_param(IS_RCC_SAI2CLK(pPeriphClkInit->Sai2ClockSelection));
1595
1596 switch (pPeriphClkInit->Sai2ClockSelection)
1597 {
1598 case RCC_SAI2CLKSOURCE_PLL1Q: /* PLL is used as clock source for SAI2*/
1599 /* Enable SAI Clock output generated from System PLL . */
1600 __HAL_RCC_PLL1_CLKOUT_ENABLE(RCC_PLL1_DIVQ);
1601 /* SAI2 clock source config set later after clock selection check */
1602 break;
1603
1604 case RCC_SAI2CLKSOURCE_PLL2P: /* PLL2 is used as clock source for SAI2*/
1605 /* PLL2 P input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */
1606 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
1607 /* SAI2 clock source config set later after clock selection check */
1608 break;
1609
1610 case RCC_SAI2CLKSOURCE_PLL3P: /* PLL3 is used as clock source for SAI2*/
1611 /* PLL3 P input clock, parameters M, N & P configuration and clock output (PLL3ClockOut) */
1612 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
1613 /* SAI2 clock source config set later after clock selection check */
1614 break;
1615
1616 case RCC_SAI2CLKSOURCE_PIN: /* External clock is used as source of SAI2 clock*/
1617 case RCC_SAI2CLKSOURCE_CLKP: /* CLKP is used as source of SAI2 clock*/
1618 /* SAI2 clock source config set later after clock selection check */
1619 break;
1620
1621 default:
1622 ret = HAL_ERROR;
1623 break;
1624 }
1625
1626 if (ret == HAL_OK)
1627 {
1628 /* Set the source of SAI2 clock*/
1629 __HAL_RCC_SAI2_CONFIG(pPeriphClkInit->Sai2ClockSelection);
1630 }
1631 else
1632 {
1633 /* set overall return value */
1634 status = ret;
1635 }
1636 }
1637 #endif /* SAI2*/
1638
1639 /*-------------------------- ADCDAC clock source configuration ----------------------*/
1640 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADCDAC) == RCC_PERIPHCLK_ADCDAC)
1641 {
1642 /* Check the parameters */
1643 assert_param(IS_RCC_ADCDACCLKSOURCE(pPeriphClkInit->AdcDacClockSelection));
1644
1645 switch (pPeriphClkInit->AdcDacClockSelection)
1646 {
1647
1648 case RCC_ADCDACCLKSOURCE_HCLK: /* Bus clock is used as source of ADCDAC clock*/
1649 case RCC_ADCDACCLKSOURCE_SYSCLK: /* System clock is used as source of ADCDAC clock*/
1650 /* ADCDAC clock source config set later after clock selection check */
1651 break;
1652
1653 case RCC_ADCDACCLKSOURCE_PLL2R:
1654 /* PLL2 input clock, parameters M, N & R configuration and clock output (PLL2ClockOut) */
1655 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
1656 break;
1657
1658 case RCC_ADCDACCLKSOURCE_HSE:/* HSE clock is used as source of ADCDAC clock*/
1659 case RCC_ADCDACCLKSOURCE_HSI:/* HSI clock is used as source of ADCDAC clock*/
1660 case RCC_ADCDACCLKSOURCE_CSI:/* CSI clock is used as source of ADCDAC clock*/
1661 /* ADCDAC clock source configuration done later after clock selection check */
1662 break;
1663
1664
1665 default:
1666 ret = HAL_ERROR;
1667 break;
1668 }
1669
1670 if (ret == HAL_OK)
1671 {
1672 /* Configure the ADCDAC interface clock source */
1673 __HAL_RCC_ADCDAC_CONFIG(pPeriphClkInit->AdcDacClockSelection);
1674 }
1675 else
1676 {
1677 /* set overall return value */
1678 status = ret;
1679 }
1680
1681 }
1682
1683 /*-------------------------- DAC low-power clock source configuration ----------------------*/
1684 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DAC_LP) == RCC_PERIPHCLK_DAC_LP)
1685 {
1686 /* Check the parameters */
1687 assert_param(IS_RCC_DACLPCLKSOURCE(pPeriphClkInit->DacLowPowerClockSelection));
1688
1689 switch (pPeriphClkInit->DacLowPowerClockSelection)
1690 {
1691
1692 case RCC_DACLPCLKSOURCE_LSE:
1693 /* LSE oscillator is used as source of DAC low-power clock */
1694 /* DAC clock source configuration done later after clock selection check */
1695 break;
1696
1697 case RCC_DACLPCLKSOURCE_LSI:
1698 /* LSI is used as clock source for DAC low-power clock */
1699 /* DAC clock source configuration done later after clock selection check */
1700 break;
1701
1702 default:
1703 ret = HAL_ERROR;
1704 break;
1705 }
1706
1707 if (ret == HAL_OK)
1708 {
1709 /* Configure the DAC low-power interface clock source */
1710 __HAL_RCC_DAC_LP_CONFIG(pPeriphClkInit->DacLowPowerClockSelection);
1711 }
1712 else
1713 {
1714 /* set overall return value */
1715 status = ret;
1716 }
1717
1718 }
1719
1720 /*-------------------------- RTC clock source configuration ----------------------*/
1721 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
1722 {
1723
1724 /* Check for RTC Parameters used to output RTCCLK */
1725 assert_param(IS_RCC_RTCCLKSOURCE(pPeriphClkInit->RTCClockSelection));
1726
1727 /* Enable write access to Backup domain */
1728 SET_BIT(PWR->DBPCR, PWR_DBPCR_DBP);
1729
1730 /* Wait for Backup domain Write protection disable */
1731 tickstart = HAL_GetTick();
1732
1733 while (HAL_IS_BIT_CLR(PWR->DBPCR, PWR_DBPCR_DBP))
1734 {
1735 if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
1736 {
1737 ret = HAL_TIMEOUT;
1738 break;
1739 }
1740 }
1741
1742 if (ret == HAL_OK)
1743 {
1744 /* Reset the Backup domain only if the RTC Clock source selection is modified from default */
1745 tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL);
1746
1747 if ((tmpregister != RCC_RTCCLKSOURCE_NO_CLK) && (tmpregister != pPeriphClkInit->RTCClockSelection))
1748 {
1749 /* Store the content of BDCR register before the reset of Backup Domain */
1750 tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL));
1751 /* RTC Clock selection can be changed only if the Backup Domain is reset */
1752 __HAL_RCC_BACKUPRESET_FORCE();
1753 __HAL_RCC_BACKUPRESET_RELEASE();
1754 /* Restore the Content of BDCR register */
1755 RCC->BDCR = tmpregister;
1756 }
1757
1758 /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
1759 if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON))
1760 {
1761 /* Get Start Tick*/
1762 tickstart = HAL_GetTick();
1763
1764 /* Wait till LSE is ready */
1765 while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
1766 {
1767 if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
1768 {
1769 ret = HAL_TIMEOUT;
1770 break;
1771 }
1772 }
1773 }
1774
1775 if (ret == HAL_OK)
1776 {
1777 /* Apply new RTC clock source selection */
1778 __HAL_RCC_RTC_CONFIG(pPeriphClkInit->RTCClockSelection);
1779 }
1780 else
1781 {
1782 /* set overall return value */
1783 status = ret;
1784 }
1785 }
1786 else
1787 {
1788 /* set overall return value */
1789 status = ret;
1790 }
1791
1792 }
1793
1794 /*------------------------------ RNG Configuration -------------------------*/
1795 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG)
1796 {
1797
1798 /* Check the parameters */
1799 assert_param(IS_RCC_RNGCLKSOURCE(pPeriphClkInit->RngClockSelection));
1800
1801 switch (pPeriphClkInit->RngClockSelection)
1802 {
1803
1804 case RCC_RNGCLKSOURCE_HSI48: /* HSI48 is used as clock source for RNG*/
1805
1806 /* RNG clock source configuration done later after clock selection check */
1807 break;
1808
1809 case RCC_RNGCLKSOURCE_PLL1Q: /* PLL1 is used as clock source for RNG*/
1810 /* Enable PLL1Q Clock output generated from System PLL . */
1811 __HAL_RCC_PLL1_CLKOUT_ENABLE(RCC_PLL1_DIVQ);
1812 /* RNG clock source configuration done later after clock selection check */
1813 break;
1814 case RCC_RNGCLKSOURCE_LSE:
1815 /* LSE oscillator is used as source of RNG clock */
1816 /* RNG clock source configuration done later after clock selection check */
1817 break;
1818
1819 case RCC_RNGCLKSOURCE_LSI: /* HSI48 is used as clock source for RNG*/
1820
1821 /* RNG clock source configuration done later after clock selection check */
1822 break;
1823
1824 default:
1825 ret = HAL_ERROR;
1826 break;
1827 }
1828
1829 if (ret == HAL_OK)
1830 {
1831 /* Set the source of RNG clock*/
1832 __HAL_RCC_RNG_CONFIG(pPeriphClkInit->RngClockSelection);
1833 }
1834 else
1835 {
1836 /* set overall return value */
1837 status = ret;
1838 }
1839
1840 }
1841
1842 #if defined(SDMMC1)
1843 /*-------------------------- SDMMC1 clock source configuration -------------------*/
1844 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)
1845 {
1846
1847 /* Check the parameters */
1848 assert_param(IS_RCC_SDMMC1CLKSOURCE(pPeriphClkInit->Sdmmc1ClockSelection));
1849
1850 switch (pPeriphClkInit->Sdmmc1ClockSelection)
1851 {
1852 case RCC_SDMMC1CLKSOURCE_PLL1Q: /* PLL1 is used as clock source for SDMMC1 kernel clock*/
1853 /* Enable PLL1Q Clock output generated from System PLL . */
1854 __HAL_RCC_PLL1_CLKOUT_ENABLE(RCC_PLL1_DIVQ);
1855 /* SDMMC1 kernel clock source config set later after clock selection check */
1856 break;
1857
1858 case RCC_SDMMC1CLKSOURCE_PLL2R: /* PLL2 is used as clock source for SDMMC1 kernel clock*/
1859 /* PLL2R input clock, parameters M, N & R configuration and clock output (PLL2ClockOut) */
1860 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
1861 /* SDMMC1 kernel clock source config set later after clock selection check */
1862 break;
1863
1864 default:
1865 ret = HAL_ERROR;
1866 break;
1867 }
1868
1869 if (ret == HAL_OK)
1870 {
1871 /* Configure the SDMMC1 clock source */
1872 __HAL_RCC_SDMMC1_CONFIG(pPeriphClkInit->Sdmmc1ClockSelection);
1873 }
1874 else
1875 {
1876 /* set overall return value */
1877 status = ret;
1878 }
1879
1880 }
1881 #endif /* SDMMC1 */
1882
1883 #if defined(SDMMC2)
1884 /*-------------------------- SDMMC2 clock source configuration -------------------*/
1885 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2)
1886 {
1887
1888 /* Check the parameters */
1889 assert_param(IS_RCC_SDMMC2CLKSOURCE(pPeriphClkInit->Sdmmc2ClockSelection));
1890
1891 switch (pPeriphClkInit->Sdmmc2ClockSelection)
1892 {
1893 case RCC_SDMMC2CLKSOURCE_PLL1Q: /* PLL1 is used as clock source for SDMMC2 kernel clock*/
1894 /* Enable PLL1Q Clock output generated from System PLL . */
1895 __HAL_RCC_PLL1_CLKOUT_ENABLE(RCC_PLL1_DIVQ);
1896 /* SDMMC2 kernel clock source config set later after clock selection check */
1897 break;
1898
1899 case RCC_SDMMC2CLKSOURCE_PLL2R: /* PLL2 is used as clock source for SDMMC2 kernel clock*/
1900 /* PLL2R input clock, parameters M, N & R configuration and clock output (PLL2ClockOut) */
1901 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
1902 /* SDMMC2 kernel clock source config set later after clock selection check */
1903 break;
1904
1905 default:
1906 ret = HAL_ERROR;
1907 break;
1908 }
1909
1910 if (ret == HAL_OK)
1911 {
1912 /* Configure the SDMMC2 clock source */
1913 __HAL_RCC_SDMMC2_CONFIG(pPeriphClkInit->Sdmmc2ClockSelection);
1914 }
1915 else
1916 {
1917 /* set overall return value */
1918 status = ret;
1919 }
1920
1921 }
1922 #endif /* SDMMC2 */
1923
1924 /*-------------------------- SPI1 clock source configuration ----------------*/
1925 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI1) == RCC_PERIPHCLK_SPI1)
1926 {
1927
1928 /* Check the parameters */
1929 assert_param(IS_RCC_SPI1CLKSOURCE(pPeriphClkInit->Spi1ClockSelection));
1930
1931 switch (pPeriphClkInit->Spi1ClockSelection)
1932 {
1933 case RCC_SPI1CLKSOURCE_PLL1Q: /* PLL1 is used as clock source for SPI1 */
1934 /* Enable SPI Clock output generated from System PLL . */
1935 __HAL_RCC_PLL1_CLKOUT_ENABLE(RCC_PLL1_DIVQ);
1936
1937 /* SPI1 clock source configuration done later after clock selection check */
1938 break;
1939
1940 case RCC_SPI1CLKSOURCE_PLL2P: /* PLL2 is used as clock source for SPI1*/
1941 /* PLL2 P input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */
1942 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
1943
1944 /* SPI1 clock source configuration done later after clock selection check */
1945 break;
1946
1947 #if defined(RCC_SPI1CLKSOURCE_PLL3P)
1948 case RCC_SPI1CLKSOURCE_PLL3P: /* PLL3 is used as clock source for SPI1 */
1949 /* PLL3 P input clock, parameters M, N & P configuration and clock output (PLL3ClockOut) */
1950 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
1951
1952 /* SPI1 clock source configuration done later after clock selection check */
1953 break;
1954 #endif /* RCC_SPI1CLKSOURCE_PLL3P */
1955
1956 case RCC_SPI1CLKSOURCE_PIN:
1957 /* External clock is used as source of SPI1 clock*/
1958 /* SPI1 clock source configuration done later after clock selection check */
1959 break;
1960
1961 case RCC_SPI1CLKSOURCE_CLKP:
1962 /* HSI, HSE, or CSI oscillator is used as source of SPI1 clock */
1963 /* SPI1 clock source configuration done later after clock selection check */
1964 break;
1965
1966 default:
1967 ret = HAL_ERROR;
1968 break;
1969 }
1970
1971 if (ret == HAL_OK)
1972 {
1973 /* Configure the SPI1 clock source */
1974 __HAL_RCC_SPI1_CONFIG(pPeriphClkInit->Spi1ClockSelection);
1975 }
1976 else
1977 {
1978 /* set overall return value */
1979 status = ret;
1980 }
1981
1982 }
1983
1984 /*-------------------------- SPI2 clock source configuration ----------------*/
1985 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI2) == RCC_PERIPHCLK_SPI2)
1986 {
1987
1988 /* Check the parameters */
1989 assert_param(IS_RCC_SPI2CLKSOURCE(pPeriphClkInit->Spi2ClockSelection));
1990
1991 switch (pPeriphClkInit->Spi2ClockSelection)
1992 {
1993 case RCC_SPI2CLKSOURCE_PLL1Q: /* PLL1 is used as clock source for SPI2 */
1994 /* Enable SPI Clock output generated from System PLL . */
1995 __HAL_RCC_PLL1_CLKOUT_ENABLE(RCC_PLL1_DIVQ);
1996
1997 /* SPI2 clock source configuration done later after clock selection check */
1998 break;
1999
2000 case RCC_SPI2CLKSOURCE_PLL2P: /* PLL2 is used as clock source for SPI2*/
2001 /* PLL2 P input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */
2002 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
2003
2004 /* SPI2 clock source configuration done later after clock selection check */
2005 break;
2006
2007 #if defined(RCC_SPI2CLKSOURCE_PLL3P)
2008 case RCC_SPI2CLKSOURCE_PLL3P: /* PLL3 is used as clock source for SPI2 */
2009 /* PLL3 P input clock, parameters M, N & P configuration and clock output (PLL3ClockOut) */
2010 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
2011
2012 /* SPI2 clock source configuration done later after clock selection check */
2013 break;
2014 #endif /* RCC_SPI2CLKSOURCE_PLL3P */
2015
2016 case RCC_SPI2CLKSOURCE_PIN:
2017 /* External clock is used as source of SPI2 clock*/
2018 /* SPI2 clock source configuration done later after clock selection check */
2019 break;
2020
2021 case RCC_SPI2CLKSOURCE_CLKP:
2022 /* HSI, HSE, or CSI oscillator is used as source of SPI2 clock */
2023 /* SPI2 clock source configuration done later after clock selection check */
2024 break;
2025
2026 default:
2027 ret = HAL_ERROR;
2028 break;
2029 }
2030
2031 if (ret == HAL_OK)
2032 {
2033 /* Configure the SPI2 clock source */
2034 __HAL_RCC_SPI2_CONFIG(pPeriphClkInit->Spi2ClockSelection);
2035 }
2036 else
2037 {
2038 /* set overall return value */
2039 status = ret;
2040 }
2041
2042 }
2043
2044 /*-------------------------- SPI3 clock source configuration ----------------*/
2045 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI3) == RCC_PERIPHCLK_SPI3)
2046 {
2047
2048 /* Check the parameters */
2049 assert_param(IS_RCC_SPI3CLKSOURCE(pPeriphClkInit->Spi3ClockSelection));
2050
2051 switch (pPeriphClkInit->Spi3ClockSelection)
2052 {
2053 case RCC_SPI3CLKSOURCE_PLL1Q: /* PLL1 is used as clock source for SPI3 */
2054 /* Enable SPI Clock output generated from System PLL . */
2055 __HAL_RCC_PLL1_CLKOUT_ENABLE(RCC_PLL1_DIVQ);
2056
2057 /* SPI3 clock source configuration done later after clock selection check */
2058 break;
2059
2060 case RCC_SPI3CLKSOURCE_PLL2P: /* PLL2 is used as clock source for SPI3*/
2061 /* PLL2 P input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */
2062 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
2063
2064 /* SPI3 clock source configuration done later after clock selection check */
2065 break;
2066
2067 #if defined(RCC_SPI3CLKSOURCE_PLL3P)
2068 case RCC_SPI3CLKSOURCE_PLL3P: /* PLL3 is used as clock source for SPI3 */
2069 /* PLL3 P input clock, parameters M, N & P configuration and clock output (PLL3ClockOut) */
2070 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
2071
2072 /* SPI3 clock source configuration done later after clock selection check */
2073 break;
2074 #endif /* RCC_SPI3CLKSOURCE_PLL3P */
2075
2076 case RCC_SPI3CLKSOURCE_PIN:
2077 /* External clock is used as source of SPI3 clock*/
2078 /* SPI3 clock source configuration done later after clock selection check */
2079 break;
2080
2081 case RCC_SPI3CLKSOURCE_CLKP:
2082 /* HSI, HSE, or CSI oscillator is used as source of SPI3 clock */
2083 /* SPI3 clock source configuration done later after clock selection check */
2084 break;
2085
2086 default:
2087 ret = HAL_ERROR;
2088 break;
2089 }
2090
2091 if (ret == HAL_OK)
2092 {
2093 /* Configure the SPI3 clock source */
2094 __HAL_RCC_SPI3_CONFIG(pPeriphClkInit->Spi3ClockSelection);
2095 }
2096 else
2097 {
2098 /* set overall return value */
2099 status = ret;
2100 }
2101
2102 }
2103
2104 #if defined(SPI4)
2105 /*-------------------------- SPI4 clock source configuration ----------------*/
2106 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI4) == RCC_PERIPHCLK_SPI4)
2107 {
2108
2109 /* Check the parameters */
2110 assert_param(IS_RCC_SPI4CLKSOURCE(pPeriphClkInit->Spi4ClockSelection));
2111
2112 switch (pPeriphClkInit->Spi4ClockSelection)
2113 {
2114 case RCC_SPI4CLKSOURCE_PCLK2: /* PCLK2 (APB2 Clock) is used as clock source for SPI4 */
2115 /* SPI4 clock source configuration done later after clock selection check */
2116 break;
2117
2118 case RCC_SPI4CLKSOURCE_PLL2Q: /* PLL2 is used as clock source for SPI4*/
2119 /* PLL2 Q input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */
2120 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
2121
2122 /* SPI4 clock source configuration done later after clock selection check */
2123 break;
2124
2125 case RCC_SPI4CLKSOURCE_PLL3Q: /* PLL3 is used as clock source for SPI4 */
2126 /* PLL3 Q input clock, parameters M, N & P configuration and clock output (PLL3ClockOut) */
2127 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
2128
2129 /* SPI4 clock source configuration done later after clock selection check */
2130 break;
2131
2132 case RCC_SPI4CLKSOURCE_HSI:
2133 /* HSI oscillator is used as source of SPI4 clock*/
2134 /* SPI4 clock source configuration done later after clock selection check */
2135 break;
2136
2137 case RCC_SPI4CLKSOURCE_CSI:
2138 /* CSI oscillator is used as source of SPI4 clock */
2139 /* SPI4 clock source configuration done later after clock selection check */
2140 break;
2141
2142 case RCC_SPI4CLKSOURCE_HSE:
2143 /* HSE oscillator is used as source of SPI4 clock */
2144 /* SPI4 clock source configuration done later after clock selection check */
2145 break;
2146
2147 default:
2148 ret = HAL_ERROR;
2149 break;
2150 }
2151
2152 if (ret == HAL_OK)
2153 {
2154 /* Configure the SPI4 clock source */
2155 __HAL_RCC_SPI4_CONFIG(pPeriphClkInit->Spi4ClockSelection);
2156 }
2157 else
2158 {
2159 /* set overall return value */
2160 status = ret;
2161 }
2162
2163 }
2164 #endif /* SPI4 */
2165
2166 #if defined(SPI5)
2167 /*-------------------------- SPI5 clock source configuration ----------------*/
2168 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI5) == RCC_PERIPHCLK_SPI5)
2169 {
2170
2171 /* Check the parameters */
2172 assert_param(IS_RCC_SPI5CLKSOURCE(pPeriphClkInit->Spi5ClockSelection));
2173
2174 switch (pPeriphClkInit->Spi5ClockSelection)
2175 {
2176 case RCC_SPI5CLKSOURCE_PCLK3: /* PCLK3 (APB3 Clock) is used as clock source for SPI5 */
2177 /* SPI5 clock source configuration done later after clock selection check */
2178 break;
2179
2180 case RCC_SPI5CLKSOURCE_PLL2Q: /* PLL2 is used as clock source for SPI5*/
2181 /* PLL2 Q input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */
2182 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
2183
2184 /* SPI5 clock source configuration done later after clock selection check */
2185 break;
2186
2187 case RCC_SPI5CLKSOURCE_PLL3Q: /* PLL3 is used as clock source for SPI5 */
2188 /* PLL3 Q input clock, parameters M, N & P configuration and clock output (PLL3ClockOut) */
2189 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
2190
2191 /* SPI5 clock source configuration done later after clock selection check */
2192 break;
2193
2194 case RCC_SPI5CLKSOURCE_HSI:
2195 /* HSI oscillator is used as source of SPI5 clock*/
2196 /* SPI5 clock source configuration done later after clock selection check */
2197 break;
2198
2199 case RCC_SPI5CLKSOURCE_CSI:
2200 /* CSI oscillator is used as source of SPI5 clock */
2201 /* SPI5 clock source configuration done later after clock selection check */
2202 break;
2203
2204 case RCC_SPI5CLKSOURCE_HSE:
2205 /* HSE oscillator is used as source of SPI5 clock */
2206 /* SPI5 clock source configuration done later after clock selection check */
2207 break;
2208
2209 default:
2210 ret = HAL_ERROR;
2211 break;
2212 }
2213
2214 if (ret == HAL_OK)
2215 {
2216 /* Configure the SPI5 clock source */
2217 __HAL_RCC_SPI5_CONFIG(pPeriphClkInit->Spi5ClockSelection);
2218 }
2219 else
2220 {
2221 /* set overall return value */
2222 status = ret;
2223 }
2224
2225 }
2226 #endif /* SPI5 */
2227
2228 #if defined(SPI6)
2229 /*-------------------------- SPI6 clock source configuration ----------------*/
2230 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6)
2231 {
2232
2233 /* Check the parameters */
2234 assert_param(IS_RCC_SPI6CLKSOURCE(pPeriphClkInit->Spi6ClockSelection));
2235
2236 switch (pPeriphClkInit->Spi6ClockSelection)
2237 {
2238 case RCC_SPI6CLKSOURCE_PCLK2: /* PCLK2 (APB2 Clock) is used as clock source for SPI6 */
2239 /* SPI6 clock source configuration done later after clock selection check */
2240 break;
2241
2242 case RCC_SPI6CLKSOURCE_PLL2Q: /* PLL2 is used as clock source for SPI6*/
2243 /* PLL2 Q input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */
2244 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
2245
2246 /* SPI6 clock source configuration done later after clock selection check */
2247 break;
2248
2249 case RCC_SPI6CLKSOURCE_PLL3Q: /* PLL3 is used as clock source for SPI6 */
2250 /* PLL3 Q input clock, parameters M, N & P configuration and clock output (PLL3ClockOut) */
2251 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
2252
2253 /* SPI6 clock source configuration done later after clock selection check */
2254 break;
2255
2256 case RCC_SPI6CLKSOURCE_HSI:
2257 /* HSI oscillator is used as source of SPI6 clock*/
2258 /* SPI6 clock source configuration done later after clock selection check */
2259 break;
2260
2261 case RCC_SPI6CLKSOURCE_CSI:
2262 /* CSI oscillator is used as source of SPI6 clock */
2263 /* SPI6 clock source configuration done later after clock selection check */
2264 break;
2265
2266 case RCC_SPI6CLKSOURCE_HSE:
2267 /* HSE oscillator is used as source of SPI6 clock */
2268 /* SPI6 clock source configuration done later after clock selection check */
2269 break;
2270
2271 default:
2272 ret = HAL_ERROR;
2273 break;
2274 }
2275
2276 if (ret == HAL_OK)
2277 {
2278 /* Configure the SPI6 clock source */
2279 __HAL_RCC_SPI6_CONFIG(pPeriphClkInit->Spi6ClockSelection);
2280 }
2281 else
2282 {
2283 /* set overall return value */
2284 status = ret;
2285 }
2286
2287 }
2288 #endif /* SPI6 */
2289
2290 #if defined(OCTOSPI1)
2291 /*-------------------------- OctoSPIx clock source configuration ----------------*/
2292 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI)
2293 {
2294 /* Check the parameters */
2295 assert_param(IS_RCC_OSPICLKSOURCE(pPeriphClkInit->OspiClockSelection));
2296
2297 switch (pPeriphClkInit->OspiClockSelection)
2298 {
2299 case RCC_OSPICLKSOURCE_HCLK: /* HCLK is used as clock source for OCTOSPI */
2300
2301 /* OCTOSPI clock source config set later after clock selection check */
2302 break;
2303
2304 case RCC_OSPICLKSOURCE_PLL1Q: /* PLL1 Q is used as clock source for OCTOSPI*/
2305
2306 /* Enable PLL1 Q CLK output */
2307 __HAL_RCC_PLL1_CLKOUT_ENABLE(RCC_PLL1_DIVQ);
2308 break;
2309
2310 case RCC_OSPICLKSOURCE_PLL2R: /* PLL2 is used as clock source for OCTOSPI*/
2311 /* PLL2 R input clock, parameters M, N & R configuration and clock output (PLL2ClockOut) */
2312 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
2313 /* OCTOSPI clock source config set later after clock selection check */
2314 break;
2315
2316 case RCC_OSPICLKSOURCE_CLKP: /* CLKP is used as source of OCTOSPI clock*/
2317 /* OCTOSPI clock source config set later after clock selection check */
2318 break;
2319
2320 default:
2321 ret = HAL_ERROR;
2322 break;
2323 }
2324
2325 if (ret == HAL_OK)
2326 {
2327 /* Configure the OctoSPI clock source */
2328 __HAL_RCC_OSPI_CONFIG(pPeriphClkInit->OspiClockSelection);
2329 }
2330 else
2331 {
2332 /* set overall return value */
2333 status = ret;
2334 }
2335 }
2336 #endif /* OCTOSPI1*/
2337
2338 #if defined(FDCAN2)
2339
2340 /*-------------------------- FDCAN12 kernel clock source configuration -------------*/
2341 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN12) == RCC_PERIPHCLK_FDCAN12)
2342 {
2343 assert_param(IS_RCC_FDCAN12CLK(pPeriphClkInit->Fdcan12ClockSelection));
2344
2345 switch (pPeriphClkInit->Fdcan12ClockSelection)
2346 {
2347 case RCC_FDCAN12CLKSOURCE_HSE: /* HSE is used as source of FDCAN2 kernel clock*/
2348 /* FDCAN2 kernel clock source config set later after clock selection check */
2349 break;
2350
2351 case RCC_FDCAN12CLKSOURCE_PLL1Q: /* PLL1 is used as clock source for FDCAN12 kernel clock*/
2352 /* Enable PLL1Q Clock output generated from System PLL . */
2353 __HAL_RCC_PLL1_CLKOUT_ENABLE(RCC_PLL1_DIVQ);
2354 /* FDCAN2 kernel clock source config set later after clock selection check */
2355 break;
2356
2357 case RCC_FDCAN12CLKSOURCE_PLL2Q: /* PLL2 is used as clock source for FDCAN12 kernel clock*/
2358 /* PLL2Q input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */
2359 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
2360 /* FDCAN2 kernel clock source config set later after clock selection check */
2361 break;
2362
2363 default:
2364 ret = HAL_ERROR;
2365 break;
2366 }
2367
2368 if (ret == HAL_OK)
2369 {
2370 /* Set the source of FDCAN12 kernel clock*/
2371 __HAL_RCC_FDCAN12_CONFIG(pPeriphClkInit->Fdcan12ClockSelection);
2372 }
2373 else
2374 {
2375 /* set overall return value */
2376 status = ret;
2377 }
2378 }
2379
2380 #else
2381
2382 /*-------------------------- FDCAN1 kernel clock source configuration -------------*/
2383 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN1) == RCC_PERIPHCLK_FDCAN1)
2384 {
2385 assert_param(IS_RCC_FDCAN1CLK(pPeriphClkInit->Fdcan1ClockSelection));
2386
2387 switch (pPeriphClkInit->Fdcan1ClockSelection)
2388 {
2389 case RCC_FDCAN1CLKSOURCE_HSE: /* HSE is used as source of FDCAN1 kernel clock*/
2390 /* FDCAN1 kernel clock source config set later after clock selection check */
2391 break;
2392
2393 case RCC_FDCAN1CLKSOURCE_PLL1Q: /* PLL1 is used as clock source for FDCAN1 kernel clock*/
2394 /* Enable PLL1Q Clock output generated from System PLL . */
2395 __HAL_RCC_PLL1_CLKOUT_ENABLE(RCC_PLL1_DIVQ);
2396 /* FDCAN1 kernel clock source config set later after clock selection check */
2397 break;
2398
2399 case RCC_FDCAN1CLKSOURCE_PLL2Q: /* PLL2 is used as clock source for FDCAN1 kernel clock*/
2400 /* PLL2Q input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */
2401 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
2402 /* FDCAN1 kernel clock source config set later after clock selection check */
2403 break;
2404
2405 default:
2406 ret = HAL_ERROR;
2407 break;
2408 }
2409
2410 if (ret == HAL_OK)
2411 {
2412 /* Set the source of FDCAN1 kernel clock*/
2413 __HAL_RCC_FDCAN1_CONFIG(pPeriphClkInit->Fdcan1ClockSelection);
2414 }
2415 else
2416 {
2417 /* set overall return value */
2418 status = ret;
2419 }
2420 }
2421
2422 #endif /*FDCAN2*/
2423
2424 /*------------------------------ USB Configuration -------------------------*/
2425 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
2426 {
2427
2428 /* Check the parameters */
2429 assert_param(IS_RCC_USBCLKSOURCE(pPeriphClkInit->UsbClockSelection));
2430
2431 switch (pPeriphClkInit->UsbClockSelection)
2432 {
2433 case RCC_USBCLKSOURCE_PLL1Q: /* PLL is used as clock source for USB*/
2434 /* Enable USB Clock output generated form System USB . */
2435 __HAL_RCC_PLL1_CLKOUT_ENABLE(RCC_PLL1_DIVQ);
2436
2437 /* USB clock source configuration done later after clock selection check */
2438 break;
2439
2440 #if defined(RCC_USBCLKSOURCE_PLL3Q)
2441 case RCC_USBCLKSOURCE_PLL3Q: /* PLL3 is used as clock source for USB*/
2442 /* PLL3Q input clock, parameters M, N & Q configuration and clock output (PLL3ClockOut) */
2443 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
2444 #else
2445 case RCC_USBCLKSOURCE_PLL2Q: /* PLL2 is used as clock source for USB*/
2446 /* PLL2Q input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */
2447 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
2448 #endif /* RCC_USBCLKSOURCE_PLL3Q */
2449 /* USB clock source configuration done later after clock selection check */
2450 break;
2451
2452 case RCC_USBCLKSOURCE_HSI48:
2453 /* HSI48 oscillator is used as source of USB clock */
2454 /* USB clock source configuration done later after clock selection check */
2455 break;
2456
2457 default:
2458 ret = HAL_ERROR;
2459 break;
2460 }
2461
2462 if (ret == HAL_OK)
2463 {
2464 /* Set the source of USB clock*/
2465 __HAL_RCC_USB_CONFIG(pPeriphClkInit->UsbClockSelection);
2466 }
2467 else
2468 {
2469 /* set overall return value */
2470 status = ret;
2471 }
2472
2473 }
2474
2475 #if defined(CEC)
2476 /*-------------------------- CEC clock source configuration ----------------*/
2477 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
2478 {
2479
2480 /* Check the parameters */
2481 assert_param(IS_RCC_CECCLKSOURCE(pPeriphClkInit->CecClockSelection));
2482
2483 /* Configure the CEC clock source */
2484 __HAL_RCC_CEC_CONFIG(pPeriphClkInit->CecClockSelection);
2485
2486 }
2487 #endif /* CEC */
2488
2489 return status;
2490 }
2491
2492
2493
2494 /**
2495 * @brief Get the pPeriphClkInit according to the internal RCC configuration registers.
2496 * @param pPeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
2497 * returns the configuration information for the Extended Peripherals
2498 * clocks (ADC12, DAC, SDMMC1, SDMMC2, OCTOSPI1, TIM, LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, LPTIM6,
2499 * SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, USART1, USART2, USART3, UART4, UART5, USART6, UART7, UART8,
2500 * UART9, USART10, USART11, UART12, LPUART1, I2C1, I2C2, I2C3, I2C4, I3C1, I3C2, CEC, FDCAN12, SAI1,
2501 * SAI2, USB,), PLL2 and PLL3.
2502 * @retval None
2503 */
HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef * pPeriphClkInit)2504 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphClkInit)
2505 {
2506 /* Set all possible values for the extended clock type parameter------------*/
2507 pPeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
2508 RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
2509 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_ADCDAC | \
2510 RCC_PERIPHCLK_DAC_LP | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG | \
2511 RCC_PERIPHCLK_I3C1 | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | \
2512 RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_CKPER | RCC_PERIPHCLK_USB;
2513
2514 #if defined(UART4)
2515 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_UART4;
2516 #endif /* UART4 */
2517 #if defined(UART5)
2518 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_UART5;
2519 #endif /* UART5 */
2520 #if defined(USART6)
2521 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USART6;
2522 #endif /* UART6 */
2523 #if defined(UART7)
2524 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_UART7;
2525 #endif /* UART7 */
2526 #if defined(UART8)
2527 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_UART8;
2528 #endif /* UART8 */
2529 #if defined(UART9)
2530 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_UART9;
2531 #endif /* UART9 */
2532 #if defined(USART10)
2533 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USART10;
2534 #endif /* UART10 */
2535 #if defined(USART11)
2536 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USART11;
2537 #endif /* UART11 */
2538 #if defined(UART12)
2539 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_UART12;
2540 #endif /* UART12 */
2541 #if defined(I2C3)
2542 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C3;
2543 #endif /* I2C3 */
2544 #if defined(I2C4)
2545 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C4;
2546 #endif /* I2C4 */
2547 #if defined(I3C2)
2548 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I3C2;
2549 #endif /* I3C2 */
2550 #if defined(LPTIM3)
2551 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LPTIM3;
2552 #endif /* LPTIM3 */
2553 #if defined(LPTIM4)
2554 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LPTIM4;
2555 #endif /* LPTIM4 */
2556 #if defined(LPTIM5)
2557 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LPTIM5;
2558 #endif /* LPTIM5 */
2559 #if defined(LPTIM6)
2560 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LPTIM6;
2561 #endif /* LPTIM6 */
2562 #if defined(SPI4)
2563 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SPI4;
2564 #endif /* SPI4 */
2565 #if defined(SPI5)
2566 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SPI5;
2567 #endif /* SPI5 */
2568 #if defined(SPI6)
2569 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SPI6;
2570 #endif /* SPI6 */
2571 #if defined(SAI1)
2572 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI1;
2573 #endif /* SAI1 */
2574 #if defined(SAI2)
2575 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI2;
2576 #endif /* SAI2 */
2577 #if defined(FDCAN2)
2578 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_FDCAN12;
2579 #else
2580 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_FDCAN1;
2581 #endif /* FDCAN2*/
2582 #if defined(SDMMC1)
2583 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SDMMC1;
2584 #endif /* SDMMC1*/
2585 #if defined(SDMMC2)
2586 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SDMMC2;
2587 #endif /* SDMMC2*/
2588 #if defined(OCTOSPI1)
2589 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_OSPI;
2590 #endif /* OCTOSPI1 */
2591 #if defined(CEC)
2592 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_CEC;
2593 #endif /* CEC */
2594
2595 /* Get the PLL2 Clock configuration -----------------------------------------------*/
2596 pPeriphClkInit->PLL2.PLL2Source = (uint32_t)((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2SRC) >> RCC_PLL2CFGR_PLL2SRC_Pos);
2597 pPeriphClkInit->PLL2.PLL2M = (uint32_t)((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2M) >> RCC_PLL2CFGR_PLL2M_Pos);
2598 pPeriphClkInit->PLL2.PLL2N = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2N) >> RCC_PLL2DIVR_PLL2N_Pos) + 1U;
2599 pPeriphClkInit->PLL2.PLL2P = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2P) >> RCC_PLL2DIVR_PLL2P_Pos) + 1U;
2600 pPeriphClkInit->PLL2.PLL2Q = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2Q) >> RCC_PLL2DIVR_PLL2Q_Pos) + 1U;
2601 pPeriphClkInit->PLL2.PLL2R = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2R) >> RCC_PLL2DIVR_PLL2R_Pos) + 1U;
2602 pPeriphClkInit->PLL2.PLL2RGE = (uint32_t)((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2RGE) >> RCC_PLL2CFGR_PLL2RGE_Pos);
2603 pPeriphClkInit->PLL2.PLL2FRACN = (uint32_t)((RCC->PLL2FRACR & RCC_PLL2FRACR_PLL2FRACN) >> \
2604 RCC_PLL2FRACR_PLL2FRACN_Pos);
2605
2606 #if defined(RCC_CR_PLL3ON)
2607 /* Get the PLL3 Clock configuration -----------------------------------------------*/
2608 pPeriphClkInit->PLL3.PLL3Source = (uint32_t)((RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3SRC) >> RCC_PLL3CFGR_PLL3SRC_Pos);
2609 pPeriphClkInit->PLL3.PLL3M = (uint32_t)((RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3M) >> RCC_PLL3CFGR_PLL3M_Pos);
2610 pPeriphClkInit->PLL3.PLL3N = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3N) >> RCC_PLL3DIVR_PLL3N_Pos) + 1U;
2611 pPeriphClkInit->PLL3.PLL3P = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3P) >> RCC_PLL3DIVR_PLL3P_Pos) + 1U;
2612 pPeriphClkInit->PLL3.PLL3Q = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3Q) >> RCC_PLL3DIVR_PLL3Q_Pos) + 1U;
2613 pPeriphClkInit->PLL3.PLL3R = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3R) >> RCC_PLL3DIVR_PLL3R_Pos) + 1U;
2614 pPeriphClkInit->PLL3.PLL3RGE = (uint32_t)((RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3RGE) >> RCC_PLL3CFGR_PLL3RGE_Pos);
2615 pPeriphClkInit->PLL3.PLL3FRACN = (uint32_t)((RCC->PLL3FRACR & RCC_PLL3FRACR_PLL3FRACN) >> \
2616 RCC_PLL3FRACR_PLL3FRACN_Pos);
2617 #endif /* RCC_CR_PLL3ON */
2618
2619 /* Get the USART1 clock source ---------------------------------------------*/
2620 pPeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE();
2621
2622 /* Get the USART2 clock source ---------------------------------------------*/
2623 pPeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE();
2624
2625 /* Get the USART3 clock source ---------------------------------------------*/
2626 pPeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE();
2627
2628 #if defined(UART4)
2629 /* Get the UART4 clock source ----------------------------------------------*/
2630 pPeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE();
2631 #endif /* UART4 */
2632
2633 #if defined(UART5)
2634 /* Get the UART5 clock source ----------------------------------------------*/
2635 pPeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE();
2636 #endif /* UART5 */
2637
2638 #if defined(USART6)
2639 /* Get the USART6 clock source ---------------------------------------------*/
2640 pPeriphClkInit->Usart6ClockSelection = __HAL_RCC_GET_USART6_SOURCE();
2641 #endif /* USART6 */
2642
2643 #if defined(UART7)
2644 /* Get the UART7 clock source ---------------------------------------------*/
2645 pPeriphClkInit->Uart7ClockSelection = __HAL_RCC_GET_UART7_SOURCE();
2646 #endif /* UART7 */
2647
2648 #if defined(UART8)
2649 /* Get the UART8 clock source ---------------------------------------------*/
2650 pPeriphClkInit->Uart8ClockSelection = __HAL_RCC_GET_UART8_SOURCE();
2651 #endif /* UART8 */
2652
2653 #if defined(UART9)
2654 /* Get the UART9 clock source ---------------------------------------------*/
2655 pPeriphClkInit->Uart9ClockSelection = __HAL_RCC_GET_UART9_SOURCE();
2656 #endif /* UART9 */
2657
2658 #if defined(USART10)
2659 /* Get the USART10 clock source ---------------------------------------------*/
2660 pPeriphClkInit->Usart10ClockSelection = __HAL_RCC_GET_USART10_SOURCE();
2661 #endif /* USART10 */
2662
2663 #if defined(USART11)
2664 /* Get the USART11 clock source ---------------------------------------------*/
2665 pPeriphClkInit->Usart11ClockSelection = __HAL_RCC_GET_USART11_SOURCE();
2666 #endif /* USART11 */
2667
2668 #if defined(UART12)
2669 /* Get the UART12 clock source ---------------------------------------------*/
2670 pPeriphClkInit->Uart12ClockSelection = __HAL_RCC_GET_UART12_SOURCE();
2671 #endif /* UART12 */
2672
2673 /* Get the LPUART1 clock source --------------------------------------------*/
2674 pPeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE();
2675
2676 /* Get the I2C1 clock source -----------------------------------------------*/
2677 pPeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();
2678
2679 /* Get the I2C2 clock source -----------------------------------------------*/
2680 pPeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE();
2681
2682 #if defined(I2C3)
2683 /* Get the I2C3 clock source -----------------------------------------------*/
2684 pPeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE();
2685 #endif /* I2C3 */
2686
2687 #if defined(I2C4)
2688 /* Get the I2C4 clock source -----------------------------------------------*/
2689 pPeriphClkInit->I2c4ClockSelection = __HAL_RCC_GET_I2C4_SOURCE();
2690 #endif /* I2C4 */
2691
2692 /* Get the I3C1 clock source -----------------------------------------------*/
2693 pPeriphClkInit->I3c1ClockSelection = __HAL_RCC_GET_I3C1_SOURCE();
2694
2695 #if defined(I3C2)
2696 /* Get the I3C2 clock source -----------------------------------------------*/
2697 pPeriphClkInit->I3c2ClockSelection = __HAL_RCC_GET_I3C2_SOURCE();
2698 #endif /* I3C2 */
2699
2700 /* Get the LPTIM1 clock source ---------------------------------------------*/
2701 pPeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE();
2702
2703 /* Get the LPTIM2 clock source ---------------------------------------------*/
2704 pPeriphClkInit->Lptim2ClockSelection = __HAL_RCC_GET_LPTIM2_SOURCE();
2705
2706 #if defined(LPTIM3)
2707 /* Get the LPTIM3 clock source ---------------------------------------------*/
2708 pPeriphClkInit->Lptim3ClockSelection = __HAL_RCC_GET_LPTIM3_SOURCE();
2709 #endif /* LPTIM3 */
2710
2711 #if defined(LPTIM4)
2712 /* Get the LPTIM4 clock source ---------------------------------------------*/
2713 pPeriphClkInit->Lptim4ClockSelection = __HAL_RCC_GET_LPTIM4_SOURCE();
2714 #endif /* LPTIM4 */
2715
2716 #if defined(LPTIM5)
2717 /* Get the LPTIM5 clock source ---------------------------------------------*/
2718 pPeriphClkInit->Lptim5ClockSelection = __HAL_RCC_GET_LPTIM5_SOURCE();
2719 #endif /* LPTIM5 */
2720
2721 #if defined(LPTIM6)
2722 /* Get the LPTIM6 clock source ---------------------------------------------*/
2723 pPeriphClkInit->Lptim6ClockSelection = __HAL_RCC_GET_LPTIM6_SOURCE();
2724 #endif /* LPTIM6 */
2725
2726 #if defined(FDCAN2)
2727 /* Get the FDCAN2 clock source ---------------------------------------------*/
2728 pPeriphClkInit->Fdcan12ClockSelection = __HAL_RCC_GET_FDCAN12_SOURCE();
2729 #else
2730 /* Get the FDCAN1 clock source ---------------------------------------------*/
2731 pPeriphClkInit->Fdcan1ClockSelection = __HAL_RCC_GET_FDCAN1_SOURCE();
2732 #endif /* FDCAN2*/
2733
2734 #if defined(SAI1)
2735 /* Get the SAI1 clock source -----------------------------------------------*/
2736 pPeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();
2737 #endif /* SAI1 */
2738
2739 #if defined(SAI2)
2740 /* Get the SAI2 clock source -----------------------------------------------*/
2741 pPeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE();
2742 #endif /* SAI2 */
2743
2744 #if defined(SDMMC1)
2745 /* Get the SDMMC1 clock source ----------------------------------------------*/
2746 pPeriphClkInit->Sdmmc1ClockSelection = __HAL_RCC_GET_SDMMC1_SOURCE();
2747 #endif /* SDMMC1 */
2748
2749 #if defined(SDMMC2)
2750 /* Get the SDMMC2 clock source ----------------------------------------------*/
2751 pPeriphClkInit->Sdmmc2ClockSelection = __HAL_RCC_GET_SDMMC2_SOURCE();
2752 #endif /* SDMMC2 */
2753
2754 /* Get the ADCDAC clock source ---------------------------------------------*/
2755 pPeriphClkInit->AdcDacClockSelection = __HAL_RCC_GET_ADCDAC_SOURCE();
2756
2757 /* Get the DAC low-power clock source ---------------------------------------------*/
2758 pPeriphClkInit->DacLowPowerClockSelection = __HAL_RCC_GET_DAC_LP_SOURCE();
2759
2760 #if defined(OCTOSPI1)
2761 /* Get the OSPI clock source -----------------------------------------------*/
2762 pPeriphClkInit->OspiClockSelection = __HAL_RCC_GET_OSPI_SOURCE();
2763 #endif /* OCTOSPI1 */
2764
2765 /* Get the SPI1 clock source -----------------------------------------------*/
2766 pPeriphClkInit->Spi1ClockSelection = __HAL_RCC_GET_SPI1_SOURCE();
2767
2768 /* Get the SPI2 clock source -----------------------------------------------*/
2769 pPeriphClkInit->Spi2ClockSelection = __HAL_RCC_GET_SPI2_SOURCE();
2770
2771 /* Get the SPI3 clock source -----------------------------------------------*/
2772 pPeriphClkInit->Spi3ClockSelection = __HAL_RCC_GET_SPI3_SOURCE();
2773
2774 #if defined(SPI4)
2775 /* Get the SPI4 clock source -----------------------------------------------*/
2776 pPeriphClkInit->Spi4ClockSelection = __HAL_RCC_GET_SPI4_SOURCE();
2777 #endif /* SPI4 */
2778
2779 #if defined(SPI5)
2780 /* Get the SPI5 clock source -----------------------------------------------*/
2781 pPeriphClkInit->Spi5ClockSelection = __HAL_RCC_GET_SPI5_SOURCE();
2782 #endif /* SPI5 */
2783
2784 #if defined(SPI6)
2785 /* Get the SPI6 clock source -----------------------------------------------*/
2786 pPeriphClkInit->Spi6ClockSelection = __HAL_RCC_GET_SPI6_SOURCE();
2787 #endif /* SPI6 */
2788
2789 /* Get the RTC clock source ------------------------------------------------*/
2790 pPeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE();
2791
2792 /* Get the RNG clock source ------------------------------------------------*/
2793 pPeriphClkInit->RngClockSelection = __HAL_RCC_GET_RNG_SOURCE();
2794
2795 /* Get the CKPER clock source ------------------------------------------------*/
2796 pPeriphClkInit->CkperClockSelection = __HAL_RCC_GET_CLKP_SOURCE();
2797
2798 #if defined(CEC)
2799 /* Get the CEC clock source ------------------------------------------------*/
2800 pPeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE();
2801 #endif /* CEC */
2802
2803 /* Get the USB clock source ------------------------------------------------*/
2804 pPeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE();
2805
2806 /* Get the TIM Prescaler configuration -------------------------------------*/
2807 if ((RCC->CFGR1 & RCC_CFGR1_TIMPRE) == 0U)
2808 {
2809 pPeriphClkInit->TimPresSelection = RCC_TIMPRES_DEACTIVATED;
2810 }
2811 else
2812 {
2813 pPeriphClkInit->TimPresSelection = RCC_TIMPRES_ACTIVATED;
2814 }
2815 }
2816
2817 /**
2818 * @brief Returns the PLL1 clock frequencies : PLL1_P_Frequency, PLL1_R_Frequency and PLL1_Q_Frequency
2819 * @note The PLL1 clock frequencies computed by this function may not be the real
2820 * frequency in the chip. It is calculated based on the predefined
2821 * constant and the selected clock source:
2822 * @note The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by
2823 the PLL factors.
2824 * @note This function can be used by the user application to compute the
2825 * baud-rate for the communication peripherals or configure other parameters.
2826 *
2827 * @note Each time PLL1CLK changes, this function must be called to update the
2828 * right PLL1CLK value. Otherwise, any configuration based on this function will be incorrect.
2829 * @param pPLL1_Clocks pointer to PLL1_ClocksTypeDef structure.
2830 * @retval None
2831 */
HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef * pPLL1_Clocks)2832 void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef *pPLL1_Clocks)
2833 {
2834 uint32_t pll1source;
2835 uint32_t pll1m;
2836 uint32_t pll1n;
2837 uint32_t pll1fracen;
2838 uint32_t hsivalue;
2839 float_t fracn1;
2840 float_t pll1vco;
2841
2842 /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL1M) * PLL1N
2843 PLL1xCLK = PLL1_VCO / PLL1x
2844 */
2845
2846 pll1n = (RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N);
2847 pll1source = (RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC);
2848 pll1m = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos);
2849 pll1fracen = RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1FRACEN;
2850 fracn1 = (float_t)(uint32_t)(pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_PLL1FRACN) >> \
2851 RCC_PLL1FRACR_PLL1FRACN_Pos));
2852
2853 if (pll1m != 0U)
2854 {
2855 switch (pll1source)
2856 {
2857
2858 case RCC_PLL1_SOURCE_HSI: /* HSI used as PLL1 clock source */
2859 hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
2860 pll1vco = ((float_t)hsivalue / (float_t)pll1m) * ((float_t)(uint32_t)pll1n + (fracn1 / (float_t)0x2000) + \
2861 (float_t)1);
2862 break;
2863
2864 case RCC_PLL1_SOURCE_CSI: /* CSI used as PLL1 clock source */
2865 pll1vco = ((float_t)CSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)pll1n + (fracn1 / (float_t)0x2000) + \
2866 (float_t)1);
2867 break;
2868
2869 case RCC_PLL1_SOURCE_HSE: /* HSE used as PLL1 clock source */
2870 pll1vco = ((float_t)HSE_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)pll1n + (fracn1 / (float_t)0x2000) + \
2871 (float_t)1);
2872 break;
2873
2874 default:
2875 hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
2876 pll1vco = ((float_t)hsivalue / (float_t)pll1m) * ((float_t)(uint32_t)pll1n + (fracn1 / (float_t)0x2000) + \
2877 (float_t)1);
2878 break;
2879 }
2880
2881 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
2882 {
2883 if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL1_DIVP) != 0U)
2884 {
2885 pPLL1_Clocks->PLL1_P_Frequency = \
2886 (uint32_t)(float_t)(pll1vco / \
2887 ((float_t)(uint32_t)((RCC->PLL1DIVR & \
2888 RCC_PLL1DIVR_PLL1P) >> \
2889 RCC_PLL1DIVR_PLL1P_Pos) + \
2890 (float_t)1));
2891 }
2892 else
2893 {
2894 pPLL1_Clocks->PLL1_P_Frequency = 0U;
2895 }
2896 }
2897 else
2898 {
2899 pPLL1_Clocks->PLL1_P_Frequency = 0U;
2900 }
2901
2902 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
2903 {
2904 if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL1_DIVQ) != 0U)
2905 {
2906 pPLL1_Clocks->PLL1_Q_Frequency = \
2907 (uint32_t)(float_t)(pll1vco / \
2908 ((float_t)(uint32_t)((RCC->PLL1DIVR & \
2909 RCC_PLL1DIVR_PLL1Q) >> \
2910 RCC_PLL1DIVR_PLL1Q_Pos) + \
2911 (float_t)1));
2912 }
2913 else
2914 {
2915 pPLL1_Clocks->PLL1_Q_Frequency = 0U;
2916 }
2917 }
2918 else
2919 {
2920 pPLL1_Clocks->PLL1_Q_Frequency = 0U;
2921 }
2922
2923 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
2924 {
2925 if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL1_DIVR) != 0U)
2926 {
2927 pPLL1_Clocks->PLL1_R_Frequency = \
2928 (uint32_t)(float_t)(pll1vco / \
2929 ((float_t)(uint32_t)((RCC->PLL1DIVR & \
2930 RCC_PLL1DIVR_PLL1R) >> \
2931 RCC_PLL1DIVR_PLL1R_Pos) + \
2932 (float_t)1)) ;
2933 }
2934 else
2935 {
2936 pPLL1_Clocks->PLL1_R_Frequency = 0U;
2937 }
2938 }
2939 else
2940 {
2941 pPLL1_Clocks->PLL1_R_Frequency = 0U;
2942 }
2943
2944 }
2945 else
2946 {
2947 pPLL1_Clocks->PLL1_P_Frequency = 0U;
2948 pPLL1_Clocks->PLL1_Q_Frequency = 0U;
2949 pPLL1_Clocks->PLL1_R_Frequency = 0U;
2950 }
2951
2952 }
2953
2954 /**
2955 * @brief Returns the PLL2 clock frequencies: PLL2_P_Frequency, PLL2_R_Frequency and PLL2_Q_Frequency
2956 * @note The PLL2 clock frequencies computed by this function may not be the real
2957 * frequency in the chip. It is calculated based on the predefined
2958 * constant and the selected clock source:
2959 * @note The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by
2960 the PLL factors.
2961 * @note This function can be used by the user application to compute the
2962 * baud-rate for the communication peripherals or configure other parameters.
2963 *
2964 * @note Each time PLL2CLK changes, this function must be called to update the
2965 * right PLL2CLK value. Otherwise, any configuration based on this function will be incorrect.
2966 * @param pPLL2_Clocks pointer to PLL2_ClocksTypeDef structure.
2967 * @retval None
2968 */
HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef * pPLL2_Clocks)2969 void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef *pPLL2_Clocks)
2970 {
2971 uint32_t pll2source;
2972 uint32_t pll2m;
2973 uint32_t pll2n;
2974 uint32_t pll2fracen;
2975 uint32_t hsivalue;
2976 float_t fracn2;
2977 float_t pll2vco;
2978
2979 /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL2M) * PLL2N
2980 PLL2xCLK = PLL2_VCO / PLL2x
2981 */
2982 pll2n = (RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2N);
2983 pll2source = (RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2SRC);
2984 pll2m = ((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2M) >> RCC_PLL2CFGR_PLL2M_Pos);
2985 pll2fracen = RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2FRACEN;
2986 fracn2 = (float_t)(uint32_t)(pll2fracen * ((RCC->PLL2FRACR & RCC_PLL2FRACR_PLL2FRACN) >> \
2987 RCC_PLL2FRACR_PLL2FRACN_Pos));
2988
2989 if (pll2m != 0U)
2990 {
2991 switch (pll2source)
2992 {
2993 case RCC_PLL2SOURCE_HSI: /* HSI used as PLL clock source */
2994 hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
2995 pll2vco = ((float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)pll2n + (fracn2 / (float_t)0x2000) + \
2996 (float_t)1);
2997 break;
2998
2999 case RCC_PLL2SOURCE_CSI: /* CSI used as PLL clock source */
3000 pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)pll2n + (fracn2 / (float_t)0x2000) + \
3001 (float_t)1);
3002 break;
3003
3004 case RCC_PLL2SOURCE_HSE: /* HSE used as PLL clock source */
3005 pll2vco = ((float_t)HSE_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)pll2n + (fracn2 / (float_t)0x2000) + \
3006 (float_t)1);
3007 break;
3008
3009 default:
3010 hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
3011 pll2vco = ((float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)pll2n + (fracn2 / (float_t)0x2000) + \
3012 (float_t)1);
3013 break;
3014 }
3015
3016 if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL2_DIVP) != 0U)
3017 {
3018 pPLL2_Clocks->PLL2_P_Frequency = \
3019 (uint32_t)(float_t)(pll2vco / \
3020 ((float_t)(uint32_t)((RCC->PLL2DIVR & \
3021 RCC_PLL2DIVR_PLL2P) >> \
3022 RCC_PLL2DIVR_PLL2P_Pos) + (float_t)1));
3023 }
3024 else
3025 {
3026 pPLL2_Clocks->PLL2_P_Frequency = 0U;
3027 }
3028 if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL2_DIVQ) != 0U)
3029 {
3030 pPLL2_Clocks->PLL2_Q_Frequency = \
3031 (uint32_t)(float_t)(pll2vco / \
3032 ((float_t)(uint32_t)((RCC->PLL2DIVR & \
3033 RCC_PLL2DIVR_PLL2Q) >> \
3034 RCC_PLL2DIVR_PLL2Q_Pos) + (float_t)1));
3035 }
3036 else
3037 {
3038 pPLL2_Clocks->PLL2_Q_Frequency = 0U;
3039 }
3040 if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL2_DIVR) != 0U)
3041 {
3042 pPLL2_Clocks->PLL2_R_Frequency = \
3043 (uint32_t)(float_t)(pll2vco / \
3044 ((float_t)(uint32_t)((RCC->PLL2DIVR & \
3045 RCC_PLL2DIVR_PLL2R) >> \
3046 RCC_PLL2DIVR_PLL2R_Pos) + (float_t)1));
3047 }
3048 else
3049 {
3050 pPLL2_Clocks->PLL2_R_Frequency = 0U;
3051 }
3052 }
3053 else
3054 {
3055 pPLL2_Clocks->PLL2_P_Frequency = 0U;
3056 pPLL2_Clocks->PLL2_Q_Frequency = 0U;
3057 pPLL2_Clocks->PLL2_R_Frequency = 0U;
3058 }
3059 }
3060
3061 #if defined(RCC_CR_PLL3ON)
3062 /**
3063 * @brief Returns the PLL3 clock frequencies: PLL3_P_Frequency, PLL3_R_Frequency and PLL3_Q_Frequency
3064 * @note The PLL3 clock frequencies computed by this function may not be the real
3065 * frequency in the chip. It is calculated based on the predefined
3066 * constant and the selected clock source:
3067 * @note The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by
3068 the PLL factors.
3069 * @note This function can be used by the user application to compute the
3070 * baud-rate for the communication peripherals or configure other parameters.
3071 *
3072 * @note Each time PLL3CLK changes, this function must be called to update the
3073 * right PLL3CLK value. Otherwise, any configuration based on this function will be incorrect.
3074 * @param pPLL3_Clocks pointer to PLL3_ClocksTypeDef structure.
3075 * @retval None
3076 */
HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef * pPLL3_Clocks)3077 void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *pPLL3_Clocks)
3078 {
3079 uint32_t pll3source;
3080 uint32_t pll3m;
3081 uint32_t pll3n;
3082 uint32_t pll3fracen;
3083 uint32_t hsivalue;
3084 float_t fracn3;
3085 float_t pll3vco;
3086
3087 /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL3M) * PLL3N
3088 PLL3xCLK = PLL3_VCO / PLL3x
3089 */
3090 pll3n = (RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3N);
3091 pll3source = (RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3SRC);
3092 pll3m = ((RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3M) >> RCC_PLL3CFGR_PLL3M_Pos);
3093 pll3fracen = RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3FRACEN;
3094 fracn3 = (float_t)(uint32_t)(pll3fracen * ((RCC->PLL3FRACR & RCC_PLL3FRACR_PLL3FRACN) >> \
3095 RCC_PLL3FRACR_PLL3FRACN_Pos));
3096
3097 if (pll3m != 0U)
3098 {
3099 switch (pll3source)
3100 {
3101 case RCC_PLL3SOURCE_HSI: /* HSI used as PLL clock source */
3102 hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
3103 pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)pll3n + (fracn3 / (float_t)0x2000) + \
3104 (float_t)1);
3105 break;
3106
3107 case RCC_PLL3SOURCE_CSI: /* CSI used as PLL clock source */
3108 pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)pll3n + (fracn3 / (float_t)0x2000) + \
3109 (float_t)1);
3110 break;
3111
3112 case RCC_PLL3SOURCE_HSE: /* HSE used as PLL clock source */
3113 pll3vco = ((float_t)HSE_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)pll3n + (fracn3 / (float_t)0x2000) + \
3114 (float_t)1);
3115 break;
3116
3117 default:
3118 hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
3119 pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)pll3n + (fracn3 / (float_t)0x2000) + \
3120 (float_t)1);
3121 break;
3122 }
3123
3124 if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL3_DIVP) != 0U)
3125 {
3126 pPLL3_Clocks->PLL3_P_Frequency = \
3127 (uint32_t)(float_t)(pll3vco / \
3128 ((float_t)(uint32_t)((RCC->PLL3DIVR & \
3129 RCC_PLL3DIVR_PLL3P) >> \
3130 RCC_PLL3DIVR_PLL3P_Pos) + (float_t)1));
3131 }
3132 else
3133 {
3134 pPLL3_Clocks->PLL3_P_Frequency = 0U;
3135 }
3136 if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL3_DIVQ) != 0U)
3137 {
3138 pPLL3_Clocks->PLL3_Q_Frequency = \
3139 (uint32_t)(float_t)(pll3vco / \
3140 ((float_t)(uint32_t)((RCC->PLL3DIVR & \
3141 RCC_PLL3DIVR_PLL3Q) >> \
3142 RCC_PLL3DIVR_PLL3Q_Pos) + (float_t)1));
3143 }
3144 else
3145 {
3146 pPLL3_Clocks->PLL3_Q_Frequency = 0U;
3147 }
3148 if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL3_DIVR) != 0U)
3149 {
3150 pPLL3_Clocks->PLL3_R_Frequency = \
3151 (uint32_t)(float_t)(pll3vco / \
3152 ((float_t)(uint32_t)((RCC->PLL3DIVR & \
3153 RCC_PLL3DIVR_PLL3R) >> \
3154 RCC_PLL3DIVR_PLL3R_Pos) + (float_t)1));
3155 }
3156 else
3157 {
3158 pPLL3_Clocks->PLL3_R_Frequency = 0U;
3159 }
3160 }
3161 else
3162 {
3163 pPLL3_Clocks->PLL3_P_Frequency = 0U;
3164 pPLL3_Clocks->PLL3_Q_Frequency = 0U;
3165 pPLL3_Clocks->PLL3_R_Frequency = 0U;
3166 }
3167 }
3168 #endif /* RCC_CR_PLL3ON */
3169
3170 /**
3171 * @brief Return the peripheral clock frequency for peripherals
3172 * @note Return 0 if peripheral clock identifier not managed by this API
3173 * @param PeriphClk Peripheral clock identifier
3174 * This parameter can be one of the following values:
3175 * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock
3176 * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
3177 * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock
3178 * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock (*)
3179 * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock (*)
3180 * @arg @ref RCC_PERIPHCLK_USART6 USART6 peripheral clock (*)
3181 * @arg @ref RCC_PERIPHCLK_UART7 UART7 peripheral clock (*)
3182 * @arg @ref RCC_PERIPHCLK_UART8 UART8 peripheral clock (*)
3183 * @arg @ref RCC_PERIPHCLK_UART9 UART9 peripheral clock (*)
3184 * @arg @ref RCC_PERIPHCLK_USART10 USART10 peripheral clock (*)
3185 * @arg @ref RCC_PERIPHCLK_USART11 USART11 peripheral clock (*)
3186 * @arg @ref RCC_PERIPHCLK_UART12 UART12 peripheral clock (*)
3187 * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock
3188 * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock
3189 * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
3190 * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock (*)
3191 * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock (*)
3192 * @arg @ref RCC_PERIPHCLK_I3C1 I3C1 peripheral clock
3193 * @arg @ref RCC_PERIPHCLK_I3C2 I3C2 peripheral clock (***)
3194 * @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock
3195 * @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock
3196 * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock (*)
3197 * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock (*)
3198 * @arg @ref RCC_PERIPHCLK_ADCDAC ADCDAC peripheral clock
3199 * @arg @ref RCC_PERIPHCLK_ADC1 ADC1 peripheral clock
3200 * @arg @ref RCC_PERIPHCLK_ADC2 ADC2 peripheral clock
3201 * @arg @ref RCC_PERIPHCLK_SDMMC1 SDMMC1 peripheral clock (*)
3202 * @arg @ref RCC_PERIPHCLK_SDMMC2 SDMMC2 peripheral clock (**)
3203 * @arg @ref RCC_PERIPHCLK_CKPER CKPER peripheral clock
3204 * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
3205 * @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock
3206 * @arg @ref RCC_PERIPHCLK_SPI1 SPI1 peripheral clock
3207 * @arg @ref RCC_PERIPHCLK_SPI2 SPI2 peripheral clock
3208 * @arg @ref RCC_PERIPHCLK_SPI3 SPI3 peripheral clock
3209 * @arg @ref RCC_PERIPHCLK_SPI4 SPI4 peripheral clock (*)
3210 * @arg @ref RCC_PERIPHCLK_SPI5 SPI5 peripheral clock (*)
3211 * @arg @ref RCC_PERIPHCLK_SPI6 SPI6 peripheral clock (*)
3212 * @arg @ref RCC_PERIPHCLK_OSPI OCTOSPI peripheral clock (*)
3213 * @arg @ref RCC_PERIPHCLK_FDCAN12 FDCAN12 peripheral clock (**)
3214 * @arg @ref RCC_PERIPHCLK_FDCAN1 FDCAN1 peripheral clock (*)
3215 * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock (*)
3216 * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
3217 * @arg @ref RCC_PERIPHCLK_LPTIM3 LPTIM3 peripheral clock (*)
3218 * @arg @ref RCC_PERIPHCLK_LPTIM4 LPTIM4 peripheral clock (*)
3219 * @arg @ref RCC_PERIPHCLK_LPTIM5 LPTIM5 peripheral clock (*)
3220 * @arg @ref RCC_PERIPHCLK_LPTIM6 LPTIM6 peripheral clock (*)
3221 * @arg @ref RCC_PERIPHCLK_DAC_LP DAC low-power peripheral clock
3222 * @arg @ref RCC_PERIPHCLK_TIM TIM peripheral clock
3223 *
3224 * @retval Frequency in Hz
3225 *
3226 * (*) : For stm32h56xxx and stm32h57xxx family lines only.
3227 * (**) : For stm32h563xx and stm32h57xxx family lines only.
3228 * (***) : For stm32h503xx family line only.
3229 */
HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk)3230 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk)
3231 {
3232 PLL1_ClocksTypeDef pll1_clocks;
3233 PLL2_ClocksTypeDef pll2_clocks;
3234 #if defined(RCC_CR_PLL3ON)
3235 PLL3_ClocksTypeDef pll3_clocks;
3236 #endif /* RCC_CR_PLL3ON */
3237
3238 uint32_t frequency;
3239 uint32_t ckpclocksource;
3240 uint32_t srcclk;
3241
3242 /* Check the parameters */
3243 assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
3244
3245 if (PeriphClk == RCC_PERIPHCLK_RTC)
3246 {
3247 /* Get the current RTC source */
3248 srcclk = __HAL_RCC_GET_RTC_SOURCE();
3249
3250 /* Check if LSE is ready and if RTC clock selection is LSE */
3251 if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_RTCCLKSOURCE_LSE))
3252 {
3253 frequency = LSE_VALUE;
3254 }
3255 /* Check if LSI is ready and if RTC clock selection is LSI */
3256 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_RTCCLKSOURCE_LSI))
3257 {
3258 frequency = LSI_VALUE;
3259 }
3260 /* Check if HSE is ready and if RTC clock selection is HSI_DIVx*/
3261 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_RTCCLKSOURCE_HSE_DIVx))
3262 {
3263 if (__HAL_RCC_GET_RTC_HSE_PRESCALER() >= RCC_RTC_HSE_DIV2)
3264 {
3265 frequency = (HSE_VALUE / ((uint32_t)(__HAL_RCC_GET_RTC_HSE_PRESCALER() >> RCC_CFGR1_RTCPRE_Pos)));
3266 }
3267 else
3268 {
3269 frequency = 0U;
3270 }
3271
3272 }
3273 /* Clock not enabled for RTC*/
3274 else
3275 {
3276 frequency = 0U;
3277 }
3278 }
3279 else
3280 {
3281 /* Other external peripheral clock source than RTC */
3282 switch (PeriphClk)
3283 {
3284 #if defined (SAI1)
3285 case RCC_PERIPHCLK_SAI1:
3286
3287 srcclk = __HAL_RCC_GET_SAI1_SOURCE();
3288
3289 switch (srcclk)
3290 {
3291 case RCC_SAI1CLKSOURCE_PLL1Q: /* PLL1Q is the clock source for SAI1 */
3292 {
3293 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
3294 frequency = pll1_clocks.PLL1_Q_Frequency;
3295 break;
3296 }
3297 case RCC_SAI1CLKSOURCE_PLL2P: /* PLL2P is the clock source for SAI1 */
3298 {
3299 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
3300 frequency = pll2_clocks.PLL2_P_Frequency;
3301 break;
3302 }
3303 case RCC_SAI1CLKSOURCE_PLL3P: /* PLLI3P is the clock source for SAI1 */
3304 {
3305 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
3306 frequency = pll3_clocks.PLL3_P_Frequency;
3307 break;
3308 }
3309 case RCC_SAI1CLKSOURCE_PIN:
3310 {
3311 frequency = EXTERNAL_CLOCK_VALUE;
3312 break;
3313 }
3314 case RCC_SAI1CLKSOURCE_CLKP: /* CLKP is the clock source for SAI1 */
3315 {
3316
3317 ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
3318
3319 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
3320 {
3321 /* In Case the CKPER Source is HSI */
3322 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
3323 }
3324
3325 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
3326 {
3327 /* In Case the CKPER Source is CSI */
3328 frequency = CSI_VALUE;
3329 }
3330
3331 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
3332 {
3333 /* In Case the CKPER Source is HSE */
3334 frequency = HSE_VALUE;
3335 }
3336
3337 else
3338 {
3339 /* In Case the CKPER is disabled*/
3340 frequency = 0U;
3341 }
3342
3343 break;
3344 }
3345 default :
3346 {
3347 frequency = 0U;
3348 break;
3349 }
3350 }
3351 break;
3352 #endif /*SAI1*/
3353
3354 #if defined(SAI2)
3355 case RCC_PERIPHCLK_SAI2:
3356
3357 srcclk = __HAL_RCC_GET_SAI2_SOURCE();
3358
3359 switch (srcclk)
3360 {
3361 case RCC_SAI2CLKSOURCE_PLL1Q: /* PLL1Q is the clock source for SAI2 */
3362 {
3363 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
3364 frequency = pll1_clocks.PLL1_Q_Frequency;
3365 break;
3366 }
3367 case RCC_SAI2CLKSOURCE_PLL2P: /* PLL2P is the clock source for SAI2 */
3368 {
3369 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
3370 frequency = pll2_clocks.PLL2_P_Frequency;
3371 break;
3372 }
3373 case RCC_SAI2CLKSOURCE_PLL3P: /* PLLI3P is the clock source for SAI2 */
3374 {
3375 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
3376 frequency = pll3_clocks.PLL3_P_Frequency;
3377 break;
3378 }
3379 case RCC_SAI2CLKSOURCE_PIN:
3380 {
3381 frequency = EXTERNAL_CLOCK_VALUE;
3382 break;
3383 }
3384 case RCC_SAI2CLKSOURCE_CLKP: /* CLKP is the clock source for SAI2 */
3385 {
3386
3387 ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
3388
3389 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
3390 {
3391 /* In Case the CKPER Source is HSI */
3392 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
3393 }
3394
3395 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
3396 {
3397 /* In Case the CKPER Source is CSI */
3398 frequency = CSI_VALUE;
3399 }
3400
3401 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
3402 {
3403 /* In Case the CKPER Source is HSE */
3404 frequency = HSE_VALUE;
3405 }
3406
3407 else
3408 {
3409 /* In Case the CKPER is disabled*/
3410 frequency = 0U;
3411 }
3412
3413 break;
3414 }
3415 default :
3416 {
3417 frequency = 0U;
3418 break;
3419 }
3420 }
3421 break;
3422 #endif /* SAI2 */
3423
3424 #if defined(SDMMC1)
3425 case RCC_PERIPHCLK_SDMMC1:
3426 srcclk = __HAL_RCC_GET_SDMMC1_SOURCE();
3427 if (srcclk == RCC_SDMMC1CLKSOURCE_PLL1Q)
3428 {
3429 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
3430 frequency = pll1_clocks.PLL1_Q_Frequency;
3431 }
3432 else if (srcclk == RCC_SDMMC1CLKSOURCE_PLL2R)
3433 {
3434 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
3435 frequency = pll2_clocks.PLL2_R_Frequency;
3436 }
3437 else
3438 {
3439 frequency = 0U;
3440 }
3441 break;
3442 #endif /* SDMMC1 */
3443
3444 #if defined(SDMMC2)
3445 case RCC_PERIPHCLK_SDMMC2:
3446 srcclk = __HAL_RCC_GET_SDMMC2_SOURCE();
3447 if (srcclk == RCC_SDMMC2CLKSOURCE_PLL1Q)
3448 {
3449 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
3450 frequency = pll1_clocks.PLL1_Q_Frequency;
3451 }
3452 else if (srcclk == RCC_SDMMC2CLKSOURCE_PLL2R)
3453 {
3454 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
3455 frequency = pll2_clocks.PLL2_R_Frequency;
3456 }
3457 else
3458 {
3459 frequency = 0U;
3460 }
3461 break;
3462 #endif /* SDMMC2 */
3463
3464 case RCC_PERIPHCLK_USART1:
3465 /* Get the current USART1 source */
3466 srcclk = __HAL_RCC_GET_USART1_SOURCE();
3467
3468 if (srcclk == RCC_USART1CLKSOURCE_PCLK2)
3469 {
3470 frequency = HAL_RCC_GetPCLK2Freq();
3471 }
3472 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) && (srcclk == RCC_USART1CLKSOURCE_PLL2Q))
3473 {
3474 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
3475 frequency = pll2_clocks.PLL2_Q_Frequency;
3476 }
3477 #if defined(RCC_USART1CLKSOURCE_PLL3Q)
3478 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) && (srcclk == RCC_USART1CLKSOURCE_PLL3Q))
3479 {
3480 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
3481 frequency = pll3_clocks.PLL3_Q_Frequency;
3482 }
3483 #endif /* RCC_USART1CLKSOURCE_PLL3Q */
3484 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART1CLKSOURCE_HSI))
3485 {
3486 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
3487 }
3488 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_USART1CLKSOURCE_CSI))
3489 {
3490 frequency = CSI_VALUE;
3491 }
3492 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART1CLKSOURCE_LSE))
3493 {
3494 frequency = LSE_VALUE;
3495 }
3496 /* Clock not enabled for USART1 */
3497 else
3498 {
3499 frequency = 0U;
3500 }
3501 break;
3502
3503 case RCC_PERIPHCLK_USART2:
3504 /* Get the current USART2 source */
3505 srcclk = __HAL_RCC_GET_USART2_SOURCE();
3506
3507 if (srcclk == RCC_USART2CLKSOURCE_PCLK1)
3508 {
3509 frequency = HAL_RCC_GetPCLK1Freq();
3510 }
3511 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) && (srcclk == RCC_USART2CLKSOURCE_PLL2Q))
3512 {
3513 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
3514 frequency = pll2_clocks.PLL2_Q_Frequency;
3515 }
3516 #if defined(RCC_USART2CLKSOURCE_PLL3Q)
3517 else if ((srcclk == RCC_USART2CLKSOURCE_PLL3Q))
3518 {
3519 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
3520 frequency = pll3_clocks.PLL3_Q_Frequency;
3521 }
3522 #endif /* RCC_USART2CLKSOURCE_PLL3Q */
3523 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART2CLKSOURCE_HSI))
3524 {
3525 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
3526 }
3527 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_USART2CLKSOURCE_CSI))
3528 {
3529 frequency = CSI_VALUE;
3530 }
3531 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART2CLKSOURCE_LSE))
3532 {
3533 frequency = LSE_VALUE;
3534 }
3535 /* Clock not enabled for USART2 */
3536 else
3537 {
3538 frequency = 0U;
3539 }
3540 break;
3541
3542 case RCC_PERIPHCLK_USART3:
3543 /* Get the current USART3 source */
3544 srcclk = __HAL_RCC_GET_USART3_SOURCE();
3545
3546 if (srcclk == RCC_USART3CLKSOURCE_PCLK1)
3547 {
3548 frequency = HAL_RCC_GetPCLK1Freq();
3549 }
3550 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) && (srcclk == RCC_USART3CLKSOURCE_PLL2Q))
3551 {
3552 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
3553 frequency = pll2_clocks.PLL2_Q_Frequency;
3554 }
3555 #if defined(RCC_USART3CLKSOURCE_PLL3Q)
3556 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) && (srcclk == RCC_USART3CLKSOURCE_PLL3Q))
3557 {
3558 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
3559 frequency = pll3_clocks.PLL3_Q_Frequency;
3560 }
3561 #endif /* RCC_USART3CLKSOURCE_PLL3S */
3562 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART3CLKSOURCE_HSI))
3563 {
3564 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
3565 }
3566 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_USART3CLKSOURCE_CSI))
3567 {
3568 frequency = CSI_VALUE;
3569 }
3570 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART3CLKSOURCE_LSE))
3571 {
3572 frequency = LSE_VALUE;
3573 }
3574 /* Clock not enabled for USART3 */
3575 else
3576 {
3577 frequency = 0U;
3578 }
3579 break;
3580
3581 #if defined(UART4)
3582 case RCC_PERIPHCLK_UART4:
3583 /* Get the current UART4 source */
3584 srcclk = __HAL_RCC_GET_UART4_SOURCE();
3585
3586 if (srcclk == RCC_UART4CLKSOURCE_PCLK1)
3587 {
3588 frequency = HAL_RCC_GetPCLK1Freq();
3589 }
3590 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) && (srcclk == RCC_UART4CLKSOURCE_PLL2Q))
3591 {
3592 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
3593 frequency = pll2_clocks.PLL2_Q_Frequency;
3594 }
3595 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) && (srcclk == RCC_UART4CLKSOURCE_PLL3Q))
3596 {
3597 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
3598 frequency = pll3_clocks.PLL3_Q_Frequency;
3599 }
3600 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_UART4CLKSOURCE_HSI))
3601 {
3602 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
3603 }
3604 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_UART4CLKSOURCE_CSI))
3605 {
3606 frequency = CSI_VALUE;
3607 }
3608 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_UART4CLKSOURCE_LSE))
3609 {
3610 frequency = LSE_VALUE;
3611 }
3612 /* Clock not enabled for UART4 */
3613 else
3614 {
3615 frequency = 0U;
3616 }
3617 break;
3618 #endif /* UART4 */
3619
3620 #if defined(UART5)
3621 case RCC_PERIPHCLK_UART5:
3622 /* Get the current UART5 source */
3623 srcclk = __HAL_RCC_GET_UART5_SOURCE();
3624
3625 if (srcclk == RCC_UART5CLKSOURCE_PCLK1)
3626 {
3627 frequency = HAL_RCC_GetPCLK1Freq();
3628 }
3629 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) && (srcclk == RCC_UART5CLKSOURCE_PLL2Q))
3630 {
3631 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
3632 frequency = pll2_clocks.PLL2_Q_Frequency;
3633 }
3634 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) && (srcclk == RCC_UART5CLKSOURCE_PLL3Q))
3635 {
3636 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
3637 frequency = pll3_clocks.PLL3_Q_Frequency;
3638 }
3639 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_UART5CLKSOURCE_HSI))
3640 {
3641 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
3642 }
3643 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_UART5CLKSOURCE_CSI))
3644 {
3645 frequency = CSI_VALUE;
3646 }
3647 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_UART5CLKSOURCE_LSE))
3648 {
3649 frequency = LSE_VALUE;
3650 }
3651 /* Clock not enabled for UART5 */
3652 else
3653 {
3654 frequency = 0U;
3655 }
3656 break;
3657 #endif /* UART5 */
3658
3659 #if defined(USART6)
3660 case RCC_PERIPHCLK_USART6:
3661 /* Get the current USART6 source */
3662 srcclk = __HAL_RCC_GET_USART6_SOURCE();
3663
3664 if (srcclk == RCC_USART6CLKSOURCE_PCLK1)
3665 {
3666 frequency = HAL_RCC_GetPCLK1Freq();
3667 }
3668 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) && (srcclk == RCC_USART6CLKSOURCE_PLL2Q))
3669 {
3670 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
3671 frequency = pll2_clocks.PLL2_Q_Frequency;
3672 }
3673 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) && (srcclk == RCC_USART6CLKSOURCE_PLL3Q))
3674 {
3675 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
3676 frequency = pll3_clocks.PLL3_Q_Frequency;
3677 }
3678 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART6CLKSOURCE_HSI))
3679 {
3680 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
3681 }
3682 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_USART6CLKSOURCE_CSI))
3683 {
3684 frequency = CSI_VALUE;
3685 }
3686 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART6CLKSOURCE_LSE))
3687 {
3688 frequency = LSE_VALUE;
3689 }
3690 /* Clock not enabled for USART6 */
3691 else
3692 {
3693 frequency = 0U;
3694 }
3695 break;
3696 #endif /* USART6 */
3697
3698 #if defined(UART7)
3699 case RCC_PERIPHCLK_UART7:
3700 /* Get the current UART7 source */
3701 srcclk = __HAL_RCC_GET_UART7_SOURCE();
3702
3703 if (srcclk == RCC_UART7CLKSOURCE_PCLK1)
3704 {
3705 frequency = HAL_RCC_GetPCLK1Freq();
3706 }
3707 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) && (srcclk == RCC_UART7CLKSOURCE_PLL2Q))
3708 {
3709 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
3710 frequency = pll2_clocks.PLL2_Q_Frequency;
3711 }
3712 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) && (srcclk == RCC_UART7CLKSOURCE_PLL3Q))
3713 {
3714 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
3715 frequency = pll3_clocks.PLL3_Q_Frequency;
3716 }
3717 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_UART7CLKSOURCE_HSI))
3718 {
3719 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
3720 }
3721 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_UART7CLKSOURCE_CSI))
3722 {
3723 frequency = CSI_VALUE;
3724 }
3725 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_UART7CLKSOURCE_LSE))
3726 {
3727 frequency = LSE_VALUE;
3728 }
3729 /* Clock not enabled for UART7 */
3730 else
3731 {
3732 frequency = 0U;
3733 }
3734 break;
3735 #endif /* UART7 */
3736
3737 #if defined(UART8)
3738 case RCC_PERIPHCLK_UART8:
3739 /* Get the current UART8 source */
3740 srcclk = __HAL_RCC_GET_UART8_SOURCE();
3741
3742 if (srcclk == RCC_UART8CLKSOURCE_PCLK1)
3743 {
3744 frequency = HAL_RCC_GetPCLK1Freq();
3745 }
3746 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) && (srcclk == RCC_UART8CLKSOURCE_PLL2Q))
3747 {
3748 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
3749 frequency = pll2_clocks.PLL2_Q_Frequency;
3750 }
3751 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) && (srcclk == RCC_UART8CLKSOURCE_PLL3Q))
3752 {
3753 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
3754 frequency = pll3_clocks.PLL3_Q_Frequency;
3755 }
3756 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_UART8CLKSOURCE_HSI))
3757 {
3758 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
3759 }
3760 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_UART8CLKSOURCE_CSI))
3761 {
3762 frequency = CSI_VALUE;
3763 }
3764 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_UART8CLKSOURCE_LSE))
3765 {
3766 frequency = LSE_VALUE;
3767 }
3768 /* Clock not enabled for UART8 */
3769 else
3770 {
3771 frequency = 0U;
3772 }
3773 break;
3774 #endif /* UART8 */
3775
3776 #if defined(UART9)
3777 case RCC_PERIPHCLK_UART9:
3778 /* Get the current UART9 source */
3779 srcclk = __HAL_RCC_GET_UART9_SOURCE();
3780
3781 if (srcclk == RCC_UART9CLKSOURCE_PCLK1)
3782 {
3783 frequency = HAL_RCC_GetPCLK1Freq();
3784 }
3785 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) && (srcclk == RCC_UART9CLKSOURCE_PLL2Q))
3786 {
3787 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
3788 frequency = pll2_clocks.PLL2_Q_Frequency;
3789 }
3790 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) && (srcclk == RCC_UART9CLKSOURCE_PLL3Q))
3791 {
3792 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
3793 frequency = pll3_clocks.PLL3_Q_Frequency;
3794 }
3795 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_UART9CLKSOURCE_HSI))
3796 {
3797 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
3798 }
3799 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_UART9CLKSOURCE_CSI))
3800 {
3801 frequency = CSI_VALUE;
3802 }
3803 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_UART9CLKSOURCE_LSE))
3804 {
3805 frequency = LSE_VALUE;
3806 }
3807 /* Clock not enabled for UART9 */
3808 else
3809 {
3810 frequency = 0U;
3811 }
3812 break;
3813 #endif /* UART9 */
3814
3815 #if defined(USART10)
3816 case RCC_PERIPHCLK_USART10:
3817 /* Get the current USART10 source */
3818 srcclk = __HAL_RCC_GET_USART10_SOURCE();
3819
3820 if (srcclk == RCC_USART10CLKSOURCE_PCLK1)
3821 {
3822 frequency = HAL_RCC_GetPCLK1Freq();
3823 }
3824 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) && (srcclk == RCC_USART10CLKSOURCE_PLL2Q))
3825 {
3826 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
3827 frequency = pll2_clocks.PLL2_Q_Frequency;
3828 }
3829 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) && (srcclk == RCC_USART10CLKSOURCE_PLL3Q))
3830 {
3831 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
3832 frequency = pll3_clocks.PLL3_Q_Frequency;
3833 }
3834 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART10CLKSOURCE_HSI))
3835 {
3836 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
3837 }
3838 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_USART10CLKSOURCE_CSI))
3839 {
3840 frequency = CSI_VALUE;
3841 }
3842 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART10CLKSOURCE_LSE))
3843 {
3844 frequency = LSE_VALUE;
3845 }
3846 /* Clock not enabled for USART10 */
3847 else
3848 {
3849 frequency = 0U;
3850 }
3851 break;
3852 #endif /* USART10 */
3853
3854 #if defined(USART11)
3855 case RCC_PERIPHCLK_USART11:
3856 /* Get the current USART11 source */
3857 srcclk = __HAL_RCC_GET_USART11_SOURCE();
3858
3859 if (srcclk == RCC_USART11CLKSOURCE_PCLK1)
3860 {
3861 frequency = HAL_RCC_GetPCLK1Freq();
3862 }
3863 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) && (srcclk == RCC_USART11CLKSOURCE_PLL2Q))
3864 {
3865 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
3866 frequency = pll2_clocks.PLL2_Q_Frequency;
3867 }
3868 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) && (srcclk == RCC_USART11CLKSOURCE_PLL3Q))
3869 {
3870 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
3871 frequency = pll3_clocks.PLL3_Q_Frequency;
3872 }
3873 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART11CLKSOURCE_HSI))
3874 {
3875 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
3876 }
3877 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_USART11CLKSOURCE_CSI))
3878 {
3879 frequency = CSI_VALUE;
3880 }
3881 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART11CLKSOURCE_LSE))
3882 {
3883 frequency = LSE_VALUE;
3884 }
3885 /* Clock not enabled for USART11 */
3886 else
3887 {
3888 frequency = 0U;
3889 }
3890 break;
3891 #endif /* USART11 */
3892
3893 #if defined(UART12)
3894 case RCC_PERIPHCLK_UART12:
3895 /* Get the current UART12 source */
3896 srcclk = __HAL_RCC_GET_UART12_SOURCE();
3897
3898 if (srcclk == RCC_UART12CLKSOURCE_PCLK1)
3899 {
3900 frequency = HAL_RCC_GetPCLK1Freq();
3901 }
3902 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) && (srcclk == RCC_UART12CLKSOURCE_PLL2Q))
3903 {
3904 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
3905 frequency = pll2_clocks.PLL2_Q_Frequency;
3906 }
3907 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) && (srcclk == RCC_UART12CLKSOURCE_PLL3Q))
3908 {
3909 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
3910 frequency = pll3_clocks.PLL3_Q_Frequency;
3911 }
3912 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_UART12CLKSOURCE_HSI))
3913 {
3914 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
3915 }
3916 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_UART12CLKSOURCE_CSI))
3917 {
3918 frequency = CSI_VALUE;
3919 }
3920 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_UART12CLKSOURCE_LSE))
3921 {
3922 frequency = LSE_VALUE;
3923 }
3924 /* Clock not enabled for UART12 */
3925 else
3926 {
3927 frequency = 0U;
3928 }
3929 break;
3930 #endif /* UART12 */
3931
3932 case RCC_PERIPHCLK_LPUART1:
3933 /* Get the current LPUART1 source */
3934 srcclk = __HAL_RCC_GET_LPUART1_SOURCE();
3935
3936 if (srcclk == RCC_LPUART1CLKSOURCE_PCLK3)
3937 {
3938 frequency = HAL_RCC_GetPCLK3Freq();
3939 }
3940 else if (srcclk == RCC_LPUART1CLKSOURCE_PLL2Q)
3941 {
3942 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
3943 frequency = pll2_clocks.PLL2_Q_Frequency;
3944 }
3945 #if defined(RCC_LPUART1CLKSOURCE_PLL3Q)
3946 else if (srcclk == RCC_LPUART1CLKSOURCE_PLL3Q)
3947 {
3948 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
3949 frequency = pll3_clocks.PLL3_Q_Frequency;
3950 }
3951 #endif /* RCC_LPUART1CLKSOURCE_PLL3Q */
3952 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPUART1CLKSOURCE_HSI))
3953 {
3954 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
3955 }
3956 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_LPUART1CLKSOURCE_CSI))
3957 {
3958 frequency = CSI_VALUE;
3959 }
3960 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPUART1CLKSOURCE_LSE))
3961 {
3962 frequency = LSE_VALUE;
3963 }
3964 /* Clock not enabled for LPUART1 */
3965 else
3966 {
3967 frequency = 0U;
3968 }
3969 break;
3970
3971 case RCC_PERIPHCLK_ADCDAC:
3972 /* Get the current ADCDAC source */
3973 srcclk = __HAL_RCC_GET_ADCDAC_SOURCE();
3974
3975 if (srcclk == RCC_ADCDACCLKSOURCE_HCLK)
3976 {
3977 frequency = HAL_RCC_GetHCLKFreq();
3978 }
3979 else if (srcclk == RCC_ADCDACCLKSOURCE_SYSCLK)
3980 {
3981 frequency = HAL_RCC_GetSysClockFreq();
3982 }
3983 else if (srcclk == RCC_ADCDACCLKSOURCE_PLL2R)
3984 {
3985 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
3986 frequency = pll2_clocks.PLL2_R_Frequency;
3987 }
3988 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_ADCDACCLKSOURCE_HSE))
3989 {
3990 frequency = HSE_VALUE;
3991 }
3992 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_ADCDACCLKSOURCE_HSI))
3993 {
3994 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
3995 }
3996 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_ADCDACCLKSOURCE_CSI))
3997 {
3998 frequency = CSI_VALUE;
3999 }
4000 /* Clock not enabled for ADCDAC */
4001 else
4002 {
4003 frequency = 0U;
4004 }
4005 break;
4006
4007
4008 case RCC_PERIPHCLK_DAC_LP:
4009 /* Get the current DAC low-power source */
4010 srcclk = __HAL_RCC_GET_DAC_LP_SOURCE();
4011
4012 if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_DACLPCLKSOURCE_LSE))
4013 {
4014 frequency = LSE_VALUE;
4015 }
4016 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_DACLPCLKSOURCE_LSI))
4017 {
4018 frequency = LSI_VALUE;
4019 }
4020
4021 /* Clock not enabled for DAC */
4022 else
4023 {
4024 frequency = 0U;
4025 }
4026 break;
4027
4028 case RCC_PERIPHCLK_I2C1:
4029 /* Get the current I2C1 source */
4030 srcclk = __HAL_RCC_GET_I2C1_SOURCE();
4031
4032 if (srcclk == RCC_I2C1CLKSOURCE_PCLK1)
4033 {
4034 frequency = HAL_RCC_GetPCLK1Freq();
4035 }
4036 #if defined(RCC_I2C1CLKSOURCE_PLL3R)
4037 else if (srcclk == RCC_I2C1CLKSOURCE_PLL3R)
4038 {
4039 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
4040 frequency = pll3_clocks.PLL3_R_Frequency;
4041 }
4042 #else
4043 else if (srcclk == RCC_I2C1CLKSOURCE_PLL2R)
4044 {
4045 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
4046 frequency = pll2_clocks.PLL2_R_Frequency;
4047 }
4048 #endif /* RCC_I2C1CLKSOURCE_PLL3R */
4049 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C1CLKSOURCE_HSI))
4050 {
4051 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
4052 }
4053 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_I2C1CLKSOURCE_CSI))
4054 {
4055 frequency = CSI_VALUE;
4056 }
4057 /* Clock not enabled for I2C1 */
4058 else
4059 {
4060 frequency = 0U;
4061 }
4062 break;
4063
4064 case RCC_PERIPHCLK_I2C2:
4065 /* Get the current I2C2 source */
4066 srcclk = __HAL_RCC_GET_I2C2_SOURCE();
4067
4068 if (srcclk == RCC_I2C2CLKSOURCE_PCLK1)
4069 {
4070 frequency = HAL_RCC_GetPCLK1Freq();
4071 }
4072 #if defined(RCC_I2C2CLKSOURCE_PLL3R)
4073 else if (srcclk == RCC_I2C2CLKSOURCE_PLL3R)
4074 {
4075 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
4076 frequency = pll3_clocks.PLL3_R_Frequency;
4077 }
4078 #else
4079 else if (srcclk == RCC_I2C2CLKSOURCE_PLL2R)
4080 {
4081 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
4082 frequency = pll2_clocks.PLL2_R_Frequency;
4083 }
4084 #endif /* RCC_I2C2CLKSOURCE_PLL3R */
4085 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C2CLKSOURCE_HSI))
4086 {
4087 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
4088 }
4089 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_I2C2CLKSOURCE_CSI))
4090 {
4091 frequency = CSI_VALUE;
4092 }
4093 /* Clock not enabled for I2C2 */
4094 else
4095 {
4096 frequency = 0U;
4097 }
4098 break;
4099
4100 #if defined(I2C3)
4101 case RCC_PERIPHCLK_I2C3:
4102 /* Get the current I2C3 source */
4103 srcclk = __HAL_RCC_GET_I2C3_SOURCE();
4104
4105 if (srcclk == RCC_I2C3CLKSOURCE_PCLK3)
4106 {
4107 frequency = HAL_RCC_GetPCLK3Freq();
4108 }
4109 else if (srcclk == RCC_I2C3CLKSOURCE_PLL3R)
4110 {
4111 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
4112 frequency = pll3_clocks.PLL3_R_Frequency;
4113 }
4114 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C3CLKSOURCE_HSI))
4115 {
4116 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
4117 }
4118 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_I2C3CLKSOURCE_CSI))
4119 {
4120 frequency = CSI_VALUE;
4121 }
4122 /* Clock not enabled for I2C3 */
4123 else
4124 {
4125 frequency = 0U;
4126 }
4127 break;
4128 #endif /* I2C3 */
4129
4130 #if defined(I2C4)
4131 case RCC_PERIPHCLK_I2C4:
4132 /* Get the current I2C4 source */
4133 srcclk = __HAL_RCC_GET_I2C4_SOURCE();
4134
4135 if (srcclk == RCC_I2C4CLKSOURCE_PCLK3)
4136 {
4137 frequency = HAL_RCC_GetPCLK3Freq();
4138 }
4139 else if (srcclk == RCC_I2C4CLKSOURCE_PLL3R)
4140 {
4141 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
4142 frequency = pll3_clocks.PLL3_R_Frequency;
4143 }
4144 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C4CLKSOURCE_HSI))
4145 {
4146 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
4147 }
4148 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_I2C4CLKSOURCE_CSI))
4149 {
4150 frequency = CSI_VALUE;
4151 }
4152 /* Clock not enabled for I2C4 */
4153 else
4154 {
4155 frequency = 0U;
4156 }
4157 break;
4158 #endif /* I2C4 */
4159
4160 case RCC_PERIPHCLK_I3C1:
4161 /* Get the current I3C1 source */
4162 srcclk = __HAL_RCC_GET_I3C1_SOURCE();
4163
4164 if (srcclk == RCC_I3C1CLKSOURCE_PCLK1)
4165 {
4166 frequency = HAL_RCC_GetPCLK1Freq();
4167 }
4168 #if defined(RCC_I3C1CLKSOURCE_PLL3R)
4169 else if (srcclk == RCC_I3C1CLKSOURCE_PLL3R)
4170 {
4171 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
4172 frequency = pll3_clocks.PLL3_R_Frequency;
4173 }
4174 #else
4175 else if (srcclk == RCC_I3C1CLKSOURCE_PLL2R)
4176 {
4177 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
4178 frequency = pll2_clocks.PLL2_R_Frequency;
4179 }
4180 #endif /* RCC_I3C1CLKSOURCE_PLL3R */
4181 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I3C1CLKSOURCE_HSI))
4182 {
4183 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
4184 }
4185 /* Clock not enabled for I3C1 */
4186 else
4187 {
4188 frequency = 0U;
4189 }
4190 break;
4191
4192 #if defined(I3C2)
4193 case RCC_PERIPHCLK_I3C2:
4194 /* Get the current I3C2 source */
4195 srcclk = __HAL_RCC_GET_I3C2_SOURCE();
4196
4197 if (srcclk == RCC_I3C2CLKSOURCE_PCLK3)
4198 {
4199 frequency = HAL_RCC_GetPCLK3Freq();
4200 }
4201 else if (srcclk == RCC_I3C2CLKSOURCE_PLL2R)
4202 {
4203 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
4204 frequency = pll2_clocks.PLL2_R_Frequency;
4205 }
4206 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I3C2CLKSOURCE_HSI))
4207 {
4208 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
4209 }
4210 /* Clock not enabled for I3C2 */
4211 else
4212 {
4213 frequency = 0U;
4214 }
4215 break;
4216 #endif /* I3C2*/
4217
4218 case RCC_PERIPHCLK_LPTIM1:
4219 /* Get the current LPTIM1 source */
4220 srcclk = __HAL_RCC_GET_LPTIM1_SOURCE();
4221
4222 switch (srcclk)
4223 {
4224 case RCC_LPTIM1CLKSOURCE_PCLK3:
4225 {
4226 frequency = HAL_RCC_GetPCLK3Freq();
4227 break;
4228 }
4229 case RCC_LPTIM1CLKSOURCE_PLL2P:
4230 {
4231 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
4232 frequency = pll2_clocks.PLL2_P_Frequency;
4233 break;
4234 }
4235 #if defined(RCC_LPTIM1CLKSOURCE_PLL3R)
4236 case RCC_LPTIM1CLKSOURCE_PLL3R:
4237 {
4238 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
4239 frequency = pll3_clocks.PLL3_R_Frequency;
4240 break;
4241 }
4242 #endif /* RCC_LPTIM1CLKSOURCE_PLL3R */
4243 case RCC_LPTIM1CLKSOURCE_LSE:
4244 {
4245 if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))
4246 {
4247 frequency = LSE_VALUE;
4248 }
4249 else
4250 {
4251 frequency = 0;
4252 }
4253 break;
4254 }
4255 case RCC_LPTIM1CLKSOURCE_LSI:
4256 {
4257 if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY))
4258 {
4259 frequency = LSI_VALUE;
4260 }
4261 else
4262 {
4263 frequency = 0;
4264 }
4265 break;
4266 }
4267 case RCC_LPTIM1CLKSOURCE_CLKP: /* CLKP is the clock source for LPTIM1 */
4268 {
4269 ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
4270
4271 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
4272 {
4273 /* In Case the CKPER Source is HSI */
4274 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
4275 }
4276
4277 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
4278 {
4279 /* In Case the CKPER Source is CSI */
4280 frequency = CSI_VALUE;
4281 }
4282
4283 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
4284 {
4285 /* In Case the CKPER Source is HSE */
4286 frequency = HSE_VALUE;
4287 }
4288
4289 else
4290 {
4291 /* In Case the CKPER is disabled*/
4292 frequency = 0;
4293 }
4294
4295 break;
4296 }
4297 default :
4298 {
4299 frequency = 0U;
4300 break;
4301 }
4302 }
4303 break;
4304
4305 case RCC_PERIPHCLK_LPTIM2:
4306 /* Get the current LPTIM2 source */
4307 srcclk = __HAL_RCC_GET_LPTIM2_SOURCE();
4308
4309 switch (srcclk)
4310 {
4311 case RCC_LPTIM2CLKSOURCE_PCLK1:
4312 {
4313 frequency = HAL_RCC_GetPCLK1Freq();
4314 break;
4315 }
4316 case RCC_LPTIM2CLKSOURCE_PLL2P:
4317 {
4318 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
4319 frequency = pll2_clocks.PLL2_P_Frequency;
4320 break;
4321 }
4322 #if defined(RCC_LPTIM2CLKSOURCE_PLL3R)
4323 case RCC_LPTIM2CLKSOURCE_PLL3R:
4324 {
4325 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
4326 frequency = pll3_clocks.PLL3_R_Frequency;
4327 break;
4328 }
4329 #endif /* RCC_LPTIM2CLKSOURCE_PLL3R */
4330 case RCC_LPTIM2CLKSOURCE_LSE:
4331 {
4332 if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))
4333 {
4334 frequency = LSE_VALUE;
4335 }
4336 else
4337 {
4338 frequency = 0;
4339 }
4340 break;
4341 }
4342 case RCC_LPTIM2CLKSOURCE_LSI:
4343 {
4344 if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY))
4345 {
4346 frequency = LSI_VALUE;
4347 }
4348 else
4349 {
4350 frequency = 0;
4351 }
4352 break;
4353 }
4354 case RCC_LPTIM2CLKSOURCE_CLKP: /* CLKP is the clock source for LPTIM2 */
4355 {
4356 ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
4357
4358 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
4359 {
4360 /* In Case the CKPER Source is HSI */
4361 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
4362 }
4363
4364 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
4365 {
4366 /* In Case the CKPER Source is CSI */
4367 frequency = CSI_VALUE;
4368 }
4369
4370 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
4371 {
4372 /* In Case the CKPER Source is HSE */
4373 frequency = HSE_VALUE;
4374 }
4375
4376 else
4377 {
4378 /* In Case the CKPER is disabled*/
4379 frequency = 0;
4380 }
4381
4382 break;
4383 }
4384 default :
4385 {
4386 frequency = 0U;
4387 break;
4388 }
4389 }
4390 break;
4391
4392 #if defined(LPTIM3)
4393 case RCC_PERIPHCLK_LPTIM3:
4394 /* Get the current LPTIM3 source */
4395 srcclk = __HAL_RCC_GET_LPTIM3_SOURCE();
4396
4397 switch (srcclk)
4398 {
4399 case RCC_LPTIM3CLKSOURCE_PCLK3:
4400 {
4401 frequency = HAL_RCC_GetPCLK3Freq();
4402 break;
4403 }
4404 case RCC_LPTIM3CLKSOURCE_PLL2P:
4405 {
4406 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
4407 frequency = pll2_clocks.PLL2_P_Frequency;
4408 break;
4409 }
4410 case RCC_LPTIM3CLKSOURCE_PLL3R:
4411 {
4412 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
4413 frequency = pll3_clocks.PLL3_R_Frequency;
4414 break;
4415 }
4416 case RCC_LPTIM3CLKSOURCE_LSE:
4417 {
4418 if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))
4419 {
4420 frequency = LSE_VALUE;
4421 }
4422 else
4423 {
4424 frequency = 0;
4425 }
4426 break;
4427 }
4428 case RCC_LPTIM3CLKSOURCE_LSI:
4429 {
4430 if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY))
4431 {
4432 frequency = LSI_VALUE;
4433 }
4434 else
4435 {
4436 frequency = 0;
4437 }
4438 break;
4439 }
4440 case RCC_LPTIM3CLKSOURCE_CLKP: /* CLKP is the clock source for LPTIM3 */
4441 {
4442 ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
4443
4444 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
4445 {
4446 /* In Case the CKPER Source is HSI */
4447 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
4448 }
4449
4450 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
4451 {
4452 /* In Case the CKPER Source is CSI */
4453 frequency = CSI_VALUE;
4454 }
4455
4456 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
4457 {
4458 /* In Case the CKPER Source is HSE */
4459 frequency = HSE_VALUE;
4460 }
4461
4462 else
4463 {
4464 /* In Case the CKPER is disabled*/
4465 frequency = 0;
4466 }
4467
4468 break;
4469 }
4470 default :
4471 {
4472 frequency = 0U;
4473 break;
4474 }
4475 }
4476 break;
4477 #endif /* LPTIM3 */
4478
4479 #if defined(LPTIM4)
4480 case RCC_PERIPHCLK_LPTIM4:
4481 /* Get the current LPTIM4 source */
4482 srcclk = __HAL_RCC_GET_LPTIM4_SOURCE();
4483
4484 switch (srcclk)
4485 {
4486 case RCC_LPTIM4CLKSOURCE_PCLK3:
4487 {
4488 frequency = HAL_RCC_GetPCLK3Freq();
4489 break;
4490 }
4491 case RCC_LPTIM4CLKSOURCE_PLL2P:
4492 {
4493 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
4494 frequency = pll2_clocks.PLL2_P_Frequency;
4495 break;
4496 }
4497 case RCC_LPTIM4CLKSOURCE_PLL3R:
4498 {
4499 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
4500 frequency = pll3_clocks.PLL3_R_Frequency;
4501 break;
4502 }
4503 case RCC_LPTIM4CLKSOURCE_LSE:
4504 {
4505 if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))
4506 {
4507 frequency = LSE_VALUE;
4508 }
4509 else
4510 {
4511 frequency = 0;
4512 }
4513 break;
4514 }
4515 case RCC_LPTIM4CLKSOURCE_LSI:
4516 {
4517 if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY))
4518 {
4519 frequency = LSI_VALUE;
4520 }
4521 else
4522 {
4523 frequency = 0;
4524 }
4525 break;
4526 }
4527 case RCC_LPTIM4CLKSOURCE_CLKP: /* CLKP is the clock source for LPTIM4 */
4528 {
4529 ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
4530
4531 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
4532 {
4533 /* In Case the CKPER Source is HSI */
4534 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
4535 }
4536
4537 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
4538 {
4539 /* In Case the CKPER Source is CSI */
4540 frequency = CSI_VALUE;
4541 }
4542
4543 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
4544 {
4545 /* In Case the CKPER Source is HSE */
4546 frequency = HSE_VALUE;
4547 }
4548
4549 else
4550 {
4551 /* In Case the CKPER is disabled*/
4552 frequency = 0;
4553 }
4554
4555 break;
4556 }
4557 default :
4558 {
4559 frequency = 0U;
4560 break;
4561 }
4562 }
4563 break;
4564 #endif /* LPTIM4 */
4565
4566 #if defined(LPTIM5)
4567 case RCC_PERIPHCLK_LPTIM5:
4568 /* Get the current LPTIM5 source */
4569 srcclk = __HAL_RCC_GET_LPTIM5_SOURCE();
4570
4571 switch (srcclk)
4572 {
4573 case RCC_LPTIM5CLKSOURCE_PCLK3:
4574 {
4575 frequency = HAL_RCC_GetPCLK3Freq();
4576 break;
4577 }
4578 case RCC_LPTIM5CLKSOURCE_PLL2P:
4579 {
4580 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
4581 frequency = pll2_clocks.PLL2_P_Frequency;
4582 break;
4583 }
4584 case RCC_LPTIM5CLKSOURCE_PLL3R:
4585 {
4586 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
4587 frequency = pll3_clocks.PLL3_R_Frequency;
4588 break;
4589 }
4590 case RCC_LPTIM5CLKSOURCE_LSE:
4591 {
4592 if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))
4593 {
4594 frequency = LSE_VALUE;
4595 }
4596 else
4597 {
4598 frequency = 0;
4599 }
4600 break;
4601 }
4602 case RCC_LPTIM5CLKSOURCE_LSI:
4603 {
4604 if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY))
4605 {
4606 frequency = LSI_VALUE;
4607 }
4608 else
4609 {
4610 frequency = 0;
4611 }
4612 break;
4613 }
4614 case RCC_LPTIM5CLKSOURCE_CLKP: /* CLKP is the clock source for LPTIM5 */
4615 {
4616 ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
4617
4618 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
4619 {
4620 /* In Case the CKPER Source is HSI */
4621 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
4622 }
4623
4624 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
4625 {
4626 /* In Case the CKPER Source is CSI */
4627 frequency = CSI_VALUE;
4628 }
4629
4630 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
4631 {
4632 /* In Case the CKPER Source is HSE */
4633 frequency = HSE_VALUE;
4634 }
4635
4636 else
4637 {
4638 /* In Case the CKPER is disabled*/
4639 frequency = 0;
4640 }
4641
4642 break;
4643 }
4644 default :
4645 {
4646 frequency = 0U;
4647 break;
4648 }
4649 }
4650 break;
4651 #endif /* LPTIM5 */
4652
4653 #if defined(LPTIM6)
4654 case RCC_PERIPHCLK_LPTIM6:
4655 /* Get the current LPTIM6 source */
4656 srcclk = __HAL_RCC_GET_LPTIM6_SOURCE();
4657
4658 switch (srcclk)
4659 {
4660 case RCC_LPTIM6CLKSOURCE_PCLK3:
4661 {
4662 frequency = HAL_RCC_GetPCLK3Freq();
4663 break;
4664 }
4665 case RCC_LPTIM6CLKSOURCE_PLL2P:
4666 {
4667 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
4668 frequency = pll2_clocks.PLL2_P_Frequency;
4669 break;
4670 }
4671 case RCC_LPTIM6CLKSOURCE_PLL3R:
4672 {
4673 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
4674 frequency = pll3_clocks.PLL3_R_Frequency;
4675 break;
4676 }
4677 case RCC_LPTIM6CLKSOURCE_LSE:
4678 {
4679 if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))
4680 {
4681 frequency = LSE_VALUE;
4682 }
4683 else
4684 {
4685 frequency = 0;
4686 }
4687 break;
4688 }
4689 case RCC_LPTIM6CLKSOURCE_LSI:
4690 {
4691 if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY))
4692 {
4693 frequency = LSI_VALUE;
4694 }
4695 else
4696 {
4697 frequency = 0;
4698 }
4699 break;
4700 }
4701 case RCC_LPTIM6CLKSOURCE_CLKP: /* CLKP is the clock source for LPTIM6 */
4702 {
4703 ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
4704
4705 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
4706 {
4707 /* In Case the CKPER Source is HSI */
4708 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
4709 }
4710
4711 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
4712 {
4713 /* In Case the CKPER Source is CSI */
4714 frequency = CSI_VALUE;
4715 }
4716
4717 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
4718 {
4719 /* In Case the CKPER Source is HSE */
4720 frequency = HSE_VALUE;
4721 }
4722
4723 else
4724 {
4725 /* In Case the CKPER is disabled*/
4726 frequency = 0;
4727 }
4728
4729 break;
4730 }
4731 default :
4732 {
4733 frequency = 0U;
4734 break;
4735 }
4736 }
4737 break;
4738 #endif /* LPTIM6 */
4739
4740 #if defined(FDCAN2)
4741 case RCC_PERIPHCLK_FDCAN12:
4742 /* Get the current FDCAN2 kernel source */
4743 srcclk = __HAL_RCC_GET_FDCAN12_SOURCE();
4744
4745 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_FDCAN12CLKSOURCE_HSE))
4746 {
4747 frequency = HSE_VALUE;
4748 }
4749 else if (srcclk == RCC_FDCAN12CLKSOURCE_PLL1Q)
4750 {
4751 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
4752 frequency = pll1_clocks.PLL1_Q_Frequency;
4753 }
4754 else if (srcclk == RCC_FDCAN12CLKSOURCE_PLL2Q)
4755 {
4756 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
4757 frequency = pll2_clocks.PLL2_Q_Frequency;
4758 }
4759 /* Clock not enabled for FDCAN2 */
4760 else
4761 {
4762 frequency = 0U;
4763 }
4764 break;
4765
4766 #else
4767
4768 case RCC_PERIPHCLK_FDCAN1:
4769 /* Get the current FDCAN1 kernel source */
4770 srcclk = __HAL_RCC_GET_FDCAN1_SOURCE();
4771
4772 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_FDCAN1CLKSOURCE_HSE))
4773 {
4774 frequency = HSE_VALUE;
4775 }
4776 else if (srcclk == RCC_FDCAN1CLKSOURCE_PLL1Q)
4777 {
4778 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
4779 frequency = pll1_clocks.PLL1_Q_Frequency;
4780 }
4781 else if (srcclk == RCC_FDCAN1CLKSOURCE_PLL2Q)
4782 {
4783 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
4784 frequency = pll2_clocks.PLL2_Q_Frequency;
4785 }
4786 /* Clock not enabled for FDCAN1 */
4787 else
4788 {
4789 frequency = 0U;
4790 }
4791 break;
4792
4793 #endif /* FDCAN2 */
4794
4795 case RCC_PERIPHCLK_SPI1:
4796 /* Get the current SPI1 kernel source */
4797 srcclk = __HAL_RCC_GET_SPI1_SOURCE();
4798 switch (srcclk)
4799 {
4800 case RCC_SPI1CLKSOURCE_PLL1Q:
4801 {
4802 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
4803 frequency = pll1_clocks.PLL1_Q_Frequency;
4804 break;
4805 }
4806 case RCC_SPI1CLKSOURCE_PLL2P:
4807 {
4808 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
4809 frequency = pll2_clocks.PLL2_P_Frequency;
4810 break;
4811 }
4812 #if defined(RCC_SPI1CLKSOURCE_PLL3P)
4813 case RCC_SPI1CLKSOURCE_PLL3P:
4814 {
4815 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
4816 frequency = pll3_clocks.PLL3_P_Frequency;
4817 break;
4818 }
4819 #endif /* RCC_SPI1CLKSOURCE_PLL3P */
4820 case RCC_SPI1CLKSOURCE_PIN:
4821 {
4822 frequency = EXTERNAL_CLOCK_VALUE;
4823 break;
4824 }
4825 case RCC_SPI1CLKSOURCE_CLKP:
4826 {
4827 ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
4828
4829 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
4830 {
4831 /* In Case the CKPER Source is HSI */
4832 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
4833 }
4834
4835 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
4836 {
4837 /* In Case the CKPER Source is CSI */
4838 frequency = CSI_VALUE;
4839 }
4840
4841 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
4842 {
4843 /* In Case the CKPER Source is HSE */
4844 frequency = HSE_VALUE;
4845 }
4846
4847 else
4848 {
4849 /* In Case the CKPER is disabled*/
4850 frequency = 0;
4851 }
4852
4853 break;
4854 }
4855 default:
4856 {
4857 frequency = 0;
4858 break;
4859 }
4860 }
4861 break;
4862
4863 case RCC_PERIPHCLK_SPI2:
4864 /* Get the current SPI2 kernel source */
4865 srcclk = __HAL_RCC_GET_SPI2_SOURCE();
4866 switch (srcclk)
4867 {
4868 case RCC_SPI2CLKSOURCE_PLL1Q:
4869 {
4870 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
4871 frequency = pll1_clocks.PLL1_Q_Frequency;
4872 break;
4873 }
4874 case RCC_SPI2CLKSOURCE_PLL2P:
4875 {
4876 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
4877 frequency = pll2_clocks.PLL2_P_Frequency;
4878 break;
4879 }
4880 #if defined(RCC_SPI2CLKSOURCE_PLL3P)
4881 case RCC_SPI2CLKSOURCE_PLL3P:
4882 {
4883 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
4884 frequency = pll3_clocks.PLL3_P_Frequency;
4885 break;
4886 }
4887 #endif /* RCC_SPI2CLKSOURCE_PLL3P */
4888 case RCC_SPI2CLKSOURCE_PIN:
4889 {
4890 frequency = EXTERNAL_CLOCK_VALUE;
4891 break;
4892 }
4893 case RCC_SPI2CLKSOURCE_CLKP:
4894 {
4895 ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
4896
4897 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
4898 {
4899 /* In Case the CKPER Source is HSI */
4900 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
4901 }
4902
4903 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
4904 {
4905 /* In Case the CKPER Source is CSI */
4906 frequency = CSI_VALUE;
4907 }
4908
4909 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
4910 {
4911 /* In Case the CKPER Source is HSE */
4912 frequency = HSE_VALUE;
4913 }
4914
4915 else
4916 {
4917 /* In Case the CKPER is disabled*/
4918 frequency = 0;
4919 }
4920
4921 break;
4922 }
4923 default:
4924 {
4925 frequency = 0;
4926 break;
4927 }
4928 }
4929 break;
4930
4931 case RCC_PERIPHCLK_SPI3:
4932 /* Get the current SPI3 kernel source */
4933 srcclk = __HAL_RCC_GET_SPI3_SOURCE();
4934 switch (srcclk)
4935 {
4936 case RCC_SPI3CLKSOURCE_PLL1Q:
4937 {
4938 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
4939 frequency = pll1_clocks.PLL1_Q_Frequency;
4940 break;
4941 }
4942 case RCC_SPI3CLKSOURCE_PLL2P:
4943 {
4944 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
4945 frequency = pll2_clocks.PLL2_P_Frequency;
4946 break;
4947 }
4948 #if defined(RCC_SPI3CLKSOURCE_PLL3P)
4949 case RCC_SPI3CLKSOURCE_PLL3P:
4950 {
4951 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
4952 frequency = pll3_clocks.PLL3_P_Frequency;
4953 break;
4954 }
4955 #endif /* RCC_SPI3CLKSOURCE_PLL3P */
4956 case RCC_SPI3CLKSOURCE_PIN:
4957 {
4958 frequency = EXTERNAL_CLOCK_VALUE;
4959 break;
4960 }
4961 case RCC_SPI3CLKSOURCE_CLKP:
4962 {
4963 ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
4964
4965 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
4966 {
4967 /* In Case the CKPER Source is HSI */
4968 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
4969 }
4970
4971 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
4972 {
4973 /* In Case the CKPER Source is CSI */
4974 frequency = CSI_VALUE;
4975 }
4976
4977 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
4978 {
4979 /* In Case the CKPER Source is HSE */
4980 frequency = HSE_VALUE;
4981 }
4982
4983 else
4984 {
4985 /* In Case the CKPER is disabled*/
4986 frequency = 0;
4987 }
4988
4989 break;
4990 }
4991 default:
4992 {
4993 frequency = 0;
4994 break;
4995 }
4996 }
4997 break;
4998
4999 #if defined(SPI4)
5000 case RCC_PERIPHCLK_SPI4:
5001 /* Get the current SPI4 kernel source */
5002 srcclk = __HAL_RCC_GET_SPI4_SOURCE();
5003
5004 if (srcclk == RCC_SPI4CLKSOURCE_PCLK2)
5005 {
5006 frequency = HAL_RCC_GetPCLK2Freq();
5007 }
5008 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) && (srcclk == RCC_SPI4CLKSOURCE_PLL2Q))
5009 {
5010 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
5011 frequency = pll2_clocks.PLL2_Q_Frequency;
5012 }
5013 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) && (srcclk == RCC_SPI4CLKSOURCE_PLL3Q))
5014 {
5015 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
5016 frequency = pll3_clocks.PLL3_Q_Frequency;
5017 }
5018 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_SPI4CLKSOURCE_HSI))
5019 {
5020 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
5021 }
5022 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_SPI4CLKSOURCE_CSI))
5023 {
5024 frequency = CSI_VALUE;
5025 }
5026 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_SPI4CLKSOURCE_HSE))
5027 {
5028 frequency = HSE_VALUE;
5029 }
5030 /* Clock not enabled for SPI4 */
5031 else
5032 {
5033 frequency = 0U;
5034 }
5035
5036 break;
5037 #endif /* SPI4 */
5038
5039 #if defined(SPI5)
5040 case RCC_PERIPHCLK_SPI5:
5041 /* Get the current SPI5 kernel source */
5042 srcclk = __HAL_RCC_GET_SPI5_SOURCE();
5043
5044 if (srcclk == RCC_SPI5CLKSOURCE_PCLK3)
5045 {
5046 frequency = HAL_RCC_GetPCLK3Freq();
5047 }
5048 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) && (srcclk == RCC_SPI5CLKSOURCE_PLL2Q))
5049 {
5050 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
5051 frequency = pll2_clocks.PLL2_Q_Frequency;
5052 }
5053 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) && (srcclk == RCC_SPI5CLKSOURCE_PLL3Q))
5054 {
5055 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
5056 frequency = pll3_clocks.PLL3_Q_Frequency;
5057 }
5058 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_SPI5CLKSOURCE_HSI))
5059 {
5060 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
5061 }
5062 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_SPI5CLKSOURCE_CSI))
5063 {
5064 frequency = CSI_VALUE;
5065 }
5066 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_SPI5CLKSOURCE_HSE))
5067 {
5068 frequency = HSE_VALUE;
5069 }
5070 /* Clock not enabled for SPI5 */
5071 else
5072 {
5073 frequency = 0U;
5074 }
5075
5076 break;
5077 #endif /* SPI5 */
5078
5079 #if defined(SPI6)
5080 case RCC_PERIPHCLK_SPI6:
5081 /* Get the current SPI6 kernel source */
5082 srcclk = __HAL_RCC_GET_SPI6_SOURCE();
5083
5084 if (srcclk == RCC_SPI6CLKSOURCE_PCLK2)
5085 {
5086 frequency = HAL_RCC_GetPCLK2Freq();
5087 }
5088 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) && (srcclk == RCC_SPI6CLKSOURCE_PLL2Q))
5089 {
5090 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
5091 frequency = pll2_clocks.PLL2_Q_Frequency;
5092 }
5093 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) && (srcclk == RCC_SPI6CLKSOURCE_PLL3Q))
5094 {
5095 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
5096 frequency = pll3_clocks.PLL3_Q_Frequency;
5097 }
5098 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_SPI6CLKSOURCE_HSI))
5099 {
5100 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
5101 }
5102 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_SPI6CLKSOURCE_CSI))
5103 {
5104 frequency = CSI_VALUE;
5105 }
5106 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_SPI6CLKSOURCE_HSE))
5107 {
5108 frequency = HSE_VALUE;
5109 }
5110 /* Clock not enabled for SPI6 */
5111 else
5112 {
5113 frequency = 0U;
5114 }
5115
5116 break;
5117 #endif /* SPI6 */
5118
5119 #if defined(OCTOSPI1)
5120 case RCC_PERIPHCLK_OSPI:
5121 /* Get the current OSPI kernel source */
5122 srcclk = __HAL_RCC_GET_OSPI_SOURCE();
5123
5124 switch (srcclk)
5125 {
5126 case RCC_OSPICLKSOURCE_HCLK:
5127 {
5128 frequency = HAL_RCC_GetHCLKFreq();
5129 break;
5130 }
5131 case RCC_OSPICLKSOURCE_PLL1Q:
5132 {
5133 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
5134 frequency = pll1_clocks.PLL1_Q_Frequency;
5135 break;
5136 }
5137 case RCC_OSPICLKSOURCE_PLL2R:
5138 {
5139 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
5140 frequency = pll2_clocks.PLL2_R_Frequency;
5141 break;
5142 }
5143 case RCC_OSPICLKSOURCE_CLKP:
5144 {
5145 ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
5146
5147 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
5148 {
5149 /* In Case the CKPER Source is HSI */
5150 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
5151 }
5152
5153 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
5154 {
5155 /* In Case the CKPER Source is CSI */
5156 frequency = CSI_VALUE;
5157 }
5158
5159 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
5160 {
5161 /* In Case the CKPER Source is HSE */
5162 frequency = HSE_VALUE;
5163 }
5164
5165 else
5166 {
5167 /* In Case the CKPER is disabled*/
5168 frequency = 0U;
5169 }
5170
5171 break;
5172 }
5173 default:
5174 {
5175 frequency = 0U;
5176 break;
5177 }
5178 }
5179 break;
5180 #endif /* OCTOSPI1*/
5181
5182 #if defined(CEC)
5183 case RCC_PERIPHCLK_CEC:
5184 /* Get the current CEC source */
5185 srcclk = __HAL_RCC_GET_CEC_SOURCE();
5186
5187 if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_CECCLKSOURCE_LSE))
5188 {
5189 frequency = LSE_VALUE;
5190 }
5191 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_CECCLKSOURCE_LSI))
5192 {
5193 frequency = LSI_VALUE;
5194 }
5195 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_CECCLKSOURCE_CSI_DIV122))
5196 {
5197 frequency = CSI_VALUE / 122U;
5198 }
5199
5200 /* Clock not enabled for CEC */
5201 else
5202 {
5203 frequency = 0U;
5204 }
5205 break;
5206 #endif /* CEC */
5207
5208 case RCC_PERIPHCLK_RNG:
5209 /* Get the current RNG source */
5210 srcclk = __HAL_RCC_GET_RNG_SOURCE();
5211
5212 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSI48RDY)) && (srcclk == RCC_RNGCLKSOURCE_HSI48))
5213 {
5214 frequency = HSI48_VALUE;
5215 }
5216 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) && (srcclk == RCC_RNGCLKSOURCE_PLL1Q))
5217 {
5218 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
5219 frequency = pll1_clocks.PLL1_Q_Frequency;
5220 }
5221 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_RNGCLKSOURCE_LSE))
5222 {
5223 frequency = LSE_VALUE;
5224 }
5225 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_RNGCLKSOURCE_LSI))
5226 {
5227 frequency = LSI_VALUE;
5228 }
5229
5230 /* Clock not enabled for RNG */
5231 else
5232 {
5233 frequency = 0U;
5234 }
5235 break;
5236
5237 case RCC_PERIPHCLK_USB:
5238 /* Get the current USB kernel source */
5239 srcclk = __HAL_RCC_GET_USB_SOURCE();
5240
5241 if (srcclk == RCC_USBCLKSOURCE_PLL1Q)
5242 {
5243 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
5244 frequency = pll1_clocks.PLL1_Q_Frequency;
5245 break;
5246 }
5247 #if defined(RCC_USBCLKSOURCE_PLL3Q)
5248 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) && (srcclk == RCC_USBCLKSOURCE_PLL3Q))
5249 {
5250 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
5251 frequency = pll3_clocks.PLL3_Q_Frequency;
5252 }
5253 #else
5254 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) && (srcclk == RCC_USBCLKSOURCE_PLL2Q))
5255 {
5256 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
5257 frequency = pll2_clocks.PLL2_Q_Frequency;
5258 }
5259 #endif /* RCC_USBCLKSOURCE_PLL3 */
5260 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSI48RDY)) && (srcclk == RCC_USBCLKSOURCE_HSI48))
5261 {
5262 frequency = HSI48_VALUE;
5263 }
5264 /* Clock not enabled for USB */
5265 else
5266 {
5267 frequency = 0U;
5268 }
5269
5270 break;
5271
5272
5273 default:
5274 frequency = 0U;
5275 break;
5276 }
5277 }
5278
5279 return (frequency);
5280 }
5281
5282 /**
5283 * @}
5284 */
5285
5286 /** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions
5287 * @brief Extended Clock management functions
5288 *
5289 @verbatim
5290 ===============================================================================
5291 ##### Extended clock management functions #####
5292 ===============================================================================
5293 [..]
5294 This subsection provides a set of functions allowing to control the
5295 activation or deactivation of PLL2, PLL3, LSE CSS,
5296 Low speed clock output and clock after wake-up from STOP mode.
5297 @endverbatim
5298 * @{
5299 */
5300
5301 /**
5302 * @brief Initialize and Enable the PLL2 according to the specified
5303 * parameters in the RCC_PLL2InitTypeDef.
5304 * @param pPLL2Init pointer to an RCC_PLL2InitTypeDef structure that
5305 * contains the configuration information for the PLL2
5306 * @retval HAL status
5307 */
HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef * pPLL2Init)5308 HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *pPLL2Init)
5309 {
5310 uint32_t tickstart;
5311 HAL_StatusTypeDef status = HAL_OK;
5312
5313 /* check for PLL2 Parameters used to output PLL2CLK */
5314 assert_param(IS_RCC_PLL2_SOURCE(pPLL2Init->PLL2Source));
5315 assert_param(IS_RCC_PLL2_DIVM_VALUE(pPLL2Init->PLL2M));
5316 assert_param(IS_RCC_PLL2_MULN_VALUE(pPLL2Init->PLL2N));
5317 assert_param(IS_RCC_PLL2_DIVP_VALUE(pPLL2Init->PLL2P));
5318 assert_param(IS_RCC_PLL2_DIVQ_VALUE(pPLL2Init->PLL2Q));
5319 assert_param(IS_RCC_PLL2_DIVR_VALUE(pPLL2Init->PLL2R));
5320 assert_param(IS_RCC_PLL2_CLOCKOUT_VALUE(pPLL2Init->PLL2ClockOut));
5321 assert_param(IS_RCC_PLL2_VCIRGE_VALUE(pPLL2Init->PLL2RGE));
5322 assert_param(IS_RCC_PLL2_VCORGE_VALUE(pPLL2Init->PLL2VCOSEL));
5323 assert_param(IS_RCC_PLL2_FRACN_VALUE(pPLL2Init->PLL2FRACN));
5324
5325 /* Disable the PLL2 */
5326 __HAL_RCC_PLL2_DISABLE();
5327
5328 /* Get Start Tick*/
5329 tickstart = HAL_GetTick();
5330
5331 /* Wait till PLL2 is ready to be updated */
5332 while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != 0U)
5333 {
5334 if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
5335 {
5336 status = HAL_TIMEOUT;
5337 break;
5338 }
5339 }
5340
5341 if (status == HAL_OK)
5342 {
5343 /* Make sure PLL2Source is ready */
5344 status = RCCEx_PLLSource_Enable(pPLL2Init->PLL2Source);
5345
5346 if (status == HAL_OK)
5347 {
5348 /* Configure the PLL2 clock source, multiplication factor N, */
5349 /* and division factors M, P, Q and R */
5350 __HAL_RCC_PLL2_CONFIG(pPLL2Init->PLL2Source, pPLL2Init->PLL2M, pPLL2Init->PLL2N,
5351 pPLL2Init->PLL2P, pPLL2Init->PLL2Q, pPLL2Init->PLL2R);
5352
5353 /* Disable PLL2FRACN . */
5354 __HAL_RCC_PLL2_FRACN_DISABLE();
5355
5356 /* Configure PLL2 FRACN */
5357 __HAL_RCC_PLL2_FRACN_CONFIG(pPLL2Init->PLL2FRACN);
5358
5359 /* Enable PLL2FRACN */
5360 __HAL_RCC_PLL2_FRACN_ENABLE();
5361
5362 /* Select PLL2 input reference frequency range: VCI */
5363 __HAL_RCC_PLL2_VCIRANGE(pPLL2Init->PLL2RGE);
5364
5365 /* Select PLL2 output frequency range : VCO */
5366 __HAL_RCC_PLL2_VCORANGE(pPLL2Init->PLL2VCOSEL);
5367
5368 /* Configure the PLL2 Clock output(s) */
5369 __HAL_RCC_PLL2_CLKOUT_ENABLE(pPLL2Init->PLL2ClockOut);
5370
5371 /* Enable the PLL2 again by setting PLL2ON to 1*/
5372 __HAL_RCC_PLL2_ENABLE();
5373
5374 /* Get Start Tick*/
5375 tickstart = HAL_GetTick();
5376
5377 /* Wait till PLL2 is ready */
5378 while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) == 0U)
5379 {
5380 if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
5381 {
5382 status = HAL_TIMEOUT;
5383 break;
5384 }
5385 }
5386 }
5387 }
5388
5389 return status;
5390 }
5391
5392 /**
5393 * @brief Disable PLL2.
5394 * @retval HAL status
5395 */
HAL_RCCEx_DisablePLL2(void)5396 HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void)
5397 {
5398 uint32_t tickstart;
5399 HAL_StatusTypeDef status = HAL_OK;
5400
5401 /* Disable the PLL2 */
5402 __HAL_RCC_PLL2_DISABLE();
5403
5404 /* Get Start Tick*/
5405 tickstart = HAL_GetTick();
5406
5407 /* Wait till PLL2 is disabled */
5408 while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != 0U)
5409 {
5410 if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
5411 {
5412 status = HAL_TIMEOUT;
5413 break;
5414 }
5415 }
5416
5417 /* To save power, disable the PLL2 Source, FRACN and Clock outputs */
5418 CLEAR_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2PEN | RCC_PLL2CFGR_PLL2QEN | RCC_PLL2CFGR_PLL2REN | RCC_PLL2CFGR_PLL2SRC |
5419 RCC_PLL2CFGR_PLL2FRACEN);
5420
5421 return status;
5422 }
5423
5424 #if defined(RCC_CR_PLL3ON)
5425 /**
5426 * @brief Initialize and Enable the PLL3 according to the specified
5427 * parameters in the RCC_PLL3InitTypeDef.
5428 * @param pPLL3Init pointer to an RCC_PLL3InitTypeDef structure that
5429 * contains the configuration information for the PLL3
5430 * @retval HAL status.
5431 */
HAL_RCCEx_EnablePLL3(RCC_PLL3InitTypeDef * pPLL3Init)5432 HAL_StatusTypeDef HAL_RCCEx_EnablePLL3(RCC_PLL3InitTypeDef *pPLL3Init)
5433 {
5434 uint32_t tickstart;
5435 HAL_StatusTypeDef status = HAL_OK;
5436
5437 /* check for PLL3 Parameters used to output PLL3CLK */
5438 assert_param(IS_RCC_PLL3_SOURCE(pPLL3Init->PLL3Source));
5439 assert_param(IS_RCC_PLL3_DIVM_VALUE(pPLL3Init->PLL3M));
5440 assert_param(IS_RCC_PLL3_MULN_VALUE(pPLL3Init->PLL3N));
5441 assert_param(IS_RCC_PLL3_DIVP_VALUE(pPLL3Init->PLL3P));
5442 assert_param(IS_RCC_PLL3_DIVQ_VALUE(pPLL3Init->PLL3Q));
5443 assert_param(IS_RCC_PLL3_DIVR_VALUE(pPLL3Init->PLL3R));
5444 assert_param(IS_RCC_PLL3_CLOCKOUT_VALUE(pPLL3Init->PLL3ClockOut));
5445 assert_param(IS_RCC_PLL3_VCIRGE_VALUE(pPLL3Init->PLL3RGE));
5446 assert_param(IS_RCC_PLL3_VCORGE_VALUE(pPLL3Init->PLL3VCOSEL));
5447 assert_param(IS_RCC_PLL3_FRACN_VALUE(pPLL3Init->PLL3FRACN));
5448
5449 /* Disable the PLL3 */
5450 __HAL_RCC_PLL3_DISABLE();
5451
5452 /* Get Start Tick*/
5453 tickstart = HAL_GetTick();
5454
5455 /* Wait till PLL3 is ready to be updated */
5456 while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != 0U)
5457 {
5458 if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE)
5459 {
5460 status = HAL_TIMEOUT;
5461 break;
5462 }
5463 }
5464
5465 if (status == HAL_OK)
5466 {
5467 /* Make sure PLL3Source is ready */
5468 status = RCCEx_PLLSource_Enable(pPLL3Init->PLL3Source);
5469
5470 if (status == HAL_OK)
5471 {
5472 /* Configure the PLL3 clock source, multiplication factor N, */
5473 /* and division factors M and P */
5474 __HAL_RCC_PLL3_CONFIG(pPLL3Init->PLL3Source, pPLL3Init->PLL3M, pPLL3Init->PLL3N, pPLL3Init->PLL3P,
5475 pPLL3Init->PLL3Q, pPLL3Init->PLL3R);
5476
5477 /* Disable PLL3FRACN . */
5478 __HAL_RCC_PLL3_FRACN_DISABLE();
5479
5480 /* Configure PLL3 FRACN */
5481 __HAL_RCC_PLL3_FRACN_CONFIG(pPLL3Init->PLL3FRACN);
5482
5483 /* Enable PLL3FRACN . */
5484 __HAL_RCC_PLL3_FRACN_ENABLE();
5485
5486 /* Select PLL3 input reference frequency range: VCI */
5487 __HAL_RCC_PLL3_VCIRANGE(pPLL3Init->PLL3RGE);
5488
5489 /* Select PLL3 output frequency range : VCO */
5490 __HAL_RCC_PLL3_VCORANGE(pPLL3Init->PLL3VCOSEL);
5491
5492 /* Configure the PLL3 Clock output(s) */
5493 __HAL_RCC_PLL3_CLKOUT_ENABLE(pPLL3Init->PLL3ClockOut);
5494
5495 /* Enable the PLL3 again by setting PLL3ON to 1*/
5496 __HAL_RCC_PLL3_ENABLE();
5497
5498 /* Get Start Tick*/
5499 tickstart = HAL_GetTick();
5500
5501 /* Wait till PLL3 is ready */
5502 while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) == 0U)
5503 {
5504 if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE)
5505 {
5506 status = HAL_TIMEOUT;
5507 break;
5508 }
5509 }
5510 }
5511 }
5512
5513 return status;
5514 }
5515
5516
5517 /**
5518 * @brief Disable PLL3.
5519 * @retval HAL status.
5520 */
HAL_RCCEx_DisablePLL3(void)5521 HAL_StatusTypeDef HAL_RCCEx_DisablePLL3(void)
5522 {
5523 uint32_t tickstart;
5524 HAL_StatusTypeDef status = HAL_OK;
5525
5526 /* Disable the PLL3 */
5527 __HAL_RCC_PLL3_DISABLE();
5528
5529 /* Get Start Tick*/
5530 tickstart = HAL_GetTick();
5531
5532 /* Wait till PLL3 is ready */
5533 while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != 0U)
5534 {
5535 if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE)
5536 {
5537 status = HAL_TIMEOUT;
5538 break;
5539 }
5540 }
5541
5542 /* To save power, disable the PLL3 Source and Clock outputs */
5543 CLEAR_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3PEN | RCC_PLL3CFGR_PLL3QEN | RCC_PLL3CFGR_PLL3REN | RCC_PLL3CFGR_PLL3SRC |
5544 RCC_PLL3CFGR_PLL3FRACEN);
5545
5546 return status;
5547 }
5548 #endif /* RCC_CR_PLL3ON */
5549
5550 /**
5551 * @brief Configure the oscillator clock source for wakeup from Stop and HSE CSS backup clock.
5552 * @param WakeUpClk Wakeup clock
5553 * This parameter can be one of the following values:
5554 * @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI oscillator selection
5555 * @arg @ref RCC_STOP_WAKEUPCLOCK_CSI CSI oscillator selection
5556 * @note This function shall not be called after the Clock Security System on HSE has been
5557 * enabled.
5558 * @retval None
5559 */
HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk)5560 void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk)
5561 {
5562 assert_param(IS_RCC_STOP_WAKEUPCLOCK(WakeUpClk));
5563
5564 __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(WakeUpClk);
5565 }
5566
5567 /**
5568 * @brief Configure the oscillator Kernel clock source for wakeup from Stop
5569 * @param WakeUpClk: Kernel Wakeup clock
5570 * This parameter can be one of the following values:
5571 * @arg RCC_STOP_KERWAKEUPCLOCK_HSI: HSI oscillator selection
5572 * @arg RCC_STOP_KERWAKEUPCLOCK_CSI: CSI oscillator selection
5573 * @retval None
5574 */
HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk)5575 void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk)
5576 {
5577 assert_param(IS_RCC_STOP_KERWAKEUPCLOCK(WakeUpClk));
5578
5579 __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(WakeUpClk);
5580 }
5581
5582 /**
5583 * @brief Enable the LSE Clock Security System.
5584 * @note Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled
5585 * with HAL_RCC_OscConfig() and the LSE oscillator clock is to be selected as RTC
5586 * clock with HAL_RCCEx_PeriphCLKConfig().
5587 * @retval None
5588 */
HAL_RCCEx_EnableLSECSS(void)5589 void HAL_RCCEx_EnableLSECSS(void)
5590 {
5591 SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
5592 }
5593
5594 /**
5595 * @brief Disable the LSE Clock Security System.
5596 * @note LSE Clock Security System can only be disabled after a LSE failure detection.
5597 * @retval None
5598 */
HAL_RCCEx_DisableLSECSS(void)5599 void HAL_RCCEx_DisableLSECSS(void)
5600 {
5601 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
5602 }
5603
5604 /**
5605 * @brief Handle the RCC LSE Clock Security System interrupt request.
5606 * @retval None
5607 */
HAL_RCCEx_LSECSS_IRQHandler(void)5608 void HAL_RCCEx_LSECSS_IRQHandler(void)
5609 {
5610 if (READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) != 0U)
5611 {
5612 /* RCC LSE Clock Security System interrupt user callback */
5613 HAL_RCCEx_LSECSS_Callback();
5614 }
5615 }
5616
5617 /**
5618 * @brief RCCEx LSE Clock Security System interrupt callback.
5619 * @retval none
5620 */
HAL_RCCEx_LSECSS_Callback(void)5621 __weak void HAL_RCCEx_LSECSS_Callback(void)
5622 {
5623 /* NOTE : This function should not be modified, when the callback is needed,
5624 the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file
5625 */
5626 }
5627
5628 /**
5629 * @brief Select the Low Speed Microcontroller Clock source to output on LSCO pin (PB2).
5630 * @param LSCOSource specifies the Low Speed clock source to output.
5631 * This parameter can be one of the following values:
5632 * @arg @ref RCC_LSCOSOURCE_LSI LSI clock selected as LSCO source
5633 * @arg @ref RCC_LSCOSOURCE_LSE LSE clock selected as LSCO source
5634 * @retval None
5635 */
HAL_RCCEx_EnableLSCO(uint32_t LSCOSource)5636 void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource)
5637 {
5638 GPIO_InitTypeDef GPIO_InitStruct;
5639 FlagStatus backupchanged = RESET;
5640
5641 /* Check the parameters */
5642 assert_param(IS_RCC_LSCOSOURCE(LSCOSource));
5643
5644 /* LSCO Pin Clock Enable */
5645 __LSCO_CLK_ENABLE();
5646
5647 /* Configure the LSCO pin in analog mode */
5648 GPIO_InitStruct.Pin = LSCO_PIN;
5649 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
5650 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
5651 GPIO_InitStruct.Pull = GPIO_NOPULL;
5652 HAL_GPIO_Init(LSCO_GPIO_PORT, &GPIO_InitStruct);
5653
5654 /* Update LSCOSEL clock source in Backup Domain control register */
5655 if (HAL_IS_BIT_CLR(PWR->DBPCR, PWR_DBPCR_DBP))
5656 {
5657 HAL_PWR_EnableBkUpAccess();
5658 backupchanged = SET;
5659 }
5660
5661 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL | RCC_BDCR_LSCOEN, LSCOSource | RCC_BDCR_LSCOEN);
5662
5663 if (backupchanged == SET)
5664 {
5665 HAL_PWR_DisableBkUpAccess();
5666 }
5667 }
5668
5669 /**
5670 * @brief Disable the Low Speed Microcontroller Clock Output.
5671 * @retval None
5672 */
HAL_RCCEx_DisableLSCO(void)5673 void HAL_RCCEx_DisableLSCO(void)
5674 {
5675 FlagStatus backupchanged = RESET;
5676
5677 /* Update LSCOEN bit in Backup Domain control register */
5678 if (HAL_IS_BIT_CLR(PWR->DBPCR, PWR_DBPCR_DBP))
5679 {
5680 /* Enable access to the backup domain */
5681 HAL_PWR_EnableBkUpAccess();
5682 backupchanged = SET;
5683 }
5684
5685 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
5686
5687 /* Restore previous configuration */
5688 if (backupchanged == SET)
5689 {
5690 /* Disable access to the backup domain */
5691 HAL_PWR_DisableBkUpAccess();
5692 }
5693 }
5694
5695 /**
5696 * @}
5697 */
5698
5699 #if defined(CRS)
5700
5701 /** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions
5702 * @brief Extended Clock Recovery System Control functions
5703 *
5704 @verbatim
5705 ===============================================================================
5706 ##### Extended Clock Recovery System Control functions #####
5707 ===============================================================================
5708 [..]
5709 For devices with Clock Recovery System feature (CRS), RCC Extension HAL driver can be used as follows:
5710
5711 (#) In System clock config, HSI48 needs to be enabled
5712
5713 (#) Enable CRS clock in IP MSP init which will use CRS functions
5714
5715 (#) Call CRS functions as follows:
5716 (##) Prepare synchronization configuration necessary for HSI48 calibration
5717 (+++) Default values can be set for frequency Error Measurement (reload and error limit)
5718 and also HSI48 oscillator smooth trimming.
5719 (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate
5720 directly reload value with target and synchronization frequencies values
5721 (##) Call function HAL_RCCEx_CRSConfig which
5722 (+++) Resets CRS registers to their default values.
5723 (+++) Configures CRS registers with synchronization configuration
5724 (+++) Enables automatic calibration and frequency error counter feature
5725 Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the
5726 periodic USB SOF will not be generated by the host. No SYNC signal will therefore be
5727 provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock
5728 precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs
5729 should be used as SYNC signal.
5730
5731 (##) A polling function is provided to wait for complete synchronization
5732 (+++) Call function HAL_RCCEx_CRSWaitSynchronization()
5733 (+++) According to CRS status, user can decide to adjust again the calibration or continue
5734 application if synchronization is OK
5735
5736 (#) User can retrieve information related to synchronization in calling function
5737 HAL_RCCEx_CRSGetSynchronizationInfo()
5738
5739 (#) Regarding synchronization status and synchronization information, user can try a new calibration
5740 in changing synchronization configuration and call again HAL_RCCEx_CRSConfig.
5741 Note: When the SYNC event is detected during the downcounting phase (before reaching the zero value),
5742 it means that the actual frequency is lower than the target (and so, that the TRIM value should be
5743 incremented), while when it is detected during the upcounting phase it means that the actual frequency
5744 is higher (and that the TRIM value should be decremented).
5745
5746 (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go
5747 through CRS Handler (CRS_IRQn/CRS_IRQHandler)
5748 (++) Call function HAL_RCCEx_CRSConfig()
5749 (++) Enable CRS_IRQn (thanks to NVIC functions)
5750 (++) Enable CRS interrupt (__HAL_RCC_CRS_ENABLE_IT)
5751 (++) Implement CRS status management in the following user callbacks called from
5752 HAL_RCCEx_CRS_IRQHandler():
5753 (+++) HAL_RCCEx_CRS_SyncOkCallback()
5754 (+++) HAL_RCCEx_CRS_SyncWarnCallback()
5755 (+++) HAL_RCCEx_CRS_ExpectedSyncCallback()
5756 (+++) HAL_RCCEx_CRS_ErrorCallback()
5757
5758 (#) To force a SYNC EVENT, user can use the function HAL_RCCEx_CRSSoftwareSynchronizationGenerate().
5759 This function can be called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler)
5760
5761 @endverbatim
5762 * @{
5763 */
5764
5765 /**
5766 * @brief Start automatic synchronization for polling mode
5767 * @param pInit Pointer on RCC_CRSInitTypeDef structure
5768 * @retval None
5769 */
HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef * pInit)5770 void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit)
5771 {
5772 uint32_t value;
5773
5774 /* Check the parameters */
5775 assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler));
5776 assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source));
5777 assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity));
5778 assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue));
5779 assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue));
5780 assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue));
5781
5782 /* CONFIGURATION */
5783
5784 /* Before configuration, reset CRS registers to their default values*/
5785 __HAL_RCC_CRS_FORCE_RESET();
5786 __HAL_RCC_CRS_RELEASE_RESET();
5787
5788 /* Set the SYNCDIV[2:0] bits according to Prescaler value */
5789 /* Set the SYNCSRC[1:0] bits according to Source value */
5790 /* Set the SYNCSPOL bit according to Polarity value */
5791 value = (pInit->Prescaler | pInit->Source | pInit->Polarity);
5792 /* Set the RELOAD[15:0] bits according to ReloadValue value */
5793 value |= pInit->ReloadValue;
5794 /* Set the FELIM[7:0] bits according to ErrorLimitValue value */
5795 value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_Pos);
5796 WRITE_REG(CRS->CFGR, value);
5797
5798 /* Adjust HSI48 oscillator smooth trimming */
5799 /* Set the TRIM[5:0] bits according to RCC_CRS_HSI48CalibrationValue value */
5800 MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_Pos));
5801
5802 /* START AUTOMATIC SYNCHRONIZATION*/
5803
5804 /* Enable Automatic trimming & Frequency error counter */
5805 SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN);
5806 }
5807
5808 /**
5809 * @brief Generate the software synchronization event
5810 * @retval None
5811 */
HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void)5812 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void)
5813 {
5814 SET_BIT(CRS->CR, CRS_CR_SWSYNC);
5815 }
5816
5817 /**
5818 * @brief Return synchronization info
5819 * @param pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure
5820 * @retval None
5821 */
HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef * pSynchroInfo)5822 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo)
5823 {
5824 /* Check the parameter */
5825 assert_param(pSynchroInfo != (void *)NULL);
5826
5827 /* Get the reload value */
5828 pSynchroInfo->ReloadValue = (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
5829
5830 /* Get HSI48 oscillator smooth trimming */
5831 pSynchroInfo->HSI48CalibrationValue = (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos);
5832
5833 /* Get Frequency error capture */
5834 pSynchroInfo->FreqErrorCapture = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos);
5835
5836 /* Get Frequency error direction */
5837 pSynchroInfo->FreqErrorDirection = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
5838 }
5839
5840 /**
5841 * @brief Wait for CRS Synchronization status.
5842 * @param Timeout Duration of the timeout
5843 * @note Timeout is based on the maximum time to receive a SYNC event based on synchronization
5844 * frequency.
5845 * @note If Timeout set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned.
5846 * @retval Combination of Synchronization status
5847 * This parameter can be a combination of the following values:
5848 * @arg @ref RCC_CRS_TIMEOUT
5849 * @arg @ref RCC_CRS_SYNCOK
5850 * @arg @ref RCC_CRS_SYNCWARN
5851 * @arg @ref RCC_CRS_SYNCERR
5852 * @arg @ref RCC_CRS_SYNCMISS
5853 * @arg @ref RCC_CRS_TRIMOVF
5854 */
HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)5855 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
5856 {
5857 uint32_t crsstatus = RCC_CRS_NONE;
5858 uint32_t tickstart;
5859
5860 /* Get timeout */
5861 tickstart = HAL_GetTick();
5862
5863 /* Wait for CRS flag or timeout detection */
5864 do
5865 {
5866 if (Timeout != HAL_MAX_DELAY)
5867 {
5868 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
5869 {
5870 crsstatus = RCC_CRS_TIMEOUT;
5871 }
5872 }
5873 /* Check CRS SYNCOK flag */
5874 if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK))
5875 {
5876 /* CRS SYNC event OK */
5877 crsstatus |= RCC_CRS_SYNCOK;
5878
5879 /* Clear CRS SYNC event OK bit */
5880 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK);
5881 }
5882
5883 /* Check CRS SYNCWARN flag */
5884 if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN))
5885 {
5886 /* CRS SYNC warning */
5887 crsstatus |= RCC_CRS_SYNCWARN;
5888
5889 /* Clear CRS SYNCWARN bit */
5890 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN);
5891 }
5892
5893 /* Check CRS TRIM overflow flag */
5894 if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF))
5895 {
5896 /* CRS SYNC Error */
5897 crsstatus |= RCC_CRS_TRIMOVF;
5898
5899 /* Clear CRS Error bit */
5900 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF);
5901 }
5902
5903 /* Check CRS Error flag */
5904 if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR))
5905 {
5906 /* CRS SYNC Error */
5907 crsstatus |= RCC_CRS_SYNCERR;
5908
5909 /* Clear CRS Error bit */
5910 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR);
5911 }
5912
5913 /* Check CRS SYNC Missed flag */
5914 if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS))
5915 {
5916 /* CRS SYNC Missed */
5917 crsstatus |= RCC_CRS_SYNCMISS;
5918
5919 /* Clear CRS SYNC Missed bit */
5920 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS);
5921 }
5922
5923 /* Check CRS Expected SYNC flag */
5924 if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC))
5925 {
5926 /* frequency error counter reached a zero value */
5927 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC);
5928 }
5929 } while (RCC_CRS_NONE == crsstatus);
5930
5931 return crsstatus;
5932 }
5933
5934 /**
5935 * @brief Handle the Clock Recovery System interrupt request.
5936 * @retval None
5937 */
HAL_RCCEx_CRS_IRQHandler(void)5938 void HAL_RCCEx_CRS_IRQHandler(void)
5939 {
5940 uint32_t crserror = RCC_CRS_NONE;
5941 /* Get current IT flags and IT sources values */
5942 uint32_t itflags = READ_REG(CRS->ISR);
5943 uint32_t itsources = READ_REG(CRS->CR);
5944
5945 /* Check CRS SYNCOK flag */
5946 if (((itflags & RCC_CRS_FLAG_SYNCOK) != 0U) && ((itsources & RCC_CRS_IT_SYNCOK) != 0U))
5947 {
5948 /* Clear CRS SYNC event OK flag */
5949 WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
5950
5951 /* user callback */
5952 HAL_RCCEx_CRS_SyncOkCallback();
5953 }
5954 /* Check CRS SYNCWARN flag */
5955 else if (((itflags & RCC_CRS_FLAG_SYNCWARN) != 0U) && ((itsources & RCC_CRS_IT_SYNCWARN) != 0U))
5956 {
5957 /* Clear CRS SYNCWARN flag */
5958 WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
5959
5960 /* user callback */
5961 HAL_RCCEx_CRS_SyncWarnCallback();
5962 }
5963 /* Check CRS Expected SYNC flag */
5964 else if (((itflags & RCC_CRS_FLAG_ESYNC) != 0U) && ((itsources & RCC_CRS_IT_ESYNC) != 0U))
5965 {
5966 /* frequency error counter reached a zero value */
5967 WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
5968
5969 /* user callback */
5970 HAL_RCCEx_CRS_ExpectedSyncCallback();
5971 }
5972 /* Check CRS Error flags */
5973 else
5974 {
5975 if (((itflags & RCC_CRS_FLAG_ERR) != 0U) && ((itsources & RCC_CRS_IT_ERR) != 0U))
5976 {
5977 if ((itflags & RCC_CRS_FLAG_SYNCERR) != 0U)
5978 {
5979 crserror |= RCC_CRS_SYNCERR;
5980 }
5981 if ((itflags & RCC_CRS_FLAG_SYNCMISS) != 0U)
5982 {
5983 crserror |= RCC_CRS_SYNCMISS;
5984 }
5985 if ((itflags & RCC_CRS_FLAG_TRIMOVF) != 0U)
5986 {
5987 crserror |= RCC_CRS_TRIMOVF;
5988 }
5989
5990 /* Clear CRS Error flags */
5991 WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
5992
5993 /* user error callback */
5994 HAL_RCCEx_CRS_ErrorCallback(crserror);
5995 }
5996 }
5997 }
5998
5999 /**
6000 * @brief RCCEx Clock Recovery System SYNCOK interrupt callback.
6001 * @retval none
6002 */
HAL_RCCEx_CRS_SyncOkCallback(void)6003 __weak void HAL_RCCEx_CRS_SyncOkCallback(void)
6004 {
6005 /* NOTE : This function should not be modified, when the callback is needed,
6006 the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the user file
6007 */
6008 }
6009
6010 /**
6011 * @brief RCCEx Clock Recovery System SYNCWARN interrupt callback.
6012 * @retval none
6013 */
HAL_RCCEx_CRS_SyncWarnCallback(void)6014 __weak void HAL_RCCEx_CRS_SyncWarnCallback(void)
6015 {
6016 /* NOTE : This function should not be modified, when the callback is needed,
6017 the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file
6018 */
6019 }
6020
6021 /**
6022 * @brief RCCEx Clock Recovery System Expected SYNC interrupt callback.
6023 * @retval none
6024 */
HAL_RCCEx_CRS_ExpectedSyncCallback(void)6025 __weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void)
6026 {
6027 /* NOTE : This function should not be modified, when the callback is needed,
6028 the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file
6029 */
6030 }
6031
6032 /**
6033 * @brief RCCEx Clock Recovery System Error interrupt callback.
6034 * @param Error Combination of Error status.
6035 * This parameter can be a combination of the following values:
6036 * @arg @ref RCC_CRS_SYNCERR
6037 * @arg @ref RCC_CRS_SYNCMISS
6038 * @arg @ref RCC_CRS_TRIMOVF
6039 * @retval none
6040 */
HAL_RCCEx_CRS_ErrorCallback(uint32_t Error)6041 __weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error)
6042 {
6043 /* Prevent unused argument(s) compilation warning */
6044 UNUSED(Error);
6045
6046 /* NOTE : This function should not be modified, when the callback is needed,
6047 the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the user file
6048 */
6049 }
6050
6051 /**
6052 * @}
6053 */
6054
6055 #endif /* CRS */
6056
6057 /**
6058 * @}
6059 */
6060
6061 /** @addtogroup RCCEx_Private_Functions
6062 * @{
6063 */
6064
6065 /**
6066 * @brief Enable PLL1 source clock and check ready flag
6067 * @param PllSource contains the selected PLL1 source clock (HSE, HSI or CSI)
6068 * @retval HAL status
6069 */
RCCEx_PLLSource_Enable(uint32_t PllSource)6070 static HAL_StatusTypeDef RCCEx_PLLSource_Enable(uint32_t PllSource)
6071 {
6072 uint32_t tickstart;
6073 HAL_StatusTypeDef status = HAL_OK;
6074
6075 switch (PllSource)
6076 {
6077 case RCC_PLLSOURCE_CSI:
6078 /* Check whether CSI in not ready and enable it */
6079 if (READ_BIT(RCC->CR, RCC_CR_CSIRDY) == 0U)
6080 {
6081 /* Enable the Internal Low power oscillator (CSI). */
6082 __HAL_RCC_CSI_ENABLE();
6083
6084 /* Get timeout */
6085 tickstart = HAL_GetTick();
6086
6087 /* Wait till CSI is ready */
6088 while (READ_BIT(RCC->CR, RCC_CR_CSIRDY) == 0U)
6089 {
6090 if ((HAL_GetTick() - tickstart) > CSI_TIMEOUT_VALUE)
6091 {
6092 status = HAL_TIMEOUT;
6093 break;
6094 }
6095 }
6096 }
6097 break;
6098
6099 case RCC_PLLSOURCE_HSI:
6100 /* Check whether HSI in not ready and enable it */
6101 if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
6102 {
6103 /* Enable the Internal High Speed oscillator (HSI). */
6104 __HAL_RCC_HSI_ENABLE();
6105
6106 /* Get timeout */
6107 tickstart = HAL_GetTick();
6108
6109 /* Wait till HSI is ready */
6110 while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
6111 {
6112 if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
6113 {
6114 status = HAL_TIMEOUT;
6115 break;
6116 }
6117 }
6118 }
6119 break;
6120
6121 case RCC_PLLSOURCE_HSE:
6122 /* Check whether HSE in not ready and enable it */
6123 if (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
6124 {
6125 /* Enable the External High Speed oscillator (HSE). */
6126 SET_BIT(RCC->CR, RCC_CR_HSEON);
6127
6128 /* Get Start Tick*/
6129 tickstart = HAL_GetTick();
6130
6131 /* Wait till HSE is ready */
6132 while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
6133 {
6134 if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
6135 {
6136 status = HAL_TIMEOUT;
6137 break;
6138 }
6139 }
6140 }
6141 break;
6142
6143 default:
6144 status = HAL_ERROR;
6145 break;
6146 }
6147
6148 return status;
6149 }
6150
6151 /**
6152 * @brief Configure the PLL2 VCI/VCO ranges, multiplication and division factors and its output clock(s)
6153 * @param pll2 pointer to an RCC_PLL2InitTypeDef structure that
6154 * contains the configuration parameters M, N, FRACN, VCI/VCO ranges as well as PLL2 output clocks dividers
6155 * @note PLL2 is temporary disabled to apply new parameters
6156 * @retval HAL status
6157 */
RCCEx_PLL2_Config(RCC_PLL2InitTypeDef * pll2)6158 static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2)
6159 {
6160
6161 uint32_t tickstart;
6162 assert_param(IS_RCC_PLL2_SOURCE(pll2->PLL2Source));
6163 assert_param(IS_RCC_PLL2_DIVM_VALUE(pll2->PLL2M));
6164 assert_param(IS_RCC_PLL2_MULN_VALUE(pll2->PLL2N));
6165 assert_param(IS_RCC_PLL2_DIVP_VALUE(pll2->PLL2P));
6166 assert_param(IS_RCC_PLL2_DIVQ_VALUE(pll2->PLL2Q));
6167 assert_param(IS_RCC_PLL2_DIVR_VALUE(pll2->PLL2R));
6168 assert_param(IS_RCC_PLL2_CLOCKOUT_VALUE(pll2->PLL2ClockOut));
6169 assert_param(IS_RCC_PLL2_VCIRGE_VALUE(pll2->PLL2RGE));
6170 assert_param(IS_RCC_PLL2_VCORGE_VALUE(pll2->PLL2VCOSEL));
6171 assert_param(IS_RCC_PLL2_FRACN_VALUE(pll2->PLL2FRACN));
6172
6173 /* Disable PLL2. */
6174 __HAL_RCC_PLL2_DISABLE();
6175
6176 /* Get Start Tick*/
6177 tickstart = HAL_GetTick();
6178
6179 /* Wait till PLL2 is disabled */
6180 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U)
6181 {
6182 if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
6183 {
6184 return HAL_TIMEOUT;
6185 }
6186 }
6187
6188 /* Configure PLL2 multiplication and division factors. */
6189 __HAL_RCC_PLL2_CONFIG(pll2->PLL2Source,
6190 pll2->PLL2M,
6191 pll2->PLL2N,
6192 pll2->PLL2P,
6193 pll2->PLL2Q,
6194 pll2->PLL2R);
6195
6196 /* Select PLL2 input reference frequency range: VCI */
6197 __HAL_RCC_PLL2_VCIRANGE(pll2->PLL2RGE);
6198
6199 /* Select PLL2 output frequency range : VCO */
6200 __HAL_RCC_PLL2_VCORANGE(pll2->PLL2VCOSEL);
6201
6202 /* Configure the PLL2 Clock output(s) */
6203 __HAL_RCC_PLL2CLKOUT_ENABLE(pll2->PLL2ClockOut);
6204
6205 /* Disable PLL2FRACN . */
6206 __HAL_RCC_PLL2FRACN_DISABLE();
6207
6208 /* Configures PLL2 clock Fractional Part Of The Multiplication Factor */
6209 __HAL_RCC_PLL2FRACN_CONFIG(pll2->PLL2FRACN);
6210
6211 /* Enable PLL2FRACN . */
6212 __HAL_RCC_PLL2FRACN_ENABLE();
6213
6214 /* Enable PLL2. */
6215 __HAL_RCC_PLL2_ENABLE();
6216
6217 /* Get Start Tick*/
6218 tickstart = HAL_GetTick();
6219
6220 /* Wait till PLL2 is ready */
6221 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U)
6222 {
6223 if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
6224 {
6225 return HAL_TIMEOUT;
6226 }
6227 }
6228 return HAL_OK;
6229
6230 }
6231
6232 #if defined(RCC_CR_PLL3ON)
6233 /**
6234 * @brief Configure the PLL3 VCI/VCO ranges, multiplication and division factors and its output clock(s)
6235 * @param pll3 pointer to an RCC_PLL3InitTypeDef structure that
6236 * contains the configuration parameters M, N, FRACN, VCI/VCO ranges as well as PLL3 output clocks dividers
6237 * @note PLL3 is temporary disabled to apply new parameters
6238 * @retval HAL status.
6239 */
RCCEx_PLL3_Config(RCC_PLL3InitTypeDef * pll3)6240 static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3)
6241 {
6242
6243 uint32_t tickstart;
6244 assert_param(IS_RCC_PLL3_SOURCE(pll3->PLL3Source));
6245 assert_param(IS_RCC_PLL3_DIVM_VALUE(pll3->PLL3M));
6246 assert_param(IS_RCC_PLL3_MULN_VALUE(pll3->PLL3N));
6247 assert_param(IS_RCC_PLL3_DIVP_VALUE(pll3->PLL3P));
6248 assert_param(IS_RCC_PLL3_DIVQ_VALUE(pll3->PLL3Q));
6249 assert_param(IS_RCC_PLL3_DIVR_VALUE(pll3->PLL3R));
6250 assert_param(IS_RCC_PLL3_CLOCKOUT_VALUE(pll3->PLL3ClockOut));
6251 assert_param(IS_RCC_PLL3_VCIRGE_VALUE(pll3->PLL3RGE));
6252 assert_param(IS_RCC_PLL3_VCORGE_VALUE(pll3->PLL3VCOSEL));
6253 assert_param(IS_RCC_PLL3_FRACN_VALUE(pll3->PLL3FRACN));
6254
6255 /* Disable PLL3. */
6256 __HAL_RCC_PLL3_DISABLE();
6257
6258 /* Get Start Tick*/
6259 tickstart = HAL_GetTick();
6260
6261 /* Wait till PLL3 is disabled */
6262 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U)
6263 {
6264 if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE)
6265 {
6266 return HAL_TIMEOUT;
6267 }
6268 }
6269
6270 /* Configure PLL3 multiplication and division factors. */
6271 __HAL_RCC_PLL3_CONFIG(pll3->PLL3Source,
6272 pll3->PLL3M,
6273 pll3->PLL3N,
6274 pll3->PLL3P,
6275 pll3->PLL3Q,
6276 pll3->PLL3R);
6277
6278 /* Select PLL3 input reference frequency range: VCI */
6279 __HAL_RCC_PLL3_VCIRANGE(pll3->PLL3RGE) ;
6280
6281 /* Select PLL3 output frequency range : VCO */
6282 __HAL_RCC_PLL3_VCORANGE(pll3->PLL3VCOSEL);
6283
6284 /* Configure the PLL3 Clock output(s) */
6285 __HAL_RCC_PLL3CLKOUT_ENABLE(pll3->PLL3ClockOut);
6286
6287 /* Disable PLL3FRACN . */
6288 __HAL_RCC_PLL3FRACN_DISABLE();
6289
6290 /* Configures PLL3 clock Fractional Part Of The Multiplication Factor */
6291 __HAL_RCC_PLL3FRACN_CONFIG(pll3->PLL3FRACN);
6292
6293 /* Enable PLL3FRACN . */
6294 __HAL_RCC_PLL3FRACN_ENABLE();
6295
6296 /* Enable PLL3. */
6297 __HAL_RCC_PLL3_ENABLE();
6298
6299 /* Get Start Tick*/
6300 tickstart = HAL_GetTick();
6301
6302 /* Wait till PLL3 is ready */
6303 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U)
6304 {
6305 if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE)
6306 {
6307 return HAL_TIMEOUT;
6308 }
6309 }
6310 return HAL_OK;
6311 }
6312 #endif /* RCC_CR_PLL3ON */
6313
6314 /**
6315 * @}
6316 */
6317
6318 #endif /* HAL_RCC_MODULE_ENABLED */
6319 /**
6320 * @}
6321 */
6322
6323 /**
6324 * @}
6325 */
6326
6327
6328
