1 /**
2 ******************************************************************************
3 * @file stm32h5xx_hal_pwr.c
4 * @author MCD Application Team
5 * @brief PWR HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Power Controller (PWR) peripheral:
8 * + Initialization/De-Initialization Functions.
9 * + Peripheral Control Functions.
10 * + PWR Attributes Functions.
11 *
12 ******************************************************************************
13 * @attention
14 *
15 * Copyright (c) 2022 STMicroelectronics.
16 * All rights reserved.
17 *
18 * This software is licensed under terms that can be found in the LICENSE file
19 * in the root directory of this software component.
20 * If no LICENSE file comes with this software, it is provided AS-IS.
21 *
22 ******************************************************************************
23 */
24
25 /* Includes ------------------------------------------------------------------*/
26 #include "stm32h5xx_hal.h"
27
28 /** @addtogroup STM32H5xx_HAL_Driver
29 * @{
30 */
31
32 /** @defgroup PWR PWR
33 * @brief PWR HAL module driver
34 * @{
35 */
36
37 #if defined (HAL_PWR_MODULE_ENABLED)
38
39 /* Private typedef -----------------------------------------------------------*/
40 /* Private define ------------------------------------------------------------*/
41
42 /** @defgroup PWR_Private_Defines PWR Private Defines
43 * @{
44 */
45
46 /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
47 * @{
48 */
49 #define PVD_RISING_EDGE (0x01U) /*!< Mask for rising edge set as PVD
50 trigger */
51 #define PVD_FALLING_EDGE (0x02U) /*!< Mask for falling edge set as PVD
52 trigger */
53 #define PVD_MODE_IT (0x04U) /*!< Mask for interruption yielded by PVD
54 threshold crossing */
55 #define PVD_MODE_EVT (0x08U) /*!< Mask for event yielded by PVD threshold
56 crossing */
57 /**
58 * @}
59 */
60
61 /**
62 * @}
63 */
64
65 /* Private macro -------------------------------------------------------------*/
66 /* Private variables ---------------------------------------------------------*/
67 /* Private function prototypes -----------------------------------------------*/
68 /* Exported functions --------------------------------------------------------*/
69
70 /** @defgroup PWR_Exported_Functions PWR Exported Functions
71 * @{
72 */
73
74 /** @defgroup PWR_Exported_Functions_Group1 Initialization and De-Initialization Functions
75 * @brief Initialization and de-Initialization functions
76 *
77 @verbatim
78 ===============================================================================
79 ##### Initialization and De-Initialization Functions #####
80 ===============================================================================
81 [..]
82 @endverbatim
83 * @{
84 */
85
86 /**
87 * @brief Deinitialize the HAL PWR peripheral registers to their default reset
88 * values.
89 * @note This functionality is not available in this product.
90 * The prototype is kept just to maintain compatibility with other
91 * products.
92 * @retval None.
93 */
HAL_PWR_DeInit(void)94 void HAL_PWR_DeInit(void)
95 {
96 }
97
98 /**
99 * @brief Enable access to the backup domain (RCC Backup domain control
100 * register RCC_BDCR, RTC registers, TAMP registers, backup registers
101 * and backup SRAM).
102 * @note After a system reset, the backup domain is protected against
103 * possible unwanted write accesses.
104 * @retval None.
105 */
HAL_PWR_EnableBkUpAccess(void)106 void HAL_PWR_EnableBkUpAccess(void)
107 {
108 SET_BIT(PWR->DBPCR, PWR_DBPCR_DBP);
109 }
110
111 /**
112 * @brief Disable access to the backup domain (RCC Backup domain control
113 * register RCC_BDCR, RTC registers, TAMP registers, backup registers
114 * and backup SRAM).
115 * @retval None
116 */
HAL_PWR_DisableBkUpAccess(void)117 void HAL_PWR_DisableBkUpAccess(void)
118 {
119 CLEAR_BIT(PWR->DBPCR, PWR_DBPCR_DBP);
120 }
121 /**
122 * @}
123 */
124
125
126 /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control Functions
127 * @brief Low power modes configuration functions
128 *
129 @verbatim
130 ===============================================================================
131 ##### Peripheral Control functions #####
132 ===============================================================================
133 [..]
134 @endverbatim
135 * @{
136 */
137
138 /**
139 * @brief Configure the voltage threshold detected by the Programmed Voltage
140 * Detector (PVD).
141 * @param sConfigPVD : Pointer to a PWR_PVDTypeDef structure that contains the
142 * PVD configuration information (PVDLevel and EventMode).
143 * @retval None.
144 */
HAL_PWR_ConfigPVD(PWR_PVDTypeDef * sConfigPVD)145 HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
146 {
147 /* Check the parameters */
148 assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
149 assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
150
151 /* Set PLS[3:1] bits according to PVDLevel value */
152 MODIFY_REG(PWR->VMCR, PWR_VMCR_PLS, sConfigPVD->PVDLevel);
153
154 /* Disable PVD Event/Interrupt */
155 __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
156 __HAL_PWR_PVD_EXTI_DISABLE_IT();
157 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
158 __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
159
160 /* Configure the PVD in interrupt mode */
161 if ((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
162 {
163 __HAL_PWR_PVD_EXTI_ENABLE_IT();
164 }
165
166 /* Configure the PVD in event mode */
167 if ((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
168 {
169 __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
170 }
171
172 /* Configure the PVD in rising edge */
173 if ((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
174 {
175 __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
176 }
177
178 /* Configure the PVD in falling edge */
179 if ((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
180 {
181 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
182 }
183
184 return HAL_OK;
185 }
186
187 /**
188 * @brief Enable the programmable voltage detector (PVD).
189 * @retval None.
190 */
HAL_PWR_EnablePVD(void)191 void HAL_PWR_EnablePVD(void)
192 {
193 SET_BIT(PWR->VMCR, PWR_VMCR_PVDEN);
194 }
195
196
197 /**
198 * @brief Disable the programmable voltage detector (PVD).
199 * @retval None.
200 */
HAL_PWR_DisablePVD(void)201 void HAL_PWR_DisablePVD(void)
202 {
203 CLEAR_BIT(PWR->VMCR, PWR_VMCR_PVDEN);
204 }
205
206 /**
207 * @brief Enable the WakeUp PINx functionality.
208 * @param WakeUpPinPolarity : Specifies which Wake-Up pin to enable.
209 * This parameter can be one of the following legacy values, which
210 * sets the default (rising edge):
211 * @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3,PWR_WAKEUP_PIN4,
212 * PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6, PWR_WAKEUP_PIN7.PWR_WAKEUP_PIN8.
213 * or one of the following values where the user can explicitly states
214 * the enabled pin and the chosen polarity:
215 * @arg PWR_WAKEUP_PIN1_HIGH, PWR_WAKEUP_PIN1_LOW,
216 * PWR_WAKEUP_PIN2_HIGH, PWR_WAKEUP_PIN2_LOW,
217 * PWR_WAKEUP_PIN3_HIGH, PWR_WAKEUP_PIN3_LOW,
218 * PWR_WAKEUP_PIN4_HIGH, PWR_WAKEUP_PIN4_LOW,
219 * PWR_WAKEUP_PIN5_HIGH, PWR_WAKEUP_PIN5_LOW,
220 * PWR_WAKEUP_PIN6_HIGH, PWR_WAKEUP_PIN6_LOW,
221 * PWR_WAKEUP_PIN7_HIGH, PWR_WAKEUP_PIN7_LOW,
222 * PWR_WAKEUP_PIN8_HIGH, PWR_WAKEUP_PIN8_LOW.
223 * @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
224 * @note The PWR_WAKEUP_PIN6_HIGH, PWR_WAKEUP_PIN6_LOW, PWR_WAKEUP_PIN7_HIGH, PWR_WAKEUP_PIN7_LOW,
225 * PWR_WAKEUP_PIN8_HIGH and PWR_WAKEUP_PIN8_LOW are not available for STM32H503xx devices.
226 * @retval None.
227 */
HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)228 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)
229 {
230 /* Check the parameters */
231 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity));
232
233 /*
234 Enable and Specify the Wake-Up pin polarity and the pull configuration
235 for the event detection (rising or falling edge).
236 */
237 MODIFY_REG(PWR->WUCR, PWR_EWUP_MASK, WakeUpPinPolarity);
238 }
239
240 /**
241 * @brief Disable the WakeUp PINx functionality.
242 * @param WakeUpPinx : Specifies the Power Wake-Up pin to disable.
243 * This parameter can be one of the following values:
244 * @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3,PWR_WAKEUP_PIN4,
245 * PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6, PWR_WAKEUP_PIN7.PWR_WAKEUP_PIN8.
246 * or one of the following values where the user can explicitly states
247 * the enabled pin and the chosen polarity:
248 * @arg PWR_WAKEUP_PIN1_HIGH, PWR_WAKEUP_PIN1_LOW,
249 * PWR_WAKEUP_PIN2_HIGH, PWR_WAKEUP_PIN2_LOW,
250 * PWR_WAKEUP_PIN3_HIGH, PWR_WAKEUP_PIN3_LOW,
251 * PWR_WAKEUP_PIN4_HIGH, PWR_WAKEUP_PIN4_LOW,
252 * PWR_WAKEUP_PIN5_HIGH, PWR_WAKEUP_PIN5_LOW,
253 * PWR_WAKEUP_PIN6_HIGH, PWR_WAKEUP_PIN6_LOW,
254 * PWR_WAKEUP_PIN7_HIGH, PWR_WAKEUP_PIN7_LOW,
255 * PWR_WAKEUP_PIN8_HIGH, PWR_WAKEUP_PIN8_LOW.
256 * @note The PWR_WAKEUP_PIN6_HIGH, PWR_WAKEUP_PIN6_LOW, PWR_WAKEUP_PIN7_HIGH, PWR_WAKEUP_PIN7_LOW,
257 * PWR_WAKEUP_PIN8_HIGH and PWR_WAKEUP_PIN8_LOW are not available for STM32H503xx devices.
258 * @retval None.
259 */
HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)260 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
261 {
262 /* Check the parameters */
263 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
264
265 /* Disable the wake up pin selected */
266 CLEAR_BIT(PWR->WUCR, (PWR_WUCR_WUPEN & WakeUpPinx));
267 }
268
269 /**
270 * @brief Enter the CPU in SLEEP mode.
271 * @note In SLEEP mode, all I/O pins keep the same state as in Run mode.
272 * @note CPU clock is off and all peripherals including Cortex-M33 core such
273 * as NVIC and SysTick can run and wake up the CPU when an interrupt
274 * or an event occurs.
275 * @param Regulator : Specifies the regulator state in Sleep mode.
276 * This parameter can be one of the following values :
277 * @arg @ref PWR_MAINREGULATOR_ON
278 * @arg @ref PWR_LOWPOWERREGULATOR_ON
279 * @note This parameter is not available in this product.
280 * The parameter is kept just to maintain compatibility with other
281 * products.
282 * @param SLEEPEntry : Specifies if SLEEP mode is entered with WFI or WFE
283 * instruction.
284 * This parameter can be one of the following values :
285 * @arg @ref PWR_SLEEPENTRY_WFI enter SLEEP mode with Wait
286 * For Interrupt request.
287 * @arg @ref PWR_SLEEPENTRY_WFE enter SLEEP mode with Wait
288 * For Event request.
289 * @note When WFI entry is used, ticks interrupt must be disabled to avoid
290 * unexpected CPU wake up.
291 * @retval None.
292 */
HAL_PWR_EnterSLEEPMode(uint32_t Regulator,uint8_t SLEEPEntry)293 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
294 {
295 UNUSED(Regulator);
296
297 /* Check the parameter */
298 assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
299
300 /* Clear SLEEPDEEP bit of Cortex System Control Register */
301 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
302
303 /* Select SLEEP mode entry */
304 if (SLEEPEntry == PWR_SLEEPENTRY_WFI)
305 {
306 /* Wait For Interrupt Request */
307 __WFI();
308 }
309 else
310 {
311 /* Wait For Event Request */
312 __SEV();
313 __WFE();
314 __WFE();
315 }
316 }
317
318 /**
319 * @brief Enter the whole system to STOP mode.
320 * @note In STOP mode, the regulator remains in main regulator mode,
321 * allowing a very fast wakeup time but with much higher consumption
322 * comparing to other STOP modes.
323 * @note STOP offers the largest number of active peripherals and wakeup
324 * sources, a smaller wakeup time but a higher consumption.
325 * STOP mode achieves the lowest power consumption while retaining
326 * the content of SRAM and registers. All clocks in the VCORE domain
327 * are stopped. The PLL, the HSI, the CSI and the HSE crystal oscillators
328 * are disabled. The LSE or LSI is still running.
329 * @note The system clock when exiting from Stop mode can be either HSI
330 * or CSI, depending on software configuration.
331 * @param Regulator : Specifies the regulator state in Sleep mode.
332 * This parameter can be one of the following values :
333 * @arg @ref PWR_MAINREGULATOR_ON
334 * @arg @ref PWR_LOWPOWERREGULATOR_ON
335 * @note This parameter is not available in this product.
336 * The parameter is kept just to maintain compatibility with other
337 * products.
338 * @param STOPEntry : Specifies if STOP mode is entered with WFI or WFE
339 * instruction.
340 * This parameter can be one of the following values :
341 * @arg @ref PWR_STOPENTRY_WFI enter STOP mode with Wait
342 * For Interrupt request.
343 * @arg @ref PWR_STOPENTRY_WFE enter STOP mode with Wait
344 * For Event request.
345 * @retval None.
346 */
HAL_PWR_EnterSTOPMode(uint32_t Regulator,uint8_t STOPEntry)347 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
348 {
349 UNUSED(Regulator);
350
351 /* Check the parameter */
352 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
353
354 /* Select STOP mode */
355 CLEAR_BIT(PWR->PMCR, PWR_PMCR_LPMS);
356
357 /* Set SLEEPDEEP bit of Cortex System Control Register */
358 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
359
360 /* Select STOP mode entry */
361 if (STOPEntry == PWR_STOPENTRY_WFI)
362 {
363 /* Wait For Interrupt Request */
364 __WFI();
365 }
366 else
367 {
368 /* Wait For Event Request */
369 __SEV();
370 __WFE();
371 __WFE();
372 }
373
374 /* Reset SLEEPDEEP bit of Cortex System Control Register */
375 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
376 }
377
378 /**
379 * @brief Enter the whole system to STANDBY mode.
380 * @note The STANDBY mode is used to achieve the lowest power consumption
381 * with BOR. The internal regulator is switched off so that the VCORE
382 * domain is powered off. The PLL, the HSI, the CSI and the HSE crystal
383 * oscillators are also switched off.
384 * @note After entering STANDBY mode, SRAMs and register contents are lost
385 * except for registers and backup SRAM in the Backup domain and
386 * STANDBY circuitry.
387 * @retval None.
388 */
HAL_PWR_EnterSTANDBYMode(void)389 void HAL_PWR_EnterSTANDBYMode(void)
390 {
391 /* Select STANDBY mode */
392 SET_BIT(PWR->PMCR, PWR_PMCR_LPMS);
393
394 /* Set SLEEPDEEP bit of Cortex System Control Register */
395 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
396
397 /* This option is used to ensure that store operations are completed */
398 #if defined ( __CC_ARM)
399 __force_stores();
400 #endif /* __CC_ARM */
401
402 /* Wait For Interrupt Request */
403 __WFI();
404 }
405
406 /**
407 * @brief Indicate SLEEP-ON-EXIT feature when returning from handler mode to
408 * thread mode.
409 * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the
410 * processor re-enters SLEEP mode when an interruption handling is over.
411 * Setting this bit is useful when the processor is expected to run
412 * only on interruptions handling.
413 * @retval None.
414 */
HAL_PWR_EnableSleepOnExit(void)415 void HAL_PWR_EnableSleepOnExit(void)
416 {
417 /* Set SLEEPONEXIT bit of Cortex-M33 System Control Register */
418 SET_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk);
419 }
420
421 /**
422 * @brief Disable SLEEP-ON-EXIT feature when returning from handler mode to
423 * thread mode.
424 * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the
425 * processor re-enters SLEEP mode when an interruption handling is over.
426 * @retval None.
427 */
HAL_PWR_DisableSleepOnExit(void)428 void HAL_PWR_DisableSleepOnExit(void)
429 {
430 /* Clear SLEEPONEXIT bit of Cortex-M33 System Control Register */
431 CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk);
432 }
433
434 /**
435 * @brief Enable CORTEX SEV-ON-PEND feature.
436 * @note Sets SEVONPEND bit of SCR register. When this bit is set, any
437 * pending event / interrupt even if it's disabled or has insufficient
438 * priority to cause exception entry wakes up the Cortex-M33.
439 * @retval None.
440 */
HAL_PWR_EnableSEVOnPend(void)441 void HAL_PWR_EnableSEVOnPend(void)
442 {
443 /* Set SEVONPEND bit of Cortex-M33 System Control Register */
444 SET_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk);
445 }
446
447 /**
448 * @brief Disable CORTEX SEVONPEND feature.
449 * @note Resets SEVONPEND bit of SCR register. When this bit is reset, only
450 * enabled pending causes exception entry wakes up the Cortex-M33.
451 * @retval None.
452 */
HAL_PWR_DisableSEVOnPend(void)453 void HAL_PWR_DisableSEVOnPend(void)
454 {
455 /* Clear SEVONPEND bit of Cortex-M33 System Control Register */
456 CLEAR_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk);
457 }
458
459 /**
460 * @brief This function handles the PWR PVD interrupt request.
461 * @note This API should be called under the PVD_AVD_IRQHandler().
462 * @retval None.
463 */
HAL_PWR_PVD_IRQHandler(void)464 void HAL_PWR_PVD_IRQHandler(void)
465 {
466 uint32_t rising_flag;
467 uint32_t falling_flag;
468
469 /* Get pending flags */
470 rising_flag = READ_REG(EXTI->RPR1);
471 falling_flag = READ_REG(EXTI->FPR1);
472
473 /* Check PWR EXTI flags for PVD */
474 if (((rising_flag | falling_flag) & PWR_EXTI_LINE_PVD) != 0U)
475 {
476 /* PWR PVD interrupt user callback */
477 HAL_PWR_PVDCallback();
478
479 /* Clear PVD EXTI pending bit */
480 WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_PVD);
481 WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_PVD);
482 }
483 }
484
485 /**
486 * @brief PWR PVD interrupt callback.
487 * @retval None.
488 */
HAL_PWR_PVDCallback(void)489 __weak void HAL_PWR_PVDCallback(void)
490 {
491 /* NOTE : This function should not be modified, when the callback is needed,
492 the HAL_PWR_PVDCallback can be implemented in the user file
493 */
494 }
495 /**
496 * @}
497 */
498
499 /** @defgroup PWR_Exported_Functions_Group3 Attributes Management Functions
500 * @brief Attributes management functions
501 *
502 @verbatim
503 ===============================================================================
504 ##### PWR Attributes Functions #####
505 ===============================================================================
506 [..]
507 @endverbatim
508 * @{
509 */
510
511 /**
512 * @brief Configure the PWR item attributes.
513 * @note Available attributes are security and privilege protection.
514 * @note Security attribute can only be set only by secure access.
515 * @note Privilege attribute for secure items can be managed only by a secure
516 * priliged access.
517 * @note Privilege attribute for nsecure items can be managed by a secure
518 * priliged access or by a nsecure priliged access.
519 * @param Item : Specifies the item(s) to set attributes on.
520 * This parameter can be a combination of @ref PWR_ITEMS.
521 * @param Attributes : Specifies the available attribute(s).
522 * This parameter can be one of @ref PWR_ATTRIBUTES.
523 * @retval None.
524 */
HAL_PWR_ConfigAttributes(uint32_t Item,uint32_t Attributes)525 void HAL_PWR_ConfigAttributes(uint32_t Item, uint32_t Attributes)
526 {
527 /* Check the parameters */
528 assert_param(IS_PWR_ATTRIBUTES(Attributes));
529
530 #if defined (PWR_SECCFGR_WUP1SEC)
531 assert_param(IS_PWR_ITEMS_ATTRIBUTES(Item));
532
533 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
534 /* Secure item management (TZEN = 1) */
535 if ((Attributes & PWR_ITEM_ATTR_SEC_PRIV_MASK) == PWR_ITEM_ATTR_SEC_PRIV_MASK)
536 {
537 /* Privilege item management */
538 if ((Attributes & PWR_SEC_PRIV) == PWR_SEC_PRIV)
539 {
540 SET_BIT(PWR->SECCFGR, Item);
541 SET_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_SPRIV);
542 }
543 else
544 {
545 SET_BIT(PWR->SECCFGR, Item);
546 CLEAR_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_SPRIV);
547 }
548 }
549 /* NSecure item management */
550 else
551 {
552 /* Privilege item management */
553 if ((Attributes & PWR_NSEC_PRIV) == PWR_NSEC_PRIV)
554 {
555 CLEAR_BIT(PWR->SECCFGR, Item);
556 SET_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV);
557 }
558 else
559 {
560 CLEAR_BIT(PWR->SECCFGR, Item);
561 CLEAR_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV);
562 }
563 }
564 #else
565 /* NSecure item management (TZEN = 0) */
566 if ((Attributes & PWR_ITEM_ATTR_NSEC_PRIV_MASK) == PWR_ITEM_ATTR_NSEC_PRIV_MASK)
567 {
568 /* Privilege item management */
569 if ((Attributes & PWR_NSEC_PRIV) == PWR_NSEC_PRIV)
570 {
571 SET_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV);
572 }
573 else
574 {
575 CLEAR_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV);
576 }
577 }
578 #endif /* __ARM_FEATURE_CMSE */
579
580 #else /* PWR_SECCFGR_WUP1SEC */
581 /* Prevent unused argument(s) compilation warning */
582 UNUSED(Item);
583
584 /* NSecure item management (TZEN = 0) */
585 if ((Attributes & PWR_ITEM_ATTR_NSEC_PRIV_MASK) == PWR_ITEM_ATTR_NSEC_PRIV_MASK)
586 {
587 /* Privilege item management */
588 if ((Attributes & PWR_PRIV) == PWR_PRIV)
589 {
590 SET_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_PRIV);
591 }
592 else
593 {
594 CLEAR_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_PRIV);
595 }
596 }
597 #endif /* PWR_SECCFGR_WUP1SEC */
598
599 }
600
601
602 /**
603 * @brief Get attribute(s) of a PWR item.
604 * @param Item : Specifies the item(s) to set attributes on.
605 * This parameter can be one of @ref PWR_ITEMS.
606 * @param pAttributes : Pointer to return attribute(s).
607 * Returned value could be on of @ref PWR_ATTRIBUTES.
608 * @retval HAL Status.
609 */
HAL_PWR_GetConfigAttributes(uint32_t Item,uint32_t * pAttributes)610 HAL_StatusTypeDef HAL_PWR_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes)
611 {
612 uint32_t attributes;
613
614 /* Check attribute pointer */
615 if (pAttributes == NULL)
616 {
617 return HAL_ERROR;
618 }
619 #if defined (PWR_SECCFGR_WUP1SEC)
620 /* Check the parameter */
621 assert_param(IS_PWR_ITEMS_ATTRIBUTES(Item));
622 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
623 /* Check item security */
624 if ((PWR->SECCFGR & Item) == Item)
625 {
626 /* Get Secure privileges attribute */
627 attributes = ((PWR->PRIVCFGR & PWR_PRIVCFGR_SPRIV) == 0U) ? PWR_SEC_NPRIV : PWR_SEC_PRIV;
628 }
629 else
630 {
631 /* Get Non-Secure privileges attribute */
632 attributes = ((PWR->PRIVCFGR & PWR_PRIVCFGR_NSPRIV) == 0U) ? PWR_NSEC_NPRIV : PWR_NSEC_PRIV;
633 }
634 #else
635 /* Get Non-Secure privileges attribute */
636 attributes = ((PWR->PRIVCFGR & PWR_PRIVCFGR_NSPRIV) == 0U) ? PWR_NSEC_NPRIV : PWR_NSEC_PRIV;
637 #endif /* __ARM_FEATURE_CMSE */
638
639 #else /* PWR_SECCFGR_WUP1SEC*/
640 UNUSED(Item);
641 /* Get Non-Secure privileges attribute */
642 attributes = ((PWR->PRIVCFGR & PWR_PRIVCFGR_PRIV) == 0U) ? PWR_NPRIV : PWR_PRIV;
643 #endif /* PWR_SECCFGR_WUP1SEC */
644 /* return value */
645 *pAttributes = attributes;
646
647 return HAL_OK;
648 }
649 /**
650 * @}
651 */
652
653 /**
654 * @}
655 */
656
657 #endif /* defined (HAL_PWR_MODULE_ENABLED) */
658 /**
659 * @}
660 */
661
662 /**
663 * @}
664 */
665
