1 /**
2 ******************************************************************************
3 * @file stm32h5xx_hal_gtzc.c
4 * @author MCD Application Team
5 * @brief GTZC HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of GTZC peripheral:
8 * + TZSC Initialization and Configuration functions
9 * + TZSC-MPCWM Initialization and Configuration functions
10 * + MPCBB Initialization and Configuration functions
11 * + TZSC, TZSC-MPCWM and MPCBB Lock functions
12 * + TZIC Initialization and Configuration functions
13 *
14 ******************************************************************************
15 * @attention
16 *
17 * Copyright (c) 2022 STMicroelectronics.
18 * All rights reserved.
19 *
20 * This software is licensed under terms that can be found in the LICENSE file
21 * in the root directory of this software component.
22 * If no LICENSE file comes with this software, it is provided AS-IS.
23 *
24 ******************************************************************************
25 @verbatim
26 ==============================================================================
27 ##### GTZC main features #####
28 ==============================================================================
29 [..]
30 (+) Global TrustZone Controller (GTZC) composed of three sub-blocks:
31 (++) TZSC: TrustZone security controller
32 This sub-block defines the secure/privileged state of master and slave
33 peripherals. It also controls the secure/privileged state of subregions
34 for the watermark memory peripheral controller (MPCWM).
35 (++) MPCBB: Block-Based memory protection controller
36 This sub-block defines the secure/privileged state of all blocks
37 (512-byte pages) of the associated SRAM.
38 (++) TZIC: TrustZone illegal access controller
39 This sub-block gathers all illegal access events in the system and
40 generates a secure interrupt towards NVIC.
41
42 (+) These sub-blocks are used to configure TrustZone system security in
43 a product having bus agents with programmable-security and privileged
44 attributes (securable) such as:
45 (++) on-chip RAM with programmable secure and/or privilege blocks (pages)
46 (++) AHB and APB peripherals with programmable security and/or privilege access
47 (++) AHB master granted as secure and/or privilege
48 (++) off-chip memories with secure and/or privilege areas
49
50 [..]
51 (+) TZIC accessible only with secure privileged transactions.
52 (+) Secure and non-secure access supported for privileged and unprivileged
53 part of TZSC and MPCBB
54 (+) Set of registers to define product security settings:
55 (++) Secure and privilege blocks for internal memories
56 (++) Secure and privilege regions for external memories
57 (++) Secure and privileged access mode for securable peripherals
58
59 ==============================================================================
60 ##### How to use this driver #####
61 ==============================================================================
62 [..]
63 The GTZC HAL driver can be used as follows:
64
65 (#) Configure or get back securable peripherals attributes using
66 HAL_GTZC_TZSC_ConfigPeriphAttributes() / HAL_GTZC_TZSC_GetConfigPeriphAttributes()
67
68 (#) Configure or get back MPCWM memories attributes using
69 HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes() / HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes()
70
71 (#) Lock TZSC sub-block or get lock status using HAL_GTZC_TZSC_Lock() /
72 HAL_GTZC_TZSC_GetLock()
73
74 (#) Configure or get back MPCBB memories complete configuration using
75 HAL_GTZC_MPCBB_ConfigMem() / HAL_GTZC_MPCBB_GetConfigMem()
76
77 (#) Configure or get back MPCBB memories attributes using
78 HAL_GTZC_MPCBB_ConfigMemAttributes() / HAL_GTZC_MPCBB_GetConfigMemAttributes()
79
80 (#) Lock MPCBB configuration or get lock status using HAL_GTZC_MPCBB_Lock() /
81 HAL_GTZC_MPCBB_GetLock()
82
83 (#) Lock MPCBB super-blocks or get lock status using HAL_GTZC_MPCBB_LockConfig() /
84 HAL_GTZC_MPCBB_GetLockConfig()
85
86 (#) Illegal access detection can be configured through TZIC sub-block using
87 following functions: HAL_GTZC_TZIC_DisableIT() / HAL_GTZC_TZIC_EnableIT()
88
89 (#) Illegal access flags can be retrieved through HAL_GTZC_TZIC_GetFlag() and
90 HAL_GTZC_TZIC_ClearFlag() functions
91
92 (#) Illegal access interrupt service routines are served by HAL_GTZC_IRQHandler()
93 and user can add his own code using HAL_GTZC_TZIC_Callback()
94
95 @endverbatim
96 ******************************************************************************
97 */
98
99 /* Includes ------------------------------------------------------------------*/
100 #include "stm32h5xx_hal.h"
101
102 /** @addtogroup STM32H5xx_HAL_Driver
103 * @{
104 */
105
106 /** @defgroup GTZC GTZC
107 * @brief GTZC HAL module driver
108 * @{
109 */
110
111 #ifdef HAL_GTZC_MODULE_ENABLED
112
113 /* Private typedef -----------------------------------------------------------*/
114 /* Private constants ---------------------------------------------------------*/
115
116 /** @defgroup GTZC_Private_Constants GTZC Private Constants
117 * @{
118 */
119
120 /* Definitions for GTZC_TZSC_MPCWM */
121 #if defined (OCTOSPI1)
122 #define GTZC_TZSC_MPCWM1_MEM_SIZE 0x10000000U /* 256MB max size */
123 #endif /* defined (OCTOSPI1) */
124 #if defined (FMC_BANK1)
125 #define GTZC_TZSC_MPCWM2_MEM_SIZE 0x10000000U /* 256MB max size */
126 #endif /* defined (FMC_BANK1) */
127 #if defined (FMC_BANK3) || defined(FMC_SDRAM_BANK_1)
128 #define GTZC_TZSC_MPCWM3_MEM_SIZE 0x10000000U /* 256MB max size */
129 #endif /* defined (FMC_BANK3) || defined(FMC_SDRAM_BANK_1) */
130 #if defined(BKPSRAM_BASE)
131 #define GTZC_TZSC_MPCWM4_MEM_SIZE 0x00000800U /* 2KB max size */
132 #endif /* defined (BKPSRAM_BASE) */
133 #if defined(FMC_SDRAM_BANK_2)
134 #define GTZC_TZSC_MPCWM4_SDRAM_MEM_SIZE 0x10000000U /* 256MB max size */
135 #endif /* defined(FMC_SDRAM_BANK_2) */
136
137 /* Definitions for GTZC TZSC & TZIC ALL register values */
138 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
139 #define TZSC1_SECCFGR1_ALL (0xFFFFFFFFUL)
140 #define TZSC1_SECCFGR2_ALL (0xFF0FFF07UL)
141 #define TZSC1_SECCFGR3_ALL (0x05FFFF03UL)
142 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
143
144 #if defined (GTZC_TZIC1)
145 #define TZSC1_PRIVCFGR1_ALL (0xFFFFFFFFUL)
146 #define TZSC1_PRIVCFGR2_ALL (0xFF0FFF07UL)
147 #define TZSC1_PRIVCFGR3_ALL (0x05FFFF03UL)
148 #else
149 #define TZSC1_PRIVCFGR1_ALL (0xC21E7E33UL)
150 #define TZSC1_PRIVCFGR2_ALL (0x12080B19UL)
151 #define TZSC1_PRIVCFGR3_ALL (0x04065106UL)
152 #endif /* defined (GTZC_TZIC1) */
153
154 #if defined (GTZC_TZIC1)
155 #define TZIC1_IER1_ALL (0xFFFFFFFFUL)
156 #define TZIC1_IER2_ALL (0xFF0FFF07UL)
157 #define TZIC1_IER3_ALL (0x05FFFF03UL)
158 #define TZIC1_IER4_ALL (0x3F3F0FFFUL)
159
160 #define TZIC1_FCR1_ALL (0xFFFFFFFFUL)
161 #define TZIC1_FCR2_ALL (0xFF0FFF07UL)
162 #define TZIC1_FCR3_ALL (0x05FFFF03UL)
163 #define TZIC1_FCR4_ALL (0x3F3F0FFFUL)
164 #endif /* defined (GTZC_TZIC1) */
165 /**
166 * @}
167 */
168
169 /* Private macros ------------------------------------------------------------*/
170
171 /** @defgroup GTZC_Private_Macros GTZC Private Macros
172 * @{
173 */
174
175 #define IS_ADDRESS_IN(mem, address)\
176 ( ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_NS(mem) ) \
177 && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_NS(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) ) \
178 || ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_S(mem) ) \
179 && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_S(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) ) )
180
181 #define IS_ADDRESS_IN_S(mem, address)\
182 ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_S(mem) ) \
183 && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_S(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) )
184
185 #define IS_ADDRESS_IN_NS(mem, address)\
186 ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_NS(mem) ) \
187 && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_NS(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) )
188
189 #define GTZC_BASE_ADDRESS(mem)\
190 ( mem ## _BASE )
191
192 /**
193 * @}
194 */
195
196 /* Private variables ---------------------------------------------------------*/
197 /* Private function prototypes -----------------------------------------------*/
198 /* Exported functions --------------------------------------------------------*/
199
200 /** @defgroup GTZC_Exported_Functions GTZC Exported Functions
201 * @{
202 */
203
204 /** @defgroup GTZC_Exported_Functions_Group1 TZSC Configuration functions
205 * @brief TZSC Configuration functions
206 *
207 @verbatim
208 ==============================================================================
209 ##### TZSC Configuration functions #####
210 ==============================================================================
211 [..]
212 This section provides functions allowing to configure TZSC
213 TZSC: TrustZone Security Controller
214 @endverbatim
215 * @{
216 */
217
218 /**
219 * @brief Configure TZSC on a single peripheral or on all peripherals.
220 * @note Secure and non-secure attributes can only be set from the secure
221 * state when the system implements the security (TZEN=1).
222 * @note Privilege and non-privilege attributes can only be set from the
223 * privilege state when TZEN=0 or TZEN=1
224 * @note Security and privilege attributes can be set independently.
225 * @note Default state is non-secure and unprivileged access allowed.
226 * @param PeriphId Peripheral identifier
227 * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId.
228 * Use GTZC_PERIPH_ALL to select all peripherals.
229 * @param PeriphAttributes Peripheral attributes, see @ref GTZC_TZSC_PeriphAttributes.
230 * @retval HAL status.
231 */
HAL_GTZC_TZSC_ConfigPeriphAttributes(uint32_t PeriphId,uint32_t PeriphAttributes)232 HAL_StatusTypeDef HAL_GTZC_TZSC_ConfigPeriphAttributes(uint32_t PeriphId,
233 uint32_t PeriphAttributes)
234 {
235 uint32_t register_address;
236
237 /* check entry parameters */
238 #if defined (GTZC_TZIC1)
239 if ((PeriphAttributes > (GTZC_TZSC_PERIPH_SEC | GTZC_TZSC_PERIPH_PRIV))
240 || (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZSC_PERIPH_NUMBER)
241 || (((PeriphId & GTZC_PERIPH_ALL) != 0U)
242 && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U)))
243 #else
244 if ((PeriphAttributes > GTZC_TZSC_PERIPH_PRIV)
245 || (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZSC_PERIPH_NUMBER)
246 || (((PeriphId & GTZC_PERIPH_ALL) != 0U)
247 && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U)))
248 #endif /* defined (GTZC_TZIC1) */
249 {
250 return HAL_ERROR;
251 }
252
253 if ((PeriphId & GTZC_PERIPH_ALL) != 0U)
254 {
255 /* special case where same attributes are applied to all peripherals */
256
257 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
258 /* secure configuration */
259 if ((PeriphAttributes & GTZC_TZSC_PERIPH_SEC) == GTZC_TZSC_PERIPH_SEC)
260 {
261 SET_BIT(GTZC_TZSC1->SECCFGR1, TZSC1_SECCFGR1_ALL);
262 SET_BIT(GTZC_TZSC1->SECCFGR2, TZSC1_SECCFGR2_ALL);
263 SET_BIT(GTZC_TZSC1->SECCFGR3, TZSC1_SECCFGR3_ALL);
264 }
265 else if ((PeriphAttributes & GTZC_TZSC_PERIPH_NSEC) == GTZC_TZSC_PERIPH_NSEC)
266 {
267 CLEAR_BIT(GTZC_TZSC1->SECCFGR1, TZSC1_SECCFGR1_ALL);
268 CLEAR_BIT(GTZC_TZSC1->SECCFGR2, TZSC1_SECCFGR2_ALL);
269 CLEAR_BIT(GTZC_TZSC1->SECCFGR3, TZSC1_SECCFGR3_ALL);
270 }
271 else
272 {
273 /* do nothing */
274 }
275 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
276
277 /* privilege configuration */
278 if ((PeriphAttributes & GTZC_TZSC_PERIPH_PRIV) == GTZC_TZSC_PERIPH_PRIV)
279 {
280 SET_BIT(GTZC_TZSC1->PRIVCFGR1, TZSC1_PRIVCFGR1_ALL);
281 SET_BIT(GTZC_TZSC1->PRIVCFGR2, TZSC1_PRIVCFGR2_ALL);
282 SET_BIT(GTZC_TZSC1->PRIVCFGR3, TZSC1_PRIVCFGR3_ALL);
283 }
284 else if ((PeriphAttributes & GTZC_TZSC_PERIPH_NPRIV) == GTZC_TZSC_PERIPH_NPRIV)
285 {
286 CLEAR_BIT(GTZC_TZSC1->PRIVCFGR1, TZSC1_PRIVCFGR1_ALL);
287 CLEAR_BIT(GTZC_TZSC1->PRIVCFGR2, TZSC1_PRIVCFGR2_ALL);
288 CLEAR_BIT(GTZC_TZSC1->PRIVCFGR3, TZSC1_PRIVCFGR3_ALL);
289 }
290 else
291 {
292 /* do nothing */
293 }
294 }
295 else
296 {
297 /* common case where only one peripheral is configured */
298
299 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
300 /* secure configuration */
301 register_address = (uint32_t)&(GTZC_TZSC1->SECCFGR1)
302 + (4U * GTZC_GET_REG_INDEX(PeriphId));
303 if ((PeriphAttributes & GTZC_TZSC_PERIPH_SEC) == GTZC_TZSC_PERIPH_SEC)
304 {
305 SET_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
306 }
307 else if ((PeriphAttributes & GTZC_TZSC_PERIPH_NSEC) == GTZC_TZSC_PERIPH_NSEC)
308 {
309 CLEAR_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
310 }
311 else
312 {
313 /* do nothing */
314 }
315 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
316
317 /* privilege configuration */
318 register_address = (uint32_t)&(GTZC_TZSC1->PRIVCFGR1)
319 + (4U * GTZC_GET_REG_INDEX(PeriphId));
320 if ((PeriphAttributes & GTZC_TZSC_PERIPH_PRIV) == GTZC_TZSC_PERIPH_PRIV)
321 {
322 SET_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
323 }
324 else if ((PeriphAttributes & GTZC_TZSC_PERIPH_NPRIV) == GTZC_TZSC_PERIPH_NPRIV)
325 {
326 CLEAR_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
327 }
328 else
329 {
330 /* do nothing */
331 }
332 }
333 return HAL_OK;
334 }
335
336 /**
337 * @brief Get TZSC configuration on a single peripheral or on all peripherals.
338 * @param PeriphId Peripheral identifier.
339 * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId.
340 * Use GTZC_PERIPH_ALL to select all peripherals.
341 * @param PeriphAttributes Peripheral attribute pointer.
342 * This parameter can be a value of @ref GTZC_TZSC_PeriphAttributes.
343 * If PeriphId target a single peripheral, pointer on a single element.
344 * If all peripherals selected (GTZC_PERIPH_ALL), pointer to an array of
345 * GTZC_TZSC_PERIPH_NUMBER elements is to be provided.
346 * @retval HAL status.
347 */
HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId,uint32_t * PeriphAttributes)348 HAL_StatusTypeDef HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId,
349 uint32_t *PeriphAttributes)
350 {
351 uint32_t i;
352 uint32_t reg_value;
353 uint32_t register_address;
354
355 /* check entry parameters */
356 if ((PeriphAttributes == NULL)
357 || (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZSC_PERIPH_NUMBER)
358 || (((PeriphId & GTZC_PERIPH_ALL) != 0U)
359 && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U)))
360 {
361 return HAL_ERROR;
362 }
363
364 if ((PeriphId & GTZC_PERIPH_ALL) != 0U)
365 {
366 #if defined (GTZC_TZIC1)
367 /* get secure configuration: read each register and deploy each bit value
368 * of corresponding index in the destination array
369 */
370 reg_value = READ_REG(GTZC_TZSC1->SECCFGR1);
371 for (i = 0U; i < 32U; i++)
372 {
373 if(((reg_value & (1UL << i)) >> i) != 0U)
374 {
375 PeriphAttributes[i] = GTZC_TZSC_PERIPH_SEC;
376 }
377 else
378 {
379 PeriphAttributes[i] = GTZC_TZSC_PERIPH_NSEC;
380 }
381 }
382
383 reg_value = READ_REG(GTZC_TZSC1->SECCFGR2);
384 for (i = 32U; i < 64U; i++)
385 {
386 if(((reg_value & (1UL << (i - 32U))) >> (i - 32U)) != 0U)
387 {
388 PeriphAttributes[i] = GTZC_TZSC_PERIPH_SEC;
389 }
390 else
391 {
392 PeriphAttributes[i] = GTZC_TZSC_PERIPH_NSEC;
393 }
394 }
395
396 reg_value = READ_REG(GTZC_TZSC1->SECCFGR3);
397 for (i = 64U; i < GTZC_TZSC_PERIPH_NUMBER; i++)
398 {
399 if (((reg_value & (1UL << (i - 64U))) >> (i - 64U)) != 0U)
400 {
401 PeriphAttributes[i] = GTZC_TZSC_PERIPH_SEC;
402 }
403 else
404 {
405 PeriphAttributes[i] = GTZC_TZSC_PERIPH_NSEC;
406 }
407 }
408 #endif /* defined (GTZC_TZIC1) */
409
410 /* get privilege configuration: read each register and deploy each bit value
411 * of corresponding index in the destination array
412 */
413 reg_value = READ_REG(GTZC_TZSC1->PRIVCFGR1);
414 for (i = 0U; i < 32U; i++)
415 {
416 if(((reg_value & (1UL << i)) >> i) != 0U)
417 {
418 PeriphAttributes[i] |= GTZC_TZSC_PERIPH_PRIV;
419 }
420 else
421 {
422 PeriphAttributes[i] |= GTZC_TZSC_PERIPH_NPRIV;
423 }
424 }
425
426 reg_value = READ_REG(GTZC_TZSC1->PRIVCFGR2);
427 for (i = 32U; i < 64U; i++)
428 {
429 if(((reg_value & (1UL << (i - 32U))) >> (i - 32U)) != 0U)
430 {
431 PeriphAttributes[i] |= GTZC_TZSC_PERIPH_PRIV;
432 }
433 else
434 {
435 PeriphAttributes[i] |= GTZC_TZSC_PERIPH_NPRIV;
436 }
437 }
438
439 reg_value = READ_REG(GTZC_TZSC1->PRIVCFGR3);
440 for (i = 64U; i < GTZC_TZSC_PERIPH_NUMBER; i++)
441 {
442 if (((reg_value & (1UL << (i - 64U))) >> (i - 64U)) != 0U)
443 {
444 PeriphAttributes[i] |= GTZC_TZSC_PERIPH_PRIV;
445 }
446 else
447 {
448 PeriphAttributes[i] |= GTZC_TZSC_PERIPH_NPRIV;
449 }
450 }
451 }
452 else
453 {
454 /* common case where only one peripheral is configured */
455 #if defined (GTZC_TZIC1)
456 /* secure configuration */
457 register_address = (uint32_t)&(GTZC_TZSC1->SECCFGR1)
458 + (4U * GTZC_GET_REG_INDEX(PeriphId));
459
460 if (((READ_BIT(*(__IO uint32_t *)register_address,
461 1UL << GTZC_GET_PERIPH_POS(PeriphId))) >> GTZC_GET_PERIPH_POS(PeriphId))
462 != 0U)
463 {
464 *PeriphAttributes = GTZC_TZSC_PERIPH_SEC;
465 }
466 else
467 {
468 *PeriphAttributes = GTZC_TZSC_PERIPH_NSEC;
469 }
470 #endif /* defined (GTZC_TZIC1) */
471
472 /* privilege configuration */
473 register_address = (uint32_t)&(GTZC_TZSC1->PRIVCFGR1)
474 + (4U * GTZC_GET_REG_INDEX(PeriphId));
475
476 if (((READ_BIT(*(__IO uint32_t *)register_address,
477 1UL << GTZC_GET_PERIPH_POS(PeriphId))) >> GTZC_GET_PERIPH_POS(PeriphId))
478 != 0U)
479 {
480 *PeriphAttributes |= GTZC_TZSC_PERIPH_PRIV;
481 }
482 else
483 {
484 *PeriphAttributes |= GTZC_TZSC_PERIPH_NPRIV;
485 }
486 }
487 return HAL_OK;
488 }
489
490 /**
491 * @}
492 */
493
494
495 /** @defgroup GTZC_Exported_Functions_Group2 MPCWM Configuration functions
496 * @brief MPCWM Configuration functions
497 *
498 @verbatim
499 ==============================================================================
500 ##### MPCWM Configuration functions #####
501 ==============================================================================
502 [..]
503 This section provides functions allowing to configure MPCWM
504 MPCWM is Memory Protection Controller WaterMark
505 @endverbatim
506 * @{
507 */
508
509 /**
510 * @brief Configure a TZSC-MPCWM area.
511 * @param MemBaseAddress WM identifier.
512 * @param pMPCWM_Desc TZSC-MPCWM descriptor pointer.
513 * The structure description is available in @ref GTZC_Exported_Types.
514 * @retval HAL status.
515 */
HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes(uint32_t MemBaseAddress,const MPCWM_ConfigTypeDef * pMPCWM_Desc)516 HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes(uint32_t MemBaseAddress,
517 const MPCWM_ConfigTypeDef *pMPCWM_Desc)
518 {
519 uint32_t register_address;
520 uint32_t reg_value;
521 uint32_t size;
522 /* granularity value depends on selected memory */
523 uint32_t granularity = (MemBaseAddress == BKPSRAM_BASE) ? \
524 GTZC_TZSC_MPCWM_GRANULARITY_2 : GTZC_TZSC_MPCWM_GRANULARITY_1;
525
526 /* check entry parameters */
527 if ((pMPCWM_Desc->AreaId > GTZC_TZSC_MPCWM_ID2)
528 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
529 || (((MemBaseAddress == FMC_BANK3) || (MemBaseAddress == BKPSRAM_BASE) || \
530 (MemBaseAddress == FMC_SDRAM_BANK_1) || (MemBaseAddress == FMC_SDRAM_BANK_2))
531 #else
532 || ((MemBaseAddress == BKPSRAM_BASE)
533 #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
534 && (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID2))
535 || ((pMPCWM_Desc->Offset % granularity) != 0U)
536 || ((pMPCWM_Desc->Length % granularity) != 0U))
537 {
538 return HAL_ERROR;
539 }
540
541 /* check descriptor content vs. memory capacity */
542 switch (MemBaseAddress)
543 {
544 #if defined(OCTOSPI1)
545 case OCTOSPI1_BASE:
546 size = GTZC_TZSC_MPCWM1_MEM_SIZE;
547 if (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1)
548 {
549 register_address = (uint32_t) &(GTZC_TZSC1->MPCWM1AR);
550 }
551 else
552 {
553 /* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID2
554 * (Parameter already checked)
555 */
556 register_address = (uint32_t) &(GTZC_TZSC1->MPCWM1BR);
557 }
558 break;
559 #endif /* (OCTOSPI1) */
560 #if defined(FMC_BANK1)
561 case FMC_BANK1:
562 size = GTZC_TZSC_MPCWM2_MEM_SIZE;
563 if (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1)
564 {
565 register_address = (uint32_t) &(GTZC_TZSC1->MPCWM2AR);
566 }
567 else
568 {
569 /* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID2
570 * (Parameter already checked)
571 */
572 register_address = (uint32_t) &(GTZC_TZSC1->MPCWM2BR);
573 }
574 break;
575 #endif /* defined(FMC_BANK1) */
576 #if defined(FMC_BANK3)
577 case FMC_BANK3:
578 /* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1
579 * (Parameter already checked)
580 */
581 size = GTZC_TZSC_MPCWM3_MEM_SIZE;
582 register_address = (uint32_t) &(GTZC_TZSC1->MPCWM3AR);
583 break;
584 #endif /* defined(FMC_BANK3) */
585 #if defined(FMC_SDRAM_BANK_1)
586 case FMC_SDRAM_BANK_1:
587 /* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1
588 * (Parameter already checked)
589 */
590 size = GTZC_TZSC_MPCWM3_MEM_SIZE;
591 register_address = (uint32_t) &(GTZC_TZSC1->MPCWM3AR);
592 break;
593 #endif /* (FMC_SDRAM_BANK_1) */
594 #if defined(BKPSRAM_BASE)
595 case BKPSRAM_BASE:
596 /* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1
597 * (Parameter already checked)
598 */
599 size = GTZC_TZSC_MPCWM4_MEM_SIZE;
600 register_address = (uint32_t) &(GTZC_TZSC1->MPCWM4AR);
601 break;
602 #endif /* (BKPSRAM_BASE) */
603 #if defined(FMC_SDRAM_BANK_2)
604 case FMC_SDRAM_BANK_2:
605 /* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1
606 * (Parameter already checked)
607 */
608 size = GTZC_TZSC_MPCWM4_SDRAM_MEM_SIZE ;
609 register_address = (uint32_t) &(GTZC_TZSC1->MPCWM4AR);
610 break;
611 #endif /* (FMC_SDRAM_BANK_2) */
612 default:
613 return HAL_ERROR;
614 break;
615 }
616
617 if ((pMPCWM_Desc->Offset > size)
618 || ((pMPCWM_Desc->Offset
619 + pMPCWM_Desc->Length)
620 > size))
621 {
622 return HAL_ERROR;
623 }
624
625 /* Write watermark start and length value */
626 reg_value = ((pMPCWM_Desc->Offset / granularity)
627 << GTZC_TZSC_MPCWMR_SUBZ_START_Pos) & GTZC_TZSC_MPCWMR_SUBZ_START_Msk;
628 reg_value |= ((pMPCWM_Desc->Length / granularity)
629 << GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Pos) & GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk;
630 MODIFY_REG(*(__IO uint32_t *)register_address, GTZC_TZSC_MPCWMR_SUBZ_START_Msk | \
631 GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk, reg_value);
632
633 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
634 /* Write watermark configuration value */
635 reg_value = (pMPCWM_Desc->Attribute << GTZC_TZSC_MPCWM_CFGR_SEC_Pos) | \
636 pMPCWM_Desc->Lock | \
637 pMPCWM_Desc->AreaStatus;
638 MODIFY_REG(*(__IO uint32_t *)(register_address - 4U), (GTZC_TZSC_MPCWM_CFGR_PRIV | GTZC_TZSC_MPCWM_CFGR_SEC | \
639 GTZC_TZSC_MPCWM_CFGR_SRLOCK | GTZC_TZSC_MPCWM_CFGR_SREN), \
640 reg_value);
641 #else
642 /* Write watermark configuration value */
643 reg_value = (pMPCWM_Desc->Attribute << (GTZC_TZSC_MPCWM_CFGR_PRIV_Pos - 1)) | \
644 pMPCWM_Desc->Lock | \
645 pMPCWM_Desc->AreaStatus;
646 MODIFY_REG(*(__IO uint32_t *)(register_address - 4U), (GTZC_TZSC_MPCWM_CFGR_PRIV | GTZC_TZSC_MPCWM_CFGR_SRLOCK | \
647 GTZC_TZSC_MPCWM_CFGR_SREN), reg_value);
648 #endif /* (__ARM_FEATURE_CMSE) */
649
650 return HAL_OK;
651 }
652
653 /**
654 * @brief Get a TZSC-MPCWM area configuration.
655 * @param MemBaseAddress WM identifier.
656 * @param pMPCWM_Desc pointer to a TZSC-MPCWM descriptor.
657 * The structure description is available in @ref GTZC_Exported_Types.
658 * @retval HAL status.
659 */
HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes(uint32_t MemBaseAddress,MPCWM_ConfigTypeDef * pMPCWM_Desc)660 HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes(uint32_t MemBaseAddress, MPCWM_ConfigTypeDef *pMPCWM_Desc)
661 {
662 uint32_t register_address;
663 uint32_t reg_value;
664 uint32_t granularity = (MemBaseAddress == BKPSRAM_BASE) ? \
665 GTZC_TZSC_MPCWM_GRANULARITY_2 : GTZC_TZSC_MPCWM_GRANULARITY_1;
666
667 /* firstly take care of the first area, present on all MPCWM sub-blocks */
668 switch (MemBaseAddress)
669 {
670 #if defined(OCTOSPI1)
671 case OCTOSPI1_BASE:
672 register_address = (uint32_t) &(GTZC_TZSC1->MPCWM1AR);
673 break;
674 #endif /* (OCTOSPI1) */
675 #if defined(FMC_BANK1)
676 case FMC_BANK1:
677 register_address = (uint32_t) &(GTZC_TZSC1->MPCWM2AR);
678 break;
679 #endif /* defined(FMC_BANK1) */
680 #if defined(FMC_BANK3)
681 case FMC_BANK3:
682 register_address = (uint32_t) &(GTZC_TZSC1->MPCWM3AR);
683 break;
684 #endif /* defined(FMC_BANK3) */
685 #if defined(FMC_SDRAM_BANK_1)
686 case FMC_SDRAM_BANK_1:
687 register_address = (uint32_t) &(GTZC_TZSC1->MPCWM3AR);
688 break;
689 #endif /* (FMC_SDRAM_BANK_1) */
690 #if defined(BKPSRAM_BASE)
691 case BKPSRAM_BASE:
692 register_address = (uint32_t) &(GTZC_TZSC1->MPCWM4AR);
693 break;
694 #endif /* (BKPSRAM_BASE) */
695 #if defined(FMC_SDRAM_BANK_2)
696 case FMC_SDRAM_BANK_2:
697 register_address = (uint32_t) &(GTZC_TZSC1->MPCWM4AR);
698 break;
699 #endif /* (FMC_SDRAM_BANK_2) */
700 default:
701 return HAL_ERROR;
702 break;
703 }
704
705 /* read register and update the descriptor for first area*/
706 reg_value = READ_REG(*(__IO uint32_t *)register_address);
707 pMPCWM_Desc[0].AreaId = GTZC_TZSC_MPCWM_ID1;
708 pMPCWM_Desc[0].Offset = ((reg_value & GTZC_TZSC_MPCWMR_SUBZ_START_Msk)
709 >> GTZC_TZSC_MPCWMR_SUBZ_START_Pos) * granularity;
710 pMPCWM_Desc[0].Length = ((reg_value & GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk)
711 >> GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Pos) * granularity;
712
713 /* read configuration register and update the descriptor for first area*/
714 reg_value = READ_REG(*(__IO uint32_t *)(register_address - 4U));
715 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
716 pMPCWM_Desc[0].Attribute = (reg_value & (GTZC_TZSC_MPCWM_CFGR_PRIV | \
717 GTZC_TZSC_MPCWM_CFGR_SEC)) >> GTZC_TZSC_MPCWM_CFGR_SEC_Pos;
718 #else
719 pMPCWM_Desc[0].Attribute = (reg_value & GTZC_TZSC_MPCWM_CFGR_PRIV) >> (GTZC_TZSC_MPCWM_CFGR_PRIV_Pos - 1);
720 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
721 pMPCWM_Desc[0].Lock = reg_value & GTZC_TZSC_MPCWM_CFGR_SRLOCK;
722 pMPCWM_Desc[0].AreaStatus = reg_value & GTZC_TZSC_MPCWM_CFGR_SREN;
723
724 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
725 if ((MemBaseAddress == OCTOSPI1_BASE) || (MemBaseAddress == FMC_BANK1))
726 {
727 if (MemBaseAddress == OCTOSPI1_BASE)
728 {
729 register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM1BR);
730 }
731 else
732 {
733 register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM2BR);
734 }
735
736 /* read register and update the descriptor for second area*/
737 reg_value = READ_REG(*(__IO uint32_t *)register_address);
738 pMPCWM_Desc[1].AreaId = GTZC_TZSC_MPCWM_ID2;
739 pMPCWM_Desc[1].Offset = ((reg_value & GTZC_TZSC_MPCWMR_SUBZ_START_Msk)
740 >> GTZC_TZSC_MPCWMR_SUBZ_START_Pos) * granularity;
741 pMPCWM_Desc[1].Length = ((reg_value & GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk)
742 >> GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Pos) * granularity;
743
744 /* read configuration register and update the descriptor for second area*/
745 reg_value = READ_REG(*(__IO uint32_t *)(register_address - 4U));
746 pMPCWM_Desc[1].Attribute = reg_value & (GTZC_TZSC_MPCWM_CFGR_PRIV | \
747 GTZC_TZSC_MPCWM_CFGR_SEC);
748 pMPCWM_Desc[1].Lock = reg_value & GTZC_TZSC_MPCWM_CFGR_SRLOCK;
749 pMPCWM_Desc[1].AreaStatus = reg_value & GTZC_TZSC_MPCWM_CFGR_SREN;
750 }
751 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
752
753 return HAL_OK;
754 }
755
756 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
757 /**
758 * @}
759 */
760
761 /** @defgroup GTZC_Exported_Functions_Group3 TZSC Lock functions
762 * @brief TZSC Lock functions
763 *
764 @verbatim
765 ==============================================================================
766 ##### TZSC Lock functions #####
767 ==============================================================================
768 [..]
769 This section provides functions allowing to manage the TZSC (TrustZone
770 Security Controller) lock. It includes lock enable, and current value read.
771 @endverbatim
772 * @{
773 */
774
775 /**
776 * @brief Lock TZSC configuration.
777 * @note This function locks the configuration of TZSC_SECCFGRx and TZSC_PRIVCFGRx
778 * registers until next reset
779 * @param TZSC_Instance TZSC sub-block instance.
780 */
HAL_GTZC_TZSC_Lock(GTZC_TZSC_TypeDef * TZSC_Instance)781 void HAL_GTZC_TZSC_Lock(GTZC_TZSC_TypeDef *TZSC_Instance)
782 {
783 SET_BIT(TZSC_Instance->CR, GTZC_TZSC_CR_LCK_Msk);
784 }
785
786 /**
787 * @brief Get TZSC configuration lock state.
788 * @param TZSC_Instance TZSC sub-block instance.
789 * @retval Lock State (GTZC_TZSC_LOCK_OFF or GTZC_TZSC_LOCK_ON)
790 */
HAL_GTZC_TZSC_GetLock(const GTZC_TZSC_TypeDef * TZSC_Instance)791 uint32_t HAL_GTZC_TZSC_GetLock(const GTZC_TZSC_TypeDef *TZSC_Instance)
792 {
793 return READ_BIT(TZSC_Instance->CR, GTZC_TZSC_CR_LCK_Msk);
794 }
795
796 /**
797 * @}
798 */
799 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
800
801 /** @defgroup GTZC_Exported_Functions_Group4 MPCBB Configuration functions
802 * @brief MPCBB Configuration functions
803 *
804 @verbatim
805 ==============================================================================
806 ##### MPCBB Configuration functions #####
807 ==============================================================================
808 [..]
809 This section provides functions allowing to configure MPCBB
810 MPCBB is Memory Protection Controller Block Base
811 @endverbatim
812 * @{
813 */
814
815 /**
816 * @brief Set a complete MPCBB configuration on the SRAM passed as parameter.
817 * @param MemBaseAddress MPCBB identifier.
818 * @param pMPCBB_desc pointer to MPCBB descriptor.
819 * The structure description is available in @ref GTZC_Exported_Types.
820 * @retval HAL status.
821 */
HAL_GTZC_MPCBB_ConfigMem(uint32_t MemBaseAddress,const MPCBB_ConfigTypeDef * pMPCBB_desc)822 HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMem(uint32_t MemBaseAddress,
823 const MPCBB_ConfigTypeDef *pMPCBB_desc)
824 {
825 GTZC_MPCBB_TypeDef *mpcbb_ptr;
826 uint32_t mem_size;
827 uint32_t size_in_superblocks;
828 uint32_t i;
829
830 #if defined (GTZC_MPCBB3)
831 /* check entry parameters */
832 if ((!(IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
833 && !(IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress))
834 && !(IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress)))
835 || ((pMPCBB_desc->SecureRWIllegalMode != GTZC_MPCBB_SRWILADIS_ENABLE)
836 && (pMPCBB_desc->SecureRWIllegalMode != GTZC_MPCBB_SRWILADIS_DISABLE))
837 || ((pMPCBB_desc->InvertSecureState != GTZC_MPCBB_INVSECSTATE_NOT_INVERTED)
838 && (pMPCBB_desc->InvertSecureState != GTZC_MPCBB_INVSECSTATE_INVERTED)))
839 #else
840 if ((!(IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
841 && !(IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress)))
842 || ((pMPCBB_desc->SecureRWIllegalMode != GTZC_MPCBB_SRWILADIS_ENABLE)
843 && (pMPCBB_desc->SecureRWIllegalMode != GTZC_MPCBB_SRWILADIS_DISABLE))
844 || ((pMPCBB_desc->InvertSecureState != GTZC_MPCBB_INVSECSTATE_NOT_INVERTED)
845 && (pMPCBB_desc->InvertSecureState != GTZC_MPCBB_INVSECSTATE_INVERTED)))
846 #endif /* defined (GTZC_MPCBB3) */
847 {
848 return HAL_ERROR;
849 }
850
851 if (IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
852 {
853 mpcbb_ptr = GTZC_MPCBB1;
854 mem_size = GTZC_MEM_SIZE(SRAM1);
855 }
856 #if defined (GTZC_MPCBB3)
857 else if (IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress))
858 {
859 mpcbb_ptr = GTZC_MPCBB2;
860 mem_size = GTZC_MEM_SIZE(SRAM2);
861 }
862 else
863 {
864 mpcbb_ptr = GTZC_MPCBB3;
865 mem_size = GTZC_MEM_SIZE(SRAM3);
866 }
867 #else
868 else
869 {
870 mpcbb_ptr = GTZC_MPCBB2;
871 mem_size = GTZC_MEM_SIZE(SRAM2);
872 }
873 #endif /* defined (GTZC_MPCBB3) */
874
875 /* translate mem_size in number of super-blocks */
876 size_in_superblocks = (mem_size / GTZC_MPCBB_SUPERBLOCK_SIZE);
877
878 /* write PRIVCFGR register information */
879 for (i = 0U; i < size_in_superblocks; i++)
880 {
881 WRITE_REG(mpcbb_ptr->PRIVCFGR[i],
882 pMPCBB_desc->AttributeConfig.MPCBB_PrivConfig_array[i]);
883 }
884
885 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
886 uint32_t size_mask;
887 uint32_t reg_value;
888
889 /* write InvertSecureState and SecureRWIllegalMode properties */
890 reg_value = pMPCBB_desc->InvertSecureState;
891 reg_value |= pMPCBB_desc->SecureRWIllegalMode;
892
893 /* write SECCFGR register information */
894 for (i = 0U; i < size_in_superblocks; i++)
895 {
896 WRITE_REG(mpcbb_ptr->SECCFGR[i],
897 pMPCBB_desc->AttributeConfig.MPCBB_SecConfig_array[i]);
898 }
899
900 if (size_in_superblocks == 32U)
901 {
902 size_mask = 0xFFFFFFFFU;
903 }
904 else
905 {
906 size_mask = (1UL << size_in_superblocks) - 1U;
907 }
908 /* limitation: code not portable with memory > 512K */
909 MODIFY_REG(mpcbb_ptr->CFGLOCKR1, size_mask, pMPCBB_desc->AttributeConfig.MPCBB_LockConfig_array[0]);
910
911 /* write configuration and lock register information */
912 MODIFY_REG(mpcbb_ptr->CR,
913 GTZC_MPCBB_CR_INVSECSTATE_Msk | GTZC_MPCBB_CR_SRWILADIS_Msk, reg_value);
914
915 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
916
917 return HAL_OK;
918 }
919
920 /**
921 * @brief Get a complete MPCBB configuration on the SRAM passed as parameter.
922 * @param MemBaseAddress MPCBB identifier.
923 * @param pMPCBB_desc pointer to a MPCBB descriptor.
924 * The structure description is available in @ref GTZC_Exported_Types.
925 * @retval HAL status.
926 */
HAL_GTZC_MPCBB_GetConfigMem(uint32_t MemBaseAddress,MPCBB_ConfigTypeDef * pMPCBB_desc)927 HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMem(uint32_t MemBaseAddress,
928 MPCBB_ConfigTypeDef *pMPCBB_desc)
929 {
930 GTZC_MPCBB_TypeDef *mpcbb_ptr;
931 uint32_t mem_size;
932 uint32_t size_in_superblocks;
933 uint32_t i;
934
935 /* check entry parameters */
936 #if defined (GTZC_MPCBB3)
937 if (!(IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
938 && !(IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress))
939 && !(IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress)))
940 #else
941 if (!(IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
942 && !(IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress)))
943 #endif /* defined (GTZC_MPCBB3) */
944 {
945 return HAL_ERROR;
946 }
947
948 /* read InvertSecureState and SecureRWIllegalMode properties */
949 /* assume their Position/Mask is identical for all sub-blocks */
950 if (IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
951 {
952 mpcbb_ptr = GTZC_MPCBB1;
953 mem_size = GTZC_MEM_SIZE(SRAM1);
954 }
955 #if defined (GTZC_MPCBB3)
956 else if (IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress))
957 {
958 mpcbb_ptr = GTZC_MPCBB2;
959 mem_size = GTZC_MEM_SIZE(SRAM2);
960 }
961 else
962 {
963 mpcbb_ptr = GTZC_MPCBB3;
964 mem_size = GTZC_MEM_SIZE(SRAM3);
965 }
966 #else
967 else
968 {
969 mpcbb_ptr = GTZC_MPCBB2;
970 mem_size = GTZC_MEM_SIZE(SRAM2);
971 }
972 #endif /* */
973
974 /* translate mem_size in number of super-blocks */
975 size_in_superblocks = (mem_size / GTZC_MPCBB_SUPERBLOCK_SIZE);
976
977 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
978 uint32_t reg_value;
979 uint32_t size_mask;
980
981 /* read configuration and lock register information */
982 reg_value = READ_REG(mpcbb_ptr->CR);
983 pMPCBB_desc->InvertSecureState = (reg_value & GTZC_MPCBB_CR_INVSECSTATE_Msk);
984 pMPCBB_desc->SecureRWIllegalMode = (reg_value & GTZC_MPCBB_CR_SRWILADIS_Msk);
985 if (size_in_superblocks == 32U)
986 {
987 size_mask = 0xFFFFFFFFU;
988 }
989 else
990 {
991 size_mask = (1UL << size_in_superblocks) - 1U;
992 }
993 /* limitation: code not portable with memory > 512K */
994 pMPCBB_desc->AttributeConfig.MPCBB_LockConfig_array[0] = READ_REG(mpcbb_ptr->CFGLOCKR1)
995 & size_mask;
996 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
997
998 /* read SECCFGR / PRIVCFGR registers information */
999 for (i = 0U; i < size_in_superblocks; i++)
1000 {
1001 #if defined (GTZC_TZIC1)
1002 pMPCBB_desc->AttributeConfig.MPCBB_SecConfig_array[i] = mpcbb_ptr->SECCFGR[i];
1003 #endif /* defined (GTZC_TZIC1) */
1004 pMPCBB_desc->AttributeConfig.MPCBB_PrivConfig_array[i] = mpcbb_ptr->PRIVCFGR[i];
1005 }
1006
1007 return HAL_OK;
1008 }
1009
1010 /**
1011 * @brief Set a MPCBB attribute configuration on the SRAM passed as parameter
1012 * for a number of blocks.
1013 * @param MemAddress MPCBB identifier, and start block to configure
1014 * (must be 512 Bytes aligned).
1015 * @param NbBlocks Number of blocks to configure
1016 * (Block size is 512 Bytes).
1017 * @param pMemAttributes pointer to an array (containing "NbBlocks" elements),
1018 * with each element must be GTZC_MCPBB_BLOCK_NSEC or GTZC_MCPBB_BLOCK_SEC,
1019 * and GTZC_MCPBB_BLOCK_NPRIV or GTZC_MCPBB_BLOCK_PRIV.
1020 * @retval HAL status.
1021 */
HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress,uint32_t NbBlocks,const uint32_t * pMemAttributes)1022 HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress,
1023 uint32_t NbBlocks,
1024 const uint32_t *pMemAttributes)
1025 {
1026 GTZC_MPCBB_TypeDef *mpcbb_ptr;
1027 uint32_t base_address;
1028 uint32_t end_address;
1029 uint32_t block_start;
1030 uint32_t offset_reg_start;
1031 uint32_t offset_bit_start;
1032 uint32_t i;
1033 uint32_t do_attr_change;
1034
1035 /* firstly check that MemAddress is well 512 Bytes aligned */
1036 if ((MemAddress % GTZC_MPCBB_BLOCK_SIZE) != 0U)
1037 {
1038 return HAL_ERROR;
1039 }
1040
1041 /* check entry parameters and deduce physical base address */
1042 end_address = MemAddress + (NbBlocks * GTZC_MPCBB_BLOCK_SIZE) - 1U;
1043 if (((IS_ADDRESS_IN_NS(SRAM1, MemAddress))
1044 && (IS_ADDRESS_IN_NS(SRAM1, end_address))) != 0U)
1045 {
1046 mpcbb_ptr = GTZC_MPCBB1;
1047 base_address = SRAM1_BASE_NS;
1048 }
1049 #if defined (GTZC_TZIC1)
1050 else if (((IS_ADDRESS_IN_S(SRAM1, MemAddress))
1051 && (IS_ADDRESS_IN_S(SRAM1, end_address))) != 0U)
1052 {
1053 mpcbb_ptr = GTZC_MPCBB1;
1054 base_address = SRAM1_BASE_S;
1055 }
1056 #endif /* defined (GTZC_TZIC1) */
1057 else if (((IS_ADDRESS_IN_NS(SRAM2, MemAddress))
1058 && (IS_ADDRESS_IN_NS(SRAM2, end_address))) != 0U)
1059 {
1060 mpcbb_ptr = GTZC_MPCBB2;
1061 base_address = SRAM2_BASE_NS;
1062 }
1063 #if defined (GTZC_TZIC1)
1064 else if (((IS_ADDRESS_IN_S(SRAM2, MemAddress))
1065 && (IS_ADDRESS_IN_S(SRAM2, end_address))) != 0U)
1066 {
1067 mpcbb_ptr = GTZC_MPCBB2;
1068 base_address = SRAM2_BASE_S;
1069 }
1070 #endif /* defined (GTZC_TZIC1) */
1071 #if defined (GTZC_MPCBB3)
1072 else if (((IS_ADDRESS_IN_NS(SRAM3, MemAddress))
1073 && (IS_ADDRESS_IN_NS(SRAM3, end_address))) != 0U)
1074 {
1075 mpcbb_ptr = GTZC_MPCBB3;
1076 base_address = SRAM3_BASE_NS;
1077 }
1078 else if (((IS_ADDRESS_IN_S(SRAM3, MemAddress))
1079 && (IS_ADDRESS_IN_S(SRAM3, end_address))) != 0U)
1080 {
1081 mpcbb_ptr = GTZC_MPCBB3;
1082 base_address = SRAM3_BASE_S;
1083 }
1084 #endif /* defined (GTZC_MPCBB3) */
1085 else
1086 {
1087 return HAL_ERROR;
1088 }
1089
1090 /* get start coordinates of the configuration */
1091 block_start = (MemAddress - base_address) / GTZC_MPCBB_BLOCK_SIZE;
1092 offset_reg_start = block_start / 32U;
1093 offset_bit_start = block_start % 32U;
1094
1095 for (i = 0U; i < NbBlocks; i++)
1096 {
1097 /* Indicate change done for protection attributes */
1098 do_attr_change = 0U;
1099
1100 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1101 /* secure configuration */
1102 if ((pMemAttributes[i] & GTZC_MCPBB_BLOCK_SEC) == GTZC_MCPBB_BLOCK_SEC)
1103 {
1104 SET_BIT(mpcbb_ptr->SECCFGR[offset_reg_start],
1105 1UL << (offset_bit_start % 32U));
1106 do_attr_change = 1U;
1107 }
1108 else if ((pMemAttributes[i] & GTZC_MCPBB_BLOCK_NSEC) == GTZC_MCPBB_BLOCK_NSEC)
1109 {
1110 CLEAR_BIT(mpcbb_ptr->SECCFGR[offset_reg_start],
1111 1UL << (offset_bit_start % 32U));
1112 do_attr_change = 1U;
1113 }
1114 else
1115 {
1116 /* nothing to do */
1117 }
1118 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1119
1120 /* privilege configuration */
1121 if ((pMemAttributes[i] & GTZC_MCPBB_BLOCK_PRIV) == GTZC_MCPBB_BLOCK_PRIV)
1122 {
1123 SET_BIT(mpcbb_ptr->PRIVCFGR[offset_reg_start],
1124 1UL << (offset_bit_start % 32U));
1125 }
1126 else if ((pMemAttributes[i] & GTZC_MCPBB_BLOCK_NPRIV) == GTZC_MCPBB_BLOCK_NPRIV)
1127 {
1128 CLEAR_BIT(mpcbb_ptr->PRIVCFGR[offset_reg_start],
1129 1UL << (offset_bit_start % 32U));
1130 }
1131 else
1132 {
1133 /* if no change is done for security and privilege attributes: break the loop */
1134 if (do_attr_change == 0U)
1135 {
1136 break;
1137 }
1138 }
1139
1140 offset_bit_start++;
1141 if (offset_bit_start == 32U)
1142 {
1143 offset_bit_start = 0U;
1144 offset_reg_start++;
1145 }
1146 }
1147
1148 /* an unexpected value in pMemAttributes array leads to error status */
1149 if (i != NbBlocks)
1150 {
1151 return HAL_ERROR;
1152 }
1153
1154 return HAL_OK;
1155 }
1156
1157 /**
1158 * @brief Get a MPCBB attribute configuration on the SRAM passed as parameter
1159 * for a number of blocks.
1160 * @param MemAddress MPCBB identifier, and start block to get configuration
1161 * (must be 512 Bytes aligned).
1162 * @param NbBlocks Number of blocks to get configuration.
1163 * @param pMemAttributes pointer to an array (containing "NbBlocks" elements),
1164 * with each element will be GTZC_MCPBB_BLOCK_NSEC or GTZC_MCPBB_BLOCK_SEC,
1165 * and GTZC_MCPBB_BLOCK_NPRIV or GTZC_MCPBB_BLOCK_PRIV.
1166 * @retval HAL status.
1167 */
HAL_GTZC_MPCBB_GetConfigMemAttributes(uint32_t MemAddress,uint32_t NbBlocks,uint32_t * pMemAttributes)1168 HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMemAttributes(uint32_t MemAddress,
1169 uint32_t NbBlocks,
1170 uint32_t *pMemAttributes)
1171 {
1172 GTZC_MPCBB_TypeDef *mpcbb_ptr;
1173 uint32_t base_address;
1174 uint32_t end_address;
1175 uint32_t block_start;
1176 uint32_t offset_reg_start;
1177 uint32_t offset_bit_start;
1178 uint32_t i;
1179
1180 /* firstly check that MemAddress is well 512 Bytes aligned */
1181 if ((MemAddress % GTZC_MPCBB_BLOCK_SIZE) != 0U)
1182 {
1183 return HAL_ERROR;
1184 }
1185
1186 /* check entry parameters and deduce physical base address */
1187 end_address = MemAddress + (NbBlocks * GTZC_MPCBB_BLOCK_SIZE) - 1U;
1188 if ((IS_ADDRESS_IN_NS(SRAM1, MemAddress))
1189 && (IS_ADDRESS_IN_NS(SRAM1, end_address)))
1190 {
1191 mpcbb_ptr = GTZC_MPCBB1_NS;
1192 base_address = SRAM1_BASE_NS;
1193 }
1194 #if defined (GTZC_TZIC1)
1195 else if ((IS_ADDRESS_IN_S(SRAM1, MemAddress))
1196 && (IS_ADDRESS_IN_S(SRAM1, end_address)))
1197 {
1198 mpcbb_ptr = GTZC_MPCBB1_S;
1199 base_address = SRAM1_BASE_S;
1200 }
1201 #endif /* defined (GTZC_TZIC1) */
1202 else if ((IS_ADDRESS_IN_NS(SRAM2, MemAddress))
1203 && (IS_ADDRESS_IN_NS(SRAM2, end_address)))
1204 {
1205 mpcbb_ptr = GTZC_MPCBB2_NS;
1206 base_address = SRAM2_BASE_NS;
1207 }
1208 #if defined (GTZC_TZIC1)
1209 else if ((IS_ADDRESS_IN_S(SRAM2, MemAddress))
1210 && (IS_ADDRESS_IN_S(SRAM2, end_address)))
1211 {
1212 mpcbb_ptr = GTZC_MPCBB2_S;
1213 base_address = SRAM2_BASE_S;
1214 }
1215 #endif /* defined (GTZC_TZIC1) */
1216 #if defined (GTZC_MPCBB3)
1217 else if ((IS_ADDRESS_IN_NS(SRAM3, MemAddress))
1218 && (IS_ADDRESS_IN_NS(SRAM3, end_address)))
1219 {
1220 mpcbb_ptr = GTZC_MPCBB3_NS;
1221 base_address = SRAM3_BASE_NS;
1222 }
1223 else if ((IS_ADDRESS_IN_S(SRAM3, MemAddress))
1224 && (IS_ADDRESS_IN_S(SRAM3, end_address)))
1225 {
1226 mpcbb_ptr = GTZC_MPCBB3_S;
1227 base_address = SRAM3_BASE_S;
1228 }
1229 #endif /* defined (GTZC_MPCBB3) */
1230 else
1231 {
1232 return HAL_ERROR;
1233 }
1234
1235 /* get start coordinates of the configuration */
1236 block_start = (MemAddress - base_address) / GTZC_MPCBB_BLOCK_SIZE;
1237 offset_reg_start = block_start / 32U;
1238 offset_bit_start = block_start % 32U;
1239
1240 for (i = 0U; i < NbBlocks; i++)
1241 {
1242 #if defined (GTZC_TZIC1)
1243 pMemAttributes[i] = (READ_BIT(mpcbb_ptr->SECCFGR[offset_reg_start],
1244 1UL << (offset_bit_start % 32U))
1245 >> (offset_bit_start % 32U)) | GTZC_ATTR_SEC_MASK;
1246 #endif /* defined (GTZC_TZIC1) */
1247 pMemAttributes[i] |= (READ_BIT(mpcbb_ptr->PRIVCFGR[offset_reg_start],
1248 1UL << (offset_bit_start % 32U))
1249 >> (offset_bit_start % 32U)) | GTZC_ATTR_PRIV_MASK;
1250
1251 offset_bit_start++;
1252 if (offset_bit_start == 32U)
1253 {
1254 offset_bit_start = 0U;
1255 offset_reg_start++;
1256 }
1257 }
1258
1259 return HAL_OK;
1260 }
1261
1262 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1263 /**
1264 * @brief Lock MPCBB super-blocks on the SRAM passed as parameter.
1265 * @param MemAddress MPCBB start-address of super-block to configure
1266 * (must be 16KBytes aligned).
1267 * @param NbSuperBlocks Number of super-blocks to configure.
1268 * @param pLockAttributes pointer to an array (containing "NbSuperBlocks" elements),
1269 * with for each element:
1270 * value 0 super-block is unlocked, value 1 super-block is locked
1271 * (corresponds to GTZC_MCPBB_SUPERBLOCK_UNLOCKED and
1272 * GTZC_MCPBB_SUPERBLOCK_LOCKED values).
1273 * @retval HAL status.
1274 */
HAL_GTZC_MPCBB_LockConfig(uint32_t MemAddress,uint32_t NbSuperBlocks,const uint32_t * pLockAttributes)1275 HAL_StatusTypeDef HAL_GTZC_MPCBB_LockConfig(uint32_t MemAddress,
1276 uint32_t NbSuperBlocks,
1277 const uint32_t *pLockAttributes)
1278 {
1279 __IO uint32_t *reg_mpcbb;
1280 uint32_t base_address;
1281 uint32_t superblock_start;
1282 uint32_t offset_bit_start;
1283 uint32_t i;
1284
1285 /* firstly check that MemAddress is well 16KBytes aligned */
1286 if ((MemAddress % GTZC_MPCBB_SUPERBLOCK_SIZE) != 0U)
1287 {
1288 return HAL_ERROR;
1289 }
1290
1291 /* check entry parameters */
1292 if ((IS_ADDRESS_IN(SRAM1, MemAddress))
1293 && (IS_ADDRESS_IN(SRAM1, (MemAddress
1294 + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE)
1295 - 1U))))
1296 {
1297 base_address = GTZC_BASE_ADDRESS(SRAM1);
1298 /* limitation: code not portable with memory > 512K */
1299 reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB1_S->CFGLOCKR1;
1300 }
1301 else if ((IS_ADDRESS_IN(SRAM2, MemAddress))
1302 && (IS_ADDRESS_IN(SRAM2, (MemAddress
1303 + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE)
1304 - 1U))))
1305 {
1306 base_address = GTZC_BASE_ADDRESS(SRAM2);
1307 /* limitation: code not portable with memory > 256K */
1308 reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB2_S->CFGLOCKR1;
1309 }
1310 else if ((IS_ADDRESS_IN(SRAM3, MemAddress))
1311 && (IS_ADDRESS_IN(SRAM3, (MemAddress
1312 + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE)
1313 - 1U))))
1314 {
1315 base_address = GTZC_BASE_ADDRESS(SRAM3);
1316 /* limitation: code not portable with memory > 512K */
1317 reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB3_S->CFGLOCKR1;
1318 }
1319
1320 else
1321 {
1322 return HAL_ERROR;
1323 }
1324
1325 /* get start coordinates of the configuration */
1326 superblock_start = (MemAddress - base_address) / GTZC_MPCBB_SUPERBLOCK_SIZE;
1327 offset_bit_start = superblock_start % 32U;
1328
1329 for (i = 0U; i < NbSuperBlocks; i++)
1330 {
1331 if (pLockAttributes[i] == GTZC_MCPBB_SUPERBLOCK_LOCKED)
1332 {
1333 SET_BIT(*reg_mpcbb, 1UL << (offset_bit_start % 32U));
1334 }
1335 else if (pLockAttributes[i] == GTZC_MCPBB_SUPERBLOCK_UNLOCKED)
1336 {
1337 CLEAR_BIT(*reg_mpcbb, 1UL << (offset_bit_start % 32U));
1338 }
1339 else
1340 {
1341 break;
1342 }
1343
1344 offset_bit_start++;
1345 }
1346
1347 /* an unexpected value in pLockAttributes array leads to an error status */
1348 if (i != NbSuperBlocks)
1349 {
1350 return HAL_ERROR;
1351 }
1352
1353 return HAL_OK;
1354 }
1355
1356 /**
1357 * @brief Get MPCBB super-blocks lock configuration on the SRAM passed as parameter.
1358 * @param MemAddress MPCBB start-address of super-block to get configuration
1359 * (must be 16KBytes aligned).
1360 * @param NbSuperBlocks Number of super-blocks to get configuration.
1361 * @param pLockAttributes pointer to an array (containing "NbSuperBlocks" elements),
1362 * with for each element:
1363 * value 0 super-block is unlocked, value 1 super-block is locked
1364 * (corresponds to GTZC_MCPBB_SUPERBLOCK_UNLOCKED and
1365 * GTZC_MCPBB_SUPERBLOCK_LOCKED values).
1366 * @retval HAL status.
1367 */
HAL_GTZC_MPCBB_GetLockConfig(uint32_t MemAddress,uint32_t NbSuperBlocks,uint32_t * pLockAttributes)1368 HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLockConfig(uint32_t MemAddress,
1369 uint32_t NbSuperBlocks,
1370 uint32_t *pLockAttributes)
1371 {
1372 uint32_t reg_mpcbb;
1373 uint32_t base_address;
1374 uint32_t superblock_start;
1375 uint32_t offset_bit_start;
1376 uint32_t i;
1377
1378 /* firstly check that MemAddress is well 16KBytes aligned */
1379 if ((MemAddress % GTZC_MPCBB_SUPERBLOCK_SIZE) != 0U)
1380 {
1381 return HAL_ERROR;
1382 }
1383
1384 /* check entry parameters */
1385 if ((IS_ADDRESS_IN(SRAM1, MemAddress))
1386 && (IS_ADDRESS_IN(SRAM1, (MemAddress
1387 + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE)
1388 - 1U))))
1389 {
1390 base_address = GTZC_BASE_ADDRESS(SRAM1);
1391 /* limitation: code not portable with memory > 512K */
1392 reg_mpcbb = GTZC_MPCBB1_S->CFGLOCKR1;
1393 }
1394 else if ((IS_ADDRESS_IN(SRAM2, MemAddress))
1395 && (IS_ADDRESS_IN(SRAM2, (MemAddress
1396 + (NbSuperBlocks
1397 * GTZC_MPCBB_SUPERBLOCK_SIZE)
1398 - 1U))))
1399 {
1400 base_address = GTZC_BASE_ADDRESS(SRAM2);
1401 /* limitation: code not portable with memory > 512K */
1402 reg_mpcbb = GTZC_MPCBB2_S->CFGLOCKR1;
1403 }
1404 else if ((IS_ADDRESS_IN(SRAM3, MemAddress))
1405 && (IS_ADDRESS_IN(SRAM3, (MemAddress
1406 + (NbSuperBlocks
1407 * GTZC_MPCBB_SUPERBLOCK_SIZE)
1408 - 1U))))
1409 {
1410 base_address = GTZC_BASE_ADDRESS(SRAM3);
1411 /* limitation: code not portable with memory > 512K */
1412 reg_mpcbb = GTZC_MPCBB3_S->CFGLOCKR1;
1413 }
1414 else
1415 {
1416 return HAL_ERROR;
1417 }
1418
1419 /* get start coordinates of the configuration */
1420 superblock_start = (MemAddress - base_address) / GTZC_MPCBB_SUPERBLOCK_SIZE;
1421 offset_bit_start = superblock_start % 32U;
1422
1423 for (i = 0U; i < NbSuperBlocks; i++)
1424 {
1425 pLockAttributes[i] = (reg_mpcbb & (1UL << (offset_bit_start % 32U)))
1426 >> (offset_bit_start % 32U);
1427 offset_bit_start++;
1428 }
1429
1430 return HAL_OK;
1431 }
1432
1433 /**
1434 * @brief Lock a MPCBB configuration on the SRAM base address passed as parameter.
1435 * @note This functions locks the control register of the MPCBB until next reset.
1436 * @param MemBaseAddress MPCBB identifier.
1437 * @retval HAL status.
1438 */
HAL_GTZC_MPCBB_Lock(uint32_t MemBaseAddress)1439 HAL_StatusTypeDef HAL_GTZC_MPCBB_Lock(uint32_t MemBaseAddress)
1440 {
1441 /* check entry parameters */
1442 if (IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
1443 {
1444 SET_BIT(GTZC_MPCBB1_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
1445 }
1446 else if (IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress))
1447 {
1448 SET_BIT(GTZC_MPCBB2_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
1449 }
1450 else if (IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress))
1451 {
1452 SET_BIT(GTZC_MPCBB3_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
1453 }
1454 else
1455 {
1456 return HAL_ERROR;
1457 }
1458
1459 return HAL_OK;
1460 }
1461
1462 /**
1463 * @brief Get MPCBB configuration lock state on the SRAM base address passed as parameter.
1464 * @param MemBaseAddress MPCBB identifier.
1465 * @param pLockState pointer to Lock State (GTZC_MCPBB_LOCK_OFF or GTZC_MCPBB_LOCK_ON).
1466 * @retval HAL status.
1467 */
HAL_GTZC_MPCBB_GetLock(uint32_t MemBaseAddress,uint32_t * pLockState)1468 HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLock(uint32_t MemBaseAddress,
1469 uint32_t *pLockState)
1470 {
1471 /* check entry parameters */
1472 if (IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
1473 {
1474 *pLockState = READ_BIT(GTZC_MPCBB1_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
1475 }
1476 else if (IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress))
1477 {
1478 *pLockState = READ_BIT(GTZC_MPCBB2_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
1479 }
1480 else if (IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress))
1481 {
1482 *pLockState = READ_BIT(GTZC_MPCBB3_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
1483 }
1484 else
1485 {
1486 return HAL_ERROR;
1487 }
1488
1489 return HAL_OK;
1490 }
1491
1492 /**
1493 * @}
1494 */
1495
1496 /** @defgroup GTZC_Exported_Functions_Group5 TZIC Configuration and Control functions
1497 * @brief TZIC Configuration and Control functions
1498 *
1499 @verbatim
1500 ==============================================================================
1501 ##### TZIC Configuration and Control functions #####
1502 ==============================================================================
1503 [..]
1504 This section provides functions allowing to configure and control TZIC
1505 TZIC is Trust Zone Interrupt Controller
1506 @endverbatim
1507 * @{
1508 */
1509
1510 /**
1511 * @brief Disable the interrupt associated to a single TZIC peripheral or on all peripherals.
1512 * @param PeriphId Peripheral identifier.
1513 * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId.
1514 * Use GTZC_PERIPH_ALL to select all peripherals.
1515 * @retval HAL status.
1516 */
HAL_GTZC_TZIC_DisableIT(uint32_t PeriphId)1517 HAL_StatusTypeDef HAL_GTZC_TZIC_DisableIT(uint32_t PeriphId)
1518 {
1519 uint32_t register_address;
1520
1521 /* check entry parameters */
1522 if ((HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER)
1523 || (((PeriphId & GTZC_PERIPH_ALL) != 0U)
1524 && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U)))
1525 {
1526 return HAL_ERROR;
1527 }
1528
1529 if ((PeriphId & GTZC_PERIPH_ALL) != 0U)
1530 {
1531 /* same configuration is applied to all peripherals */
1532 WRITE_REG(GTZC_TZIC1->IER1, 0U);
1533 WRITE_REG(GTZC_TZIC1->IER2, 0U);
1534 WRITE_REG(GTZC_TZIC1->IER3, 0U);
1535 WRITE_REG(GTZC_TZIC1->IER4, 0U);
1536 }
1537 else
1538 {
1539 /* common case where only one peripheral is configured */
1540 register_address = (uint32_t)&(GTZC_TZIC1->IER1)
1541 + (4U * GTZC_GET_REG_INDEX(PeriphId));
1542 CLEAR_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
1543 }
1544
1545 return HAL_OK;
1546 }
1547
1548 /**
1549 * @brief Enable the interrupt associated to a single TZIC peripheral or on all peripherals.
1550 * @param PeriphId Peripheral identifier.
1551 * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId.
1552 * Use GTZC_PERIPH_ALL to select all peripherals.
1553 * @retval HAL status.
1554 */
HAL_GTZC_TZIC_EnableIT(uint32_t PeriphId)1555 HAL_StatusTypeDef HAL_GTZC_TZIC_EnableIT(uint32_t PeriphId)
1556 {
1557 uint32_t register_address;
1558
1559 /* check entry parameters */
1560 if ((HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER)
1561 || (((PeriphId & GTZC_PERIPH_ALL) != 0U)
1562 && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U)))
1563 {
1564 return HAL_ERROR;
1565 }
1566
1567 if ((PeriphId & GTZC_PERIPH_ALL) != 0U)
1568 {
1569 /* same configuration is applied to all peripherals */
1570 WRITE_REG(GTZC_TZIC1->IER1, TZIC1_IER1_ALL);
1571 WRITE_REG(GTZC_TZIC1->IER2, TZIC1_IER2_ALL);
1572 WRITE_REG(GTZC_TZIC1->IER3, TZIC1_IER3_ALL);
1573 WRITE_REG(GTZC_TZIC1->IER4, TZIC1_IER4_ALL);
1574 }
1575 else
1576 {
1577 /* common case where only one peripheral is configured */
1578 register_address = (uint32_t)&(GTZC_TZIC1->IER1)
1579 + (4U * GTZC_GET_REG_INDEX(PeriphId));
1580 SET_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
1581 }
1582
1583 return HAL_OK;
1584 }
1585
1586 /**
1587 * @brief Get TZIC flag on a single TZIC peripheral or on all peripherals.
1588 * @param PeriphId Peripheral identifier.
1589 * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId.
1590 * Use GTZC_PERIPH_ALL to select all peripherals.
1591 * @param pFlag Pointer to the flags.
1592 * If PeriphId target a single peripheral, pointer on a single element.
1593 * If all peripherals selected (GTZC_PERIPH_ALL), pointer to an array
1594 * of GTZC_TZIC_PERIPH_NUMBER elements.
1595 * Element content is either GTZC_TZIC_NO_ILA_EVENT
1596 * or GTZC_TZSC_ILA_EVENT_PENDING.
1597 * @retval HAL status
1598 */
HAL_GTZC_TZIC_GetFlag(uint32_t PeriphId,uint32_t * pFlag)1599 HAL_StatusTypeDef HAL_GTZC_TZIC_GetFlag(uint32_t PeriphId, uint32_t *pFlag)
1600 {
1601 uint32_t i;
1602 uint32_t reg_value;
1603 uint32_t register_address;
1604
1605 /* check entry parameters */
1606 if ((HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER)
1607 || (((PeriphId & GTZC_PERIPH_ALL) != 0U)
1608 && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U)))
1609 {
1610 return HAL_ERROR;
1611 }
1612
1613 if ((PeriphId & GTZC_PERIPH_ALL) != 0U)
1614 {
1615 /* special case where it is applied to all peripherals */
1616 reg_value = READ_REG(GTZC_TZIC1->SR1);
1617 for (i = 0U; i < 32U; i++)
1618 {
1619 pFlag[i] = (reg_value & (1UL << i)) >> i;
1620 }
1621
1622 reg_value = READ_REG(GTZC_TZIC1->SR2);
1623 for (i = 32U; i < 64U; i++)
1624 {
1625 pFlag[i] = (reg_value & (1UL << (i - 32U))) >> (i - 32U);
1626 }
1627
1628 reg_value = READ_REG(GTZC_TZIC1->SR3);
1629 for (i = 64U; i < 96U; i++)
1630 {
1631 pFlag[i] = (reg_value & (1UL << (i - 64U))) >> (i - 64U);
1632 }
1633
1634 reg_value = READ_REG(GTZC_TZIC1->SR4);
1635 for (i = 96U; i < 128U; i++)
1636 {
1637 pFlag[i] = (reg_value & (1UL << (i - 96U))) >> (i - 96U);
1638 }
1639 }
1640 else
1641 {
1642 /* common case where only one peripheral is concerned */
1643 register_address = (uint32_t)&(GTZC_TZIC1->SR1)
1644 + (4U * GTZC_GET_REG_INDEX(PeriphId));
1645 *pFlag = READ_BIT(*(__IO uint32_t *)register_address,
1646 1UL << GTZC_GET_PERIPH_POS(PeriphId)) >> GTZC_GET_PERIPH_POS(PeriphId);
1647 }
1648
1649 return HAL_OK;
1650 }
1651
1652 /**
1653 * @brief Clear TZIC flag on a single TZIC peripheral or on all peripherals.
1654 * @param PeriphId Peripheral identifier.
1655 * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId.
1656 * Use GTZC_PERIPH_ALL to select all peripherals.
1657 * @retval HAL status.
1658 */
HAL_GTZC_TZIC_ClearFlag(uint32_t PeriphId)1659 HAL_StatusTypeDef HAL_GTZC_TZIC_ClearFlag(uint32_t PeriphId)
1660 {
1661 uint32_t register_address;
1662
1663 /* check entry parameters */
1664 if ((HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER)
1665 || (((PeriphId & GTZC_PERIPH_ALL) != 0U)
1666 && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U)))
1667 {
1668 return HAL_ERROR;
1669 }
1670
1671 if ((PeriphId & GTZC_PERIPH_ALL) != 0U)
1672 {
1673 /* same configuration is applied to all peripherals */
1674 WRITE_REG(GTZC_TZIC1->FCR1, TZIC1_FCR1_ALL);
1675 WRITE_REG(GTZC_TZIC1->FCR2, TZIC1_FCR2_ALL);
1676 WRITE_REG(GTZC_TZIC1->FCR3, TZIC1_FCR3_ALL);
1677 WRITE_REG(GTZC_TZIC1->FCR4, TZIC1_FCR4_ALL);
1678 }
1679 else
1680 {
1681 /* common case where only one peripheral is configured */
1682 register_address = (uint32_t)&(GTZC_TZIC1->FCR1)
1683 + (4U * GTZC_GET_REG_INDEX(PeriphId));
1684 SET_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
1685 }
1686
1687 return HAL_OK;
1688 }
1689
1690 /**
1691 * @}
1692 */
1693
1694 /** @defgroup GTZC_Exported_Functions_Group6 IRQ related functions
1695 * @brief IRQ related functions
1696 *
1697 @verbatim
1698 ==============================================================================
1699 ##### TZIC IRQ Handler and Callback functions #####
1700 ==============================================================================
1701 [..]
1702 This section provides functions allowing to treat ISR and provide user callback
1703 @endverbatim
1704 * @{
1705 */
1706
1707 /**
1708 * @brief This function handles GTZC TZIC interrupt request.
1709 * @retval None.
1710 */
HAL_GTZC_IRQHandler(void)1711 void HAL_GTZC_IRQHandler(void)
1712 {
1713 uint32_t position;
1714 uint32_t flag;
1715 uint32_t ier_itsources;
1716 uint32_t sr_flags;
1717
1718 /* Get current IT Flags and IT sources value on 1st register of TZIC1 */
1719 ier_itsources = READ_REG(GTZC_TZIC1_S->IER1);
1720 sr_flags = READ_REG(GTZC_TZIC1_S->SR1);
1721
1722 /* Get Mask interrupt and then clear them */
1723 flag = ier_itsources & sr_flags;
1724 if (flag != 0U)
1725 {
1726 WRITE_REG(GTZC_TZIC1_S->FCR1, flag);
1727
1728 /* Loop on flag to check, which ones have been raised */
1729 position = 0U;
1730 while ((flag >> position) != 0U)
1731 {
1732 if ((flag & (1UL << position)) != 0U)
1733 {
1734 HAL_GTZC_TZIC_Callback(GTZC1_PERIPH_REG1 | position);
1735 }
1736
1737 /* Position bit to be updated */
1738 position++;
1739 }
1740 }
1741
1742 /* Get current IT Flags and IT sources value on 2nd register of TZIC1 */
1743 ier_itsources = READ_REG(GTZC_TZIC1_S->IER2);
1744 sr_flags = READ_REG(GTZC_TZIC1_S->SR2);
1745
1746 /* Get Mask interrupt and then clear them */
1747 flag = ier_itsources & sr_flags;
1748 if (flag != 0U)
1749 {
1750 WRITE_REG(GTZC_TZIC1_S->FCR2, flag);
1751
1752 /* Loop on flag to check, which ones have been raised */
1753 position = 0U;
1754 while ((flag >> position) != 0U)
1755 {
1756 if ((flag & (1UL << position)) != 0U)
1757 {
1758 HAL_GTZC_TZIC_Callback(GTZC1_PERIPH_REG2 | position);
1759 }
1760
1761 /* Position bit to be updated */
1762 position++;
1763 }
1764 }
1765
1766 /* Get current IT Flags and IT sources value on 3rd register of TZIC1 */
1767 ier_itsources = READ_REG(GTZC_TZIC1_S->IER3);
1768 sr_flags = READ_REG(GTZC_TZIC1_S->SR3);
1769
1770 /* Get Mask interrupt and then clear them */
1771 flag = ier_itsources & sr_flags;
1772 if (flag != 0U)
1773 {
1774 WRITE_REG(GTZC_TZIC1_S->FCR3, flag);
1775
1776 /* Loop on flag to check, which ones have been raised */
1777 position = 0U;
1778 while ((flag >> position) != 0U)
1779 {
1780 if ((flag & (1UL << position)) != 0U)
1781 {
1782 HAL_GTZC_TZIC_Callback(GTZC1_PERIPH_REG3 | position);
1783 }
1784
1785 /* Position bit to be updated */
1786 position++;
1787 }
1788 }
1789
1790 /* Get current IT Flags and IT sources value on 4th register of TZIC1 */
1791 ier_itsources = READ_REG(GTZC_TZIC1_S->IER4);
1792 sr_flags = READ_REG(GTZC_TZIC1_S->SR4);
1793
1794 /* Get Mask interrupt and then clear them */
1795 flag = ier_itsources & sr_flags;
1796 if(flag != 0U)
1797 {
1798 WRITE_REG(GTZC_TZIC1->FCR4, flag);
1799
1800 /* Loop on flag to check, which ones have been raised */
1801 position = 0U;
1802 while ((flag >> position) != 0U)
1803 {
1804 if ((flag & (1UL << position)) != 0U)
1805 {
1806 HAL_GTZC_TZIC_Callback(GTZC1_PERIPH_REG4 | position);
1807 }
1808
1809 /* Position bit to be updated */
1810 position++;
1811 }
1812 }
1813 }
1814
1815 /**
1816 * @brief GTZC TZIC sub-block interrupt callback.
1817 * @param PeriphId Peripheral identifier triggering the illegal access.
1818 * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId
1819 * @retval None.
1820 */
HAL_GTZC_TZIC_Callback(uint32_t PeriphId)1821 __weak void HAL_GTZC_TZIC_Callback(uint32_t PeriphId)
1822 {
1823 /* Prevent unused argument(s) compilation warning */
1824 UNUSED(PeriphId);
1825
1826 /* NOTE: This function should not be modified. When the callback is needed,
1827 * the HAL_GTZC_TZIC_Callback is to be implemented in the user file
1828 */
1829 }
1830
1831 /**
1832 * @}
1833 */
1834
1835 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1836
1837 /**
1838 * @}
1839 */
1840
1841 #endif /*HAL_GTZC_MODULE_ENABLED*/
1842
1843 /**
1844 * @}
1845 */
1846
1847 /**
1848 * @}
1849 */
1850
1851
