1/* ------------------------------------------------------------------------- */
2/*  @file:    startup_MKM34Z7.s                                              */
3/*  @purpose: CMSIS Cortex-M0P Core Device Startup File                      */
4/*            MKM34Z7                                                        */
5/*  @version: 1.2                                                            */
6/*  @date:    2015-3-6                                                       */
7/*  @build:   b230529                                                        */
8/* ------------------------------------------------------------------------- */
9/*                                                                           */
10/* Copyright 1997-2016 Freescale Semiconductor, Inc.                         */
11/* Copyright 2016-2023 NXP                                                   */
12/* SPDX-License-Identifier: BSD-3-Clause                                     */
13/*****************************************************************************/
14/* Version: GCC for ARM Embedded Processors                                  */
15/*****************************************************************************/
16    .syntax unified
17    .arch armv6-m
18
19    .section .isr_vector, "a"
20    .align 2
21    .globl __isr_vector
22__isr_vector:
23    .long   __StackTop                                      /* Top of Stack */
24    .long   Reset_Handler                                   /* Reset Handler */
25    .long   NMI_Handler                                     /* NMI Handler*/
26    .long   HardFault_Handler                               /* Hard Fault Handler*/
27    .long   0                                               /* Reserved*/
28    .long   0                                               /* Reserved*/
29    .long   0                                               /* Reserved*/
30    .long   0                                               /* Reserved*/
31    .long   0                                               /* Reserved*/
32    .long   0                                               /* Reserved*/
33    .long   0                                               /* Reserved*/
34    .long   SVC_Handler                                     /* SVCall Handler*/
35    .long   0                                               /* Reserved*/
36    .long   0                                               /* Reserved*/
37    .long   PendSV_Handler                                  /* PendSV Handler*/
38    .long   SysTick_Handler                                 /* SysTick Handler*/
39
40                                                            /* External Interrupts*/
41    .long   DMA0_IRQHandler                                 /* DMA channel 0 transfer complete*/
42    .long   DMA1_IRQHandler                                 /* DMA channel 1 transfer complete*/
43    .long   DMA2_IRQHandler                                 /* DMA channel 2 transfer complete*/
44    .long   DMA3_IRQHandler                                 /* DMA channel 3 transfer complete*/
45    .long   SPI0_SPI1_IRQHandler                            /* SPI0/SPI1 ORed interrupt*/
46    .long   PDB0_IRQHandler                                 /* PDB0 ORed interrupt*/
47    .long   PMC_IRQHandler                                  /* Low-voltage detect, low-voltage warning*/
48    .long   TMR0_IRQHandler                                 /* Quad Timer Channel 0*/
49    .long   TMR1_IRQHandler                                 /* Quad Timer Channel 1*/
50    .long   TMR2_IRQHandler                                 /* Quad Timer Channel 2*/
51    .long   TMR3_IRQHandler                                 /* Quad Timer Channel 3*/
52    .long   PIT0_PIT1_IRQHandler                            /* PIT0/PIT1 ORed interrupt*/
53    .long   LLWU_IRQHandler                                 /* Low Leakage Wakeup*/
54    .long   FTFA_IRQHandler                                 /* Command complete and read collision*/
55    .long   CMP0_CMP1_CMP2_IRQHandler                       /* CMP0/CMP1/CMP2 ORed interrupt*/
56    .long   LCD_IRQHandler                                  /* LCD interrupt*/
57    .long   ADC0_IRQHandler                                 /* ADC0 interrupt*/
58    .long   PTx_IRQHandler                                  /* Single interrupt vector for GPIOA,GPIOB,GPIOC,GPIOD,GPIOE,GPIOF,GPIOG,GPIOH,GPIOI,GPIOJ,GPIOK,GPIOL,GPIOM*/
59    .long   RNGA_IRQHandler                                 /* RNGA interrupt*/
60    .long   UART0_UART1_UART2_UART3_IRQHandler              /* UART0/UART1/UART2/UART3 ORed interrupt*/
61    .long   MMAU_IRQHandler                                 /* Memory Mapped Arithmetic Unit interrupt*/
62    .long   AFE_CH0_IRQHandler                              /* AFE Channel 0*/
63    .long   AFE_CH1_IRQHandler                              /* AFE Channel 1*/
64    .long   AFE_CH2_IRQHandler                              /* AFE Channel 2*/
65    .long   AFE_CH3_IRQHandler                              /* AFE Channel 3*/
66    .long   RTC_IRQHandler                                  /* IRTC interrupt*/
67    .long   I2C0_I2C1_IRQHandler                            /* I2C0/I2C1 ORed interrupt*/
68    .long   LPUART0_IRQHandler                              /* LPUART0 status and error interrupt*/
69    .long   MCG_IRQHandler                                  /* MCG interrupt*/
70    .long   WDOG_EWM_IRQHandler                             /* WDOG/EWM ORed interrupt*/
71    .long   LPTMR0_IRQHandler                               /* LPTMR0 interrupt*/
72    .long   XBAR_IRQHandler                                 /* XBAR interrupt*/
73
74    .size   __isr_vector, . - __isr_vector
75
76/* Flash Configuration */
77    .section .FlashConfig, "a"
78    .long 0xFFFFFFFF
79    .long 0xFFFFFFFF
80    .long 0xFFFFFFFF
81    .long 0xFFFFFFFE
82
83    .text
84    .thumb
85
86/* Reset Handler */
87
88    .thumb_func
89    .align 2
90    .globl   Reset_Handler
91    .weak    Reset_Handler
92    .type    Reset_Handler, %function
93Reset_Handler:
94    cpsid   i               /* Mask interrupts */
95    .equ    VTOR, 0xE000ED08
96    ldr     r0, =VTOR
97    ldr     r1, =__isr_vector
98    str     r1, [r0]
99    ldr     r2, [r1]
100    msr     msp, r2
101#ifndef __NO_SYSTEM_INIT
102    ldr   r0,=SystemInit
103    blx   r0
104#endif
105/*     Loop to copy data from read only memory to RAM. The ranges
106 *      of copy from/to are specified by following symbols evaluated in
107 *      linker script.
108 *      __etext: End of code section, i.e., begin of data sections to copy from.
109 *      __data_start__/__data_end__: RAM address range that data should be
110 *      copied to. Both must be aligned to 4 bytes boundary.  */
111
112    ldr    r1, =__etext
113    ldr    r2, =__data_start__
114    ldr    r3, =__data_end__
115
116    subs    r3, r2
117    ble     .LC0
118
119.LC1:
120    subs    r3, 4
121    ldr    r0, [r1,r3]
122    str    r0, [r2,r3]
123    bgt    .LC1
124.LC0:
125
126#ifdef __STARTUP_CLEAR_BSS
127/*     This part of work usually is done in C library startup code. Otherwise,
128 *     define this macro to enable it in this startup.
129 *
130 *     Loop to zero out BSS section, which uses following symbols
131 *     in linker script:
132 *      __bss_start__: start of BSS section. Must align to 4
133 *      __bss_end__: end of BSS section. Must align to 4
134 */
135    ldr r1, =__bss_start__
136    ldr r2, =__bss_end__
137
138    subs    r2, r1
139    ble .LC3
140
141    movs    r0, 0
142.LC2:
143    subs    r2, 4
144    str r0, [r1, r2]
145    bgt .LC2
146.LC3:
147#endif
148    cpsie   i               /* Unmask interrupts */
149#ifndef __START
150#define __START _start
151#endif
152#ifndef __ATOLLIC__
153    ldr   r0,=__START
154    blx   r0
155#else
156    ldr   r0,=__libc_init_array
157    blx   r0
158    ldr   r0,=main
159    bx    r0
160#endif
161    .pool
162    .size Reset_Handler, . - Reset_Handler
163
164    .align  1
165    .thumb_func
166    .weak DefaultISR
167    .type DefaultISR, %function
168DefaultISR:
169    ldr r0, =DefaultISR
170    bx r0
171    .size DefaultISR, . - DefaultISR
172
173    .align 1
174    .thumb_func
175    .weak NMI_Handler
176    .type NMI_Handler, %function
177NMI_Handler:
178    ldr   r0,=NMI_Handler
179    bx    r0
180    .size NMI_Handler, . - NMI_Handler
181
182    .align 1
183    .thumb_func
184    .weak HardFault_Handler
185    .type HardFault_Handler, %function
186HardFault_Handler:
187    ldr   r0,=HardFault_Handler
188    bx    r0
189    .size HardFault_Handler, . - HardFault_Handler
190
191    .align 1
192    .thumb_func
193    .weak SVC_Handler
194    .type SVC_Handler, %function
195SVC_Handler:
196    ldr   r0,=SVC_Handler
197    bx    r0
198    .size SVC_Handler, . - SVC_Handler
199
200    .align 1
201    .thumb_func
202    .weak PendSV_Handler
203    .type PendSV_Handler, %function
204PendSV_Handler:
205    ldr   r0,=PendSV_Handler
206    bx    r0
207    .size PendSV_Handler, . - PendSV_Handler
208
209    .align 1
210    .thumb_func
211    .weak SysTick_Handler
212    .type SysTick_Handler, %function
213SysTick_Handler:
214    ldr   r0,=SysTick_Handler
215    bx    r0
216    .size SysTick_Handler, . - SysTick_Handler
217
218    .align 1
219    .thumb_func
220    .weak DMA0_IRQHandler
221    .type DMA0_IRQHandler, %function
222DMA0_IRQHandler:
223    ldr   r0,=DMA0_DriverIRQHandler
224    bx    r0
225    .size DMA0_IRQHandler, . - DMA0_IRQHandler
226
227    .align 1
228    .thumb_func
229    .weak DMA1_IRQHandler
230    .type DMA1_IRQHandler, %function
231DMA1_IRQHandler:
232    ldr   r0,=DMA1_DriverIRQHandler
233    bx    r0
234    .size DMA1_IRQHandler, . - DMA1_IRQHandler
235
236    .align 1
237    .thumb_func
238    .weak DMA2_IRQHandler
239    .type DMA2_IRQHandler, %function
240DMA2_IRQHandler:
241    ldr   r0,=DMA2_DriverIRQHandler
242    bx    r0
243    .size DMA2_IRQHandler, . - DMA2_IRQHandler
244
245    .align 1
246    .thumb_func
247    .weak DMA3_IRQHandler
248    .type DMA3_IRQHandler, %function
249DMA3_IRQHandler:
250    ldr   r0,=DMA3_DriverIRQHandler
251    bx    r0
252    .size DMA3_IRQHandler, . - DMA3_IRQHandler
253
254    .align 1
255    .thumb_func
256    .weak SPI0_SPI1_IRQHandler
257    .type SPI0_SPI1_IRQHandler, %function
258SPI0_SPI1_IRQHandler:
259    ldr   r0,=SPI0_SPI1_DriverIRQHandler
260    bx    r0
261    .size SPI0_SPI1_IRQHandler, . - SPI0_SPI1_IRQHandler
262
263    .align 1
264    .thumb_func
265    .weak UART0_UART1_UART2_UART3_IRQHandler
266    .type UART0_UART1_UART2_UART3_IRQHandler, %function
267UART0_UART1_UART2_UART3_IRQHandler:
268    ldr   r0,=UART0_UART1_UART2_UART3_DriverIRQHandler
269    bx    r0
270    .size UART0_UART1_UART2_UART3_IRQHandler, . - UART0_UART1_UART2_UART3_IRQHandler
271
272    .align 1
273    .thumb_func
274    .weak I2C0_I2C1_IRQHandler
275    .type I2C0_I2C1_IRQHandler, %function
276I2C0_I2C1_IRQHandler:
277    ldr   r0,=I2C0_I2C1_DriverIRQHandler
278    bx    r0
279    .size I2C0_I2C1_IRQHandler, . - I2C0_I2C1_IRQHandler
280
281    .align 1
282    .thumb_func
283    .weak LPUART0_IRQHandler
284    .type LPUART0_IRQHandler, %function
285LPUART0_IRQHandler:
286    ldr   r0,=LPUART0_DriverIRQHandler
287    bx    r0
288    .size LPUART0_IRQHandler, . - LPUART0_IRQHandler
289
290
291/*    Macro to define default handlers. Default handler
292 *    will be weak symbol and just dead loops. They can be
293 *    overwritten by other handlers */
294    .macro def_irq_handler  handler_name
295    .weak \handler_name
296    .set  \handler_name, DefaultISR
297    .endm
298/* Exception Handlers */
299    def_irq_handler    DMA0_DriverIRQHandler
300    def_irq_handler    DMA1_DriverIRQHandler
301    def_irq_handler    DMA2_DriverIRQHandler
302    def_irq_handler    DMA3_DriverIRQHandler
303    def_irq_handler    SPI0_SPI1_DriverIRQHandler
304    def_irq_handler    PDB0_IRQHandler
305    def_irq_handler    PMC_IRQHandler
306    def_irq_handler    TMR0_IRQHandler
307    def_irq_handler    TMR1_IRQHandler
308    def_irq_handler    TMR2_IRQHandler
309    def_irq_handler    TMR3_IRQHandler
310    def_irq_handler    PIT0_PIT1_IRQHandler
311    def_irq_handler    LLWU_IRQHandler
312    def_irq_handler    FTFA_IRQHandler
313    def_irq_handler    CMP0_CMP1_CMP2_IRQHandler
314    def_irq_handler    LCD_IRQHandler
315    def_irq_handler    ADC0_IRQHandler
316    def_irq_handler    PTx_IRQHandler
317    def_irq_handler    RNGA_IRQHandler
318    def_irq_handler    UART0_UART1_UART2_UART3_DriverIRQHandler
319    def_irq_handler    MMAU_IRQHandler
320    def_irq_handler    AFE_CH0_IRQHandler
321    def_irq_handler    AFE_CH1_IRQHandler
322    def_irq_handler    AFE_CH2_IRQHandler
323    def_irq_handler    AFE_CH3_IRQHandler
324    def_irq_handler    RTC_IRQHandler
325    def_irq_handler    I2C0_I2C1_DriverIRQHandler
326    def_irq_handler    LPUART0_DriverIRQHandler
327    def_irq_handler    MCG_IRQHandler
328    def_irq_handler    WDOG_EWM_IRQHandler
329    def_irq_handler    LPTMR0_IRQHandler
330    def_irq_handler    XBAR_IRQHandler
331
332    .end
333