1/* ---------------------------------------------------------------------------------------*/ 2/* @file: startup_LPC54114_cm4.S */ 3/* @purpose: CMSIS Cortex-M4 Core Device Startup File */ 4/* LPC54114_cm4 */ 5/* @version: 1.0 */ 6/* @date: 2016-11-2 */ 7/* @build: b161214 */ 8/* ---------------------------------------------------------------------------------------*/ 9/* */ 10/* Copyright 1997-2016 Freescale Semiconductor, Inc. */ 11/* Copyright 2016-2018 NXP */ 12/* */ 13/* SPDX-License-Identifier: BSD-3-Clause */ 14/*****************************************************************************/ 15/* Version: GCC for ARM Embedded Processors */ 16/*****************************************************************************/ 17 .syntax unified 18 .arch armv7-m 19 20 .section .isr_vector, "a" 21 .align 2 22 .globl __Vectors 23__Vectors: 24 .long __StackTop /* Top of Stack */ 25 .long Reset_Handler /* Reset Handler */ 26 .long NMI_Handler /* NMI Handler*/ 27 .long HardFault_Handler /* Hard Fault Handler*/ 28 .long MemManage_Handler /* MPU Fault Handler*/ 29 .long BusFault_Handler /* Bus Fault Handler*/ 30 .long UsageFault_Handler /* Usage Fault Handler*/ 31 .long 0 /* Reserved*/ 32 .long 0 /* Reserved*/ 33 .long 0 /* Reserved*/ 34 .long 0 /* Reserved*/ 35 .long SVC_Handler /* SVCall Handler*/ 36 .long DebugMon_Handler /* Debug Monitor Handler*/ 37 .long 0 /* Reserved*/ 38 .long PendSV_Handler /* PendSV Handler*/ 39 .long SysTick_Handler /* SysTick Handler*/ 40 41 /* External Interrupts*/ 42 .long WDT_BOD_IRQHandler /* Watchdog Timer, Brownout detect */ 43 .long DMA0_IRQHandler /* DMA controller interrupt */ 44 .long GINT0_IRQHandler /* GPIO group 0 */ 45 .long GINT1_IRQHandler /* GPIO group 1 */ 46 .long PIN_INT0_IRQHandler /* Pin interrupt 0 or pattern match engine slice 0 */ 47 .long PIN_INT1_IRQHandler /* Pin interrupt 1 or pattern match engine slice 1 */ 48 .long PIN_INT2_IRQHandler /* Pin interrupt 2 or pattern match engine slice 2 */ 49 .long PIN_INT3_IRQHandler /* Pin interrupt 3 or pattern match engine slice 3 */ 50 .long UTICK0_IRQHandler /* Micro-tick Timer */ 51 .long MRT0_IRQHandler /* Multi-rate timer */ 52 .long CTIMER0_IRQHandler /* Standard counter/timer CTIMER0 */ 53 .long CTIMER1_IRQHandler /* Standard counter/timer CTIMER1 */ 54 .long SCT0_IRQHandler /* SCTimer/PWM */ 55 .long CTIMER3_IRQHandler /* Standard counter/timer CTIMER3 */ 56 .long FLEXCOMM0_IRQHandler /* Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM) */ 57 .long FLEXCOMM1_IRQHandler /* Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM) */ 58 .long FLEXCOMM2_IRQHandler /* Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM) */ 59 .long FLEXCOMM3_IRQHandler /* Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM) */ 60 .long FLEXCOMM4_IRQHandler /* Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM) */ 61 .long FLEXCOMM5_IRQHandler /* Flexcomm Interface 5 (USART, SPI, I2C, FLEXCOMM) */ 62 .long FLEXCOMM6_IRQHandler /* Flexcomm Interface 6 (USART, SPI, I2C, FLEXCOMM) */ 63 .long FLEXCOMM7_IRQHandler /* Flexcomm Interface 7 (USART, SPI, I2C, FLEXCOMM) */ 64 .long ADC0_SEQA_IRQHandler /* ADC0 sequence A completion */ 65 .long ADC0_SEQB_IRQHandler /* ADC0 sequence B completion */ 66 .long ADC0_THCMP_IRQHandler /* ADC0 threshold compare and error. */ 67 .long DMIC0_IRQHandler /* RTC alarm and wake-up interrupts */ 68 .long HWVAD0_IRQHandler /* Hardware Voice Activity Detector */ 69 .long USB0_NEEDCLK_IRQHandler /* USB Activity Wake-up Interrupt */ 70 .long USB0_IRQHandler /* USB device */ 71 .long RTC_IRQHandler /* RTC alarm and wake-up interrupts */ 72 .long IOH_IRQHandler /* IOH interrupt */ 73 .long MAILBOX_IRQHandler /* Mailbox interrupt */ 74 .long PIN_INT4_IRQHandler /* Pin interrupt 4 or pattern match engine slice 4 int */ 75 .long PIN_INT5_IRQHandler /* Pin interrupt 5 or pattern match engine slice 5 int */ 76 .long PIN_INT6_IRQHandler /* Pin interrupt 6 or pattern match engine slice 6 int */ 77 .long PIN_INT7_IRQHandler /* Pin interrupt 7 or pattern match engine slice 7 int */ 78 .long CTIMER2_IRQHandler /* Standard counter/timer CTIMER2 */ 79 .long CTIMER4_IRQHandler /* Standard counter/timer CTIMER4 */ 80 .long 0 /* Reserved interrupt */ 81 .long SPIFI0_IRQHandler /* SPI flash interface */ 82 .size __Vectors, . - __Vectors 83 84/* Variable to store CRP value in. No code read protection enabled by default 85 * Code Read Protection level (CRP) 86 * CRP_Level: 87 * <0xFFFFFFFF=> Disabled 88 * <0x4E697370=> NO_ISP 89 * <0x12345678=> CRP1 90 * <0x87654321=> CRP2 91 * <0x43218765=> CRP3 92 */ 93 #ifndef NO_CRP 94 .section .crp, "a" 95 .long 0xFFFFFFFF 96 #endif 97 98 99 .text 100 .thumb 101#ifndef SLAVEBOOT 102rel_vals: 103 .long 0xE000ED00 /* cpu_id */ 104 .long 0x40000800 /* cpu_ctrl */ 105 .long 0x40000804 /* coproc_boot */ 106 .long 0x40000808 /* coproc_stack */ 107 .short 0x0FFF 108 .short 0x0C24 109#endif 110/* Reset Handler */ 111 112 .thumb_func 113 .align 2 114 .globl Reset_Handler 115 .weak Reset_Handler 116 .type Reset_Handler, %function 117 118Reset_Handler: 119#ifndef SLAVEBOOT 120/* Both the M0+ and M4 core come via this shared startup code, 121 * but the M0+ and M4 core have different vector tables. 122 * Determine if the core executing this code is the master or 123 * the slave and handle each core state individually. */ 124 125shared_boot_entry: 126 ldr r6, =rel_vals 127 128 /* Flag for slave core (0) */ 129 movs r4, 0 130 movs r5, 1 131 132 /* Determine which core (M0+ or M4) this code is running on */ 133 /* r2 = (((*cpu_id) >> 4) & 0xFFF); (M4 core == 0xC24) */ 134get_current_core_id: 135 ldr r0, [r6, #0] 136 ldr r1, [r0] /* r1 = CPU ID status */ 137 lsrs r1, r1, #4 /* Right justify 12 CPU ID bits */ 138 ldrh r2, [r6, #16] /* Mask for CPU ID bits */ 139 ands r2, r1, r2 /* r2 = ARM COrtex CPU ID */ 140 ldrh r3, [r6, #18] /* Mask for CPU ID bits */ 141 cmp r3, r2 /* Core ID matches M4 identifier */ 142 bne get_master_status 143 mov r4, r5 /* Set flag for master core (1) */ 144 145 /* Determine if M4 core is the master or slave */ 146 /* r3 = ((*cpu_ctrl) & 1); (0 == m0+, 1 == M4) */ 147get_master_status: 148 ldr r0, [r6, #4] 149 ldr r3, [r0] /* r3 = SYSCON co-processor CPU control status */ 150 151 ands r3, r3, r5 /* r3 = (Bit 0: 1 = M4 is master, 0 = M4 is slave) */ 152 153 /* Select boot based on selected master core and core ID */ 154 155select_boot: 156 eors r3, r3, r4 /* r4 = (Bit 0: 0 = master, 1 = slave) */ 157 158 bne slave_boot 159 b normal_boot 160 161 /* Slave boot */ 162slave_boot: 163 ldr r0, [r6, #8] 164 ldr r2, [r0] /* r1 = SYSCON co-processor boot address */ 165 166 cmp r2, #0 /* Slave boot address = 0 (not set up)? */ 167 168 beq cpu_sleep 169 ldr r0, [r6, #12] 170 ldr r1, [r0] /* r5 = SYSCON co-processor stack address */ 171 172 mov sp, r1 /* Update slave CPU stack pointer */ 173 174 /* Be sure to update VTOR for the slave MCU to point to the */ 175 /* slave vector table in boot memory */ 176 bx r2 /* Jump to slave boot address */ 177 178 /* Slave isn't yet setup for system boot from the master */ 179 /* so sleep until the master sets it up and then reboots it */ 180cpu_sleep: 181 mov sp, r5 /* Will force exception if something happens */ 182cpu_sleep_wfi: 183 wfi /* Sleep forever until master reboots */ 184 b cpu_sleep_wfi 185#endif /* defined(SLAVEBOOT) */ 186 187#ifndef __START 188#define __START _start 189#endif 190#ifndef __ATOLLIC__ 191normal_boot: 192#ifndef __NO_SYSTEM_INIT 193 ldr r0,=SystemInit 194 blx r0 195#endif 196 /* Loop to copy data from read only memory to RAM. The ranges 197 * of copy from/to are specified by following symbols evaluated in 198 * linker script. 199 * __etext: End of code section, i.e., begin of data sections to copy from. 200 * __data_start__/__data_end__: RAM address range that data should be 201 * copied to. Both must be aligned to 4 bytes boundary. */ 202 203 ldr r1, =__etext 204 ldr r2, =__data_start__ 205 ldr r3, =__data_end__ 206 207#if 1 208/* Here are two copies of loop implemenations. First one favors code size 209 * and the second one favors performance. Default uses the first one. 210 * Change to "#if 0" to use the second one */ 211.LC0: 212 cmp r2, r3 213 ittt lt 214 ldrlt r0, [r1], #4 215 strlt r0, [r2], #4 216 blt .LC0 217#else 218 subs r3, r2 219 ble .LC1 220.LC0: 221 subs r3, #4 222 ldr r0, [r1, r3] 223 str r0, [r2, r3] 224 bgt .LC0 225.LC1: 226#endif 227 228#ifdef __STARTUP_CLEAR_BSS 229/* This part of work usually is done in C library startup code. Otherwise, 230 * define this macro to enable it in this startup. 231 * 232 * Loop to zero out BSS section, which uses following symbols 233 * in linker script: 234 * __bss_start__: start of BSS section. Must align to 4 235 * __bss_end__: end of BSS section. Must align to 4 236 */ 237 ldr r1, =__bss_start__ 238 ldr r2, =__bss_end__ 239 240 movs r0, 0 241.LC2: 242 cmp r1, r2 243 itt lt 244 strlt r0, [r1], #4 245 blt .LC2 246#endif /* __STARTUP_CLEAR_BSS */ 247 ldr r0,=__START 248 blx r0 249#else 250 ldr r0,=__libc_init_array 251 blx r0 252 ldr r0,=main 253 bx r0 254#endif 255 256 .pool 257 .size Reset_Handler, . - Reset_Handler 258 259 .align 1 260 .thumb_func 261 .weak DefaultISR 262 .type DefaultISR, %function 263DefaultISR: 264 b DefaultISR 265 .size DefaultISR, . - DefaultISR 266 267 .align 1 268 .thumb_func 269 .weak NMI_Handler 270 .type NMI_Handler, %function 271NMI_Handler: 272 ldr r0,=NMI_Handler 273 bx r0 274 .size NMI_Handler, . - NMI_Handler 275 276 .align 1 277 .thumb_func 278 .weak HardFault_Handler 279 .type HardFault_Handler, %function 280HardFault_Handler: 281 ldr r0,=HardFault_Handler 282 bx r0 283 .size HardFault_Handler, . - HardFault_Handler 284 285 .align 1 286 .thumb_func 287 .weak MemManage_Handler 288 .type MemManage_Handler, %function 289MemManage_Handler: 290 ldr r0,=MemManage_Handler 291 bx r0 292 .size MemManage_Handler, . - MemManage_Handler 293 294 .align 1 295 .thumb_func 296 .weak BusFault_Handler 297 .type BusFault_Handler, %function 298BusFault_Handler: 299 ldr r0,=BusFault_Handler 300 bx r0 301 .size BusFault_Handler, . - BusFault_Handler 302 303 .align 1 304 .thumb_func 305 .weak UsageFault_Handler 306 .type UsageFault_Handler, %function 307UsageFault_Handler: 308 ldr r0,=UsageFault_Handler 309 bx r0 310 .size UsageFault_Handler, . - UsageFault_Handler 311 312 .align 1 313 .thumb_func 314 .weak SVC_Handler 315 .type SVC_Handler, %function 316SVC_Handler: 317 ldr r0,=SVC_Handler 318 bx r0 319 .size SVC_Handler, . - SVC_Handler 320 321 .align 1 322 .thumb_func 323 .weak DebugMon_Handler 324 .type DebugMon_Handler, %function 325DebugMon_Handler: 326 ldr r0,=DebugMon_Handler 327 bx r0 328 .size DebugMon_Handler, . - DebugMon_Handler 329 330 .align 1 331 .thumb_func 332 .weak PendSV_Handler 333 .type PendSV_Handler, %function 334PendSV_Handler: 335 ldr r0,=PendSV_Handler 336 bx r0 337 .size PendSV_Handler, . - PendSV_Handler 338 339 .align 1 340 .thumb_func 341 .weak SysTick_Handler 342 .type SysTick_Handler, %function 343SysTick_Handler: 344 ldr r0,=SysTick_Handler 345 bx r0 346 .size SysTick_Handler, . - SysTick_Handler 347 348 .align 1 349 .thumb_func 350 .weak WDT_BOD_IRQHandler 351 .type WDT_BOD_IRQHandler, %function 352WDT_BOD_IRQHandler: 353 ldr r0,=WDT_BOD_DriverIRQHandler 354 bx r0 355 .size WDT_BOD_IRQHandler, . - WDT_BOD_IRQHandler 356 357 358 .align 1 359 .thumb_func 360 .weak DMA0_IRQHandler 361 .type DMA0_IRQHandler, %function 362DMA0_IRQHandler: 363 ldr r0,=DMA0_DriverIRQHandler 364 bx r0 365 .size DMA0_IRQHandler, . - DMA0_IRQHandler 366 367 .align 1 368 .thumb_func 369 .weak GINT0_IRQHandler 370 .type GINT0_IRQHandler, %function 371GINT0_IRQHandler: 372 ldr r0,=GINT0_DriverIRQHandler 373 bx r0 374 .size GINT0_IRQHandler, . - GINT0_IRQHandler 375 376 .align 1 377 .thumb_func 378 .weak GINT1_IRQHandler 379 .type GINT1_IRQHandler, %function 380GINT1_IRQHandler: 381 ldr r0,=GINT1_DriverIRQHandler 382 bx r0 383 .size GINT1_IRQHandler, . - GINT1_IRQHandler 384 385 .align 1 386 .thumb_func 387 .weak PIN_INT0_IRQHandler 388 .type PIN_INT0_IRQHandler, %function 389PIN_INT0_IRQHandler: 390 ldr r0,=PIN_INT0_DriverIRQHandler 391 bx r0 392 .size PIN_INT0_IRQHandler, . - PIN_INT0_IRQHandler 393 394 .align 1 395 .thumb_func 396 .weak PIN_INT1_IRQHandler 397 .type PIN_INT1_IRQHandler, %function 398PIN_INT1_IRQHandler: 399 ldr r0,=PIN_INT1_DriverIRQHandler 400 bx r0 401 .size PIN_INT1_IRQHandler, . - PIN_INT1_IRQHandler 402 403 .align 1 404 .thumb_func 405 .weak PIN_INT2_IRQHandler 406 .type PIN_INT2_IRQHandler, %function 407PIN_INT2_IRQHandler: 408 ldr r0,=PIN_INT2_DriverIRQHandler 409 bx r0 410 .size PIN_INT2_IRQHandler, . - PIN_INT2_IRQHandler 411 412 .align 1 413 .thumb_func 414 .weak PIN_INT3_IRQHandler 415 .type PIN_INT3_IRQHandler, %function 416PIN_INT3_IRQHandler: 417 ldr r0,=PIN_INT3_DriverIRQHandler 418 bx r0 419 .size PIN_INT3_IRQHandler, . - PIN_INT3_IRQHandler 420 421 .align 1 422 .thumb_func 423 .weak UTICK0_IRQHandler 424 .type UTICK0_IRQHandler, %function 425UTICK0_IRQHandler: 426 ldr r0,=UTICK0_DriverIRQHandler 427 bx r0 428 .size UTICK0_IRQHandler, . - UTICK0_IRQHandler 429 430 .align 1 431 .thumb_func 432 .weak MRT0_IRQHandler 433 .type MRT0_IRQHandler, %function 434MRT0_IRQHandler: 435 ldr r0,=MRT0_DriverIRQHandler 436 bx r0 437 .size MRT0_IRQHandler, . - MRT0_IRQHandler 438 439 .align 1 440 .thumb_func 441 .weak CTIMER0_IRQHandler 442 .type CTIMER0_IRQHandler, %function 443CTIMER0_IRQHandler: 444 ldr r0,=CTIMER0_DriverIRQHandler 445 bx r0 446 .size CTIMER0_IRQHandler, . - CTIMER0_IRQHandler 447 448 .align 1 449 .thumb_func 450 .weak CTIMER1_IRQHandler 451 .type CTIMER1_IRQHandler, %function 452CTIMER1_IRQHandler: 453 ldr r0,=CTIMER1_DriverIRQHandler 454 bx r0 455 .size CTIMER1_IRQHandler, . - CTIMER1_IRQHandler 456 457 458 .align 1 459 .thumb_func 460 .weak SCT0_IRQHandler 461 .type SCT0_IRQHandler, %function 462SCT0_IRQHandler: 463 ldr r0,=SCT0_DriverIRQHandler 464 bx r0 465 .size SCT0_IRQHandler, . - SCT0_IRQHandler 466 467 .align 1 468 .thumb_func 469 .weak CTIMER3_IRQHandler 470 .type CTIMER3_IRQHandler, %function 471CTIMER3_IRQHandler: 472 ldr r0,=CTIMER3_DriverIRQHandler 473 bx r0 474 .size CTIMER3_IRQHandler, . - CTIMER3_IRQHandler 475 476 .align 1 477 .thumb_func 478 .weak FLEXCOMM0_IRQHandler 479 .type FLEXCOMM0_IRQHandler, %function 480FLEXCOMM0_IRQHandler: 481 ldr r0,=FLEXCOMM0_DriverIRQHandler 482 bx r0 483 .size FLEXCOMM0_IRQHandler, . - FLEXCOMM0_IRQHandler 484 485 .align 1 486 .thumb_func 487 .weak FLEXCOMM1_IRQHandler 488 .type FLEXCOMM1_IRQHandler, %function 489FLEXCOMM1_IRQHandler: 490 ldr r0,=FLEXCOMM1_DriverIRQHandler 491 bx r0 492 .size FLEXCOMM1_IRQHandler, . - FLEXCOMM1_IRQHandler 493 494 .align 1 495 .thumb_func 496 .weak FLEXCOMM2_IRQHandler 497 .type FLEXCOMM2_IRQHandler, %function 498FLEXCOMM2_IRQHandler: 499 ldr r0,=FLEXCOMM2_DriverIRQHandler 500 bx r0 501 .size FLEXCOMM2_IRQHandler, . - FLEXCOMM2_IRQHandler 502 503 .align 1 504 .thumb_func 505 .weak FLEXCOMM3_IRQHandler 506 .type FLEXCOMM3_IRQHandler, %function 507FLEXCOMM3_IRQHandler: 508 ldr r0,=FLEXCOMM3_DriverIRQHandler 509 bx r0 510 .size FLEXCOMM3_IRQHandler, . - FLEXCOMM3_IRQHandler 511 512 .align 1 513 .thumb_func 514 .weak FLEXCOMM4_IRQHandler 515 .type FLEXCOMM4_IRQHandler, %function 516FLEXCOMM4_IRQHandler: 517 ldr r0,=FLEXCOMM4_DriverIRQHandler 518 bx r0 519 .size FLEXCOMM4_IRQHandler, . - FLEXCOMM4_IRQHandler 520 521 .align 1 522 .thumb_func 523 .weak FLEXCOMM5_IRQHandler 524 .type FLEXCOMM5_IRQHandler, %function 525FLEXCOMM5_IRQHandler: 526 ldr r0,=FLEXCOMM5_DriverIRQHandler 527 bx r0 528 .size FLEXCOMM5_IRQHandler, . - FLEXCOMM5_IRQHandler 529 530 .align 1 531 .thumb_func 532 .weak FLEXCOMM6_IRQHandler 533 .type FLEXCOMM6_IRQHandler, %function 534FLEXCOMM6_IRQHandler: 535 ldr r0,=FLEXCOMM6_DriverIRQHandler 536 bx r0 537 .size FLEXCOMM6_IRQHandler, . - FLEXCOMM6_IRQHandler 538 539 .align 1 540 .thumb_func 541 .weak FLEXCOMM7_IRQHandler 542 .type FLEXCOMM7_IRQHandler, %function 543FLEXCOMM7_IRQHandler: 544 ldr r0,=FLEXCOMM7_DriverIRQHandler 545 bx r0 546 .size FLEXCOMM7_IRQHandler, . - FLEXCOMM7_IRQHandler 547 548 549 .align 1 550 .thumb_func 551 .weak ADC0_SEQA_IRQHandler 552 .type ADC0_SEQA_IRQHandler, %function 553ADC0_SEQA_IRQHandler: 554 ldr r0,=ADC0_SEQA_DriverIRQHandler 555 bx r0 556 .size ADC0_SEQA_IRQHandler, . - ADC0_SEQA_IRQHandler 557 558 .align 1 559 .thumb_func 560 .weak ADC0_SEQB_IRQHandler 561 .type ADC0_SEQB_IRQHandler, %function 562ADC0_SEQB_IRQHandler: 563 ldr r0,=ADC0_SEQB_DriverIRQHandler 564 bx r0 565 .size ADC0_SEQB_IRQHandler, . - ADC0_SEQB_IRQHandler 566 567 .align 1 568 .thumb_func 569 .weak ADC0_THCMP_IRQHandler 570 .type ADC0_THCMP_IRQHandler, %function 571ADC0_THCMP_IRQHandler: 572 ldr r0,=ADC0_THCMP_DriverIRQHandler 573 bx r0 574 .size ADC0_THCMP_IRQHandler, . - ADC0_THCMP_IRQHandler 575 576 .align 1 577 .thumb_func 578 .weak DMIC0_IRQHandler 579 .type DMIC0_IRQHandler, %function 580DMIC0_IRQHandler: 581 ldr r0,=DMIC0_DriverIRQHandler 582 bx r0 583 .size DMIC0_IRQHandler, . - DMIC0_IRQHandler 584 585 .align 1 586 .thumb_func 587 .weak HWVAD0_IRQHandler 588 .type HWVAD0_IRQHandler, %function 589HWVAD0_IRQHandler: 590 ldr r0,=HWVAD0_DriverIRQHandler 591 bx r0 592 .size HWVAD0_IRQHandler, . - HWVAD0_IRQHandler 593 594 .align 1 595 .thumb_func 596 .weak USB0_NEEDCLK_IRQHandler 597 .type USB0_NEEDCLK_IRQHandler, %function 598USB0_NEEDCLK_IRQHandler: 599 ldr r0,=USB0_NEEDCLK_DriverIRQHandler 600 bx r0 601 .size USB0_NEEDCLK_IRQHandler, . - USB0_NEEDCLK_IRQHandler 602 603 .align 1 604 .thumb_func 605 .weak USB0_IRQHandler 606 .type USB0_IRQHandler, %function 607USB0_IRQHandler: 608 ldr r0,=USB0_DriverIRQHandler 609 bx r0 610 .size USB0_IRQHandler, . - USB0_IRQHandler 611 612 .align 1 613 .thumb_func 614 .weak RTC_IRQHandler 615 .type RTC_IRQHandler, %function 616RTC_IRQHandler: 617 ldr r0,=RTC_DriverIRQHandler 618 bx r0 619 .size RTC_IRQHandler, . - RTC_IRQHandler 620 621 .align 1 622 .thumb_func 623 .weak IOH_IRQHandler 624 .type IOH_IRQHandler, %function 625IOH_IRQHandler: 626 ldr r0,=IOH_DriverIRQHandler 627 bx r0 628 .size IOH_IRQHandler, . - IOH_IRQHandler 629 630 .align 1 631 .thumb_func 632 .weak MAILBOX_IRQHandler 633 .type MAILBOX_IRQHandler, %function 634MAILBOX_IRQHandler: 635 ldr r0,=MAILBOX_DriverIRQHandler 636 bx r0 637 .size MAILBOX_IRQHandler, . - MAILBOX_IRQHandler 638 639 640 .align 1 641 .thumb_func 642 .weak PIN_INT4_IRQHandler 643 .type PIN_INT4_IRQHandler, %function 644PIN_INT4_IRQHandler: 645 ldr r0,=PIN_INT4_DriverIRQHandler 646 bx r0 647 .size PIN_INT4_IRQHandler, . - PIN_INT4_IRQHandler 648 649 .align 1 650 .thumb_func 651 .weak PIN_INT5_IRQHandler 652 .type PIN_INT5_IRQHandler, %function 653PIN_INT5_IRQHandler: 654 ldr r0,=PIN_INT5_DriverIRQHandler 655 bx r0 656 .size PIN_INT5_IRQHandler, . - PIN_INT5_IRQHandler 657 658 .align 1 659 .thumb_func 660 .weak PIN_INT6_IRQHandler 661 .type PIN_INT6_IRQHandler, %function 662PIN_INT6_IRQHandler: 663 ldr r0,=PIN_INT6_DriverIRQHandler 664 bx r0 665 .size PIN_INT6_IRQHandler, . - PIN_INT6_IRQHandler 666 667 .align 1 668 .thumb_func 669 .weak PIN_INT7_IRQHandler 670 .type PIN_INT7_IRQHandler, %function 671PIN_INT7_IRQHandler: 672 ldr r0,=PIN_INT7_DriverIRQHandler 673 bx r0 674 .size PIN_INT7_IRQHandler, . - PIN_INT7_IRQHandler 675 676 677 .align 1 678 .thumb_func 679 .weak CTIMER2_IRQHandler 680 .type CTIMER2_IRQHandler, %function 681CTIMER2_IRQHandler: 682 ldr r0,=CTIMER2_DriverIRQHandler 683 bx r0 684 .size CTIMER2_IRQHandler, . - CTIMER2_IRQHandler 685 686 .align 1 687 .thumb_func 688 .weak CTIMER4_IRQHandler 689 .type CTIMER4_IRQHandler, %function 690CTIMER4_IRQHandler: 691 ldr r0,=CTIMER4_DriverIRQHandler 692 bx r0 693 .size CTIMER4_IRQHandler, . - CTIMER4_IRQHandler 694 695 696 .align 1 697 .thumb_func 698 .weak SPIFI0_IRQHandler 699 .type SPIFI0_IRQHandler, %function 700SPIFI0_IRQHandler: 701 ldr r0,=SPIFI0_DriverIRQHandler 702 bx r0 703 .size SPIFI0_IRQHandler, . - SPIFI0_IRQHandler 704/* Macro to define default handlers. Default handler 705 * will be weak symbol and just dead loops. They can be 706 * overwritten by other handlers */ 707 .macro def_irq_handler handler_name 708 .weak \handler_name 709 .set \handler_name, DefaultISR 710 .endm 711 712/* Exception Handlers */ 713 def_irq_handler WDT_BOD_DriverIRQHandler /* Windowed watchdog timer, Brownout detect */ 714 def_irq_handler DMA0_DriverIRQHandler /* DMA controller */ 715 def_irq_handler GINT0_DriverIRQHandler /* GPIO group 0 */ 716 def_irq_handler GINT1_DriverIRQHandler /* GPIO group 1 */ 717 def_irq_handler PIN_INT0_DriverIRQHandler /* Pin interrupt 0 or pattern match engine slice 0 */ 718 def_irq_handler PIN_INT1_DriverIRQHandler /* Pin interrupt 1or pattern match engine slice 1 */ 719 def_irq_handler PIN_INT2_DriverIRQHandler /* Pin interrupt 2 or pattern match engine slice 2 */ 720 def_irq_handler PIN_INT3_DriverIRQHandler /* Pin interrupt 3 or pattern match engine slice 3 */ 721 def_irq_handler UTICK0_DriverIRQHandler /* Micro-tick Timer */ 722 def_irq_handler MRT0_DriverIRQHandler /* Multi-rate timer */ 723 def_irq_handler CTIMER0_DriverIRQHandler /* Standard counter/timer CTIMER0 */ 724 def_irq_handler CTIMER1_DriverIRQHandler /* Standard counter/timer CTIMER1 */ 725 def_irq_handler SCT0_DriverIRQHandler /* SCTimer/PWM */ 726 def_irq_handler CTIMER3_DriverIRQHandler /* Standard counter/timer CTIMER3 */ 727 def_irq_handler FLEXCOMM0_DriverIRQHandler /* Flexcomm Interface 0 (USART, SPI, I2C) */ 728 def_irq_handler FLEXCOMM1_DriverIRQHandler /* Flexcomm Interface 1 (USART, SPI, I2C) */ 729 def_irq_handler FLEXCOMM2_DriverIRQHandler /* Flexcomm Interface 2 (USART, SPI, I2C) */ 730 def_irq_handler FLEXCOMM3_DriverIRQHandler /* Flexcomm Interface 3 (USART, SPI, I2C) */ 731 def_irq_handler FLEXCOMM4_DriverIRQHandler /* Flexcomm Interface 4 (USART, SPI, I2C) */ 732 def_irq_handler FLEXCOMM5_DriverIRQHandler /* Flexcomm Interface 5 (USART, SPI, I2C) */ 733 def_irq_handler FLEXCOMM6_DriverIRQHandler /* Flexcomm Interface 6 (USART, SPI, I2C, I2S) */ 734 def_irq_handler FLEXCOMM7_DriverIRQHandler /* Flexcomm Interface 7 (USART, SPI, I2C, I2S) */ 735 def_irq_handler ADC0_SEQA_DriverIRQHandler /* ADC0 sequence A completion. */ 736 def_irq_handler ADC0_SEQB_DriverIRQHandler /* ADC0 sequence B completion. */ 737 def_irq_handler ADC0_THCMP_DriverIRQHandler /* ADC0 threshold compare and error. */ 738 def_irq_handler DMIC0_DriverIRQHandler /* Digital microphone and DMIC subsystem */ 739 def_irq_handler HWVAD0_DriverIRQHandler /* Hardware Voice Activity Detector */ 740 def_irq_handler USB0_NEEDCLK_DriverIRQHandler /* USB Activity Wake-up Interrupt */ 741 def_irq_handler USB0_DriverIRQHandler /* USB device */ 742 def_irq_handler RTC_DriverIRQHandler /* RTC alarm and wake-up interrupts */ 743 def_irq_handler IOH_DriverIRQHandler /* IOH */ 744 def_irq_handler MAILBOX_DriverIRQHandler /* Mailbox interrupt (present on selected devices) */ 745 def_irq_handler PIN_INT4_DriverIRQHandler /* Pin interrupt 4 or pattern match engine slice 4 int */ 746 def_irq_handler PIN_INT5_DriverIRQHandler /* Pin interrupt 5 or pattern match engine slice 5 int */ 747 def_irq_handler PIN_INT6_DriverIRQHandler /* Pin interrupt 6 or pattern match engine slice 6 int */ 748 def_irq_handler PIN_INT7_DriverIRQHandler /* Pin interrupt 7 or pattern match engine slice 7 int */ 749 def_irq_handler CTIMER2_DriverIRQHandler /* Standard counter/timer CTIMER2 */ 750 def_irq_handler CTIMER4_DriverIRQHandler /* Standard counter/timer CTIMER4 */ 751 def_irq_handler SPIFI0_DriverIRQHandler /* SPI flash interface */ 752 753 .end 754
