1/**
2 * @file
3 * @brief System/hardware module for nxp_lpc54114 platform
4 *
5 * This module provides routines to initialize and support board-level
6 * hardware for the nxp_lpc54114 platform.
7 */
8
9/* ---------------------------------------------------------------------------------------*/
10/*  @file:    startup_LPC54114_cm4.S                                                      */
11/*  @purpose: CMSIS Cortex-M4 Core Device Startup File                                    */
12/*            LPC54114_cm4                                                                */
13/*  @version: 1.0                                                                         */
14/*  @date:    2016-11-2                                                                   */
15/*  @build:   b161214                                                                     */
16/* ---------------------------------------------------------------------------------------*/
17/*                                                                                        */
18/* Copyright 1997-2016 Freescale Semiconductor, Inc.                                      */
19/* Copyright 2016-2017 NXP                                                                */
20/* Redistribution and use in source and binary forms, with or without modification,       */
21/* are permitted provided that the following conditions are met:                          */
22/*                                                                                        */
23/* 1. Redistributions of source code must retain the above copyright notice, this list    */
24/*   of conditions and the following disclaimer.                                          */
25/*                                                                                        */
26/* 2. Redistributions in binary form must reproduce the above copyright notice, this      */
27/*   list of conditions and the following disclaimer in the documentation and/or          */
28/*   other materials provided with the distribution.                                      */
29/*                                                                                        */
30/* 3. Neither the name of the copyright holder nor the names of its                       */
31/*   contributors may be used to endorse or promote products derived from this            */
32/*   software without specific prior written permission.                                  */
33/*                                                                                        */
34/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND        */
35/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED          */
36/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE                 */
37/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR       */
38/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES         */
39/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;           */
40/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON         */
41/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT                */
42/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS          */
43/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
44/*****************************************************************************/
45/* Version: GCC for ARM Embedded Processors                                  */
46/*****************************************************************************/
47
48#include <toolchain.h>
49#include <linker/sections.h>
50#include <arch/cpu.h>
51
52#if defined(CONFIG_PLATFORM_SPECIFIC_INIT) && defined(CONFIG_SOC_LPC54114_M4)
53
54    .syntax unified
55    .arch armv7-m
56    .text
57    .thumb
58
59rel_vals:
60    .long   0xE000ED00   /* cpu_id */
61    .long   0x40000800   /* cpu_ctrl */
62    .long   0x40000804   /* coproc_boot */
63    .long   0x40000808   /* coproc_stack */
64    .short  0x0FFF
65    .short  0x0C24
66
67GTEXT(z_platform_init)
68SECTION_FUNC(TEXT,z_platform_init)
69
70/* Both the M0+ and M4 core come via this shared startup code,
71 * but the M0+ and M4 core have different vector tables.
72 * Determine if the core executing this code is the master or
73 * the slave and handle each core state individually. */
74
75shared_boot_entry:
76    ldr     r6, =rel_vals
77
78    /* Flag for slave core (0) */
79    movs    r4, 0
80    movs    r5, 1
81
82    /* Determine which core (M0+ or M4) this code is running on */
83    /* r2 = (((*cpu_id) >> 4) & 0xFFF); (M4 core == 0xC24) */
84get_current_core_id:
85    ldr     r0, [r6, #0]
86    ldr     r1, [r0]                        /* r1 = CPU ID status */
87    lsrs    r1, r1, #4                      /* Right justify 12 CPU ID bits */
88    ldrh    r2, [r6, #16]                   /* Mask for CPU ID bits */
89    ands    r2, r1, r2                      /* r2 = ARM COrtex CPU ID */
90    ldrh    r3, [r6, #18]                   /* Mask for CPU ID bits */
91    cmp     r3, r2                          /* Core ID matches M4 identifier */
92    bne     get_master_status
93    mov     r4, r5                          /* Set flag for master core (1) */
94
95    /* Determine if M4 core is the master or slave */
96    /* r3 = ((*cpu_ctrl) & 1); (0 == m0+, 1 == M4) */
97get_master_status:
98    ldr     r0, [r6, #4]
99    ldr     r3, [r0]                        /* r3 = SYSCON co-processor CPU control status */
100
101    ands    r3, r3, r5                      /* r3 = (Bit 0: 1 = M4 is master, 0 = M4 is slave) */
102
103    /* Select boot based on selected master core and core ID */
104
105select_boot:
106    eors    r3, r3, r4                      /* r4 = (Bit 0: 0 = master, 1 = slave) */
107
108    bne     slave_boot
109    b       normal_boot
110
111    /* Slave boot */
112slave_boot:
113    ldr     r0, [r6, #8]
114    ldr     r2, [r0]                        /* r1 = SYSCON co-processor boot address */
115
116    cmp     r2, #0                          /* Slave boot address = 0 (not set up)? */
117
118    beq     cpu_sleep
119    ldr     r0, [r6, #12]
120    ldr     r1, [r0]                        /* r5 = SYSCON co-processor stack address */
121
122    mov     sp, r1                          /* Update slave CPU stack pointer */
123
124    /* Be sure to update VTOR for the slave MCU to point to the */
125    /* slave vector table in boot memory */
126    bx      r2                              /* Jump to slave boot address */
127
128    /* Slave isn't yet setup for system boot from the master */
129    /* so sleep until the master sets it up and then reboots it */
130cpu_sleep:
131    mov     sp, r5                          /* Will force exception if something happens */
132cpu_sleep_wfi:
133    wfi                                     /* Sleep forever until master reboots */
134    b       cpu_sleep_wfi
135normal_boot:
136    bx      lr
137
138#endif
139