1/*
2 * Copyright (c) 2018 - 2020 Antmicro <www.antmicro.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/ {
8	#address-cells = <1>;
9	#size-cells = <1>;
10	compatible = "litex,vexriscv", "litex-dev";
11	model = "litex,vexriscv";
12
13
14	chosen {
15		zephyr,entropy = &prbs0;
16	};
17
18	cpus {
19		#address-cells = <1>;
20		#size-cells = <0>;
21		cpu@0 {
22			clock-frequency = <100000000>;
23			compatible = "litex,vexriscv-standard", "riscv";
24			device_type = "cpu";
25			reg = <0>;
26			riscv,isa = "rv32ima_zicsr_zifencei";
27			status = "okay";
28		};
29	};
30	soc {
31		#address-cells = <1>;
32		#size-cells = <1>;
33		compatible = "litex,vexriscv";
34		ranges;
35		intc0: interrupt-controller@bc0 {
36			compatible = "vexriscv-intc0";
37			#address-cells = <0>;
38			#interrupt-cells = <2>;
39			interrupt-controller;
40			reg = <0xbc0 0x4 0xfc0 0x4>;
41			reg-names = "irq_mask", "irq_pending";
42			riscv,max-priority = <7>;
43		};
44		uart0: serial@e0001800 {
45			compatible = "litex,uart0";
46			interrupt-parent = <&intc0>;
47			interrupts = <2 10>;
48			reg = <0xe0001800 0x4
49				0xe0001804 0x4
50				0xe0001808 0x4
51				0xe000180c 0x4
52				0xe0001810 0x4
53				0xe0001814 0x4
54				0xe0001818 0x4
55				0xe000181c 0x4>;
56			reg-names =
57				"rxtx",
58				"txfull",
59				"rxempty",
60				"ev_status",
61				"ev_pending",
62				"ev_enable",
63				"txempty",
64				"rxfull";
65			status = "disabled";
66		};
67		spi0: spi@e0002000 {
68			compatible = "litex,spi";
69			reg = <0xe0002000 0x4
70				0xe0002004 0x4
71				0xe0002008 0x4
72				0xe000200c 0x4
73				0xe0002010 0x4
74				0xe0002014 0x4>;
75			reg-names = "control",
76				"status",
77				"mosi",
78				"miso",
79				"cs",
80				"loopback";
81			status = "disabled";
82			#address-cells = <1>;
83			#size-cells = <0>;
84		};
85		timer0: timer@e0002800 {
86			compatible = "litex,timer0";
87			interrupt-parent = <&intc0>;
88			interrupts = <1 0>;
89			reg = <0xe0002800 0x4
90				0xe0002804 0x4
91				0xe0002808 0x4
92				0xe000280c 0x4
93				0xe0002810 0x4
94				0xe0002814 0x4
95				0xe0002818 0x4
96				0xe000281c 0x4
97				0xe0002820 0x4
98				0xe0002824 0x8>;
99			reg-names =
100				"load",
101				"reload",
102				"en",
103				"update_value",
104				"value",
105				"ev_status",
106				"ev_pending",
107				"ev_enable",
108				"uptime_latch",
109				"uptime_cycles";
110			status = "disabled";
111		};
112		eth0: ethernet@e0009800 {
113			compatible = "litex,eth0";
114			interrupt-parent = <&intc0>;
115			interrupts = <3 0>;
116			reg = <0xe0009800 0x4
117				0xe0009804 0x4
118				0xe0009808 0x4
119				0xe000980c 0x4
120				0xe0009810 0x4
121				0xe0009814 0x4
122				0xe0009818 0x4
123				0xe000981c 0x4
124				0xe0009820 0x4
125				0xe0009824 0x4
126				0xe0009828 0x4
127				0xe000982c 0x4
128				0xe0009830 0x4
129				0xe0009834 0x4
130				0xb0000000 0x2000>;
131			local-mac-address = [10 e2 d5 00 00 02];
132			reg-names = "rx_slot",
133				"rx_length",
134				"rx_errors",
135				"rx_ev_status",
136				"rx_ev_pending",
137				"rx_ev_enable",
138				"tx_start",
139				"tx_ready",
140				"tx_level",
141				"tx_slot",
142				"tx_length",
143				"tx_ev_status",
144				"tx_ev_pending",
145				"tx_ev_enable",
146				"buffers";
147			status = "disabled";
148		};
149		dna0: dna@e0003800 {
150			compatible = "litex,dna0";
151			/* DNA data is 57-bits long,
152			so it requires 8 bytes.
153			In LiteX each 32-bit register holds
154			only a single byte of meaningful data,
155			hence 8 registers. */
156			reg = <0xe0003800 0x20>;
157			reg-names = "mem";
158			status = "disabled";
159		};
160		i2c0: i2c@e0005000 {
161			compatible = "litex,i2c";
162			reg = <0xe0005000 0x4 0xe0005004 0x4>;
163			reg-names = "write", "read";
164			#address-cells = <1>;
165			#size-cells = <0>;
166			status = "disabled";
167		};
168		gpio_out: gpio@e0005800 {
169			compatible = "litex,gpio";
170			reg = <0xe0005800 0x4>;
171			reg-names = "control";
172			ngpios = <4>;
173			port-is-output;
174			status = "disabled";
175			gpio-controller;
176			#gpio-cells = <2>;
177		};
178		gpio_in: gpio@e0006000 {
179			compatible = "litex,gpio";
180			reg = <0xe0006000 0x4
181				0xe0006004 0x4
182				0xe0006008 0x4
183				0xe0006010 0x4
184				0xe0006014 0x4>;
185			interrupt-parent = <&intc0>;
186			interrupts = <4 2>;
187			reg-names = "base",
188				"irq_mode",
189				"irq_edge",
190				"irq_pend",
191				"irq_en";
192			ngpios = <4>;
193			status = "disabled";
194			gpio-controller;
195			#gpio-cells = <2>;
196		};
197		prbs0: prbs@e0006800 {
198			compatible = "litex,prbs";
199			reg = <0xe0006800 0x4>;
200			reg-names = "status";
201			status = "disabled";
202		};
203		pwm0: pwm@e0007000 {
204			compatible = "litex,pwm";
205			reg = <0xe0007000 0x4 0xe0007004 0x10 0xe0007014 0x10>;
206			reg-names = "enable", "width", "period";
207			status = "disabled";
208			#pwm-cells = <2>;
209		};
210		i2s_rx: i2s_rx@e000a800 {
211			compatible = "litex,i2s";
212			reg = <0xe000a800 0x4
213				0xe000a804 0x4
214				0xe000a808 0x4
215				0xe000a80c 0x4
216				0xe000a810 0x4
217				0xe000a814 0x4
218				0xb1000000 0x40000>;
219			interrupt-parent = <&intc0>;
220			interrupts = <6 2>;
221			#address-cells = <1>;
222			#size-cells = <0>;
223			reg-names = "ev_status",
224				"ev_pending",
225				"ev_enable",
226				"rx_ctl",
227				"rx_stat",
228				"rx_conf",
229				"fifo";
230			fifo_depth = <256>;
231			status = "disabled";
232		};
233		i2s_tx: i2s_tx@e000b000 {
234			compatible = "litex,i2s";
235			reg = <0xe000b000 0x4
236				0xe000b004 0x4
237				0xe000b008 0x4
238				0xe000b00c 0x4
239				0xe000b010 0x4
240				0xe000b014 0x4
241				0xb2000000 0x40000>;
242			interrupt-parent = <&intc0>;
243			interrupts = <7 2>;
244			#address-cells = <1>;
245			#size-cells = <0>;
246			reg-names = "ev_status",
247				"ev_pending",
248				"ev_enable",
249				"tx_ctl",
250				"tx_stat",
251				"tx_conf",
252				"fifo";
253			fifo_depth = <256>;
254			status = "disabled";
255		};
256		clock-outputs {
257			#address-cells = <1>;
258			#size-cells = <0>;
259			clk0: clock-controller@0 {
260				#clock-cells = <1>;
261				reg = <0>;
262				compatible = "litex,clkout";
263				clock-output-names = "CLK_0";
264				litex,clock-frequency = <11289600>;
265				litex,clock-phase = <0>;
266				litex,clock-duty-num = <1>;
267				litex,clock-duty-den = <2>;
268				litex,clock-margin = <1>;
269				litex,clock-margin-exp = <2>;
270				status = "disabled";
271			};
272			clk1: clock-controller@1 {
273				#clock-cells = <1>;
274				reg = <1>;
275				compatible = "litex,clkout";
276				clock-output-names = "CLK_1";
277				litex,clock-frequency = <22579200>;
278				litex,clock-phase = <0>;
279				litex,clock-duty-num = <1>;
280				litex,clock-duty-den = <2>;
281				litex,clock-margin = <1>;
282				litex,clock-margin-exp = <2>;
283				status = "disabled";
284			};
285		};
286		clock0: clock@e0004800 {
287			compatible = "litex,clk";
288			reg = <0xe0004800 0x4
289				0xe0004804 0x4
290				0xe0004808 0x4
291				0xe000480c 0x4
292				0xe0004810 0x4
293				0xe0004814 0x4
294				0xe0004818 0x4
295				0xe000481c 0x4>;
296			reg-names = "drp_reset",
297				"drp_locked",
298				"drp_read",
299				"drp_write",
300				"drp_drdy",
301				"drp_adr",
302				"drp_dat_w",
303				"drp_dat_r";
304			#clock-cells = <1>;
305			clocks = <&clk0 0>, <&clk1 1>;
306			clock-output-names = "CLK_0", "CLK_1";
307			litex,lock-timeout = <10>;
308			litex,drdy-timeout = <10>;
309			litex,sys-clock-frequency = <100000000>;
310			litex,divclk-divide-min = <1>;
311			litex,divclk-divide-max = <107>;
312			litex,clkfbout-mult-min = <2>;
313			litex,clkfbout-mult-max = <65>;
314			litex,vco-freq-min = <600000000>;
315			litex,vco-freq-max = <1200000000>;
316			litex,clkout-divide-min = <1>;
317			litex,clkout-divide-max = <126>;
318			litex,vco-margin = <0>;
319			status = "disabled";
320		};
321	};
322};
323