1/* 2 * Copyright (c) 2018 - 2020 Antmicro <www.antmicro.com> 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7/ { 8 #address-cells = <1>; 9 #size-cells = <1>; 10 compatible = "litex,vexriscv", "litex-dev"; 11 model = "litex,vexriscv"; 12 13 14 chosen { 15 zephyr,entropy = &prbs0; 16 }; 17 18 cpus { 19 #address-cells = <1>; 20 #size-cells = <0>; 21 cpu@0 { 22 clock-frequency = <100000000>; 23 compatible = "riscv"; 24 device_type = "cpu"; 25 reg = <0>; 26 riscv,isa = "rv32imac"; 27 status = "okay"; 28 timebase-frequency = <32768>; 29 }; 30 }; 31 soc { 32 #address-cells = <1>; 33 #size-cells = <1>; 34 compatible = "litex,vexriscv"; 35 ranges; 36 intc0: interrupt-controller@bc0 { 37 #interrupt-cells = <2>; 38 compatible = "vexriscv-intc0"; 39 interrupt-controller; 40 reg = <0xbc0 0x4 0xfc0 0x4>; 41 reg-names = "irq_mask", "irq_pending"; 42 riscv,max-priority = <7>; 43 }; 44 uart0: serial@e0001800 { 45 compatible = "litex,uart0"; 46 interrupt-parent = <&intc0>; 47 interrupts = <2 10>; 48 reg = <0xe0001800 0x18>; 49 reg-names = "control"; 50 label = "uart0"; 51 status = "disabled"; 52 }; 53 spi0: spi@e0002000 { 54 compatible = "litex,spi"; 55 interrupt-parent = <&intc0>; 56 interrupts = <5 0>; 57 reg = <0xe0002000 0x34>; 58 reg-names = "control"; 59 label = "spi0"; 60 status = "disabled"; 61 #address-cells = <1>; 62 #size-cells = <0>; 63 }; 64 timer0: timer@e0002800 { 65 compatible = "litex,timer0"; 66 interrupt-parent = <&intc0>; 67 interrupts = <1 0>; 68 reg = <0xe0002800 0x40>; 69 reg-names = "control"; 70 label = "timer0"; 71 status = "disabled"; 72 }; 73 eth0: ethernet@e0009800 { 74 compatible = "litex,eth0"; 75 interrupt-parent = <&intc0>; 76 interrupts = <3 0>; 77 reg = <0xe0009800 0x6b 0xb0000000 0x2000>; 78 local-mac-address = [10 e2 d5 00 00 02]; 79 reg-names = "control", "buffers"; 80 label = "eth0"; 81 status = "disabled"; 82 }; 83 dna0: dna@e0003800 { 84 compatible = "litex,dna0"; 85 /* DNA data is 57-bits long, 86 so it requires 8 bytes. 87 In LiteX each 32-bit register holds 88 only a single byte of meaningful data, 89 hence 8 registers. */ 90 reg = <0xe0003800 0x20>; 91 reg-names = "mem"; 92 label = "dna0"; 93 status = "disabled"; 94 }; 95 i2c0: i2c@e0005000 { 96 compatible = "litex,i2c"; 97 reg = <0xe0005000 0x4 0xe0005004 0x4>; 98 reg-names = "write", "read"; 99 label = "i2c0"; 100 #address-cells = <1>; 101 #size-cells = <0>; 102 status = "disabled"; 103 }; 104 gpio_out: gpio@e0005800 { 105 compatible = "litex,gpio"; 106 reg = <0xe0005800 0x4>; 107 reg-names = "control"; 108 ngpios = <4>; 109 label = "gpio_out"; 110 port-is-output; 111 status = "disabled"; 112 gpio-controller; 113 #gpio-cells = <2>; 114 }; 115 gpio_in: gpio@e0006000 { 116 compatible = "litex,gpio"; 117 reg = <0xe0006000 0x4 118 0xe0006004 0x1 119 0xe0006008 0x1 120 0xe0006010 0x1 121 0xe0006014 0x1>; 122 interrupt-parent = <&intc0>; 123 interrupts = <4 2>; 124 reg-names = "base", 125 "irq_mode", 126 "irq_edge", 127 "irq_pend", 128 "irq_en"; 129 ngpios = <4>; 130 label = "gpio_in"; 131 status = "disabled"; 132 gpio-controller; 133 #gpio-cells = <2>; 134 }; 135 prbs0: prbs@e0006800 { 136 compatible = "litex,prbs"; 137 reg = <0xe0006800 0x4>; 138 reg-names = "status"; 139 label = "prbs0"; 140 status = "disabled"; 141 }; 142 pwm0: pwm@e0007000 { 143 compatible = "litex,pwm"; 144 reg = <0xe0007000 0x4 0xe0007004 0x10 0xe0007014 0x10>; 145 reg-names = "enable", "width", "period"; 146 label = "pwm0"; 147 status = "disabled"; 148 #pwm-cells = <2>; 149 }; 150 i2s_rx: i2s_rx@e000a800 { 151 compatible = "litex,i2s"; 152 reg = <0xe000a800 0x20 0xb1000000 0x40000>; 153 interrupt-parent = <&intc0>; 154 interrupts = <6 2>; 155 #address-cells = <1>; 156 #size-cells = <0>; 157 reg-names = "control", "fifo"; 158 fifo_depth = <256>; 159 label = "i2s_rx"; 160 status = "disabled"; 161 }; 162 i2s_tx: i2s_tx@e000b000 { 163 compatible = "litex,i2s"; 164 reg = <0xe000b000 0x20 0xb2000000 0x40000>; 165 interrupt-parent = <&intc0>; 166 interrupts = <7 2>; 167 #address-cells = <1>; 168 #size-cells = <0>; 169 reg-names = "control", "fifo"; 170 fifo_depth = <256>; 171 label = "i2s_tx"; 172 status = "disabled"; 173 }; 174 clock-outputs { 175 #address-cells = <1>; 176 #size-cells = <0>; 177 clk0: clock-controller@0 { 178 #clock-cells = <1>; 179 reg = <0>; 180 compatible = "litex,clkout"; 181 clock-output-names = "CLK_0"; 182 litex,clock-frequency = <100000000>; 183 litex,clock-phase = <0>; 184 litex,clock-duty-num = <1>; 185 litex,clock-duty-den = <2>; 186 litex,clock-margin = <1>; 187 litex,clock-margin-exp = <2>; 188 status = "disabled"; 189 }; 190 clk1: clock-controller@1 { 191 #clock-cells = <1>; 192 reg = <1>; 193 compatible = "litex,clkout"; 194 clock-output-names = "CLK_1"; 195 litex,clock-frequency = <100000000>; 196 litex,clock-phase = <0>; 197 litex,clock-duty-num = <1>; 198 litex,clock-duty-den = <2>; 199 litex,clock-margin = <1>; 200 litex,clock-margin-exp = <2>; 201 status = "disabled"; 202 }; 203 }; 204 clock0: clock@82005000 { 205 compatible = "litex,clk"; 206 label = "clock0"; 207 reg = <0x82005000 0x1 208 0x82005004 0x1 209 0x82005008 0x1 210 0x8200500c 0x1 211 0x82005010 0x1 212 0x82005014 0x1 213 0x82005018 0x2 214 0x82005020 0x2>; 215 reg-names = "drp_reset", 216 "drp_locked", 217 "drp_read", 218 "drp_write", 219 "drp_drdy", 220 "drp_adr", 221 "drp_dat_w", 222 "drp_dat_r"; 223 #clock-cells = <1>; 224 clocks = <&clk0 0>, <&clk1 1>; 225 clock-output-names = "CLK_0", "CLK_1"; 226 litex,lock-timeout = <10>; 227 litex,drdy-timeout = <10>; 228 litex,sys-clock-frequency = <100000000>; 229 litex,divclk-divide-min = <1>; 230 litex,divclk-divide-max = <107>; 231 litex,clkfbout-mult-min = <2>; 232 litex,clkfbout-mult-max = <65>; 233 litex,vco-freq-min = <600000000>; 234 litex,vco-freq-max = <1200000000>; 235 litex,clkout-divide-min = <1>; 236 litex,clkout-divide-max = <126>; 237 litex,vco-margin = <0>; 238 status = "disabled"; 239 }; 240 }; 241}; 242
