1/*
2 * Copyright (c) 2018 Linaro Limited
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/ {
8	#address-cells = <1>;
9	#size-cells = <1>;
10
11	cpus {
12		#address-cells = <1>;
13		#size-cells = <0>;
14		cpu@0 {
15			clock-frequency = <0>;
16			compatible = "microsemi,miv", "riscv";
17			device_type = "cpu";
18			reg = <0>;
19			riscv,isa = "rv32imac";
20			hlic: interrupt-controller {
21				#interrupt-cells = <1>;
22				compatible = "riscv,cpu-intc";
23				interrupt-controller;
24			};
25		};
26	};
27
28	soc {
29		#address-cells = <1>;
30		#size-cells = <1>;
31		compatible = "microsemi,miv-soc", "simple-bus";
32		ranges;
33
34		flash0: flash@80000000 {
35			compatible = "soc-nv-flash";
36			reg = <0x80000000 0x40000>;
37		};
38
39		sram0: memory@80040000 {
40			compatible = "mmio-sram";
41			reg = <0x80040000 0x40000>;
42		};
43
44		plic: interrupt-controller@40000000 {
45			#interrupt-cells = <2>;
46			compatible = "sifive,plic-1.0.0";
47			interrupt-controller;
48			interrupts-extended = <&hlic 11>;
49			reg = <0x40000000 0x2000
50			       0x40002000 0x1fe000
51			       0x40200000 0x2000000>;
52			reg-names = "prio", "irq_en", "reg";
53			riscv,max-priority = <1>;
54			riscv,ndev = <31>;
55		};
56
57		uart0: uart@70001000 {
58			compatible = "microsemi,coreuart";
59			reg = <0x70001000 0x1000>;
60			label = "uart_0";
61			status = "disabled";
62			current-speed = <0>;
63			clock-frequency = <0>;
64		};
65	};
66};
67