1/* 2 * Copyright (c) 2020 ITE Corporation. All Rights Reserved. 3 * Copyright (c) 2019-2020 Jyunlin Chen <jyunlin.chen@ite.com.tw> 4 * 5 * SPDX-License-Identifier: Apache-2.0 6 */ 7 8#include <mem.h> 9#include <dt-bindings/interrupt-controller/ite-intc.h> 10#include <dt-bindings/i2c/i2c.h> 11#include <dt-bindings/pinctrl/it8xxx2-pinctrl.h> 12#include <dt-bindings/pwm/pwm.h> 13#include <dt-bindings/pwm/it8xxx2_pwm.h> 14#include "it8xxx2-alts-map.dtsi" 15 16/ { 17 #address-cells = <1>; 18 #size-cells = <1>; 19 20 cpus { 21 #address-cells = <1>; 22 #size-cells = <0>; 23 cpu@0 { 24 compatible = "ite,riscv-ite"; 25 device_type = "cpu"; 26 reg = <0>; 27 }; 28 }; 29 30 soc { 31 #address-cells = <1>; 32 #size-cells = <1>; 33 ranges; 34 35 bbram: bb-ram@f02200 { 36 #address-cells = <1>; 37 #size-cells = <1>; 38 compatible = "ite,it8xxx2-bbram"; 39 status = "okay"; 40 reg = <0x00f02200 0xc0>; 41 label = "BBRAM"; 42 }; 43 flashctrl: flash-controller@f01000 { 44 compatible = "ite,it8xxx2-flash-controller"; 45 reg = <0x00f01000 0x100>; 46 label = "fspi"; 47 #address-cells = <1>; 48 #size-cells = <1>; 49 50 flash0: flash@80000000 { 51 compatible = "soc-nv-flash"; 52 reg = <0x80000000 DT_SIZE_M(1)>; 53 erase-block-size = <4096>; 54 write-block-size = <4>; 55 }; 56 }; 57 pinmuxa: pinmux@f01610 { 58 compatible = "ite,it8xxx2-pinmux"; 59 reg = <0x00f01610 0x0008>; 60 label = "PINMUXA"; 61 func3_gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC 62 0xf02032 0xf02032 0xf016f0 0xf016f0>; 63 func3_en_mask = <0 0 0 0 64 0x02 0x02 0x10 0x0C >; 65 func4_gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC 66 NO_FUNC NO_FUNC NO_FUNC NO_FUNC >; 67 func4_en_mask = <0 0 0 0 68 0 0 0 0 >; 69 #pinctrl-cells = <2>; 70 }; 71 pinmuxb: pinmux@f01618 { 72 compatible = "ite,it8xxx2-pinmux"; 73 reg = <0x00f01618 0x0008>; 74 label = "PINMUXB"; 75 func3_gcr = <0xf016f5 0xf016f5 NO_FUNC NO_FUNC 76 NO_FUNC NO_FUNC NO_FUNC 0xf01600>; 77 func3_en_mask = <0x01 0x02 0 0 78 0 0 0 0x02 >; 79 func4_gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC 80 NO_FUNC NO_FUNC NO_FUNC 0xf016f1>; 81 func4_en_mask = <0 0 0 0 82 0 0 0 0x40 >; 83 #pinctrl-cells = <2>; 84 }; 85 pinmuxc: pinmux@f01620 { 86 compatible = "ite,it8xxx2-pinmux"; 87 reg = <0x00f01620 0x0008>; 88 label = "PINMUXC"; 89 func3_gcr = <NO_FUNC NO_FUNC NO_FUNC 0xf016f0 90 NO_FUNC 0xf016f0 NO_FUNC 0xf016f3>; 91 func3_en_mask = <0 0 0 0x10 92 0 0x10 0 0x02 >; 93 func4_gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC 94 NO_FUNC NO_FUNC NO_FUNC 0xf016f6>; 95 func4_en_mask = <0 0 0 0 96 0 0 0 0x80 >; 97 #pinctrl-cells = <2>; 98 }; 99 pinmuxd: pinmux@f01628 { 100 compatible = "ite,it8xxx2-pinmux"; 101 reg = <0x00f01628 0x0008>; 102 label = "PINMUXD"; 103 func3_gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC 104 NO_FUNC 0xf016f0 NO_FUNC NO_FUNC>; 105 func3_en_mask = <0 0 0 0 106 0 0x02 0 0 >; 107 func4_gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC 108 NO_FUNC NO_FUNC NO_FUNC NO_FUNC>; 109 func4_en_mask = <0 0 0 0 110 0 0 0 0 >; 111 #pinctrl-cells = <2>; 112 }; 113 pinmuxe: pinmux@f01630 { 114 compatible = "ite,it8xxx2-pinmux"; 115 reg = <0x00f01630 0x0008>; 116 label = "PINMUXE"; 117 func3_gcr = <0xf02032 NO_FUNC NO_FUNC NO_FUNC 118 NO_FUNC 0xf016f0 NO_FUNC 0xf02032>; 119 func3_en_mask = <0x01 0 0 0 120 0 0x08 0 0x01 >; 121 func4_gcr = <0xf016f3 NO_FUNC NO_FUNC NO_FUNC 122 NO_FUNC NO_FUNC NO_FUNC NO_FUNC >; 123 func4_en_mask = <0x01 0 0 0 124 0 0 0 0 >; 125 #pinctrl-cells = <2>; 126 }; 127 pinmuxf: pinmux@f01638 { 128 compatible = "ite,it8xxx2-pinmux"; 129 reg = <0x00f01638 0x0008>; 130 label = "PINMUXF"; 131 func3_gcr = <NO_FUNC NO_FUNC 0xf016f0 0xf016f0 132 NO_FUNC NO_FUNC 0xf016f1 0xf016f1>; 133 func3_en_mask = <0 0 0x02 0x02 134 0 0 0x10 0x10 >; 135 func4_gcr = <NO_FUNC NO_FUNC 0xf016f1 0xf016f1 136 NO_FUNC NO_FUNC NO_FUNC NO_FUNC >; 137 func4_en_mask = <0 0 0x20 0x20 138 0 0 0 0 >; 139 #pinctrl-cells = <2>; 140 }; 141 pinmuxg: pinmux@f01640 { 142 compatible = "ite,it8xxx2-pinmux"; 143 reg = <0x00f01640 0x0008>; 144 label = "PINMUXG"; 145 func3_gcr = <0xf016f0 0xf016f0 0xf016f0 NO_FUNC 146 NO_FUNC NO_FUNC 0xf016f0 NO_FUNC>; 147 func3_en_mask = <0x20 0x08 0x10 0 148 0 0 0x02 0 >; 149 func4_gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC 150 NO_FUNC NO_FUNC NO_FUNC NO_FUNC>; 151 func4_en_mask = <0 0 0 0 152 0 0 0 0 >; 153 #pinctrl-cells = <2>; 154 }; 155 pinmuxh: pinmux@f01648 { 156 compatible = "ite,it8xxx2-pinmux"; 157 reg = <0x00f01648 0x0008>; 158 label = "PINMUXH"; 159 func3_gcr = <NO_FUNC 0xf016f1 0xf016f1 NO_FUNC 160 NO_FUNC 0xf016f5 0xf016f5 NO_FUNC>; 161 func3_en_mask = <0 0x20 0x20 0 162 0 0x04 0x08 0 >; 163 func4_gcr = <NO_FUNC 0xf016f5 0xf016f5 NO_FUNC 164 NO_FUNC NO_FUNC NO_FUNC NO_FUNC>; 165 func4_en_mask = <0 0x04 0x08 0 166 0 0 0 0 >; 167 #pinctrl-cells = <2>; 168 }; 169 pinmuxi: pinmux@f01650 { 170 compatible = "ite,it8xxx2-pinmux"; 171 reg = <0x00f01650 0x0008>; 172 label = "PINMUXI"; 173 func3_gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC 174 NO_FUNC 0xf016f0 0xf016f0 0xf016f0>; 175 func3_en_mask = <0 0 0 0 176 0 0x08 0x08 0x08 >; 177 func4_gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC 178 NO_FUNC NO_FUNC NO_FUNC NO_FUNC >; 179 func4_en_mask = <0 0 0 0 180 0 0 0 0 >; 181 #pinctrl-cells = <2>; 182 }; 183 pinmuxj: pinmux@f01658 { 184 compatible = "ite,it8xxx2-pinmux"; 185 reg = <0x00f01658 0x0008>; 186 label = "PINMUXJ"; 187 func3_gcr = <0xf016f4 NO_FUNC 0xf016f4 0xf016f4 188 0xf016f0 0xf016f0 NO_FUNC NO_FUNC>; 189 func3_en_mask = <0x01 0 0x01 0x02 190 0x02 0x03 0 0 >; 191 func4_gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC 192 NO_FUNC NO_FUNC NO_FUNC NO_FUNC>; 193 func4_en_mask = <0 0 0 0 194 0 0 0 0 >; 195 #pinctrl-cells = <2>; 196 }; 197 pinmuxk: pinmux@f01690 { 198 compatible = "ite,it8xxx2-pinmux"; 199 reg = <0x00f01690 0x0008>; 200 label = "PINMUXK"; 201 func3_gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC 202 NO_FUNC NO_FUNC NO_FUNC NO_FUNC>; 203 func3_en_mask = <0 0 0 0 204 0 0 0 0 >; 205 func4_gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC 206 NO_FUNC NO_FUNC NO_FUNC NO_FUNC>; 207 func4_en_mask = <0 0 0 0 208 0 0 0 0 >; 209 #pinctrl-cells = <2>; 210 }; 211 pinmuxl: pinmux@f01698 { 212 compatible = "ite,it8xxx2-pinmux"; 213 reg = <0x00f01698 0x0008>; 214 label = "PINMUXL"; 215 func3_gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC 216 NO_FUNC NO_FUNC NO_FUNC NO_FUNC>; 217 func3_en_mask = <0 0 0 0 218 0 0 0 0 >; 219 func4_gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC 220 NO_FUNC NO_FUNC NO_FUNC NO_FUNC>; 221 func4_en_mask = <0 0 0 0 222 0 0 0 0 >; 223 #pinctrl-cells = <2>; 224 }; 225 pinmuxm: pinmux@f016a0 { 226 compatible = "ite,it8xxx2-pinmux"; 227 reg = <0x00f016a0 0x0008>; 228 label = "PINMUXM"; 229 func3_gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC 230 NO_FUNC NO_FUNC NO_FUNC NO_FUNC>; 231 func3_en_mask = <0 0 0 0 232 0 0 0 0 >; 233 func4_gcr = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC 234 NO_FUNC NO_FUNC NO_FUNC NO_FUNC>; 235 func4_en_mask = <0 0 0 0 236 0 0 0 0 >; 237 #pinctrl-cells = <2>; 238 }; 239 sram0: memory@80101000 { 240 compatible = "mmio-sram"; 241 reg = <0x80101000 DT_SIZE_K(56)>; 242 }; 243 intc: interrupt-controller@f03f00 { 244 #interrupt-cells = <2>; 245 compatible = "ite,it8xxx2-intc"; 246 interrupt-controller; 247 reg = <0x00f03f00 0x0100>; 248 }; 249 uart1: uart@f02700 { 250 compatible = "ns16550"; 251 reg = <0x00f02700 0x0020>; 252 status = "disabled"; 253 label = "console"; 254 current-speed = <115200>; 255 clock-frequency = <1804800>; 256 interrupts = <38 IRQ_TYPE_EDGE_RISING>; 257 interrupt-parent = <&intc>; 258 }; 259 uart2: uart@f02800 { 260 compatible = "ns16550"; 261 reg = <0x00f02800 0x0020>; 262 status = "disabled"; 263 label = "UART_2"; 264 current-speed = <460800>; 265 clock-frequency = <1804800>; 266 interrupts = <39 IRQ_TYPE_EDGE_RISING>; 267 interrupt-parent = <&intc>; 268 }; 269 270 twd0: watchdog@f01f00 { 271 compatible = "ite,it8xxx2-watchdog"; 272 reg = <0x00f01f00 0x0062>; 273 label = "TWD_0"; 274 interrupts = <IT8XXX2_IRQ_TIMER1 IRQ_TYPE_EDGE_RISING /* Warning timer */ 275 IT8XXX2_IRQ_TIMER2 IRQ_TYPE_EDGE_RISING>; /* One shot timer */ 276 interrupt-parent = <&intc>; 277 }; 278 279 timer: timer@f01f10 { 280 compatible = "ite,it8xxx2-timer"; 281 reg = <0x00f01f10 0x0052>; 282 label = "TIMER"; 283 interrupts = <IT8XXX2_IRQ_TIMER3 IRQ_TYPE_EDGE_RISING /* Event timer */ 284 IT8XXX2_IRQ_TIMER4 IRQ_TYPE_EDGE_RISING /* Free run timer */ 285 IT8XXX2_IRQ_TIMER5 IRQ_TYPE_EDGE_RISING 286 IT8XXX2_IRQ_TIMER6 IRQ_TYPE_EDGE_RISING 287 IT8XXX2_IRQ_TIMER7 IRQ_TYPE_EDGE_RISING 288 IT8XXX2_IRQ_TIMER8 IRQ_TYPE_EDGE_RISING>; 289 interrupt-parent = <&intc>; 290 }; 291 292 gpioa: gpio@f01601 { 293 compatible = "ite,it8xxx2-gpio"; 294 reg = <0x00f01601 1 /* GPDR (set) */ 295 0x00f01610 8 /* GPCR */ 296 0x00f01661 1 /* GPDMR (get) */ 297 0x00f01671 1>; /* GPOTR */ 298 ngpios = <8>; 299 label = "GPIO_A"; 300 gpio-controller; 301 interrupts = <IT8XXX2_IRQ_WU91 IRQ_TYPE_LEVEL_HIGH 302 IT8XXX2_IRQ_WU92 IRQ_TYPE_LEVEL_HIGH 303 IT8XXX2_IRQ_WU93 IRQ_TYPE_LEVEL_HIGH 304 IT8XXX2_IRQ_WU80 IRQ_TYPE_LEVEL_HIGH 305 IT8XXX2_IRQ_WU81 IRQ_TYPE_LEVEL_HIGH 306 IT8XXX2_IRQ_WU82 IRQ_TYPE_LEVEL_HIGH 307 IT8XXX2_IRQ_WU83 IRQ_TYPE_LEVEL_HIGH 308 IT8XXX2_IRQ_WU100 IRQ_TYPE_LEVEL_HIGH>; 309 interrupt-parent = <&intc>; 310 #gpio-cells = <2>; 311 }; 312 313 gpiob: gpio@f01602 { 314 compatible = "ite,it8xxx2-gpio"; 315 reg = <0x00f01602 1 /* GPDR (set) */ 316 0x00f01618 8 /* GPCR */ 317 0x00f01662 1 /* GPDMR (get) */ 318 0x00f01672 1>; /* GPOTR */ 319 ngpios = <8>; 320 label = "GPIO_B"; 321 gpio-controller; 322 interrupts = <IT8XXX2_IRQ_WU101 IRQ_TYPE_LEVEL_HIGH 323 IT8XXX2_IRQ_WU102 IRQ_TYPE_LEVEL_HIGH 324 IT8XXX2_IRQ_WU84 IRQ_TYPE_LEVEL_HIGH 325 IT8XXX2_IRQ_WU103 IRQ_TYPE_LEVEL_HIGH 326 IT8XXX2_IRQ_WU94 IRQ_TYPE_LEVEL_HIGH 327 IT8XXX2_IRQ_WU104 IRQ_TYPE_LEVEL_HIGH 328 IT8XXX2_IRQ_WU105 IRQ_TYPE_LEVEL_HIGH 329 IT8XXX2_IRQ_WU106 IRQ_TYPE_LEVEL_HIGH>; 330 interrupt-parent = <&intc>; 331 #gpio-cells = <2>; 332 }; 333 334 gpioc: gpio@f01603 { 335 compatible = "ite,it8xxx2-gpio"; 336 reg = <0x00f01603 1 /* GPDR (set) */ 337 0x00f01620 8 /* GPCR */ 338 0x00f01663 1 /* GPDMR (get) */ 339 0x00f01673 1>; /* GPOTR */ 340 ngpios = <8>; 341 label = "GPIO_C"; 342 gpio-controller; 343 interrupts = <IT8XXX2_IRQ_WU85 IRQ_TYPE_LEVEL_HIGH 344 IT8XXX2_IRQ_WU107 IRQ_TYPE_LEVEL_HIGH 345 IT8XXX2_IRQ_WU95 IRQ_TYPE_LEVEL_HIGH 346 IT8XXX2_IRQ_WU108 IRQ_TYPE_LEVEL_HIGH 347 IT8XXX2_IRQ_WU22 IRQ_TYPE_LEVEL_HIGH 348 IT8XXX2_IRQ_WU109 IRQ_TYPE_LEVEL_HIGH 349 IT8XXX2_IRQ_WU23 IRQ_TYPE_LEVEL_HIGH 350 IT8XXX2_IRQ_WU86 IRQ_TYPE_LEVEL_HIGH>; 351 interrupt-parent = <&intc>; 352 #gpio-cells = <2>; 353 }; 354 355 gpiod: gpio@f01604 { 356 compatible = "ite,it8xxx2-gpio"; 357 reg = <0x00f01604 1 /* GPDR (set) */ 358 0x00f01628 8 /* GPCR */ 359 0x00f01664 1 /* GPDMR (get) */ 360 0x00f01674 1>; /* GPOTR */ 361 ngpios = <8>; 362 label = "GPIO_D"; 363 gpio-controller; 364 interrupts = <IT8XXX2_IRQ_WU20 IRQ_TYPE_LEVEL_HIGH 365 IT8XXX2_IRQ_WU21 IRQ_TYPE_LEVEL_HIGH 366 IT8XXX2_IRQ_WU24 IRQ_TYPE_LEVEL_HIGH 367 IT8XXX2_IRQ_WU110 IRQ_TYPE_LEVEL_HIGH 368 IT8XXX2_IRQ_WU111 IRQ_TYPE_LEVEL_HIGH 369 IT8XXX2_IRQ_WU112 IRQ_TYPE_LEVEL_HIGH 370 IT8XXX2_IRQ_WU113 IRQ_TYPE_LEVEL_HIGH 371 IT8XXX2_IRQ_WU87 IRQ_TYPE_LEVEL_HIGH>; 372 interrupt-parent = <&intc>; 373 #gpio-cells = <2>; 374 }; 375 376 gpioe: gpio@f01605 { 377 compatible = "ite,it8xxx2-gpio"; 378 reg = <0x00f01605 1 /* GPDR (set) */ 379 0x00f01630 8 /* GPCR */ 380 0x00f01665 1 /* GPDMR (get) */ 381 0x00f01675 1>; /* GPOTR */ 382 ngpios = <8>; 383 label = "GPIO_E"; 384 gpio-controller; 385 interrupts = <IT8XXX2_IRQ_WU70 IRQ_TYPE_LEVEL_HIGH 386 IT8XXX2_IRQ_WU71 IRQ_TYPE_LEVEL_HIGH 387 IT8XXX2_IRQ_WU72 IRQ_TYPE_LEVEL_HIGH 388 IT8XXX2_IRQ_WU73 IRQ_TYPE_LEVEL_HIGH 389 IT8XXX2_IRQ_WU114 IRQ_TYPE_LEVEL_HIGH 390 IT8XXX2_IRQ_WU40 IRQ_TYPE_LEVEL_HIGH 391 IT8XXX2_IRQ_WU45 IRQ_TYPE_LEVEL_HIGH 392 IT8XXX2_IRQ_WU46 IRQ_TYPE_LEVEL_HIGH>; 393 interrupt-parent = <&intc>; 394 #gpio-cells = <2>; 395 }; 396 397 gpiof: gpio@f01606 { 398 compatible = "ite,it8xxx2-gpio"; 399 reg = <0x00f01606 1 /* GPDR (set) */ 400 0x00f01638 8 /* GPCR */ 401 0x00f01666 1 /* GPDMR (get) */ 402 0x00f01676 1>; /* GPOTR */ 403 ngpios = <8>; 404 label = "GPIO_F"; 405 gpio-controller; 406 interrupts = <IT8XXX2_IRQ_WU96 IRQ_TYPE_LEVEL_HIGH 407 IT8XXX2_IRQ_WU97 IRQ_TYPE_LEVEL_HIGH 408 IT8XXX2_IRQ_WU98 IRQ_TYPE_LEVEL_HIGH 409 IT8XXX2_IRQ_WU99 IRQ_TYPE_LEVEL_HIGH 410 IT8XXX2_IRQ_WU64 IRQ_TYPE_LEVEL_HIGH 411 IT8XXX2_IRQ_WU65 IRQ_TYPE_LEVEL_HIGH 412 IT8XXX2_IRQ_WU66 IRQ_TYPE_LEVEL_HIGH 413 IT8XXX2_IRQ_WU67 IRQ_TYPE_LEVEL_HIGH>; 414 interrupt-parent = <&intc>; 415 #gpio-cells = <2>; 416 }; 417 418 gpiog: gpio@f01607 { 419 compatible = "ite,it8xxx2-gpio"; 420 reg = <0x00f01607 1 /* GPDR (set) */ 421 0x00f01640 8 /* GPCR */ 422 0x00f01667 1 /* GPDMR (get) */ 423 0x00f01677 1>; /* GPOTR */ 424 ngpios = <8>; 425 label = "GPIO_G"; 426 gpio-controller; 427 interrupts = <IT8XXX2_IRQ_WU115 IRQ_TYPE_LEVEL_HIGH 428 IT8XXX2_IRQ_WU116 IRQ_TYPE_LEVEL_HIGH 429 IT8XXX2_IRQ_WU117 IRQ_TYPE_LEVEL_HIGH 430 IT8XXX2_IRQ_WU123 IRQ_TYPE_LEVEL_HIGH 431 IT8XXX2_IRQ_WU124 IRQ_TYPE_LEVEL_HIGH 432 IT8XXX2_IRQ_WU125 IRQ_TYPE_LEVEL_HIGH 433 IT8XXX2_IRQ_WU118 IRQ_TYPE_LEVEL_HIGH 434 IT8XXX2_IRQ_WU126 IRQ_TYPE_LEVEL_HIGH>; 435 interrupt-parent = <&intc>; 436 #gpio-cells = <2>; 437 }; 438 439 gpioh: gpio@f01608 { 440 compatible = "ite,it8xxx2-gpio"; 441 reg = <0x00f01608 1 /* GPDR (set) */ 442 0x00f01648 8 /* GPCR */ 443 0x00f01668 1 /* GPDMR (get) */ 444 0x00f01678 1>; /* GPOTR */ 445 ngpios = <8>; 446 label = "GPIO_H"; 447 gpio-controller; 448 interrupts = <IT8XXX2_IRQ_WU60 IRQ_TYPE_LEVEL_HIGH 449 IT8XXX2_IRQ_WU61 IRQ_TYPE_LEVEL_HIGH 450 IT8XXX2_IRQ_WU62 IRQ_TYPE_LEVEL_HIGH 451 IT8XXX2_IRQ_WU63 IRQ_TYPE_LEVEL_HIGH 452 IT8XXX2_IRQ_WU88 IRQ_TYPE_LEVEL_HIGH 453 IT8XXX2_IRQ_WU89 IRQ_TYPE_LEVEL_HIGH 454 IT8XXX2_IRQ_WU90 IRQ_TYPE_LEVEL_HIGH 455 0 IRQ_TYPE_LEVEL_HIGH>; 456 interrupt-parent = <&intc>; 457 #gpio-cells = <2>; 458 }; 459 460 gpioi: gpio@f01609 { 461 compatible = "ite,it8xxx2-gpio"; 462 reg = <0x00f01609 1 /* GPDR (set) */ 463 0x00f01650 8 /* GPCR */ 464 0x00f01669 1 /* GPDMR (get) */ 465 0x00f01679 1>; /* GPOTR */ 466 ngpios = <8>; 467 label = "GPIO_I"; 468 gpio-controller; 469 interrupts = <IT8XXX2_IRQ_WU119 IRQ_TYPE_LEVEL_HIGH 470 IT8XXX2_IRQ_WU120 IRQ_TYPE_LEVEL_HIGH 471 IT8XXX2_IRQ_WU121 IRQ_TYPE_LEVEL_HIGH 472 IT8XXX2_IRQ_WU122 IRQ_TYPE_LEVEL_HIGH 473 IT8XXX2_IRQ_WU74 IRQ_TYPE_LEVEL_HIGH 474 IT8XXX2_IRQ_WU75 IRQ_TYPE_LEVEL_HIGH 475 IT8XXX2_IRQ_WU76 IRQ_TYPE_LEVEL_HIGH 476 IT8XXX2_IRQ_WU77 IRQ_TYPE_LEVEL_HIGH>; 477 interrupt-parent = <&intc>; 478 #gpio-cells = <2>; 479 }; 480 481 gpioj: gpio@f0160a { 482 compatible = "ite,it8xxx2-gpio"; 483 reg = <0x00f0160a 1 /* GPDR (set) */ 484 0x00f01658 8 /* GPCR */ 485 0x00f0166a 1 /* GPDMR (get) */ 486 0x00f0167a 1>; /* GPOTR */ 487 ngpios = <8>; 488 label = "GPIO_J"; 489 gpio-controller; 490 interrupts = <IT8XXX2_IRQ_WU128 IRQ_TYPE_LEVEL_HIGH 491 IT8XXX2_IRQ_WU129 IRQ_TYPE_LEVEL_HIGH 492 IT8XXX2_IRQ_WU130 IRQ_TYPE_LEVEL_HIGH 493 IT8XXX2_IRQ_WU131 IRQ_TYPE_LEVEL_HIGH 494 IT8XXX2_IRQ_WU132 IRQ_TYPE_LEVEL_HIGH 495 IT8XXX2_IRQ_WU133 IRQ_TYPE_LEVEL_HIGH 496 IT8XXX2_IRQ_WU134 IRQ_TYPE_LEVEL_HIGH 497 IT8XXX2_IRQ_WU135 IRQ_TYPE_LEVEL_HIGH>; 498 interrupt-parent = <&intc>; 499 #gpio-cells = <2>; 500 }; 501 502 gpiok: gpio@f0160b { 503 compatible = "ite,it8xxx2-gpio"; 504 reg = <0x00f0160b 1 /* GPDR (set) */ 505 0x00f01690 8 /* GPCR */ 506 0x00f0166b 1 /* GPDMR (get) */ 507 0x00f0167b 1>; /* GPOTR */ 508 ngpios = <8>; 509 label = "GPIO_K"; 510 gpio-controller; 511 interrupts = <IT8XXX2_IRQ_WU50 IRQ_TYPE_LEVEL_HIGH 512 IT8XXX2_IRQ_WU51 IRQ_TYPE_LEVEL_HIGH 513 IT8XXX2_IRQ_WU52 IRQ_TYPE_LEVEL_HIGH 514 IT8XXX2_IRQ_WU53 IRQ_TYPE_LEVEL_HIGH 515 IT8XXX2_IRQ_WU54 IRQ_TYPE_LEVEL_HIGH 516 IT8XXX2_IRQ_WU55 IRQ_TYPE_LEVEL_HIGH 517 IT8XXX2_IRQ_WU56 IRQ_TYPE_LEVEL_HIGH 518 IT8XXX2_IRQ_WU57 IRQ_TYPE_LEVEL_HIGH>; 519 interrupt-parent = <&intc>; 520 #gpio-cells = <2>; 521 }; 522 523 gpiol: gpio@f0160c { 524 compatible = "ite,it8xxx2-gpio"; 525 reg = <0x00f0160c 1 /* GPDR (set) */ 526 0x00f01698 8 /* GPCR */ 527 0x00f0166c 1 /* GPDMR (get) */ 528 0x00f0167c 1>; /* GPOTR */ 529 ngpios = <8>; 530 label = "GPIO_L"; 531 gpio-controller; 532 interrupts = <IT8XXX2_IRQ_WU136 IRQ_TYPE_LEVEL_HIGH 533 IT8XXX2_IRQ_WU137 IRQ_TYPE_LEVEL_HIGH 534 IT8XXX2_IRQ_WU138 IRQ_TYPE_LEVEL_HIGH 535 IT8XXX2_IRQ_WU139 IRQ_TYPE_LEVEL_HIGH 536 IT8XXX2_IRQ_WU140 IRQ_TYPE_LEVEL_HIGH 537 IT8XXX2_IRQ_WU141 IRQ_TYPE_LEVEL_HIGH 538 IT8XXX2_IRQ_WU142 IRQ_TYPE_LEVEL_HIGH 539 IT8XXX2_IRQ_WU143 IRQ_TYPE_LEVEL_HIGH>; 540 interrupt-parent = <&intc>; 541 #gpio-cells = <2>; 542 }; 543 544 gpiom: gpio@f0160d { 545 compatible = "ite,it8xxx2-gpio"; 546 reg = <0x00f0160d 1 /* GPDR (set) */ 547 0x00f016a0 8 /* GPCR */ 548 0x00f0166d 1 /* GPDMR (get) */ 549 0x00f0167d 1>; /* GPOTR */ 550 ngpios = <7>; 551 label = "GPIO_M"; 552 gpio-controller; 553 interrupts = <IT8XXX2_IRQ_WU144 IRQ_TYPE_LEVEL_HIGH 554 IT8XXX2_IRQ_WU145 IRQ_TYPE_LEVEL_HIGH 555 IT8XXX2_IRQ_WU146 IRQ_TYPE_LEVEL_HIGH 556 IT8XXX2_IRQ_WU147 IRQ_TYPE_LEVEL_HIGH 557 IT8XXX2_IRQ_WU148 IRQ_TYPE_LEVEL_HIGH 558 IT8XXX2_IRQ_WU149 IRQ_TYPE_LEVEL_HIGH 559 IT8XXX2_IRQ_WU150 IRQ_TYPE_LEVEL_HIGH 560 0 IRQ_TYPE_LEVEL_HIGH>; 561 interrupt-parent = <&intc>; 562 #gpio-cells = <2>; 563 }; 564 565 spi0:spi@f02600 { 566 #address-cells = <1>; 567 #size-cells = <0>; 568 compatible = "ite,it8xxx2-sspi"; 569 reg = <0x00f02600 0x40>; 570 label = "SPI0"; 571 interrupt-parent = <&intc>; 572 interrupts = <37 IRQ_TYPE_EDGE_RISING>; 573 clock-frequency = <115200>; 574 }; 575 spi1:spi@f02640 { 576 #address-cells = <1>; 577 #size-cells = <0>; 578 compatible = "ite,it8xxx2-sspi"; 579 reg = <0x00f02640 0x40>; 580 label = "SPI1"; 581 interrupts = <37 IRQ_TYPE_EDGE_RISING>; 582 interrupt-parent = <&intc>; 583 status = "okay"; 584 }; 585 adc0: adc@f01900 { 586 compatible = "ite,it8xxx2-adc"; 587 reg = <0xf01900 0x45>; 588 interrupts = <8 IRQ_TYPE_NONE>; 589 interrupt-parent = <&intc>; 590 status = "disabled"; 591 label = "ADC_0"; 592 #io-channel-cells = <1>; 593 pinctrl-0 = <&pinctrl_adc0 /* ADC0*/ 594 &pinctrl_adc1 /* ADC1*/ 595 &pinctrl_adc2 /* ADC2*/ 596 &pinctrl_adc3 /* ADC3*/ 597 &pinctrl_adc4 /* ADC4*/ 598 &pinctrl_adc5 /* ADC5*/ 599 &pinctrl_adc6 /* ADC6*/ 600 &pinctrl_adc7>; /* ADC7*/ 601 }; 602 i2c0: i2c@f01c40 { 603 compatible = "ite,it8xxx2-i2c"; 604 #address-cells = <1>; 605 #size-cells = <0>; 606 reg = <0x00f01c40 0x0040>; 607 interrupts = <9 IRQ_TYPE_EDGE_FALLING>; 608 interrupt-parent = <&intc>; 609 status = "disabled"; 610 label = "I2C_0"; 611 port-num = <0>; 612 gpio-dev = <&gpiob>; 613 pinctrl-0 = <&pinctrl_i2c_clk0 /* GPB3 */ 614 &pinctrl_i2c_data0>; /* GPB4 */ 615 }; 616 i2c1: i2c@f01c80 { 617 compatible = "ite,it8xxx2-i2c"; 618 #address-cells = <1>; 619 #size-cells = <0>; 620 reg = <0x00f01c80 0x0040>; 621 interrupts = <10 IRQ_TYPE_EDGE_FALLING>; 622 interrupt-parent = <&intc>; 623 status = "disabled"; 624 label = "I2C_1"; 625 port-num = <1>; 626 gpio-dev = <&gpioc>; 627 pinctrl-0 = <&pinctrl_i2c_clk1 /* GPC1 */ 628 &pinctrl_i2c_data1>; /* GPC2 */ 629 }; 630 i2c2: i2c@f01cc0 { 631 compatible = "ite,it8xxx2-i2c"; 632 #address-cells = <1>; 633 #size-cells = <0>; 634 reg = <0x00f01cc0 0x0040>; 635 interrupts = <16 IRQ_TYPE_EDGE_FALLING>; 636 interrupt-parent = <&intc>; 637 status = "disabled"; 638 label = "I2C_2"; 639 port-num = <2>; 640 gpio-dev = <&gpiof>; 641 pinctrl-0 = <&pinctrl_i2c_clk2 /* GPF6 */ 642 &pinctrl_i2c_data2>; /* GPF7 */ 643 }; 644 i2c3: i2c@f03680 { 645 compatible = "ite,it8xxx2-i2c"; 646 #address-cells = <1>; 647 #size-cells = <0>; 648 reg = <0x00f03680 0x0080>; 649 interrupts = <4 IRQ_TYPE_EDGE_FALLING>; 650 interrupt-parent = <&intc>; 651 status = "disabled"; 652 label = "I2C_3"; 653 port-num = <3>; 654 gpio-dev = <&gpioh>; 655 pinctrl-0 = <&pinctrl_i2c_clk3 /* GPH1 */ 656 &pinctrl_i2c_data3>; /* GPH2 */ 657 }; 658 i2c4: i2c@f03500 { 659 compatible = "ite,it8xxx2-i2c"; 660 #address-cells = <1>; 661 #size-cells = <0>; 662 reg = <0x00f03500 0x0080>; 663 interrupts = <152 IRQ_TYPE_EDGE_FALLING>; 664 interrupt-parent = <&intc>; 665 status = "disabled"; 666 label = "I2C_4"; 667 port-num = <4>; 668 gpio-dev = <&gpioe>; 669 pinctrl-0 = <&pinctrl_i2c_clk4 /* GPE0 */ 670 &pinctrl_i2c_data4>; /* GPE7 */ 671 }; 672 i2c5: i2c@f03580 { 673 compatible = "ite,it8xxx2-i2c"; 674 #address-cells = <1>; 675 #size-cells = <0>; 676 reg = <0x00f03580 0x0080>; 677 interrupts = <153 IRQ_TYPE_EDGE_FALLING>; 678 interrupt-parent = <&intc>; 679 status = "disabled"; 680 label = "I2C_5"; 681 port-num = <5>; 682 gpio-dev = <&gpioa>; 683 pinctrl-0 = <&pinctrl_i2c_clk5 /* GPA4 */ 684 &pinctrl_i2c_data5>; /* GPA5 */ 685 }; 686 687 ecpm: clock-controller@f01e00 { 688 compatible = "ite,it8xxx2-ecpm"; 689 reg = <0x00f01e00 0x11>; 690 reg-names = "ecpm"; 691 label = "EC_PM"; 692 }; 693 prs: pwmprs@f01800 { 694 compatible = "ite,it8xxx2-pwmprs"; 695 reg = <0x00f01800 1>; 696 label = "prescaler"; 697 }; 698 pwm0: pwm@f01802 { 699 compatible = "ite,it8xxx2-pwm"; 700 reg = <0x00f01802 1 /* DCR */ 701 0x00f0180c 1 /* PCSSG */ 702 0x00f0180f 1 /* PCSG */ 703 0x00f0180a 1>; /* PWMPOL */ 704 channel = <PWM_CHANNEL_0>; 705 label = "pwm_0"; 706 status = "disabled"; 707 pwmctrl = <&prs>; 708 pinctrl-0 = <&pinctrl_pwm0>; /* GPA0 */ 709 #pwm-cells = <2>; 710 }; 711 pwm1: pwm@f01803 { 712 compatible = "ite,it8xxx2-pwm"; 713 reg = <0x00f01803 1 /* DCR */ 714 0x00f0180c 1 /* PCSSG */ 715 0x00f0180f 1 /* PCSG */ 716 0x00f0180a 1>; /* PWMPOL */ 717 channel = <PWM_CHANNEL_1>; 718 label = "pwm_1"; 719 status = "disabled"; 720 pwmctrl = <&prs>; 721 pinctrl-0 = <&pinctrl_pwm1>; /* GPA1 */ 722 #pwm-cells = <2>; 723 }; 724 pwm2: pwm@f01804 { 725 compatible = "ite,it8xxx2-pwm"; 726 reg = <0x00f01804 1 /* DCR */ 727 0x00f0180c 1 /* PCSSG */ 728 0x00f0180f 1 /* PCSG */ 729 0x00f0180a 1>; /* PWMPOL */ 730 channel = <PWM_CHANNEL_2>; 731 label = "pwm_2"; 732 status = "disabled"; 733 pwmctrl = <&prs>; 734 pinctrl-0 = <&pinctrl_pwm2>; /* GPA2 */ 735 #pwm-cells = <2>; 736 }; 737 pwm3: pwm@f01805 { 738 compatible = "ite,it8xxx2-pwm"; 739 reg = <0x00f01805 1 /* DCR */ 740 0x00f0180c 1 /* PCSSG */ 741 0x00f0180f 1 /* PCSG */ 742 0x00f0180a 1>; /* PWMPOL */ 743 channel = <PWM_CHANNEL_3>; 744 label = "pwm_3"; 745 status = "disabled"; 746 pwmctrl = <&prs>; 747 pinctrl-0 = <&pinctrl_pwm3>; /* GPA3 */ 748 #pwm-cells = <2>; 749 }; 750 pwm4: pwm@f01806 { 751 compatible = "ite,it8xxx2-pwm"; 752 reg = <0x00f01806 1 /* DCR */ 753 0x00f0180d 1 /* PCSSG */ 754 0x00f0180f 1 /* PCSG */ 755 0x00f0180a 1>; /* PWMPOL */ 756 channel = <PWM_CHANNEL_4>; 757 label = "pwm_4"; 758 status = "disabled"; 759 pwmctrl = <&prs>; 760 pinctrl-0 = <&pinctrl_pwm4>; /* GPA4 */ 761 #pwm-cells = <2>; 762 }; 763 pwm5: pwm@f01807 { 764 compatible = "ite,it8xxx2-pwm"; 765 reg = <0x00f01807 1 /* DCR */ 766 0x00f0180d 1 /* PCSSG */ 767 0x00f0180f 1 /* PCSG */ 768 0x00f0180a 1>; /* PWMPOL */ 769 channel = <PWM_CHANNEL_5>; 770 label = "pwm_5"; 771 status = "disabled"; 772 pwmctrl = <&prs>; 773 pinctrl-0 = <&pinctrl_pwm5>; /* GPA5 */ 774 #pwm-cells = <2>; 775 }; 776 pwm6: pwm@f01808 { 777 compatible = "ite,it8xxx2-pwm"; 778 reg = <0x00f01808 1 /* DCR */ 779 0x00f0180d 1 /* PCSSG */ 780 0x00f0180f 1 /* PCSG */ 781 0x00f0180a 1>; /* PWMPOL */ 782 channel = <PWM_CHANNEL_6>; 783 label = "pwm_6"; 784 status = "disabled"; 785 pwmctrl = <&prs>; 786 pinctrl-0 = <&pinctrl_pwm6>; /* GPA6 */ 787 #pwm-cells = <2>; 788 }; 789 pwm7: pwm@f01809 { 790 compatible = "ite,it8xxx2-pwm"; 791 reg = <0x00f01809 1 /* DCR */ 792 0x00f0180d 1 /* PCSSG */ 793 0x00f0180f 1 /* PCSG */ 794 0x00f0180a 1>; /* PWMPOL */ 795 channel = <PWM_CHANNEL_7>; 796 label = "pwm_7"; 797 status = "disabled"; 798 pwmctrl = <&prs>; 799 pinctrl-0 = <&pinctrl_pwm7>; /* GPA7 */ 800 #pwm-cells = <2>; 801 }; 802 803 gctrl: general-control@f02000 { 804 compatible = "ite,it8xxx2-gctrl"; 805 reg = <0x00f02000 0x100>; 806 label = "GCTRL"; 807 }; 808 }; 809}; 810
