1/*
2 * Copyright (c) 2020 Antmicro <www.antmicro.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <mem.h>
8#include <arm/armv7-m.dtsi>
9#include <zephyr/dt-bindings/gpio/gpio.h>
10
11/ {
12	cpus {
13		#address-cells = <1>;
14		#size-cells = <0>;
15
16		cpu0: cpu@0 {
17			device_type = "cpu";
18			compatible = "arm,cortex-m4f";
19			reg = <0>;
20			#address-cells = <1>;
21			#size-cells = <1>;
22
23			mpu: mpu@e000ed90 {
24				compatible = "arm,armv7m-mpu";
25				reg = <0xe000ed90 0x40>;
26			};
27		};
28	};
29
30	sram0: memory@20000000 {
31		compatible = "mmio-sram";
32		reg = <0x20000000 DT_SIZE_K(512)>;
33	};
34
35	uartclk: uart-clock {
36		compatible = "fixed-clock";
37		clock-frequency = <5120000>;
38		#clock-cells = <0>;
39	};
40
41	soc {
42		uart0: uart@40010000 {
43			compatible = "arm,pl011";
44			reg = <0x40010000 DT_SIZE_K(4)>;
45			clocks = <&uartclk>;
46			interrupts = <7 3>;
47			interrupt-names = "rx";
48		};
49
50		uart1: uart@40020000 {
51			compatible = "quicklogic,usbserialport-s3b";
52			reg = <0x40020000 DT_SIZE_K(4)>;
53			status = "disabled";
54		};
55
56		gpio: gpio@40005000 {
57			compatible = "quicklogic,eos-s3-gpio";
58			reg = <0x40005000 DT_SIZE_K(4)>;
59			status = "disabled";
60			interrupts = <5 2>;
61			#gpio-cells = <2>;
62			ngpios = <8>;
63			pin-secondary-config = <0x00>;
64			gpio-controller;
65		};
66
67		pinctrl: pinctrl@40004c00 {
68			compatible = "quicklogic,eos-s3-pinctrl";
69			reg = <0x40004c00 0x1b0>;
70		};
71	};
72};
73
74&nvic {
75	arm,num-irq-priority-bits = <3>;
76};
77