1/*
2 * Copyright (c) 2020 Antmicro <www.antmicro.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <mem.h>
8#include <arm/armv7-m.dtsi>
9#include <dt-bindings/gpio/gpio.h>
10
11/ {
12	cpus {
13		#address-cells = <1>;
14		#size-cells = <0>;
15
16		cpu0: cpu@0 {
17			device_type = "cpu";
18			compatible = "arm,cortex-m4f";
19			reg = <0>;
20			#address-cells = <1>;
21			#size-cells = <1>;
22
23			mpu: mpu@e000ed90 {
24				compatible = "arm,armv7m-mpu";
25				reg = <0xe000ed90 0x40>;
26				arm,num-mpu-regions = <8>;
27			};
28		};
29	};
30
31	sram0: memory@20000000 {
32		compatible = "mmio-sram";
33		reg = <0x20000000 DT_SIZE_K(512)>;
34	};
35
36	uartclk: uart-clock {
37		compatible = "fixed-clock";
38		clock-frequency = <5120000>;
39		#clock-cells = <0>;
40	};
41
42	soc {
43		uart0: uart@40010000 {
44			compatible = "arm,pl011";
45			reg = <0x40010000 DT_SIZE_K(4)>;
46			clocks = <&uartclk>;
47			interrupts = <7 3>;
48			interrupt-names = "rx";
49			label = "UART_0";
50		};
51
52		gpio: gpio {
53			compatible = "quicklogic,eos-s3-gpio";
54			status = "disabled";
55			interrupts = <5 2>;
56			#gpio-cells = <2>;
57			ngpios = <8>;
58			pin-secondary-config = <0x00>;
59			gpio-controller;
60			label = "GPIO";
61		};
62	};
63};
64
65&nvic {
66	arm,num-irq-priority-bits = <3>;
67};
68