1/* 2 * Copyright (c) 2020 Gerson Fernando Budke <nandojve@gmail.com> 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <arm/armv7-m.dtsi> 8#include <zephyr/dt-bindings/i2c/i2c.h> 9#include <zephyr/dt-bindings/gpio/gpio.h> 10#include <zephyr/dt-bindings/clock/atmel_sam_pmc.h> 11 12/ { 13 chosen { 14 zephyr,flash-controller = &flashcalw; 15 zephyr,entropy = &trng; 16 }; 17 18 cpus { 19 #address-cells = <1>; 20 #size-cells = <0>; 21 22 cpu0: cpu@0 { 23 device_type = "cpu"; 24 compatible = "arm,cortex-m4"; 25 reg = <0>; 26 #address-cells = <1>; 27 #size-cells = <1>; 28 29 mpu: mpu@e000ed90 { 30 compatible = "arm,armv7m-mpu"; 31 reg = <0xe000ed90 0x40>; 32 }; 33 }; 34 }; 35 36 sram0: memory@20000000 { 37 compatible = "mmio-sram"; 38 }; 39 40 /** 41 * HRAM1 are 4k SRAM that can be used by PicoCache or just extra 42 * memory available. The PicoCache will be keep disable to ensures 43 * deterministic behaviour. That way the extra memory can be 44 * exclusive for USB descriptors 45 */ 46 sram1: memory@21000000 { 47 compatible = "zephyr,memory-region", "mmio-sram"; 48 reg = <0x21000000 DT_SIZE_K(4)>; 49 zephyr,memory-region = "SRAM1"; 50 }; 51 52 soc { 53 pmc: pmc@400e0000 { 54 compatible = "atmel,sam-pmc"; 55 reg = <0x400e0000 0x740>; 56 interrupts = <22 0>; 57 #clock-cells = <2>; 58 status = "okay"; 59 }; 60 61 flashcalw: flash-controller@400a0000 { 62 compatible = "atmel,sam4l-flashcalw-controller"; 63 reg = <0x400a0000 0x400>; 64 interrupts = <0 0>; 65 #address-cells = <1>; 66 #size-cells = <1>; 67 68 flash0: flash@0 { 69 compatible = "soc-nv-flash"; 70 71 write-block-size = <8>; 72 erase-block-size = <512>; 73 }; 74 75 /* 76 * No driver implemented yet, keeped it disabled 77 */ 78 status = "disabled"; 79 }; 80 81 twim0: twim@40018000 { 82 compatible = "atmel,sam-i2c-twim"; 83 clock-frequency = <I2C_BITRATE_STANDARD>; 84 reg = <0x40018000 0x4000>; 85 interrupts = <61 0>; 86 clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; 87 status = "disabled"; 88 #address-cells = <1>; 89 #size-cells = <0>; 90 }; 91 twim1: twim@4001c000 { 92 compatible = "atmel,sam-i2c-twim"; 93 clock-frequency = <I2C_BITRATE_STANDARD>; 94 reg = <0x4001c000 0x4000>; 95 interrupts = <63 0>; 96 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; 97 status = "disabled"; 98 #address-cells = <1>; 99 #size-cells = <0>; 100 }; 101 twim2: twim@40078000 { 102 compatible = "atmel,sam-i2c-twim"; 103 clock-frequency = <I2C_BITRATE_STANDARD>; 104 reg = <0x40078000 0x4000>; 105 interrupts = <77 0>; 106 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; 107 status = "disabled"; 108 #address-cells = <1>; 109 #size-cells = <0>; 110 }; 111 twim3: twim@4007c000 { 112 compatible = "atmel,sam-i2c-twim"; 113 clock-frequency = <I2C_BITRATE_STANDARD>; 114 reg = <0x4007c000 0x4000>; 115 interrupts = <78 0>; 116 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; 117 status = "disabled"; 118 #address-cells = <1>; 119 #size-cells = <0>; 120 }; 121 122 spi0: spi@40008000 { 123 compatible = "atmel,sam-spi"; 124 reg = <0x40008000 0x4000>; 125 interrupts = <54 0>; 126 clocks = <&pmc PMC_TYPE_PERIPHERAL 1>; 127 status = "disabled"; 128 #address-cells = <1>; 129 #size-cells = <0>; 130 }; 131 132 usart0: usart@40024000 { 133 compatible = "atmel,sam-usart"; 134 reg = <0x40024000 0x4000>; 135 interrupts = <65 1>; 136 clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; 137 status = "disabled"; 138 }; 139 usart1: usart@40028000 { 140 compatible = "atmel,sam-usart"; 141 reg = <0x40028000 0x4000>; 142 interrupts = <66 1>; 143 clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; 144 status = "disabled"; 145 }; 146 usart2: usart@4002c000 { 147 compatible = "atmel,sam-usart"; 148 reg = <0x4002c000 0x4000>; 149 interrupts = <67 1>; 150 clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; 151 status = "disabled"; 152 }; 153 usart3: usart@40030000 { 154 compatible = "atmel,sam-usart"; 155 reg = <0x40030000 0x4000>; 156 interrupts = <68 1>; 157 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; 158 status = "disabled"; 159 }; 160 161 usbc: usbd@400a5000 { 162 compatible = "atmel,sam-usbc"; 163 reg = <0x400a5000 0x1000>; 164 interrupts = <18 5>; 165 interrupt-names = "usbc"; 166 maximum-speed = "full-speed"; 167 num-bidir-endpoints = <8>; 168 clocks = <&pmc PMC_TYPE_PERIPHERAL 101>; 169 status = "disabled"; 170 }; 171 172 pinctrl: pinctrl@400e1000 { 173 compatible = "atmel,sam-pinctrl"; 174 #address-cells = <1>; 175 #size-cells = <1>; 176 ranges = <0x400e1000 0x400e1000 0x800>; 177 178 gpioa: gpio@400e1000 { 179 compatible = "atmel,sam4l-gpio"; 180 reg = <0x400e1000 0x200>; 181 interrupts = <25 1>, <26 1>, <27 1>, <28 1>; 182 clocks = <&pmc PMC_TYPE_PERIPHERAL 68>; 183 gpio-controller; 184 #gpio-cells = <2>; 185 #atmel,pin-cells = <2>; 186 }; 187 gpiob: gpio@400e1200 { 188 compatible = "atmel,sam4l-gpio"; 189 reg = <0x400e1200 0x200>; 190 interrupts = <29 1>, <30 1>, <31 1>, <32 1>; 191 clocks = <&pmc PMC_TYPE_PERIPHERAL 68>; 192 gpio-controller; 193 #gpio-cells = <2>; 194 #atmel,pin-cells = <2>; 195 }; 196 gpioc: gpio@400e1400 { 197 compatible = "atmel,sam4l-gpio"; 198 reg = <0x400e1400 0x200>; 199 interrupts = <33 1>, <34 1>, <35 1>, <36 1>; 200 clocks = <&pmc PMC_TYPE_PERIPHERAL 68>; 201 gpio-controller; 202 #gpio-cells = <2>; 203 #atmel,pin-cells = <2>; 204 }; 205 }; 206 207 tc0: tc@40010000 { 208 compatible = "atmel,sam-tc"; 209 reg = <0x40010000 0x100>; 210 interrupts = <55 0 211 56 0 212 57 0>; 213 clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; 214 status = "disabled"; 215 }; 216 217 tc1: tc@40014000 { 218 compatible = "atmel,sam-tc"; 219 reg = <0x40014000 0x100>; 220 interrupts = <58 0 221 59 0 222 60 0>; 223 clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; 224 status = "disabled"; 225 }; 226 227 trng: random@40068000 { 228 compatible = "atmel,sam-trng"; 229 reg = <0x40068000 0x4000>; 230 interrupts = <73 0>; 231 clocks = <&pmc PMC_TYPE_PERIPHERAL 17>; 232 status = "okay"; 233 }; 234 235 uid: device_uid@80020c { 236 compatible = "atmel,sam4l-uid"; 237 reg = <0x80020c 0xf>; 238 status = "okay"; 239 }; 240 }; 241}; 242 243&nvic { 244 arm,num-irq-priority-bits = <4>; 245}; 246
