1/* 2 * Copyright (c) 2020 Gerson Fernando Budke <nandojve@gmail.com> 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <arm/armv7-m.dtsi> 8#include <zephyr/dt-bindings/i2c/i2c.h> 9#include <zephyr/dt-bindings/gpio/gpio.h> 10#include <zephyr/dt-bindings/clock/atmel_sam_pmc.h> 11 12/ { 13 chosen { 14 zephyr,flash-controller = &flashcalw; 15 zephyr,entropy = &trng; 16 }; 17 18 cpus { 19 #address-cells = <1>; 20 #size-cells = <0>; 21 22 cpu0: cpu@0 { 23 device_type = "cpu"; 24 compatible = "arm,cortex-m4"; 25 reg = <0>; 26 #address-cells = <1>; 27 #size-cells = <1>; 28 29 mpu: mpu@e000ed90 { 30 compatible = "arm,armv7m-mpu"; 31 reg = <0xe000ed90 0x40>; 32 arm,num-mpu-regions = <8>; 33 }; 34 }; 35 }; 36 37 sram0: memory@20000000 { 38 compatible = "mmio-sram"; 39 }; 40 41 /** 42 * HRAM1 are 4k SRAM that can be used by PicoCache or just extra 43 * memory available. The PicoCache will be keep disable to ensures 44 * deterministic behaviour. That way the extra memory can be 45 * exclusive for USB descriptors 46 */ 47 sram1: memory@21000000 { 48 compatible = "zephyr,memory-region", "mmio-sram"; 49 reg = <0x21000000 DT_SIZE_K(4)>; 50 zephyr,memory-region = "SRAM1"; 51 }; 52 53 soc { 54 pmc: pmc@400e0000 { 55 compatible = "atmel,sam-pmc"; 56 reg = <0x400e0000 0x740>; 57 interrupts = <22 0>; 58 #clock-cells = <2>; 59 status = "okay"; 60 }; 61 62 flashcalw: flash-controller@400a0000 { 63 compatible = "atmel,sam4l-flashcalw-controller"; 64 reg = <0x400a0000 0x400>; 65 interrupts = <0 0>; 66 #address-cells = <1>; 67 #size-cells = <1>; 68 69 flash0: flash@0 { 70 compatible = "soc-nv-flash"; 71 72 write-block-size = <8>; 73 erase-block-size = <512>; 74 }; 75 76 /* 77 * No driver implemented yet, keeped it disabled 78 */ 79 status = "disabled"; 80 }; 81 82 twim0: twim@40018000 { 83 compatible = "atmel,sam-i2c-twim"; 84 clock-frequency = <I2C_BITRATE_STANDARD>; 85 reg = <0x40018000 0x4000>; 86 interrupts = <61 0>; 87 clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; 88 status = "disabled"; 89 #address-cells = <1>; 90 #size-cells = <0>; 91 }; 92 twim1: twim@4001c000 { 93 compatible = "atmel,sam-i2c-twim"; 94 clock-frequency = <I2C_BITRATE_STANDARD>; 95 reg = <0x4001c000 0x4000>; 96 interrupts = <63 0>; 97 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; 98 status = "disabled"; 99 #address-cells = <1>; 100 #size-cells = <0>; 101 }; 102 twim2: twim@40078000 { 103 compatible = "atmel,sam-i2c-twim"; 104 clock-frequency = <I2C_BITRATE_STANDARD>; 105 reg = <0x40078000 0x4000>; 106 interrupts = <77 0>; 107 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; 108 status = "disabled"; 109 #address-cells = <1>; 110 #size-cells = <0>; 111 }; 112 twim3: twim@4007c000 { 113 compatible = "atmel,sam-i2c-twim"; 114 clock-frequency = <I2C_BITRATE_STANDARD>; 115 reg = <0x4007c000 0x4000>; 116 interrupts = <78 0>; 117 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; 118 status = "disabled"; 119 #address-cells = <1>; 120 #size-cells = <0>; 121 }; 122 123 spi0: spi@40008000 { 124 compatible = "atmel,sam-spi"; 125 reg = <0x40008000 0x4000>; 126 interrupts = <54 0>; 127 clocks = <&pmc PMC_TYPE_PERIPHERAL 1>; 128 status = "disabled"; 129 #address-cells = <1>; 130 #size-cells = <0>; 131 }; 132 133 usart0: usart@40024000 { 134 compatible = "atmel,sam-usart"; 135 reg = <0x40024000 0x4000>; 136 interrupts = <65 1>; 137 clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; 138 status = "disabled"; 139 }; 140 usart1: usart@40028000 { 141 compatible = "atmel,sam-usart"; 142 reg = <0x40028000 0x4000>; 143 interrupts = <66 1>; 144 clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; 145 status = "disabled"; 146 }; 147 usart2: usart@4002c000 { 148 compatible = "atmel,sam-usart"; 149 reg = <0x4002c000 0x4000>; 150 interrupts = <67 1>; 151 clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; 152 status = "disabled"; 153 }; 154 usart3: usart@40030000 { 155 compatible = "atmel,sam-usart"; 156 reg = <0x40030000 0x4000>; 157 interrupts = <68 1>; 158 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; 159 status = "disabled"; 160 }; 161 162 usbc: usbd@400a5000 { 163 compatible = "atmel,sam-usbc"; 164 reg = <0x400a5000 0x1000>; 165 interrupts = <18 5>; 166 interrupt-names = "usbc"; 167 maximum-speed = "full-speed"; 168 num-bidir-endpoints = <8>; 169 clocks = <&pmc PMC_TYPE_PERIPHERAL 101>; 170 status = "disabled"; 171 }; 172 173 pinctrl: pinctrl@400e1000 { 174 compatible = "atmel,sam-pinctrl"; 175 #address-cells = <1>; 176 #size-cells = <1>; 177 ranges = <0x400e1000 0x400e1000 0x800>; 178 179 gpioa: gpio@400e1000 { 180 compatible = "atmel,sam4l-gpio"; 181 reg = <0x400e1000 0x200>; 182 interrupts = <25 1>, <26 1>, <27 1>, <28 1>; 183 clocks = <&pmc PMC_TYPE_PERIPHERAL 68>; 184 gpio-controller; 185 #gpio-cells = <2>; 186 #atmel,pin-cells = <2>; 187 }; 188 gpiob: gpio@400e1200 { 189 compatible = "atmel,sam4l-gpio"; 190 reg = <0x400e1200 0x200>; 191 interrupts = <29 1>, <30 1>, <31 1>, <32 1>; 192 clocks = <&pmc PMC_TYPE_PERIPHERAL 68>; 193 gpio-controller; 194 #gpio-cells = <2>; 195 #atmel,pin-cells = <2>; 196 }; 197 gpioc: gpio@400e1400 { 198 compatible = "atmel,sam4l-gpio"; 199 reg = <0x400e1400 0x200>; 200 interrupts = <33 1>, <34 1>, <35 1>, <36 1>; 201 clocks = <&pmc PMC_TYPE_PERIPHERAL 68>; 202 gpio-controller; 203 #gpio-cells = <2>; 204 #atmel,pin-cells = <2>; 205 }; 206 }; 207 208 tc0: tc@40010000 { 209 compatible = "atmel,sam-tc"; 210 reg = <0x40010000 0x100>; 211 interrupts = <55 0 212 56 0 213 57 0>; 214 clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; 215 status = "disabled"; 216 }; 217 218 tc1: tc@40014000 { 219 compatible = "atmel,sam-tc"; 220 reg = <0x40014000 0x100>; 221 interrupts = <58 0 222 59 0 223 60 0>; 224 clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; 225 status = "disabled"; 226 }; 227 228 trng: random@40068000 { 229 compatible = "atmel,sam-trng"; 230 reg = <0x40068000 0x4000>; 231 interrupts = <73 0>; 232 clocks = <&pmc PMC_TYPE_PERIPHERAL 17>; 233 status = "okay"; 234 }; 235 236 uid: device_uid@80020c { 237 compatible = "atmel,sam4l-uid"; 238 reg = <0x80020c 0xf>; 239 status = "okay"; 240 }; 241 }; 242}; 243 244&nvic { 245 arm,num-irq-priority-bits = <4>; 246}; 247
