1/* 2 * Copyright (c) 2020 Gerson Fernando Budke <nandojve@gmail.com> 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <arm/armv7-m.dtsi> 8#include <dt-bindings/i2c/i2c.h> 9#include <dt-bindings/gpio/gpio.h> 10 11#include "sam4l-pinctrl.dtsi" 12 13/ { 14 chosen { 15 zephyr,flash-controller = &flashcalw; 16 zephyr,entropy = &trng; 17 }; 18 19 cpus { 20 #address-cells = <1>; 21 #size-cells = <0>; 22 23 cpu0: cpu@0 { 24 device_type = "cpu"; 25 compatible = "arm,cortex-m4"; 26 reg = <0>; 27 #address-cells = <1>; 28 #size-cells = <1>; 29 30 mpu: mpu@e000ed90 { 31 compatible = "arm,armv7m-mpu"; 32 reg = <0xe000ed90 0x40>; 33 arm,num-mpu-regions = <8>; 34 }; 35 }; 36 }; 37 38 sram0: memory@20000000 { 39 compatible = "mmio-sram"; 40 }; 41 42 /** 43 * HRAM1 are 4k SRAM that can be used by PicoCache or just extra 44 * memory available. The PicoCache will be keep disable to ensures 45 * deterministic behaviour. That way the extra memory can be 46 * exclusive for USB descriptors 47 */ 48 sram1: memory@21000000 { 49 compatible = "mmio-sram"; 50 reg = <0x21000000 DT_SIZE_K(4)>; 51 }; 52 53 soc { 54 flashcalw: flash-controller@400a0000 { 55 compatible = "atmel,sam-flash-controller"; 56 label = "FLASH_CTRL"; 57 reg = <0x400a0000 0x400>; 58 interrupts = <0 0>; 59 peripheral-id = <32>; 60 #address-cells = <1>; 61 #size-cells = <1>; 62 63 flash0: flash@0 { 64 compatible = "soc-nv-flash"; 65 label = "FLASH_0"; 66 67 write-block-size = <16>; 68 }; 69 }; 70 71 twim0: twim@40018000 { 72 compatible = "atmel,sam-i2c-twim"; 73 clock-frequency = <I2C_BITRATE_STANDARD>; 74 reg = <0x40018000 0x4000>; 75 interrupts = <61 0>; 76 peripheral-id = <4>; 77 label = "TWIM_0"; 78 status = "disabled"; 79 #address-cells = <1>; 80 #size-cells = <0>; 81 pinctrl-0 = <&pa23b_twi0_twd0 &pa24b_twi0_twck0>; 82 }; 83 twim1: twim@4001c000 { 84 compatible = "atmel,sam-i2c-twim"; 85 clock-frequency = <I2C_BITRATE_STANDARD>; 86 reg = <0x4001c000 0x4000>; 87 interrupts = <63 0>; 88 peripheral-id = <6>; 89 label = "TWIM_1"; 90 status = "disabled"; 91 #address-cells = <1>; 92 #size-cells = <0>; 93 pinctrl-0 = <&pb0a_twi1_twd1 &pb1a_twi1_twck1>; 94 }; 95 twim2: twim@40078000 { 96 compatible = "atmel,sam-i2c-twim"; 97 clock-frequency = <I2C_BITRATE_STANDARD>; 98 reg = <0x40078000 0x4000>; 99 interrupts = <77 0>; 100 peripheral-id = <21>; 101 label = "TWIM_2"; 102 status = "disabled"; 103 #address-cells = <1>; 104 #size-cells = <0>; 105 pinctrl-0 = <&pa21e_twi2_twd2 &pa22e_twi2_twck2>; 106 }; 107 twim3: twim@4007c000 { 108 compatible = "atmel,sam-i2c-twim"; 109 clock-frequency = <I2C_BITRATE_STANDARD>; 110 reg = <0x4007c000 0x4000>; 111 interrupts = <78 0>; 112 peripheral-id = <22>; 113 label = "TWIM_3"; 114 status = "disabled"; 115 #address-cells = <1>; 116 #size-cells = <0>; 117 pinctrl-0 = <&pb14c_twi3_twd3 &pb15c_twi3_twck3>; 118 }; 119 120 spi0: spi@40008000 { 121 compatible = "atmel,sam-spi"; 122 reg = <0x40008000 0x4000>; 123 interrupts = <54 0>; 124 peripheral-id = <1>; 125 label = "SPI_0"; 126 status = "disabled"; 127 #address-cells = <1>; 128 #size-cells = <0>; 129 }; 130 131 usart0: usart@40024000 { 132 compatible = "atmel,sam-usart"; 133 reg = <0x40024000 0x4000>; 134 interrupts = <65 1>; 135 peripheral-id = <8>; 136 status = "disabled"; 137 label = "USART_0"; 138 }; 139 usart1: usart@40028000 { 140 compatible = "atmel,sam-usart"; 141 reg = <0x40028000 0x4000>; 142 interrupts = <66 1>; 143 peripheral-id = <9>; 144 status = "disabled"; 145 label = "USART_1"; 146 }; 147 usart2: usart@4002c000 { 148 compatible = "atmel,sam-usart"; 149 reg = <0x4002c000 0x4000>; 150 interrupts = <67 1>; 151 peripheral-id = <10>; 152 status = "disabled"; 153 label = "USART_2"; 154 }; 155 usart3: usart@40030000 { 156 compatible = "atmel,sam-usart"; 157 reg = <0x40030000 0x4000>; 158 interrupts = <68 1>; 159 peripheral-id = <11>; 160 status = "disabled"; 161 label = "USART_3"; 162 }; 163 164 usbc: usbd@400a5000 { 165 compatible = "atmel,sam-usbc"; 166 #address-cells = <1>; 167 #size-cells = <0>; 168 reg = <0x400a5000 0x1000>; 169 interrupts = <18 5>; 170 interrupt-names = "usbc"; 171 maximum-speed = "full-speed"; 172 num-bidir-endpoints = <8>; 173 peripheral-id = <101>; 174 status = "disabled"; 175 label = "USBC"; 176 pinctrl-0 = <&pa25a_usbc_dm &pa26a_usbc_dp>; 177 }; 178 179 pinctrl@400e1000 { 180 compatible = "atmel,sam-pinctrl"; 181 #address-cells = <1>; 182 #size-cells = <1>; 183 ranges = <0x400e1000 0x400e1000 0x800>; 184 185 gpioa: gpio@400e1000 { 186 compatible = "atmel,sam4l-gpio"; 187 reg = <0x400e1000 0x200>; 188 interrupts = <25 1>, <26 1>, <27 1>, <28 1>; 189 peripheral-id = <68>; 190 label = "GPIO_A"; 191 gpio-controller; 192 #gpio-cells = <2>; 193 #atmel,pin-cells = <2>; 194 }; 195 gpiob: gpio@400e1200 { 196 compatible = "atmel,sam4l-gpio"; 197 reg = <0x400e1200 0x200>; 198 interrupts = <29 1>, <30 1>, <31 1>, <32 1>; 199 peripheral-id = <68>; 200 label = "GPIO_B"; 201 gpio-controller; 202 #gpio-cells = <2>; 203 #atmel,pin-cells = <2>; 204 }; 205 gpioc: gpio@400e1400 { 206 compatible = "atmel,sam4l-gpio"; 207 reg = <0x400e1400 0x200>; 208 interrupts = <33 1>, <34 1>, <35 1>, <36 1>; 209 peripheral-id = <68>; 210 label = "GPIO_C"; 211 gpio-controller; 212 #gpio-cells = <2>; 213 #atmel,pin-cells = <2>; 214 }; 215 }; 216 217 tc0: tc@40010000 { 218 compatible = "atmel,sam-tc"; 219 reg = <0x40010000 0x100>; 220 interrupts = <55 0 221 56 0 222 57 0>; 223 peripheral-id = <2>; 224 status = "disabled"; 225 label = "TC0"; 226 pinctrl-0 = <>; 227 }; 228 229 tc1: tc@40014000 { 230 compatible = "atmel,sam-tc"; 231 reg = <0x40014000 0x100>; 232 interrupts = <58 0 233 59 0 234 60 0>; 235 peripheral-id = <3>; 236 status = "disabled"; 237 label = "TC1"; 238 pinctrl-0 = <>; 239 }; 240 241 trng: random@40068000 { 242 compatible = "atmel,sam-trng"; 243 reg = <0x40068000 0x4000>; 244 interrupts = <73 0>; 245 peripheral-id = <17>; 246 status = "okay"; 247 label = "TRNG"; 248 }; 249 250 uid: device_uid@80020c { 251 compatible = "atmel,sam4l-uid"; 252 reg = <0x80020c 0xf>; 253 status = "okay"; 254 }; 255 }; 256}; 257 258&nvic { 259 arm,num-irq-priority-bits = <4>; 260}; 261
