1 /*
2 * Copyright 2019-2022 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include "fsl_vref.h"
9
10 /* Component ID definition, used by tools. */
11 #ifndef FSL_COMPONENT_ID
12 #define FSL_COMPONENT_ID "platform.drivers.vref_1"
13 #endif
14
15 /*******************************************************************************
16 * Prototypes
17 ******************************************************************************/
18
19 /*!
20 * @brief Gets the instance from the base address
21 *
22 * @param base VREF peripheral base address
23 *
24 * @return The VREF instance
25 */
26 static uint32_t VREF_GetInstance(VREF_Type *base);
27
28 /*******************************************************************************
29 * Variables
30 ******************************************************************************/
31
32 /*! @brief Pointers to VREF bases for each instance. */
33 static VREF_Type *const s_vrefBases[] = VREF_BASE_PTRS;
34
35 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
36 /*! @brief Pointers to VREF clocks for each instance. */
37 static const clock_ip_name_t s_vrefClocks[] = VREF_CLOCKS;
38 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
39
40 /*******************************************************************************
41 * Code
42 ******************************************************************************/
43
VREF_GetInstance(VREF_Type * base)44 static uint32_t VREF_GetInstance(VREF_Type *base)
45 {
46 uint32_t instance;
47
48 /* Find the instance index from base address mappings. */
49 /*
50 * $Branch Coverage Justification$
51 * (instance >= ARRAY_SIZE(s_vrefBases)) not covered. The peripheral base
52 * address is always valid and checked by assert.
53 */
54 for (instance = 0; instance < ARRAY_SIZE(s_vrefBases); instance++)
55 {
56 /*
57 * $Branch Coverage Justification$
58 * (s_vrefBases[instance] != base) not covered. The peripheral base
59 * address is always valid and checked by assert.
60 */
61 if (s_vrefBases[instance] == base)
62 {
63 break;
64 }
65 }
66
67 assert(instance < ARRAY_SIZE(s_vrefBases));
68
69 return instance;
70 }
71
72 /*!
73 * brief Enables the clock gate and configures the VREF module according to the configuration structure.
74 *
75 * This function must be called before calling all other VREF driver functions, read/write registers, and
76 * configurations with user-defined settings. The example below shows how to set up vref_config_t parameters
77 * and how to call the VREF_Init function by passing in these parameters.
78 * code
79 * vref_config_t vrefConfig;
80 * VREF_GetDefaultConfig(VREF, &vrefConfig);
81 * vrefConfig.bufferMode = kVREF_ModeHighPowerBuffer;
82 * VREF_Init(VREF, &vrefConfig);
83 * endcode
84 *
85 * param base VREF peripheral address.
86 * param config Pointer to the configuration structure.
87 */
VREF_Init(VREF_Type * base,const vref_config_t * config)88 void VREF_Init(VREF_Type *base, const vref_config_t *config)
89 {
90 assert(config != NULL);
91
92 uint32_t tmp32 = 0UL;
93
94 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
95 /* Ungate clock for VREF */
96 CLOCK_EnableClock(s_vrefClocks[VREF_GetInstance(base)]);
97 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
98
99 base->CSR |= VREF_CSR_LPBGEN_MASK;
100 /* After enabling low power bandgap, delay 20 us. */
101 SDK_DelayAtLeastUs(20U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
102
103 /* Provides bias current for other peripherals. */
104 if (config->enableLowPowerBuff)
105 {
106 base->CSR |= VREF_CSR_LPBG_BUF_EN_MASK;
107 }
108
109 if (config->bufferMode != kVREF_ModeBandgapOnly)
110 {
111 if (config->enableHCBandgap)
112 {
113 tmp32 |= VREF_CSR_HCBGEN_MASK;
114 }
115
116 if (config->enableInternalVoltageRegulator)
117 {
118 tmp32 |= VREF_CSR_REGEN_MASK;
119 }
120
121 if (config->enableChopOscillator)
122 {
123 tmp32 |= (VREF_CSR_REGEN_MASK | VREF_CSR_CHOPEN_MASK);
124 }
125
126 if (config->enableCurvatureCompensation)
127 {
128 tmp32 |= VREF_CSR_ICOMPEN_MASK;
129 }
130
131 if (config->bufferMode == kVREF_ModeLowPowerBuffer)
132 {
133 tmp32 |= VREF_CSR_BUF21EN_MASK;
134 }
135 else
136 {
137 tmp32 |= (VREF_CSR_BUF21EN_MASK | VREF_CSR_HI_PWR_LV_MASK);
138 }
139
140 base->CSR |= tmp32;
141 /* After enabling high accurancy bandgap, delay 400 us. */
142 SDK_DelayAtLeastUs(400U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
143 }
144 }
145
146 /*!
147 * brief Stops and disables the clock for the VREF module.
148 *
149 * This function should be called to shut down the module.
150 * This is an example.
151 * code
152 * vref_config_t vrefUserConfig;
153 * VREF_GetDefaultConfig(VREF, &vrefUserConfig);
154 * VREF_Init(VREF, &vrefUserConfig);
155 * ...
156 * VREF_Deinit(VREF);
157 * endcode
158 *
159 * param base VREF peripheral address.
160 */
VREF_Deinit(VREF_Type * base)161 void VREF_Deinit(VREF_Type *base)
162 {
163 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
164 /* Gate clock for VREF */
165 CLOCK_DisableClock(s_vrefClocks[VREF_GetInstance(base)]);
166 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
167 }
168
169 /*!
170 * brief Initializes the VREF configuration structure.
171 *
172 * This function initializes the VREF configuration structure to default values.
173 * This is an example.
174 * code
175 * config->bufferMode = kVREF_ModeHighPowerBuffer;
176 * config->enableInternalVoltageRegulator = true;
177 * config->enableChopOscillator = true;
178 * config->enableHCBandgap = true;
179 * config->enableCurvatureCompensation = true;
180 * config->enableLowPowerBuff = true;
181 * endcode
182 *
183 * param config Pointer to the initialization structure.
184 */
VREF_GetDefaultConfig(vref_config_t * config)185 void VREF_GetDefaultConfig(vref_config_t *config)
186 {
187 assert(NULL != config);
188
189 /* Initializes the configure structure to zero. */
190 (void)memset(config, 0, sizeof(*config));
191
192 config->bufferMode = kVREF_ModeHighPowerBuffer;
193 config->enableInternalVoltageRegulator = true;
194 config->enableChopOscillator = true;
195 config->enableHCBandgap = true;
196 config->enableCurvatureCompensation = true;
197 config->enableLowPowerBuff = true;
198 }
199
200 /*!
201 * brief Sets a TRIM value for the accurate 1.0V bandgap output.
202 *
203 * This function sets a TRIM value for the reference voltage. It will trim the accurate 1.0V bandgap by 0.5mV each step.
204 *
205 * param base VREF peripheral address.
206 * param trimValue Value of the trim register to set the output reference voltage (maximum 0x3F (6-bit)).
207 */
VREF_SetVrefTrimVal(VREF_Type * base,uint8_t trimValue)208 void VREF_SetVrefTrimVal(VREF_Type *base, uint8_t trimValue)
209 {
210 uint32_t tmp32 = base->UTRIM;
211
212 tmp32 &= (~VREF_UTRIM_VREFTRIM_MASK);
213 tmp32 |= VREF_UTRIM_VREFTRIM(trimValue);
214
215 base->UTRIM = tmp32;
216
217 if (VREF_CSR_CHOPEN_MASK == (base->CSR & VREF_CSR_CHOPEN_MASK))
218 {
219 /* After enabling high accurancy bandgap, delay 400 us. */
220 SDK_DelayAtLeastUs(400U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
221 }
222 else
223 {
224 /*Wait internal HC voltage reference stable*/
225 /*
226 * $Branch Coverage Justification$
227 * while ((base->CSR & VREF_CSR_VREFST_MASK) != 0U) not covered. Test unfeasible,
228 * the internal HC voltage stable state is too short not to catch.
229 */
230 while ((base->CSR & VREF_CSR_VREFST_MASK) == 0U)
231 {
232 }
233 }
234 }
235
236 /*!
237 * brief Sets a TRIM value for the accurate buffered VREF output.
238 *
239 * This function sets a TRIM value for the reference voltage. If buffer mode be set to other values (Buf21
240 * enabled), it will trim the VREF_OUT by 0.1V each step from 1.0V to 2.1V.
241 *
242 * note When Buf21 is enabled, the value of UTRIM[TRIM2V1] should be ranged from 0b0000 to 0b1011 in order to trim the
243 * output voltage from 1.0V to 2.1V, other values will make the VREF_OUT to default value, 1.0V.
244 *
245 * param base VREF peripheral address.
246 * param trim21Value Value of the trim register to set the output reference voltage (maximum 0xF (4-bit)).
247 */
VREF_SetTrim21Val(VREF_Type * base,uint8_t trim21Value)248 void VREF_SetTrim21Val(VREF_Type *base, uint8_t trim21Value)
249 {
250 uint32_t tmp32 = base->UTRIM;
251
252 tmp32 &= (~VREF_UTRIM_TRIM2V1_MASK);
253 tmp32 |= VREF_UTRIM_TRIM2V1(trim21Value);
254
255 base->UTRIM = tmp32;
256
257 if (VREF_CSR_CHOPEN_MASK == (base->CSR & VREF_CSR_CHOPEN_MASK))
258 {
259 /* After enabling high accurancy bandgap, delay 400 us. */
260 SDK_DelayAtLeastUs(400U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
261 }
262 else
263 {
264 /*Wait internal HC voltage reference stable*/
265 /*
266 * $Branch Coverage Justification$
267 * while ((base->CSR & VREF_CSR_VREFST_MASK) != 0U) not covered. Test unfeasible,
268 * the internal HC voltage stable state is too short not to catch.
269 */
270 while ((base->CSR & VREF_CSR_VREFST_MASK) == 0U)
271 {
272 }
273 }
274 }
275
276 /*!
277 * brief Reads the VREF trim value.
278 *
279 * This function gets the TRIM value from the UTRIM register. It reads UTRIM[VREFTRIM] (13:8)
280 *
281 * param base VREF peripheral address.
282 * return 6-bit value of trim setting.
283 */
VREF_GetVrefTrimVal(VREF_Type * base)284 uint8_t VREF_GetVrefTrimVal(VREF_Type *base)
285 {
286 uint8_t trimValue;
287
288 trimValue = (uint8_t)((base->UTRIM & VREF_UTRIM_VREFTRIM_MASK) >> VREF_UTRIM_VREFTRIM_SHIFT);
289
290 return trimValue;
291 }
292
293 /*!
294 * brief Reads the VREF 2.1V trim value.
295 *
296 * This function gets the TRIM value from the UTRIM register. It reads UTRIM[TRIM2V1] (3:0),
297 *
298 * param base VREF peripheral address.
299 * return 4-bit value of trim setting.
300 */
VREF_GetTrim21Val(VREF_Type * base)301 uint8_t VREF_GetTrim21Val(VREF_Type *base)
302 {
303 uint8_t trimValue;
304
305 trimValue = (uint8_t)((base->UTRIM & VREF_UTRIM_TRIM2V1_MASK) >> VREF_UTRIM_TRIM2V1_SHIFT);
306
307 return trimValue;
308 }
309
