1 /*
2 * Copyright (c) 2017 Christer Weinigel.
3 * Copyright (c) 2017, I-SENSE group of ICCS
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 /**
9 * @file
10 * @brief USB device controller shim driver for STM32 devices
11 *
12 * This driver uses the STM32 Cube low level drivers to talk to the USB
13 * device controller on the STM32 family of devices using the
14 * STM32Cube HAL layer.
15 */
16
17 #include <soc.h>
18 #include <stm32_ll_bus.h>
19 #include <stm32_ll_pwr.h>
20 #include <stm32_ll_rcc.h>
21 #include <stm32_ll_system.h>
22 #include <string.h>
23 #include <zephyr/usb/usb_device.h>
24 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
25 #include <zephyr/sys/util.h>
26 #include <zephyr/drivers/gpio.h>
27 #include <zephyr/drivers/pinctrl.h>
28 #include "stm32_hsem.h"
29
30 #define LOG_LEVEL CONFIG_USB_DRIVER_LOG_LEVEL
31 #include <zephyr/logging/log.h>
32 #include <zephyr/irq.h>
33 LOG_MODULE_REGISTER(usb_dc_stm32);
34
35 #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otgfs) && DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otghs)
36 #error "Only one interface should be enabled at a time, OTG FS or OTG HS"
37 #endif
38
39 /*
40 * Vbus sensing is determined based on the presence of the hardware detection
41 * pin(s) in the device tree. E.g: pinctrl-0 = <&usb_otg_fs_vbus_pa9 ...>;
42 *
43 * The detection pins are dependent on the enabled USB driver and the physical
44 * interface(s) offered by the hardware. These are mapped to PA9 and/or PB13
45 * (subject to MCU), being the former the most widespread option.
46 */
47 #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otghs)
48 #define DT_DRV_COMPAT st_stm32_otghs
49 #define USB_IRQ_NAME otghs
50 #define USB_VBUS_SENSING (DT_NODE_EXISTS(DT_CHILD(DT_NODELABEL(pinctrl), usb_otg_hs_vbus_pa9)) || \
51 DT_NODE_EXISTS(DT_CHILD(DT_NODELABEL(pinctrl), usb_otg_hs_vbus_pb13)))
52 #elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otgfs)
53 #define DT_DRV_COMPAT st_stm32_otgfs
54 #define USB_IRQ_NAME otgfs
55 #define USB_VBUS_SENSING DT_NODE_EXISTS(DT_CHILD(DT_NODELABEL(pinctrl), usb_otg_fs_vbus_pa9))
56 #elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32_usb)
57 #define DT_DRV_COMPAT st_stm32_usb
58 #define USB_IRQ_NAME usb
59 #define USB_VBUS_SENSING false
60 #endif
61
62 #define USB_BASE_ADDRESS DT_INST_REG_ADDR(0)
63 #define USB_IRQ DT_INST_IRQ_BY_NAME(0, USB_IRQ_NAME, irq)
64 #define USB_IRQ_PRI DT_INST_IRQ_BY_NAME(0, USB_IRQ_NAME, priority)
65 #define USB_NUM_BIDIR_ENDPOINTS DT_INST_PROP(0, num_bidir_endpoints)
66 #define USB_RAM_SIZE DT_INST_PROP(0, ram_size)
67
68 static const struct stm32_pclken pclken[] = STM32_DT_INST_CLOCKS(0);
69
70 #if DT_INST_NODE_HAS_PROP(0, maximum_speed)
71 #define USB_MAXIMUM_SPEED DT_INST_PROP(0, maximum_speed)
72 #endif
73
74 PINCTRL_DT_INST_DEFINE(0);
75 static const struct pinctrl_dev_config *usb_pcfg =
76 PINCTRL_DT_INST_DEV_CONFIG_GET(0);
77
78 #define USB_OTG_HS_EMB_PHY (DT_HAS_COMPAT_STATUS_OKAY(st_stm32_usbphyc) && \
79 DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otghs))
80
81 #define USB_OTG_HS_ULPI_PHY (DT_HAS_COMPAT_STATUS_OKAY(usb_ulpi_phy) && \
82 DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otghs))
83
84 #if USB_OTG_HS_ULPI_PHY
85 static const struct gpio_dt_spec ulpi_reset =
86 GPIO_DT_SPEC_GET_OR(DT_PHANDLE(DT_INST(0, st_stm32_otghs), phys), reset_gpios, {0});
87 #endif
88
89 /*
90 * USB, USB_OTG_FS and USB_DRD_FS are defined in STM32Cube HAL and allows to
91 * distinguish between two kind of USB DC. STM32 F0, F3, L0 and G4 series
92 * support USB device controller. STM32 F4 and F7 series support USB_OTG_FS
93 * device controller. STM32 F1 and L4 series support either USB or USB_OTG_FS
94 * device controller.STM32 G0 series supports USB_DRD_FS device controller.
95 *
96 * WARNING: Don't mix USB defined in STM32Cube HAL and CONFIG_USB_* from Zephyr
97 * Kconfig system.
98 */
99 #if defined(USB) || defined(USB_DRD_FS)
100
101 #define EP0_MPS 64U
102 #define EP_MPS 64U
103
104 /*
105 * USB BTABLE is stored in the PMA. The size of BTABLE is 4 bytes
106 * per endpoint.
107 *
108 */
109 #define USB_BTABLE_SIZE (8 * USB_NUM_BIDIR_ENDPOINTS)
110
111 #else /* USB_OTG_FS */
112
113 /*
114 * STM32L4 series USB LL API doesn't provide HIGH and HIGH_IN_FULL speed
115 * defines.
116 */
117 #if defined(CONFIG_SOC_SERIES_STM32L4X)
118 #define USB_OTG_SPEED_HIGH 0U
119 #define USB_OTG_SPEED_HIGH_IN_FULL 1U
120 #endif /* CONFIG_SOC_SERIES_STM32L4X */
121
122 #define EP0_MPS USB_OTG_MAX_EP0_SIZE
123
124 #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otghs)
125 #define EP_MPS USB_OTG_HS_MAX_PACKET_SIZE
126 #elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otgfs) || DT_HAS_COMPAT_STATUS_OKAY(st_stm32_usb)
127 #define EP_MPS USB_OTG_FS_MAX_PACKET_SIZE
128 #endif
129
130 /* We need n TX IN FIFOs */
131 #define TX_FIFO_NUM USB_NUM_BIDIR_ENDPOINTS
132
133 /* We need a minimum size for RX FIFO */
134 #define USB_FIFO_RX_MIN 160
135
136 /* 4-byte words TX FIFO */
137 #define TX_FIFO_WORDS ((USB_RAM_SIZE - USB_FIFO_RX_MIN - 64) / 4)
138
139 /* Allocate FIFO memory evenly between the TX FIFOs */
140 /* except the first TX endpoint need only 64 bytes */
141 #define TX_FIFO_EP_WORDS (TX_FIFO_WORDS / (TX_FIFO_NUM - 1))
142
143 #endif /* USB */
144
145 /* Size of a USB SETUP packet */
146 #define SETUP_SIZE 8
147
148 /* Helper macros to make it easier to work with endpoint numbers */
149 #define EP0_IDX 0
150 #define EP0_IN (EP0_IDX | USB_EP_DIR_IN)
151 #define EP0_OUT (EP0_IDX | USB_EP_DIR_OUT)
152
153 /* Endpoint state */
154 struct usb_dc_stm32_ep_state {
155 uint16_t ep_mps; /** Endpoint max packet size */
156 uint16_t ep_pma_buf_len; /** Previously allocated buffer size */
157 uint8_t ep_type; /** Endpoint type (STM32 HAL enum) */
158 uint8_t ep_stalled; /** Endpoint stall flag */
159 usb_dc_ep_callback cb; /** Endpoint callback function */
160 uint32_t read_count; /** Number of bytes in read buffer */
161 uint32_t read_offset; /** Current offset in read buffer */
162 struct k_sem write_sem; /** Write boolean semaphore */
163 };
164
165 /* Driver state */
166 struct usb_dc_stm32_state {
167 PCD_HandleTypeDef pcd; /* Storage for the HAL_PCD api */
168 usb_dc_status_callback status_cb; /* Status callback */
169 struct usb_dc_stm32_ep_state out_ep_state[USB_NUM_BIDIR_ENDPOINTS];
170 struct usb_dc_stm32_ep_state in_ep_state[USB_NUM_BIDIR_ENDPOINTS];
171 uint8_t ep_buf[USB_NUM_BIDIR_ENDPOINTS][EP_MPS];
172
173 #if defined(USB) || defined(USB_DRD_FS)
174 uint32_t pma_offset;
175 #endif /* USB */
176 };
177
178 static struct usb_dc_stm32_state usb_dc_stm32_state;
179
180 /* Internal functions */
181
usb_dc_stm32_get_ep_state(uint8_t ep)182 static struct usb_dc_stm32_ep_state *usb_dc_stm32_get_ep_state(uint8_t ep)
183 {
184 struct usb_dc_stm32_ep_state *ep_state_base;
185
186 if (USB_EP_GET_IDX(ep) >= USB_NUM_BIDIR_ENDPOINTS) {
187 return NULL;
188 }
189
190 if (USB_EP_DIR_IS_OUT(ep)) {
191 ep_state_base = usb_dc_stm32_state.out_ep_state;
192 } else {
193 ep_state_base = usb_dc_stm32_state.in_ep_state;
194 }
195
196 return ep_state_base + USB_EP_GET_IDX(ep);
197 }
198
usb_dc_stm32_isr(const void * arg)199 static void usb_dc_stm32_isr(const void *arg)
200 {
201 HAL_PCD_IRQHandler(&usb_dc_stm32_state.pcd);
202 }
203
204 #ifdef CONFIG_USB_DEVICE_SOF
HAL_PCD_SOFCallback(PCD_HandleTypeDef * hpcd)205 void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
206 {
207 usb_dc_stm32_state.status_cb(USB_DC_SOF, NULL);
208 }
209 #endif
210
usb_dc_stm32_clock_enable(void)211 static int usb_dc_stm32_clock_enable(void)
212 {
213 const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
214
215 if (!device_is_ready(clk)) {
216 LOG_ERR("clock control device not ready");
217 return -ENODEV;
218 }
219
220 #if defined(PWR_USBSCR_USB33SV) || defined(PWR_SVMCR_USV)
221
222 /*
223 * VDDUSB independent USB supply (PWR clock is on)
224 * with LL_PWR_EnableVDDUSB function (higher case)
225 */
226 LL_PWR_EnableVDDUSB();
227 #endif /* PWR_USBSCR_USB33SV or PWR_SVMCR_USV */
228
229 if (DT_INST_NUM_CLOCKS(0) > 1) {
230 if (clock_control_configure(clk, (clock_control_subsys_t)&pclken[1],
231 NULL) != 0) {
232 LOG_ERR("Could not select USB domain clock");
233 return -EIO;
234 }
235 }
236
237 if (clock_control_on(clk, (clock_control_subsys_t)&pclken[0]) != 0) {
238 LOG_ERR("Unable to enable USB clock");
239 return -EIO;
240 }
241
242 if (IS_ENABLED(CONFIG_USB_DC_STM32_CLOCK_CHECK)) {
243 uint32_t usb_clock_rate;
244
245 if (clock_control_get_rate(clk,
246 (clock_control_subsys_t)&pclken[1],
247 &usb_clock_rate) != 0) {
248 LOG_ERR("Failed to get USB domain clock rate");
249 return -EIO;
250 }
251
252 if (usb_clock_rate != MHZ(48)) {
253 LOG_ERR("USB Clock is not 48MHz (%d)", usb_clock_rate);
254 return -ENOTSUP;
255 }
256 }
257
258 /* Previous check won't work in case of F1/F3. Add build time check */
259 #if defined(RCC_CFGR_OTGFSPRE) || defined(RCC_CFGR_USBPRE)
260
261 #if (MHZ(48) == CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC) && !defined(STM32_PLL_USBPRE)
262 /* PLL output clock is set to 48MHz, it should not be divided */
263 #warning USBPRE/OTGFSPRE should be set in rcc node
264 #endif
265
266 #endif /* RCC_CFGR_OTGFSPRE / RCC_CFGR_USBPRE */
267
268 #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otghs)
269 #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_usbphyc)
270 LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_OTGHSULPI);
271 LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_OTGPHYC);
272 #elif defined(CONFIG_SOC_SERIES_STM32H7X)
273 #if !USB_OTG_HS_ULPI_PHY
274 /* Disable ULPI interface (for external high-speed PHY) clock in sleep
275 * mode.
276 */
277 LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI);
278 #endif
279 #else
280 /* Disable ULPI interface (for external high-speed PHY) clock in low
281 * power mode. It is disabled by default in run power mode, no need to
282 * disable it.
283 */
284 LL_AHB1_GRP1_DisableClockLowPower(LL_AHB1_GRP1_PERIPH_OTGHSULPI);
285 #endif
286 #endif
287
288 return 0;
289 }
290
usb_dc_stm32_clock_disable(void)291 static int usb_dc_stm32_clock_disable(void)
292 {
293 const struct device *clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
294
295 if (clock_control_off(clk, (clock_control_subsys_t)&pclken[0]) != 0) {
296 LOG_ERR("Unable to disable USB clock");
297 return -EIO;
298 }
299
300 return 0;
301 }
302
303 #if defined(USB_OTG_FS) || defined(USB_OTG_HS)
usb_dc_stm32_get_maximum_speed(void)304 static uint32_t usb_dc_stm32_get_maximum_speed(void)
305 {
306 /*
307 * If max-speed is not passed via DT, set it to USB controller's
308 * maximum hardware capability.
309 */
310 #if USB_OTG_HS_EMB_PHY || USB_OTG_HS_ULPI_PHY
311 uint32_t speed = USB_OTG_SPEED_HIGH;
312 #else
313 uint32_t speed = USB_OTG_SPEED_FULL;
314 #endif
315
316 #ifdef USB_MAXIMUM_SPEED
317
318 if (!strncmp(USB_MAXIMUM_SPEED, "high-speed", 10)) {
319 speed = USB_OTG_SPEED_HIGH;
320 } else if (!strncmp(USB_MAXIMUM_SPEED, "full-speed", 10)) {
321 #if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(USB_OTG_HS_EMB_PHY)
322 speed = USB_OTG_SPEED_HIGH_IN_FULL;
323 #else
324 speed = USB_OTG_SPEED_FULL;
325 #endif
326 } else {
327 LOG_DBG("Unsupported maximum speed defined in device tree. "
328 "USB controller will default to its maximum HW "
329 "capability");
330 }
331 #endif
332
333 return speed;
334 }
335 #endif /* USB_OTG_FS || USB_OTG_HS */
336
usb_dc_stm32_init(void)337 static int usb_dc_stm32_init(void)
338 {
339 HAL_StatusTypeDef status;
340 int ret;
341 unsigned int i;
342
343 #if defined(USB) || defined(USB_DRD_FS)
344 #ifdef USB
345 usb_dc_stm32_state.pcd.Instance = USB;
346 #else
347 usb_dc_stm32_state.pcd.Instance = USB_DRD_FS;
348 #endif
349 usb_dc_stm32_state.pcd.Init.speed = PCD_SPEED_FULL;
350 usb_dc_stm32_state.pcd.Init.dev_endpoints = USB_NUM_BIDIR_ENDPOINTS;
351 usb_dc_stm32_state.pcd.Init.phy_itface = PCD_PHY_EMBEDDED;
352 usb_dc_stm32_state.pcd.Init.ep0_mps = PCD_EP0MPS_64;
353 usb_dc_stm32_state.pcd.Init.low_power_enable = 0;
354 #else /* USB_OTG_FS || USB_OTG_HS */
355 #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otghs)
356 usb_dc_stm32_state.pcd.Instance = USB_OTG_HS;
357 #else
358 usb_dc_stm32_state.pcd.Instance = USB_OTG_FS;
359 #endif
360 usb_dc_stm32_state.pcd.Init.dev_endpoints = USB_NUM_BIDIR_ENDPOINTS;
361 usb_dc_stm32_state.pcd.Init.speed = usb_dc_stm32_get_maximum_speed();
362 #if USB_OTG_HS_EMB_PHY
363 usb_dc_stm32_state.pcd.Init.phy_itface = USB_OTG_HS_EMBEDDED_PHY;
364 #elif USB_OTG_HS_ULPI_PHY
365 usb_dc_stm32_state.pcd.Init.phy_itface = USB_OTG_ULPI_PHY;
366 #else
367 usb_dc_stm32_state.pcd.Init.phy_itface = PCD_PHY_EMBEDDED;
368 #endif
369 usb_dc_stm32_state.pcd.Init.ep0_mps = USB_OTG_MAX_EP0_SIZE;
370 usb_dc_stm32_state.pcd.Init.vbus_sensing_enable = USB_VBUS_SENSING ? ENABLE : DISABLE;
371
372 #ifndef CONFIG_SOC_SERIES_STM32F1X
373 usb_dc_stm32_state.pcd.Init.dma_enable = DISABLE;
374 #endif
375
376 #endif /* USB */
377
378 #ifdef CONFIG_USB_DEVICE_SOF
379 usb_dc_stm32_state.pcd.Init.Sof_enable = 1;
380 #endif /* CONFIG_USB_DEVICE_SOF */
381
382 #if defined(CONFIG_SOC_SERIES_STM32H7X)
383 #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otgfs)
384 /* The USB2 controller only works in FS mode, but the ULPI clock needs
385 * to be disabled in sleep mode for it to work. For the USB1
386 * controller, as it is an HS one, the clock is disabled in the common
387 * path.
388 */
389
390 LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI);
391 #endif
392
393 LL_PWR_EnableUSBVoltageDetector();
394
395 /* Per AN2606: USBREGEN not supported when running in FS mode. */
396 LL_PWR_DisableUSBReg();
397 while (!LL_PWR_IsActiveFlag_USB()) {
398 LOG_INF("PWR not active yet");
399 k_sleep(K_MSEC(100));
400 }
401 #endif
402
403 LOG_DBG("Pinctrl signals configuration");
404 ret = pinctrl_apply_state(usb_pcfg, PINCTRL_STATE_DEFAULT);
405 if (ret < 0) {
406 LOG_ERR("USB pinctrl setup failed (%d)", ret);
407 return ret;
408 }
409
410 LOG_DBG("HAL_PCD_Init");
411 status = HAL_PCD_Init(&usb_dc_stm32_state.pcd);
412 if (status != HAL_OK) {
413 LOG_ERR("PCD_Init failed, %d", (int)status);
414 return -EIO;
415 }
416
417 /* On a soft reset force USB to reset first and switch it off
418 * so the USB connection can get re-initialized
419 */
420 LOG_DBG("HAL_PCD_Stop");
421 status = HAL_PCD_Stop(&usb_dc_stm32_state.pcd);
422 if (status != HAL_OK) {
423 LOG_ERR("PCD_Stop failed, %d", (int)status);
424 return -EIO;
425 }
426
427 LOG_DBG("HAL_PCD_Start");
428 status = HAL_PCD_Start(&usb_dc_stm32_state.pcd);
429 if (status != HAL_OK) {
430 LOG_ERR("PCD_Start failed, %d", (int)status);
431 return -EIO;
432 }
433
434 usb_dc_stm32_state.out_ep_state[EP0_IDX].ep_mps = EP0_MPS;
435 usb_dc_stm32_state.out_ep_state[EP0_IDX].ep_type = EP_TYPE_CTRL;
436 usb_dc_stm32_state.in_ep_state[EP0_IDX].ep_mps = EP0_MPS;
437 usb_dc_stm32_state.in_ep_state[EP0_IDX].ep_type = EP_TYPE_CTRL;
438
439 #if defined(USB) || defined(USB_DRD_FS)
440 /* Start PMA configuration for the endpoints after the BTABLE. */
441 usb_dc_stm32_state.pma_offset = USB_BTABLE_SIZE;
442
443 for (i = 0U; i < USB_NUM_BIDIR_ENDPOINTS; i++) {
444 k_sem_init(&usb_dc_stm32_state.in_ep_state[i].write_sem, 1, 1);
445 }
446 #else /* USB_OTG_FS */
447
448 /* TODO: make this dynamic (depending usage) */
449 HAL_PCDEx_SetRxFiFo(&usb_dc_stm32_state.pcd, USB_FIFO_RX_MIN);
450 for (i = 0U; i < USB_NUM_BIDIR_ENDPOINTS; i++) {
451 if (i == 0) {
452 /* first endpoint need only 64 byte for EP_TYPE_CTRL */
453 HAL_PCDEx_SetTxFiFo(&usb_dc_stm32_state.pcd, i, 16);
454 } else {
455 HAL_PCDEx_SetTxFiFo(&usb_dc_stm32_state.pcd, i,
456 TX_FIFO_EP_WORDS);
457 }
458 k_sem_init(&usb_dc_stm32_state.in_ep_state[i].write_sem, 1, 1);
459 }
460 #endif /* USB */
461
462 IRQ_CONNECT(USB_IRQ, USB_IRQ_PRI,
463 usb_dc_stm32_isr, 0, 0);
464 irq_enable(USB_IRQ);
465 return 0;
466 }
467
468 /* Zephyr USB device controller API implementation */
469
usb_dc_attach(void)470 int usb_dc_attach(void)
471 {
472 int ret;
473
474 LOG_DBG("");
475
476 #ifdef SYSCFG_CFGR1_USB_IT_RMP
477 /*
478 * STM32F302/F303: USB IRQ collides with CAN_1 IRQ (§14.1.3, RM0316)
479 * Remap IRQ by default to enable use of both IPs simultaneoulsy
480 * This should be done before calling any HAL function
481 */
482 if (LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_SYSCFG)) {
483 LL_SYSCFG_EnableRemapIT_USB();
484 } else {
485 LOG_ERR("System Configuration Controller clock is "
486 "disabled. Unable to enable IRQ remapping.");
487 }
488 #endif
489
490 #if USB_OTG_HS_ULPI_PHY
491 if (ulpi_reset.port != NULL) {
492 if (!gpio_is_ready_dt(&ulpi_reset)) {
493 LOG_ERR("Reset GPIO device not ready");
494 return -EINVAL;
495 }
496 if (gpio_pin_configure_dt(&ulpi_reset, GPIO_OUTPUT_INACTIVE)) {
497 LOG_ERR("Couldn't configure reset pin");
498 return -EIO;
499 }
500 }
501 #endif
502
503 ret = usb_dc_stm32_clock_enable();
504 if (ret) {
505 return ret;
506 }
507
508 ret = usb_dc_stm32_init();
509 if (ret) {
510 return ret;
511 }
512
513 /*
514 * Required for at least STM32L4 devices as they electrically
515 * isolate USB features from VddUSB. It must be enabled before
516 * USB can function. Refer to section 5.1.3 in DM00083560 or
517 * DM00310109.
518 */
519 #ifdef PWR_CR2_USV
520 #if defined(LL_APB1_GRP1_PERIPH_PWR)
521 if (LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_PWR)) {
522 LL_PWR_EnableVddUSB();
523 } else {
524 LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
525 LL_PWR_EnableVddUSB();
526 LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_PWR);
527 }
528 #else
529 LL_PWR_EnableVddUSB();
530 #endif /* defined(LL_APB1_GRP1_PERIPH_PWR) */
531 #endif /* PWR_CR2_USV */
532
533 return 0;
534 }
535
usb_dc_ep_set_callback(const uint8_t ep,const usb_dc_ep_callback cb)536 int usb_dc_ep_set_callback(const uint8_t ep, const usb_dc_ep_callback cb)
537 {
538 struct usb_dc_stm32_ep_state *ep_state = usb_dc_stm32_get_ep_state(ep);
539
540 LOG_DBG("ep 0x%02x", ep);
541
542 if (!ep_state) {
543 return -EINVAL;
544 }
545
546 ep_state->cb = cb;
547
548 return 0;
549 }
550
usb_dc_set_status_callback(const usb_dc_status_callback cb)551 void usb_dc_set_status_callback(const usb_dc_status_callback cb)
552 {
553 LOG_DBG("");
554
555 usb_dc_stm32_state.status_cb = cb;
556 }
557
usb_dc_set_address(const uint8_t addr)558 int usb_dc_set_address(const uint8_t addr)
559 {
560 HAL_StatusTypeDef status;
561
562 LOG_DBG("addr %u (0x%02x)", addr, addr);
563
564 status = HAL_PCD_SetAddress(&usb_dc_stm32_state.pcd, addr);
565 if (status != HAL_OK) {
566 LOG_ERR("HAL_PCD_SetAddress failed(0x%02x), %d", addr,
567 (int)status);
568 return -EIO;
569 }
570
571 return 0;
572 }
573
usb_dc_ep_start_read(uint8_t ep,uint8_t * data,uint32_t max_data_len)574 int usb_dc_ep_start_read(uint8_t ep, uint8_t *data, uint32_t max_data_len)
575 {
576 HAL_StatusTypeDef status;
577
578 LOG_DBG("ep 0x%02x, len %u", ep, max_data_len);
579
580 /* we flush EP0_IN by doing a 0 length receive on it */
581 if (!USB_EP_DIR_IS_OUT(ep) && (ep != EP0_IN || max_data_len)) {
582 LOG_ERR("invalid ep 0x%02x", ep);
583 return -EINVAL;
584 }
585
586 if (max_data_len > EP_MPS) {
587 max_data_len = EP_MPS;
588 }
589
590 status = HAL_PCD_EP_Receive(&usb_dc_stm32_state.pcd, ep,
591 usb_dc_stm32_state.ep_buf[USB_EP_GET_IDX(ep)],
592 max_data_len);
593 if (status != HAL_OK) {
594 LOG_ERR("HAL_PCD_EP_Receive failed(0x%02x), %d", ep,
595 (int)status);
596 return -EIO;
597 }
598
599 return 0;
600 }
601
usb_dc_ep_get_read_count(uint8_t ep,uint32_t * read_bytes)602 int usb_dc_ep_get_read_count(uint8_t ep, uint32_t *read_bytes)
603 {
604 if (!USB_EP_DIR_IS_OUT(ep) || !read_bytes) {
605 LOG_ERR("invalid ep 0x%02x", ep);
606 return -EINVAL;
607 }
608
609 *read_bytes = HAL_PCD_EP_GetRxCount(&usb_dc_stm32_state.pcd, ep);
610
611 return 0;
612 }
613
usb_dc_ep_check_cap(const struct usb_dc_ep_cfg_data * const cfg)614 int usb_dc_ep_check_cap(const struct usb_dc_ep_cfg_data * const cfg)
615 {
616 uint8_t ep_idx = USB_EP_GET_IDX(cfg->ep_addr);
617
618 LOG_DBG("ep %x, mps %d, type %d", cfg->ep_addr, cfg->ep_mps,
619 cfg->ep_type);
620
621 if ((cfg->ep_type == USB_DC_EP_CONTROL) && ep_idx) {
622 LOG_ERR("invalid endpoint configuration");
623 return -1;
624 }
625
626 if (ep_idx > (USB_NUM_BIDIR_ENDPOINTS - 1)) {
627 LOG_ERR("endpoint index/address out of range");
628 return -1;
629 }
630
631 return 0;
632 }
633
usb_dc_ep_configure(const struct usb_dc_ep_cfg_data * const ep_cfg)634 int usb_dc_ep_configure(const struct usb_dc_ep_cfg_data * const ep_cfg)
635 {
636 uint8_t ep = ep_cfg->ep_addr;
637 struct usb_dc_stm32_ep_state *ep_state = usb_dc_stm32_get_ep_state(ep);
638
639 if (!ep_state) {
640 return -EINVAL;
641 }
642
643 LOG_DBG("ep 0x%02x, previous ep_mps %u, ep_mps %u, ep_type %u",
644 ep_cfg->ep_addr, ep_state->ep_mps, ep_cfg->ep_mps,
645 ep_cfg->ep_type);
646 #if defined(USB) || defined(USB_DRD_FS)
647 if (ep_cfg->ep_mps > ep_state->ep_pma_buf_len) {
648 if (ep_cfg->ep_type == USB_DC_EP_ISOCHRONOUS) {
649 if (USB_RAM_SIZE <=
650 (usb_dc_stm32_state.pma_offset + ep_cfg->ep_mps*2)) {
651 return -EINVAL;
652 }
653 } else if (USB_RAM_SIZE <=
654 (usb_dc_stm32_state.pma_offset + ep_cfg->ep_mps)) {
655 return -EINVAL;
656 }
657
658 if (ep_cfg->ep_type == USB_DC_EP_ISOCHRONOUS) {
659 HAL_PCDEx_PMAConfig(&usb_dc_stm32_state.pcd, ep, PCD_DBL_BUF,
660 usb_dc_stm32_state.pma_offset +
661 ((usb_dc_stm32_state.pma_offset + ep_cfg->ep_mps) << 16));
662 ep_state->ep_pma_buf_len = ep_cfg->ep_mps*2;
663 usb_dc_stm32_state.pma_offset += ep_cfg->ep_mps*2;
664 } else {
665 HAL_PCDEx_PMAConfig(&usb_dc_stm32_state.pcd, ep, PCD_SNG_BUF,
666 usb_dc_stm32_state.pma_offset);
667 ep_state->ep_pma_buf_len = ep_cfg->ep_mps;
668 usb_dc_stm32_state.pma_offset += ep_cfg->ep_mps;
669 }
670 }
671 if (ep_cfg->ep_type == USB_DC_EP_ISOCHRONOUS) {
672 ep_state->ep_mps = ep_cfg->ep_mps*2;
673 } else {
674 ep_state->ep_mps = ep_cfg->ep_mps;
675 }
676 #else
677 ep_state->ep_mps = ep_cfg->ep_mps;
678 #endif
679
680 switch (ep_cfg->ep_type) {
681 case USB_DC_EP_CONTROL:
682 ep_state->ep_type = EP_TYPE_CTRL;
683 break;
684 case USB_DC_EP_ISOCHRONOUS:
685 ep_state->ep_type = EP_TYPE_ISOC;
686 break;
687 case USB_DC_EP_BULK:
688 ep_state->ep_type = EP_TYPE_BULK;
689 break;
690 case USB_DC_EP_INTERRUPT:
691 ep_state->ep_type = EP_TYPE_INTR;
692 break;
693 default:
694 return -EINVAL;
695 }
696
697 return 0;
698 }
699
usb_dc_ep_set_stall(const uint8_t ep)700 int usb_dc_ep_set_stall(const uint8_t ep)
701 {
702 struct usb_dc_stm32_ep_state *ep_state = usb_dc_stm32_get_ep_state(ep);
703 HAL_StatusTypeDef status;
704
705 LOG_DBG("ep 0x%02x", ep);
706
707 if (!ep_state) {
708 return -EINVAL;
709 }
710
711 status = HAL_PCD_EP_SetStall(&usb_dc_stm32_state.pcd, ep);
712 if (status != HAL_OK) {
713 LOG_ERR("HAL_PCD_EP_SetStall failed(0x%02x), %d", ep,
714 (int)status);
715 return -EIO;
716 }
717
718 ep_state->ep_stalled = 1U;
719
720 return 0;
721 }
722
usb_dc_ep_clear_stall(const uint8_t ep)723 int usb_dc_ep_clear_stall(const uint8_t ep)
724 {
725 struct usb_dc_stm32_ep_state *ep_state = usb_dc_stm32_get_ep_state(ep);
726 HAL_StatusTypeDef status;
727
728 LOG_DBG("ep 0x%02x", ep);
729
730 if (!ep_state) {
731 return -EINVAL;
732 }
733
734 status = HAL_PCD_EP_ClrStall(&usb_dc_stm32_state.pcd, ep);
735 if (status != HAL_OK) {
736 LOG_ERR("HAL_PCD_EP_ClrStall failed(0x%02x), %d", ep,
737 (int)status);
738 return -EIO;
739 }
740
741 ep_state->ep_stalled = 0U;
742 ep_state->read_count = 0U;
743
744 return 0;
745 }
746
usb_dc_ep_is_stalled(const uint8_t ep,uint8_t * const stalled)747 int usb_dc_ep_is_stalled(const uint8_t ep, uint8_t *const stalled)
748 {
749 struct usb_dc_stm32_ep_state *ep_state = usb_dc_stm32_get_ep_state(ep);
750
751 LOG_DBG("ep 0x%02x", ep);
752
753 if (!ep_state || !stalled) {
754 return -EINVAL;
755 }
756
757 *stalled = ep_state->ep_stalled;
758
759 return 0;
760 }
761
usb_dc_ep_enable(const uint8_t ep)762 int usb_dc_ep_enable(const uint8_t ep)
763 {
764 struct usb_dc_stm32_ep_state *ep_state = usb_dc_stm32_get_ep_state(ep);
765 HAL_StatusTypeDef status;
766
767 LOG_DBG("ep 0x%02x", ep);
768
769 if (!ep_state) {
770 return -EINVAL;
771 }
772
773 LOG_DBG("HAL_PCD_EP_Open(0x%02x, %u, %u)", ep, ep_state->ep_mps,
774 ep_state->ep_type);
775
776 status = HAL_PCD_EP_Open(&usb_dc_stm32_state.pcd, ep,
777 ep_state->ep_mps, ep_state->ep_type);
778 if (status != HAL_OK) {
779 LOG_ERR("HAL_PCD_EP_Open failed(0x%02x), %d", ep,
780 (int)status);
781 return -EIO;
782 }
783
784 if (USB_EP_DIR_IS_OUT(ep) && ep != EP0_OUT) {
785 return usb_dc_ep_start_read(ep,
786 usb_dc_stm32_state.ep_buf[USB_EP_GET_IDX(ep)],
787 ep_state->ep_mps);
788 }
789
790 return 0;
791 }
792
usb_dc_ep_disable(const uint8_t ep)793 int usb_dc_ep_disable(const uint8_t ep)
794 {
795 struct usb_dc_stm32_ep_state *ep_state = usb_dc_stm32_get_ep_state(ep);
796 HAL_StatusTypeDef status;
797
798 LOG_DBG("ep 0x%02x", ep);
799
800 if (!ep_state) {
801 return -EINVAL;
802 }
803
804 status = HAL_PCD_EP_Close(&usb_dc_stm32_state.pcd, ep);
805 if (status != HAL_OK) {
806 LOG_ERR("HAL_PCD_EP_Close failed(0x%02x), %d", ep,
807 (int)status);
808 return -EIO;
809 }
810
811 return 0;
812 }
813
usb_dc_ep_write(const uint8_t ep,const uint8_t * const data,const uint32_t data_len,uint32_t * const ret_bytes)814 int usb_dc_ep_write(const uint8_t ep, const uint8_t *const data,
815 const uint32_t data_len, uint32_t * const ret_bytes)
816 {
817 struct usb_dc_stm32_ep_state *ep_state = usb_dc_stm32_get_ep_state(ep);
818 HAL_StatusTypeDef status;
819 uint32_t len = data_len;
820 int ret = 0;
821
822 LOG_DBG("ep 0x%02x, len %u", ep, data_len);
823
824 if (!ep_state || !USB_EP_DIR_IS_IN(ep)) {
825 LOG_ERR("invalid ep 0x%02x", ep);
826 return -EINVAL;
827 }
828
829 ret = k_sem_take(&ep_state->write_sem, K_NO_WAIT);
830 if (ret) {
831 LOG_ERR("Unable to get write lock (%d)", ret);
832 return -EAGAIN;
833 }
834
835 if (!k_is_in_isr()) {
836 irq_disable(USB_IRQ);
837 }
838
839 if (ep == EP0_IN && len > USB_MAX_CTRL_MPS) {
840 len = USB_MAX_CTRL_MPS;
841 }
842
843 status = HAL_PCD_EP_Transmit(&usb_dc_stm32_state.pcd, ep,
844 (void *)data, len);
845 if (status != HAL_OK) {
846 LOG_ERR("HAL_PCD_EP_Transmit failed(0x%02x), %d", ep,
847 (int)status);
848 k_sem_give(&ep_state->write_sem);
849 ret = -EIO;
850 }
851
852 if (!ret && ep == EP0_IN && len > 0) {
853 /* Wait for an empty package as from the host.
854 * This also flushes the TX FIFO to the host.
855 */
856 usb_dc_ep_start_read(ep, NULL, 0);
857 }
858
859 if (!k_is_in_isr()) {
860 irq_enable(USB_IRQ);
861 }
862
863 if (!ret && ret_bytes) {
864 *ret_bytes = len;
865 }
866
867 return ret;
868 }
869
usb_dc_ep_read_wait(uint8_t ep,uint8_t * data,uint32_t max_data_len,uint32_t * read_bytes)870 int usb_dc_ep_read_wait(uint8_t ep, uint8_t *data, uint32_t max_data_len,
871 uint32_t *read_bytes)
872 {
873 struct usb_dc_stm32_ep_state *ep_state = usb_dc_stm32_get_ep_state(ep);
874 uint32_t read_count;
875
876 if (!ep_state) {
877 LOG_ERR("Invalid Endpoint %x", ep);
878 return -EINVAL;
879 }
880
881 read_count = ep_state->read_count;
882
883 LOG_DBG("ep 0x%02x, %u bytes, %u+%u, %p", ep, max_data_len,
884 ep_state->read_offset, read_count, data);
885
886 if (!USB_EP_DIR_IS_OUT(ep)) { /* check if OUT ep */
887 LOG_ERR("Wrong endpoint direction: 0x%02x", ep);
888 return -EINVAL;
889 }
890
891 /* When both buffer and max data to read are zero, just ignore reading
892 * and return available data in buffer. Otherwise, return data
893 * previously stored in the buffer.
894 */
895 if (data) {
896 read_count = MIN(read_count, max_data_len);
897 memcpy(data, usb_dc_stm32_state.ep_buf[USB_EP_GET_IDX(ep)] +
898 ep_state->read_offset, read_count);
899 ep_state->read_count -= read_count;
900 ep_state->read_offset += read_count;
901 } else if (max_data_len) {
902 LOG_ERR("Wrong arguments");
903 }
904
905 if (read_bytes) {
906 *read_bytes = read_count;
907 }
908
909 return 0;
910 }
911
usb_dc_ep_read_continue(uint8_t ep)912 int usb_dc_ep_read_continue(uint8_t ep)
913 {
914 struct usb_dc_stm32_ep_state *ep_state = usb_dc_stm32_get_ep_state(ep);
915
916 if (!ep_state || !USB_EP_DIR_IS_OUT(ep)) { /* Check if OUT ep */
917 LOG_ERR("Not valid endpoint: %02x", ep);
918 return -EINVAL;
919 }
920
921 /* If no more data in the buffer, start a new read transaction.
922 * DataOutStageCallback will called on transaction complete.
923 */
924 if (!ep_state->read_count) {
925 usb_dc_ep_start_read(ep, usb_dc_stm32_state.ep_buf[USB_EP_GET_IDX(ep)],
926 ep_state->ep_mps);
927 }
928
929 return 0;
930 }
931
usb_dc_ep_read(const uint8_t ep,uint8_t * const data,const uint32_t max_data_len,uint32_t * const read_bytes)932 int usb_dc_ep_read(const uint8_t ep, uint8_t *const data, const uint32_t max_data_len,
933 uint32_t * const read_bytes)
934 {
935 if (usb_dc_ep_read_wait(ep, data, max_data_len, read_bytes) != 0) {
936 return -EINVAL;
937 }
938
939 if (usb_dc_ep_read_continue(ep) != 0) {
940 return -EINVAL;
941 }
942
943 return 0;
944 }
945
usb_dc_ep_halt(const uint8_t ep)946 int usb_dc_ep_halt(const uint8_t ep)
947 {
948 return usb_dc_ep_set_stall(ep);
949 }
950
usb_dc_ep_flush(const uint8_t ep)951 int usb_dc_ep_flush(const uint8_t ep)
952 {
953 struct usb_dc_stm32_ep_state *ep_state = usb_dc_stm32_get_ep_state(ep);
954
955 if (!ep_state) {
956 return -EINVAL;
957 }
958
959 LOG_ERR("Not implemented");
960
961 return 0;
962 }
963
usb_dc_ep_mps(const uint8_t ep)964 int usb_dc_ep_mps(const uint8_t ep)
965 {
966 struct usb_dc_stm32_ep_state *ep_state = usb_dc_stm32_get_ep_state(ep);
967
968 if (!ep_state) {
969 return -EINVAL;
970 }
971
972 return ep_state->ep_mps;
973 }
974
usb_dc_wakeup_request(void)975 int usb_dc_wakeup_request(void)
976 {
977 HAL_StatusTypeDef status;
978
979 status = HAL_PCD_ActivateRemoteWakeup(&usb_dc_stm32_state.pcd);
980 if (status != HAL_OK) {
981 return -EAGAIN;
982 }
983
984 /* Must be active from 1ms to 15ms as per reference manual. */
985 k_sleep(K_MSEC(2));
986
987 status = HAL_PCD_DeActivateRemoteWakeup(&usb_dc_stm32_state.pcd);
988 if (status != HAL_OK) {
989 return -EAGAIN;
990 }
991
992 return 0;
993 }
994
usb_dc_detach(void)995 int usb_dc_detach(void)
996 {
997 HAL_StatusTypeDef status;
998 int ret;
999
1000 LOG_DBG("HAL_PCD_DeInit");
1001 status = HAL_PCD_DeInit(&usb_dc_stm32_state.pcd);
1002 if (status != HAL_OK) {
1003 LOG_ERR("PCD_DeInit failed, %d", (int)status);
1004 return -EIO;
1005 }
1006
1007 ret = usb_dc_stm32_clock_disable();
1008 if (ret) {
1009 return ret;
1010 }
1011
1012 if (irq_is_enabled(USB_IRQ)) {
1013 irq_disable(USB_IRQ);
1014 }
1015
1016 return 0;
1017 }
1018
usb_dc_reset(void)1019 int usb_dc_reset(void)
1020 {
1021 LOG_ERR("Not implemented");
1022
1023 return 0;
1024 }
1025
1026 /* Callbacks from the STM32 Cube HAL code */
1027
HAL_PCD_ResetCallback(PCD_HandleTypeDef * hpcd)1028 void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
1029 {
1030 int i;
1031
1032 LOG_DBG("");
1033
1034 HAL_PCD_EP_Open(&usb_dc_stm32_state.pcd, EP0_IN, EP0_MPS, EP_TYPE_CTRL);
1035 HAL_PCD_EP_Open(&usb_dc_stm32_state.pcd, EP0_OUT, EP0_MPS,
1036 EP_TYPE_CTRL);
1037
1038 /* The DataInCallback will never be called at this point for any pending
1039 * transactions. Reset the IN semaphores to prevent perpetual locked state.
1040 * */
1041 for (i = 0; i < USB_NUM_BIDIR_ENDPOINTS; i++) {
1042 k_sem_give(&usb_dc_stm32_state.in_ep_state[i].write_sem);
1043 }
1044
1045 if (usb_dc_stm32_state.status_cb) {
1046 usb_dc_stm32_state.status_cb(USB_DC_RESET, NULL);
1047 }
1048 }
1049
HAL_PCD_ConnectCallback(PCD_HandleTypeDef * hpcd)1050 void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
1051 {
1052 LOG_DBG("");
1053
1054 if (usb_dc_stm32_state.status_cb) {
1055 usb_dc_stm32_state.status_cb(USB_DC_CONNECTED, NULL);
1056 }
1057 }
1058
HAL_PCD_DisconnectCallback(PCD_HandleTypeDef * hpcd)1059 void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
1060 {
1061 LOG_DBG("");
1062
1063 if (usb_dc_stm32_state.status_cb) {
1064 usb_dc_stm32_state.status_cb(USB_DC_DISCONNECTED, NULL);
1065 }
1066 }
1067
HAL_PCD_SuspendCallback(PCD_HandleTypeDef * hpcd)1068 void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
1069 {
1070 LOG_DBG("");
1071
1072 if (usb_dc_stm32_state.status_cb) {
1073 usb_dc_stm32_state.status_cb(USB_DC_SUSPEND, NULL);
1074 }
1075 }
1076
HAL_PCD_ResumeCallback(PCD_HandleTypeDef * hpcd)1077 void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
1078 {
1079 LOG_DBG("");
1080
1081 if (usb_dc_stm32_state.status_cb) {
1082 usb_dc_stm32_state.status_cb(USB_DC_RESUME, NULL);
1083 }
1084 }
1085
HAL_PCD_SetupStageCallback(PCD_HandleTypeDef * hpcd)1086 void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
1087 {
1088 struct usb_setup_packet *setup = (void *)usb_dc_stm32_state.pcd.Setup;
1089 struct usb_dc_stm32_ep_state *ep_state;
1090
1091 LOG_DBG("");
1092
1093 ep_state = usb_dc_stm32_get_ep_state(EP0_OUT); /* can't fail for ep0 */
1094 __ASSERT(ep_state, "No corresponding ep_state for EP0");
1095
1096 ep_state->read_count = SETUP_SIZE;
1097 ep_state->read_offset = 0U;
1098 memcpy(&usb_dc_stm32_state.ep_buf[EP0_IDX],
1099 usb_dc_stm32_state.pcd.Setup, ep_state->read_count);
1100
1101 if (ep_state->cb) {
1102 ep_state->cb(EP0_OUT, USB_DC_EP_SETUP);
1103
1104 if (!(setup->wLength == 0U) &&
1105 usb_reqtype_is_to_device(setup)) {
1106 usb_dc_ep_start_read(EP0_OUT,
1107 usb_dc_stm32_state.ep_buf[EP0_IDX],
1108 setup->wLength);
1109 }
1110 }
1111 }
1112
HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef * hpcd,uint8_t epnum)1113 void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
1114 {
1115 uint8_t ep_idx = USB_EP_GET_IDX(epnum);
1116 uint8_t ep = ep_idx | USB_EP_DIR_OUT;
1117 struct usb_dc_stm32_ep_state *ep_state = usb_dc_stm32_get_ep_state(ep);
1118
1119 LOG_DBG("epnum 0x%02x, rx_count %u", epnum,
1120 HAL_PCD_EP_GetRxCount(&usb_dc_stm32_state.pcd, epnum));
1121
1122 /* Transaction complete, data is now stored in the buffer and ready
1123 * for the upper stack (usb_dc_ep_read to retrieve).
1124 */
1125 usb_dc_ep_get_read_count(ep, &ep_state->read_count);
1126 ep_state->read_offset = 0U;
1127
1128 if (ep_state->cb) {
1129 ep_state->cb(ep, USB_DC_EP_DATA_OUT);
1130 }
1131 }
1132
HAL_PCD_DataInStageCallback(PCD_HandleTypeDef * hpcd,uint8_t epnum)1133 void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
1134 {
1135 uint8_t ep_idx = USB_EP_GET_IDX(epnum);
1136 uint8_t ep = ep_idx | USB_EP_DIR_IN;
1137 struct usb_dc_stm32_ep_state *ep_state = usb_dc_stm32_get_ep_state(ep);
1138
1139 LOG_DBG("epnum 0x%02x", epnum);
1140
1141 __ASSERT(ep_state, "No corresponding ep_state for ep");
1142
1143 k_sem_give(&ep_state->write_sem);
1144
1145 if (ep_state->cb) {
1146 ep_state->cb(ep, USB_DC_EP_DATA_IN);
1147 }
1148 }
1149
1150 #if (defined(USB) || defined(USB_DRD_FS)) && DT_INST_NODE_HAS_PROP(0, disconnect_gpios)
HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef * hpcd,uint8_t state)1151 void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state)
1152 {
1153 struct gpio_dt_spec usb_disconnect = GPIO_DT_SPEC_INST_GET(0, disconnect_gpios);
1154
1155 gpio_pin_configure_dt(&usb_disconnect,
1156 (state ? GPIO_OUTPUT_ACTIVE : GPIO_OUTPUT_INACTIVE));
1157 }
1158 #endif /* USB && DT_INST_NODE_HAS_PROP(0, disconnect_gpios) */
1159
