1 /*
2 * Copyright (c) 2017 Christer Weinigel.
3 * Copyright (c) 2017, I-SENSE group of ICCS
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 /**
9 * @file
10 * @brief USB device controller shim driver for STM32 devices
11 *
12 * This driver uses the STM32 Cube low level drivers to talk to the USB
13 * device controller on the STM32 family of devices using the
14 * STM32Cube HAL layer.
15 */
16
17 #include <soc.h>
18 #include <stm32_ll_bus.h>
19 #include <stm32_ll_pwr.h>
20 #include <stm32_ll_rcc.h>
21 #include <stm32_ll_system.h>
22 #include <string.h>
23 #include <zephyr/usb/usb_device.h>
24 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
25 #include <zephyr/sys/util.h>
26 #include <zephyr/drivers/gpio.h>
27 #include <zephyr/drivers/pinctrl.h>
28 #include "stm32_hsem.h"
29
30 #define LOG_LEVEL CONFIG_USB_DRIVER_LOG_LEVEL
31 #include <zephyr/logging/log.h>
32 #include <zephyr/irq.h>
33 LOG_MODULE_REGISTER(usb_dc_stm32);
34
35 #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otgfs) && DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otghs)
36 #error "Only one interface should be enabled at a time, OTG FS or OTG HS"
37 #endif
38
39 /*
40 * Vbus sensing is determined based on the presence of the hardware detection
41 * pin(s) in the device tree. E.g: pinctrl-0 = <&usb_otg_fs_vbus_pa9 ...>;
42 *
43 * The detection pins are dependent on the enabled USB driver and the physical
44 * interface(s) offered by the hardware. These are mapped to PA9 and/or PB13
45 * (subject to MCU), being the former the most widespread option.
46 */
47 #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otghs)
48 #define DT_DRV_COMPAT st_stm32_otghs
49 #define USB_IRQ_NAME otghs
50 #define USB_VBUS_SENSING (DT_NODE_EXISTS(DT_CHILD(DT_NODELABEL(pinctrl), usb_otg_hs_vbus_pa9)) || \
51 DT_NODE_EXISTS(DT_CHILD(DT_NODELABEL(pinctrl), usb_otg_hs_vbus_pb13)))
52 #elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otgfs)
53 #define DT_DRV_COMPAT st_stm32_otgfs
54 #define USB_IRQ_NAME otgfs
55 #define USB_VBUS_SENSING DT_NODE_EXISTS(DT_CHILD(DT_NODELABEL(pinctrl), usb_otg_fs_vbus_pa9))
56 #elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32_usb)
57 #define DT_DRV_COMPAT st_stm32_usb
58 #define USB_IRQ_NAME usb
59 #define USB_VBUS_SENSING false
60 #endif
61
62 #define USB_BASE_ADDRESS DT_INST_REG_ADDR(0)
63 #define USB_IRQ DT_INST_IRQ_BY_NAME(0, USB_IRQ_NAME, irq)
64 #define USB_IRQ_PRI DT_INST_IRQ_BY_NAME(0, USB_IRQ_NAME, priority)
65 #define USB_NUM_BIDIR_ENDPOINTS DT_INST_PROP(0, num_bidir_endpoints)
66 #define USB_RAM_SIZE DT_INST_PROP(0, ram_size)
67
68 static const struct stm32_pclken pclken[] = STM32_DT_INST_CLOCKS(0);
69
70 #if DT_INST_NODE_HAS_PROP(0, maximum_speed)
71 #define USB_MAXIMUM_SPEED DT_INST_PROP(0, maximum_speed)
72 #endif
73
74 PINCTRL_DT_INST_DEFINE(0);
75 static const struct pinctrl_dev_config *usb_pcfg =
76 PINCTRL_DT_INST_DEV_CONFIG_GET(0);
77
78 #define USB_OTG_HS_EMB_PHY (DT_HAS_COMPAT_STATUS_OKAY(st_stm32_usbphyc) && \
79 DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otghs))
80
81 #define USB_OTG_HS_ULPI_PHY (DT_HAS_COMPAT_STATUS_OKAY(usb_ulpi_phy) && \
82 DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otghs))
83
84 #if USB_OTG_HS_ULPI_PHY
85 static const struct gpio_dt_spec ulpi_reset =
86 GPIO_DT_SPEC_GET_OR(DT_PHANDLE(DT_INST(0, st_stm32_otghs), phys), reset_gpios, {0});
87 #endif
88
89 /*
90 * USB, USB_OTG_FS and USB_DRD_FS are defined in STM32Cube HAL and allows to
91 * distinguish between two kind of USB DC. STM32 F0, F3, L0 and G4 series
92 * support USB device controller. STM32 F4 and F7 series support USB_OTG_FS
93 * device controller. STM32 F1 and L4 series support either USB or USB_OTG_FS
94 * device controller.STM32 G0 series supports USB_DRD_FS device controller.
95 *
96 * WARNING: Don't mix USB defined in STM32Cube HAL and CONFIG_USB_* from Zephyr
97 * Kconfig system.
98 */
99 #if defined(USB) || defined(USB_DRD_FS)
100
101 #define EP0_MPS 64U
102 #define EP_MPS 64U
103
104 /*
105 * USB BTABLE is stored in the PMA. The size of BTABLE is 4 bytes
106 * per endpoint.
107 *
108 */
109 #define USB_BTABLE_SIZE (8 * USB_NUM_BIDIR_ENDPOINTS)
110
111 #else /* USB_OTG_FS */
112
113 /*
114 * STM32L4 series USB LL API doesn't provide HIGH and HIGH_IN_FULL speed
115 * defines.
116 */
117 #if defined(CONFIG_SOC_SERIES_STM32L4X)
118 #define USB_OTG_SPEED_HIGH 0U
119 #define USB_OTG_SPEED_HIGH_IN_FULL 1U
120 #endif /* CONFIG_SOC_SERIES_STM32L4X */
121
122 #define EP0_MPS USB_OTG_MAX_EP0_SIZE
123
124 #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otghs)
125 #define EP_MPS USB_OTG_HS_MAX_PACKET_SIZE
126 #elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otgfs) || DT_HAS_COMPAT_STATUS_OKAY(st_stm32_usb)
127 #define EP_MPS USB_OTG_FS_MAX_PACKET_SIZE
128 #endif
129
130 /* We need one RX FIFO and n TX-IN FIFOs */
131 #define FIFO_NUM (1 + USB_NUM_BIDIR_ENDPOINTS)
132
133 /* 4-byte words FIFO */
134 #define FIFO_WORDS (USB_RAM_SIZE / 4)
135
136 /* Allocate FIFO memory evenly between the FIFOs */
137 #define FIFO_EP_WORDS (FIFO_WORDS / FIFO_NUM)
138
139 #endif /* USB */
140
141 /* Size of a USB SETUP packet */
142 #define SETUP_SIZE 8
143
144 /* Helper macros to make it easier to work with endpoint numbers */
145 #define EP0_IDX 0
146 #define EP0_IN (EP0_IDX | USB_EP_DIR_IN)
147 #define EP0_OUT (EP0_IDX | USB_EP_DIR_OUT)
148
149 /* Endpoint state */
150 struct usb_dc_stm32_ep_state {
151 uint16_t ep_mps; /** Endpoint max packet size */
152 uint16_t ep_pma_buf_len; /** Previously allocated buffer size */
153 uint8_t ep_type; /** Endpoint type (STM32 HAL enum) */
154 uint8_t ep_stalled; /** Endpoint stall flag */
155 usb_dc_ep_callback cb; /** Endpoint callback function */
156 uint32_t read_count; /** Number of bytes in read buffer */
157 uint32_t read_offset; /** Current offset in read buffer */
158 struct k_sem write_sem; /** Write boolean semaphore */
159 };
160
161 /* Driver state */
162 struct usb_dc_stm32_state {
163 PCD_HandleTypeDef pcd; /* Storage for the HAL_PCD api */
164 usb_dc_status_callback status_cb; /* Status callback */
165 struct usb_dc_stm32_ep_state out_ep_state[USB_NUM_BIDIR_ENDPOINTS];
166 struct usb_dc_stm32_ep_state in_ep_state[USB_NUM_BIDIR_ENDPOINTS];
167 uint8_t ep_buf[USB_NUM_BIDIR_ENDPOINTS][EP_MPS];
168
169 #if defined(USB) || defined(USB_DRD_FS)
170 uint32_t pma_offset;
171 #endif /* USB */
172 };
173
174 static struct usb_dc_stm32_state usb_dc_stm32_state;
175
176 /* Internal functions */
177
usb_dc_stm32_get_ep_state(uint8_t ep)178 static struct usb_dc_stm32_ep_state *usb_dc_stm32_get_ep_state(uint8_t ep)
179 {
180 struct usb_dc_stm32_ep_state *ep_state_base;
181
182 if (USB_EP_GET_IDX(ep) >= USB_NUM_BIDIR_ENDPOINTS) {
183 return NULL;
184 }
185
186 if (USB_EP_DIR_IS_OUT(ep)) {
187 ep_state_base = usb_dc_stm32_state.out_ep_state;
188 } else {
189 ep_state_base = usb_dc_stm32_state.in_ep_state;
190 }
191
192 return ep_state_base + USB_EP_GET_IDX(ep);
193 }
194
usb_dc_stm32_isr(const void * arg)195 static void usb_dc_stm32_isr(const void *arg)
196 {
197 HAL_PCD_IRQHandler(&usb_dc_stm32_state.pcd);
198 }
199
200 #ifdef CONFIG_USB_DEVICE_SOF
HAL_PCD_SOFCallback(PCD_HandleTypeDef * hpcd)201 void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
202 {
203 usb_dc_stm32_state.status_cb(USB_DC_SOF, NULL);
204 }
205 #endif
206
usb_dc_stm32_clock_enable(void)207 static int usb_dc_stm32_clock_enable(void)
208 {
209 const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
210
211 if (!device_is_ready(clk)) {
212 LOG_ERR("clock control device not ready");
213 return -ENODEV;
214 }
215
216 #ifdef CONFIG_SOC_SERIES_STM32U5X
217 /* VDDUSB independent USB supply (PWR clock is on) */
218 LL_PWR_EnableVDDUSB();
219 #endif /* CONFIG_SOC_SERIES_STM32U5X */
220
221 if (DT_INST_NUM_CLOCKS(0) > 1) {
222 if (clock_control_configure(clk, (clock_control_subsys_t)&pclken[1],
223 NULL) != 0) {
224 LOG_ERR("Could not select USB domain clock");
225 return -EIO;
226 }
227 }
228
229 if (clock_control_on(clk, (clock_control_subsys_t)&pclken[0]) != 0) {
230 LOG_ERR("Unable to enable USB clock");
231 return -EIO;
232 }
233
234 if (IS_ENABLED(CONFIG_USB_DC_STM32_CLOCK_CHECK)) {
235 uint32_t usb_clock_rate;
236
237 if (clock_control_get_rate(clk,
238 (clock_control_subsys_t)&pclken[1],
239 &usb_clock_rate) != 0) {
240 LOG_ERR("Failed to get USB domain clock rate");
241 return -EIO;
242 }
243
244 if (usb_clock_rate != MHZ(48)) {
245 LOG_ERR("USB Clock is not 48MHz (%d)", usb_clock_rate);
246 return -ENOTSUP;
247 }
248 }
249
250 /* Previous check won't work in case of F1/F3. Add build time check */
251 #if defined(RCC_CFGR_OTGFSPRE) || defined(RCC_CFGR_USBPRE)
252
253 #if (MHZ(48) == CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC) && !defined(STM32_PLL_USBPRE)
254 /* PLL output clock is set to 48MHz, it should not be divided */
255 #warning USBPRE/OTGFSPRE should be set in rcc node
256 #endif
257
258 #endif /* RCC_CFGR_OTGFSPRE / RCC_CFGR_USBPRE */
259
260 #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otghs)
261 #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_usbphyc)
262 LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_OTGHSULPI);
263 LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_OTGPHYC);
264 #elif defined(CONFIG_SOC_SERIES_STM32H7X)
265 #if !USB_OTG_HS_ULPI_PHY
266 /* Disable ULPI interface (for external high-speed PHY) clock in sleep
267 * mode.
268 */
269 LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI);
270 #endif
271 #else
272 /* Disable ULPI interface (for external high-speed PHY) clock in low
273 * power mode. It is disabled by default in run power mode, no need to
274 * disable it.
275 */
276 LL_AHB1_GRP1_DisableClockLowPower(LL_AHB1_GRP1_PERIPH_OTGHSULPI);
277 #endif
278 #endif
279
280 return 0;
281 }
282
usb_dc_stm32_clock_disable(void)283 static int usb_dc_stm32_clock_disable(void)
284 {
285 const struct device *clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
286
287 if (clock_control_off(clk, (clock_control_subsys_t)&pclken[0]) != 0) {
288 LOG_ERR("Unable to disable USB clock");
289 return -EIO;
290 }
291
292 return 0;
293 }
294
295 #if defined(USB_OTG_FS) || defined(USB_OTG_HS)
usb_dc_stm32_get_maximum_speed(void)296 static uint32_t usb_dc_stm32_get_maximum_speed(void)
297 {
298 /*
299 * If max-speed is not passed via DT, set it to USB controller's
300 * maximum hardware capability.
301 */
302 #if USB_OTG_HS_EMB_PHY || USB_OTG_HS_ULPI_PHY
303 uint32_t speed = USB_OTG_SPEED_HIGH;
304 #else
305 uint32_t speed = USB_OTG_SPEED_FULL;
306 #endif
307
308 #ifdef USB_MAXIMUM_SPEED
309
310 if (!strncmp(USB_MAXIMUM_SPEED, "high-speed", 10)) {
311 speed = USB_OTG_SPEED_HIGH;
312 } else if (!strncmp(USB_MAXIMUM_SPEED, "full-speed", 10)) {
313 #if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(USB_OTG_HS_EMB_PHY)
314 speed = USB_OTG_SPEED_HIGH_IN_FULL;
315 #else
316 speed = USB_OTG_SPEED_FULL;
317 #endif
318 } else {
319 LOG_DBG("Unsupported maximum speed defined in device tree. "
320 "USB controller will default to its maximum HW "
321 "capability");
322 }
323 #endif
324
325 return speed;
326 }
327 #endif /* USB_OTG_FS || USB_OTG_HS */
328
usb_dc_stm32_init(void)329 static int usb_dc_stm32_init(void)
330 {
331 HAL_StatusTypeDef status;
332 int ret;
333 unsigned int i;
334
335 #if defined(USB) || defined(USB_DRD_FS)
336 #ifdef USB
337 usb_dc_stm32_state.pcd.Instance = USB;
338 #else
339 usb_dc_stm32_state.pcd.Instance = USB_DRD_FS;
340 #endif
341 usb_dc_stm32_state.pcd.Init.speed = PCD_SPEED_FULL;
342 usb_dc_stm32_state.pcd.Init.dev_endpoints = USB_NUM_BIDIR_ENDPOINTS;
343 usb_dc_stm32_state.pcd.Init.phy_itface = PCD_PHY_EMBEDDED;
344 usb_dc_stm32_state.pcd.Init.ep0_mps = PCD_EP0MPS_64;
345 usb_dc_stm32_state.pcd.Init.low_power_enable = 0;
346 #else /* USB_OTG_FS || USB_OTG_HS */
347 #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otghs)
348 usb_dc_stm32_state.pcd.Instance = USB_OTG_HS;
349 #else
350 usb_dc_stm32_state.pcd.Instance = USB_OTG_FS;
351 #endif
352 usb_dc_stm32_state.pcd.Init.dev_endpoints = USB_NUM_BIDIR_ENDPOINTS;
353 usb_dc_stm32_state.pcd.Init.speed = usb_dc_stm32_get_maximum_speed();
354 #if USB_OTG_HS_EMB_PHY
355 usb_dc_stm32_state.pcd.Init.phy_itface = USB_OTG_HS_EMBEDDED_PHY;
356 #elif USB_OTG_HS_ULPI_PHY
357 usb_dc_stm32_state.pcd.Init.phy_itface = USB_OTG_ULPI_PHY;
358 #else
359 usb_dc_stm32_state.pcd.Init.phy_itface = PCD_PHY_EMBEDDED;
360 #endif
361 usb_dc_stm32_state.pcd.Init.ep0_mps = USB_OTG_MAX_EP0_SIZE;
362 usb_dc_stm32_state.pcd.Init.vbus_sensing_enable = USB_VBUS_SENSING ? ENABLE : DISABLE;
363
364 #ifndef CONFIG_SOC_SERIES_STM32F1X
365 usb_dc_stm32_state.pcd.Init.dma_enable = DISABLE;
366 #endif
367
368 #endif /* USB */
369
370 #ifdef CONFIG_USB_DEVICE_SOF
371 usb_dc_stm32_state.pcd.Init.Sof_enable = 1;
372 #endif /* CONFIG_USB_DEVICE_SOF */
373
374 #if defined(CONFIG_SOC_SERIES_STM32H7X)
375 #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otgfs)
376 /* The USB2 controller only works in FS mode, but the ULPI clock needs
377 * to be disabled in sleep mode for it to work. For the USB1
378 * controller, as it is an HS one, the clock is disabled in the common
379 * path.
380 */
381
382 LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI);
383 #endif
384
385 LL_PWR_EnableUSBVoltageDetector();
386
387 /* Per AN2606: USBREGEN not supported when running in FS mode. */
388 LL_PWR_DisableUSBReg();
389 while (!LL_PWR_IsActiveFlag_USB()) {
390 LOG_INF("PWR not active yet");
391 k_sleep(K_MSEC(100));
392 }
393 #endif
394
395 LOG_DBG("Pinctrl signals configuration");
396 ret = pinctrl_apply_state(usb_pcfg, PINCTRL_STATE_DEFAULT);
397 if (ret < 0) {
398 LOG_ERR("USB pinctrl setup failed (%d)", ret);
399 return ret;
400 }
401
402 LOG_DBG("HAL_PCD_Init");
403 status = HAL_PCD_Init(&usb_dc_stm32_state.pcd);
404 if (status != HAL_OK) {
405 LOG_ERR("PCD_Init failed, %d", (int)status);
406 return -EIO;
407 }
408
409 /* On a soft reset force USB to reset first and switch it off
410 * so the USB connection can get re-initialized
411 */
412 LOG_DBG("HAL_PCD_Stop");
413 status = HAL_PCD_Stop(&usb_dc_stm32_state.pcd);
414 if (status != HAL_OK) {
415 LOG_ERR("PCD_Stop failed, %d", (int)status);
416 return -EIO;
417 }
418
419 LOG_DBG("HAL_PCD_Start");
420 status = HAL_PCD_Start(&usb_dc_stm32_state.pcd);
421 if (status != HAL_OK) {
422 LOG_ERR("PCD_Start failed, %d", (int)status);
423 return -EIO;
424 }
425
426 usb_dc_stm32_state.out_ep_state[EP0_IDX].ep_mps = EP0_MPS;
427 usb_dc_stm32_state.out_ep_state[EP0_IDX].ep_type = EP_TYPE_CTRL;
428 usb_dc_stm32_state.in_ep_state[EP0_IDX].ep_mps = EP0_MPS;
429 usb_dc_stm32_state.in_ep_state[EP0_IDX].ep_type = EP_TYPE_CTRL;
430
431 #if defined(USB) || defined(USB_DRD_FS)
432 /* Start PMA configuration for the endpoints after the BTABLE. */
433 usb_dc_stm32_state.pma_offset = USB_BTABLE_SIZE;
434
435 for (i = 0U; i < USB_NUM_BIDIR_ENDPOINTS; i++) {
436 k_sem_init(&usb_dc_stm32_state.in_ep_state[i].write_sem, 1, 1);
437 }
438 #else /* USB_OTG_FS */
439 /* TODO: make this dynamic (depending usage) */
440 HAL_PCDEx_SetRxFiFo(&usb_dc_stm32_state.pcd, FIFO_EP_WORDS);
441 for (i = 0U; i < USB_NUM_BIDIR_ENDPOINTS; i++) {
442 HAL_PCDEx_SetTxFiFo(&usb_dc_stm32_state.pcd, i,
443 FIFO_EP_WORDS);
444 k_sem_init(&usb_dc_stm32_state.in_ep_state[i].write_sem, 1, 1);
445 }
446 #endif /* USB */
447
448 IRQ_CONNECT(USB_IRQ, USB_IRQ_PRI,
449 usb_dc_stm32_isr, 0, 0);
450 irq_enable(USB_IRQ);
451 return 0;
452 }
453
454 /* Zephyr USB device controller API implementation */
455
usb_dc_attach(void)456 int usb_dc_attach(void)
457 {
458 int ret;
459
460 LOG_DBG("");
461
462 #ifdef SYSCFG_CFGR1_USB_IT_RMP
463 /*
464 * STM32F302/F303: USB IRQ collides with CAN_1 IRQ (§14.1.3, RM0316)
465 * Remap IRQ by default to enable use of both IPs simultaneoulsy
466 * This should be done before calling any HAL function
467 */
468 if (LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_SYSCFG)) {
469 LL_SYSCFG_EnableRemapIT_USB();
470 } else {
471 LOG_ERR("System Configuration Controller clock is "
472 "disabled. Unable to enable IRQ remapping.");
473 }
474 #endif
475
476 #if USB_OTG_HS_ULPI_PHY
477 if (ulpi_reset.port != NULL) {
478 if (!device_is_ready(ulpi_reset.port)) {
479 LOG_ERR("Reset GPIO device not ready");
480 return -EINVAL;
481 }
482 if (gpio_pin_configure_dt(&ulpi_reset, GPIO_OUTPUT_INACTIVE)) {
483 LOG_ERR("Couldn't configure reset pin");
484 return -EIO;
485 }
486 }
487 #endif
488
489 ret = usb_dc_stm32_clock_enable();
490 if (ret) {
491 return ret;
492 }
493
494 ret = usb_dc_stm32_init();
495 if (ret) {
496 return ret;
497 }
498
499 /*
500 * Required for at least STM32L4 devices as they electrically
501 * isolate USB features from VDDUSB. It must be enabled before
502 * USB can function. Refer to section 5.1.3 in DM00083560 or
503 * DM00310109.
504 */
505 #ifdef PWR_CR2_USV
506 #if defined(LL_APB1_GRP1_PERIPH_PWR)
507 if (LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_PWR)) {
508 LL_PWR_EnableVddUSB();
509 } else {
510 LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
511 LL_PWR_EnableVddUSB();
512 LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_PWR);
513 }
514 #else
515 LL_PWR_EnableVddUSB();
516 #endif /* defined(LL_APB1_GRP1_PERIPH_PWR) */
517 #endif /* PWR_CR2_USV */
518
519 return 0;
520 }
521
usb_dc_ep_set_callback(const uint8_t ep,const usb_dc_ep_callback cb)522 int usb_dc_ep_set_callback(const uint8_t ep, const usb_dc_ep_callback cb)
523 {
524 struct usb_dc_stm32_ep_state *ep_state = usb_dc_stm32_get_ep_state(ep);
525
526 LOG_DBG("ep 0x%02x", ep);
527
528 if (!ep_state) {
529 return -EINVAL;
530 }
531
532 ep_state->cb = cb;
533
534 return 0;
535 }
536
usb_dc_set_status_callback(const usb_dc_status_callback cb)537 void usb_dc_set_status_callback(const usb_dc_status_callback cb)
538 {
539 LOG_DBG("");
540
541 usb_dc_stm32_state.status_cb = cb;
542 }
543
usb_dc_set_address(const uint8_t addr)544 int usb_dc_set_address(const uint8_t addr)
545 {
546 HAL_StatusTypeDef status;
547
548 LOG_DBG("addr %u (0x%02x)", addr, addr);
549
550 status = HAL_PCD_SetAddress(&usb_dc_stm32_state.pcd, addr);
551 if (status != HAL_OK) {
552 LOG_ERR("HAL_PCD_SetAddress failed(0x%02x), %d", addr,
553 (int)status);
554 return -EIO;
555 }
556
557 return 0;
558 }
559
usb_dc_ep_start_read(uint8_t ep,uint8_t * data,uint32_t max_data_len)560 int usb_dc_ep_start_read(uint8_t ep, uint8_t *data, uint32_t max_data_len)
561 {
562 HAL_StatusTypeDef status;
563
564 LOG_DBG("ep 0x%02x, len %u", ep, max_data_len);
565
566 /* we flush EP0_IN by doing a 0 length receive on it */
567 if (!USB_EP_DIR_IS_OUT(ep) && (ep != EP0_IN || max_data_len)) {
568 LOG_ERR("invalid ep 0x%02x", ep);
569 return -EINVAL;
570 }
571
572 if (max_data_len > EP_MPS) {
573 max_data_len = EP_MPS;
574 }
575
576 status = HAL_PCD_EP_Receive(&usb_dc_stm32_state.pcd, ep,
577 usb_dc_stm32_state.ep_buf[USB_EP_GET_IDX(ep)],
578 max_data_len);
579 if (status != HAL_OK) {
580 LOG_ERR("HAL_PCD_EP_Receive failed(0x%02x), %d", ep,
581 (int)status);
582 return -EIO;
583 }
584
585 return 0;
586 }
587
usb_dc_ep_get_read_count(uint8_t ep,uint32_t * read_bytes)588 int usb_dc_ep_get_read_count(uint8_t ep, uint32_t *read_bytes)
589 {
590 if (!USB_EP_DIR_IS_OUT(ep) || !read_bytes) {
591 LOG_ERR("invalid ep 0x%02x", ep);
592 return -EINVAL;
593 }
594
595 *read_bytes = HAL_PCD_EP_GetRxCount(&usb_dc_stm32_state.pcd, ep);
596
597 return 0;
598 }
599
usb_dc_ep_check_cap(const struct usb_dc_ep_cfg_data * const cfg)600 int usb_dc_ep_check_cap(const struct usb_dc_ep_cfg_data * const cfg)
601 {
602 uint8_t ep_idx = USB_EP_GET_IDX(cfg->ep_addr);
603
604 LOG_DBG("ep %x, mps %d, type %d", cfg->ep_addr, cfg->ep_mps,
605 cfg->ep_type);
606
607 if ((cfg->ep_type == USB_DC_EP_CONTROL) && ep_idx) {
608 LOG_ERR("invalid endpoint configuration");
609 return -1;
610 }
611
612 if (ep_idx > (USB_NUM_BIDIR_ENDPOINTS - 1)) {
613 LOG_ERR("endpoint index/address out of range");
614 return -1;
615 }
616
617 return 0;
618 }
619
usb_dc_ep_configure(const struct usb_dc_ep_cfg_data * const ep_cfg)620 int usb_dc_ep_configure(const struct usb_dc_ep_cfg_data * const ep_cfg)
621 {
622 uint8_t ep = ep_cfg->ep_addr;
623 struct usb_dc_stm32_ep_state *ep_state = usb_dc_stm32_get_ep_state(ep);
624
625 if (!ep_state) {
626 return -EINVAL;
627 }
628
629 LOG_DBG("ep 0x%02x, previous ep_mps %u, ep_mps %u, ep_type %u",
630 ep_cfg->ep_addr, ep_state->ep_mps, ep_cfg->ep_mps,
631 ep_cfg->ep_type);
632
633 #if defined(USB) || defined(USB_DRD_FS)
634 if (ep_cfg->ep_mps > ep_state->ep_pma_buf_len) {
635 if (USB_RAM_SIZE <=
636 (usb_dc_stm32_state.pma_offset + ep_cfg->ep_mps)) {
637 return -EINVAL;
638 }
639 HAL_PCDEx_PMAConfig(&usb_dc_stm32_state.pcd, ep, PCD_SNG_BUF,
640 usb_dc_stm32_state.pma_offset);
641 ep_state->ep_pma_buf_len = ep_cfg->ep_mps;
642 usb_dc_stm32_state.pma_offset += ep_cfg->ep_mps;
643 }
644 #endif
645 ep_state->ep_mps = ep_cfg->ep_mps;
646
647 switch (ep_cfg->ep_type) {
648 case USB_DC_EP_CONTROL:
649 ep_state->ep_type = EP_TYPE_CTRL;
650 break;
651 case USB_DC_EP_ISOCHRONOUS:
652 ep_state->ep_type = EP_TYPE_ISOC;
653 break;
654 case USB_DC_EP_BULK:
655 ep_state->ep_type = EP_TYPE_BULK;
656 break;
657 case USB_DC_EP_INTERRUPT:
658 ep_state->ep_type = EP_TYPE_INTR;
659 break;
660 default:
661 return -EINVAL;
662 }
663
664 return 0;
665 }
666
usb_dc_ep_set_stall(const uint8_t ep)667 int usb_dc_ep_set_stall(const uint8_t ep)
668 {
669 struct usb_dc_stm32_ep_state *ep_state = usb_dc_stm32_get_ep_state(ep);
670 HAL_StatusTypeDef status;
671
672 LOG_DBG("ep 0x%02x", ep);
673
674 if (!ep_state) {
675 return -EINVAL;
676 }
677
678 status = HAL_PCD_EP_SetStall(&usb_dc_stm32_state.pcd, ep);
679 if (status != HAL_OK) {
680 LOG_ERR("HAL_PCD_EP_SetStall failed(0x%02x), %d", ep,
681 (int)status);
682 return -EIO;
683 }
684
685 ep_state->ep_stalled = 1U;
686
687 return 0;
688 }
689
usb_dc_ep_clear_stall(const uint8_t ep)690 int usb_dc_ep_clear_stall(const uint8_t ep)
691 {
692 struct usb_dc_stm32_ep_state *ep_state = usb_dc_stm32_get_ep_state(ep);
693 HAL_StatusTypeDef status;
694
695 LOG_DBG("ep 0x%02x", ep);
696
697 if (!ep_state) {
698 return -EINVAL;
699 }
700
701 status = HAL_PCD_EP_ClrStall(&usb_dc_stm32_state.pcd, ep);
702 if (status != HAL_OK) {
703 LOG_ERR("HAL_PCD_EP_ClrStall failed(0x%02x), %d", ep,
704 (int)status);
705 return -EIO;
706 }
707
708 ep_state->ep_stalled = 0U;
709 ep_state->read_count = 0U;
710
711 return 0;
712 }
713
usb_dc_ep_is_stalled(const uint8_t ep,uint8_t * const stalled)714 int usb_dc_ep_is_stalled(const uint8_t ep, uint8_t *const stalled)
715 {
716 struct usb_dc_stm32_ep_state *ep_state = usb_dc_stm32_get_ep_state(ep);
717
718 LOG_DBG("ep 0x%02x", ep);
719
720 if (!ep_state || !stalled) {
721 return -EINVAL;
722 }
723
724 *stalled = ep_state->ep_stalled;
725
726 return 0;
727 }
728
usb_dc_ep_enable(const uint8_t ep)729 int usb_dc_ep_enable(const uint8_t ep)
730 {
731 struct usb_dc_stm32_ep_state *ep_state = usb_dc_stm32_get_ep_state(ep);
732 HAL_StatusTypeDef status;
733
734 LOG_DBG("ep 0x%02x", ep);
735
736 if (!ep_state) {
737 return -EINVAL;
738 }
739
740 LOG_DBG("HAL_PCD_EP_Open(0x%02x, %u, %u)", ep, ep_state->ep_mps,
741 ep_state->ep_type);
742
743 status = HAL_PCD_EP_Open(&usb_dc_stm32_state.pcd, ep,
744 ep_state->ep_mps, ep_state->ep_type);
745 if (status != HAL_OK) {
746 LOG_ERR("HAL_PCD_EP_Open failed(0x%02x), %d", ep,
747 (int)status);
748 return -EIO;
749 }
750
751 if (USB_EP_DIR_IS_OUT(ep) && ep != EP0_OUT) {
752 return usb_dc_ep_start_read(ep,
753 usb_dc_stm32_state.ep_buf[USB_EP_GET_IDX(ep)],
754 EP_MPS);
755 }
756
757 return 0;
758 }
759
usb_dc_ep_disable(const uint8_t ep)760 int usb_dc_ep_disable(const uint8_t ep)
761 {
762 struct usb_dc_stm32_ep_state *ep_state = usb_dc_stm32_get_ep_state(ep);
763 HAL_StatusTypeDef status;
764
765 LOG_DBG("ep 0x%02x", ep);
766
767 if (!ep_state) {
768 return -EINVAL;
769 }
770
771 status = HAL_PCD_EP_Close(&usb_dc_stm32_state.pcd, ep);
772 if (status != HAL_OK) {
773 LOG_ERR("HAL_PCD_EP_Close failed(0x%02x), %d", ep,
774 (int)status);
775 return -EIO;
776 }
777
778 return 0;
779 }
780
usb_dc_ep_write(const uint8_t ep,const uint8_t * const data,const uint32_t data_len,uint32_t * const ret_bytes)781 int usb_dc_ep_write(const uint8_t ep, const uint8_t *const data,
782 const uint32_t data_len, uint32_t * const ret_bytes)
783 {
784 struct usb_dc_stm32_ep_state *ep_state = usb_dc_stm32_get_ep_state(ep);
785 HAL_StatusTypeDef status;
786 uint32_t len = data_len;
787 int ret = 0;
788
789 LOG_DBG("ep 0x%02x, len %u", ep, data_len);
790
791 if (!ep_state || !USB_EP_DIR_IS_IN(ep)) {
792 LOG_ERR("invalid ep 0x%02x", ep);
793 return -EINVAL;
794 }
795
796 ret = k_sem_take(&ep_state->write_sem, K_NO_WAIT);
797 if (ret) {
798 LOG_ERR("Unable to get write lock (%d)", ret);
799 return -EAGAIN;
800 }
801
802 if (!k_is_in_isr()) {
803 irq_disable(USB_IRQ);
804 }
805
806 if (ep == EP0_IN && len > USB_MAX_CTRL_MPS) {
807 len = USB_MAX_CTRL_MPS;
808 }
809
810 status = HAL_PCD_EP_Transmit(&usb_dc_stm32_state.pcd, ep,
811 (void *)data, len);
812 if (status != HAL_OK) {
813 LOG_ERR("HAL_PCD_EP_Transmit failed(0x%02x), %d", ep,
814 (int)status);
815 k_sem_give(&ep_state->write_sem);
816 ret = -EIO;
817 }
818
819 if (!ret && ep == EP0_IN && len > 0) {
820 /* Wait for an empty package as from the host.
821 * This also flushes the TX FIFO to the host.
822 */
823 usb_dc_ep_start_read(ep, NULL, 0);
824 }
825
826 if (!k_is_in_isr()) {
827 irq_enable(USB_IRQ);
828 }
829
830 if (!ret && ret_bytes) {
831 *ret_bytes = len;
832 }
833
834 return ret;
835 }
836
usb_dc_ep_read_wait(uint8_t ep,uint8_t * data,uint32_t max_data_len,uint32_t * read_bytes)837 int usb_dc_ep_read_wait(uint8_t ep, uint8_t *data, uint32_t max_data_len,
838 uint32_t *read_bytes)
839 {
840 struct usb_dc_stm32_ep_state *ep_state = usb_dc_stm32_get_ep_state(ep);
841 uint32_t read_count;
842
843 if (!ep_state) {
844 LOG_ERR("Invalid Endpoint %x", ep);
845 return -EINVAL;
846 }
847
848 read_count = ep_state->read_count;
849
850 LOG_DBG("ep 0x%02x, %u bytes, %u+%u, %p", ep, max_data_len,
851 ep_state->read_offset, read_count, data);
852
853 if (!USB_EP_DIR_IS_OUT(ep)) { /* check if OUT ep */
854 LOG_ERR("Wrong endpoint direction: 0x%02x", ep);
855 return -EINVAL;
856 }
857
858 /* When both buffer and max data to read are zero, just ignore reading
859 * and return available data in buffer. Otherwise, return data
860 * previously stored in the buffer.
861 */
862 if (data) {
863 read_count = MIN(read_count, max_data_len);
864 memcpy(data, usb_dc_stm32_state.ep_buf[USB_EP_GET_IDX(ep)] +
865 ep_state->read_offset, read_count);
866 ep_state->read_count -= read_count;
867 ep_state->read_offset += read_count;
868 } else if (max_data_len) {
869 LOG_ERR("Wrong arguments");
870 }
871
872 if (read_bytes) {
873 *read_bytes = read_count;
874 }
875
876 return 0;
877 }
878
usb_dc_ep_read_continue(uint8_t ep)879 int usb_dc_ep_read_continue(uint8_t ep)
880 {
881 struct usb_dc_stm32_ep_state *ep_state = usb_dc_stm32_get_ep_state(ep);
882
883 if (!ep_state || !USB_EP_DIR_IS_OUT(ep)) { /* Check if OUT ep */
884 LOG_ERR("Not valid endpoint: %02x", ep);
885 return -EINVAL;
886 }
887
888 /* If no more data in the buffer, start a new read transaction.
889 * DataOutStageCallback will called on transaction complete.
890 */
891 if (!ep_state->read_count) {
892 usb_dc_ep_start_read(ep, usb_dc_stm32_state.ep_buf[USB_EP_GET_IDX(ep)],
893 EP_MPS);
894 }
895
896 return 0;
897 }
898
usb_dc_ep_read(const uint8_t ep,uint8_t * const data,const uint32_t max_data_len,uint32_t * const read_bytes)899 int usb_dc_ep_read(const uint8_t ep, uint8_t *const data, const uint32_t max_data_len,
900 uint32_t * const read_bytes)
901 {
902 if (usb_dc_ep_read_wait(ep, data, max_data_len, read_bytes) != 0) {
903 return -EINVAL;
904 }
905
906 if (usb_dc_ep_read_continue(ep) != 0) {
907 return -EINVAL;
908 }
909
910 return 0;
911 }
912
usb_dc_ep_halt(const uint8_t ep)913 int usb_dc_ep_halt(const uint8_t ep)
914 {
915 return usb_dc_ep_set_stall(ep);
916 }
917
usb_dc_ep_flush(const uint8_t ep)918 int usb_dc_ep_flush(const uint8_t ep)
919 {
920 struct usb_dc_stm32_ep_state *ep_state = usb_dc_stm32_get_ep_state(ep);
921
922 if (!ep_state) {
923 return -EINVAL;
924 }
925
926 LOG_ERR("Not implemented");
927
928 return 0;
929 }
930
usb_dc_ep_mps(const uint8_t ep)931 int usb_dc_ep_mps(const uint8_t ep)
932 {
933 struct usb_dc_stm32_ep_state *ep_state = usb_dc_stm32_get_ep_state(ep);
934
935 if (!ep_state) {
936 return -EINVAL;
937 }
938
939 return ep_state->ep_mps;
940 }
941
usb_dc_wakeup_request(void)942 int usb_dc_wakeup_request(void)
943 {
944 HAL_StatusTypeDef status;
945
946 status = HAL_PCD_ActivateRemoteWakeup(&usb_dc_stm32_state.pcd);
947 if (status != HAL_OK) {
948 return -EAGAIN;
949 }
950
951 /* Must be active from 1ms to 15ms as per reference manual. */
952 k_sleep(K_MSEC(2));
953
954 status = HAL_PCD_DeActivateRemoteWakeup(&usb_dc_stm32_state.pcd);
955 if (status != HAL_OK) {
956 return -EAGAIN;
957 }
958
959 return 0;
960 }
961
usb_dc_detach(void)962 int usb_dc_detach(void)
963 {
964 HAL_StatusTypeDef status;
965 int ret;
966
967 LOG_DBG("HAL_PCD_DeInit");
968 status = HAL_PCD_DeInit(&usb_dc_stm32_state.pcd);
969 if (status != HAL_OK) {
970 LOG_ERR("PCD_DeInit failed, %d", (int)status);
971 return -EIO;
972 }
973
974 ret = usb_dc_stm32_clock_disable();
975 if (ret) {
976 return ret;
977 }
978
979 if (irq_is_enabled(USB_IRQ)) {
980 irq_disable(USB_IRQ);
981 }
982
983 return 0;
984 }
985
usb_dc_reset(void)986 int usb_dc_reset(void)
987 {
988 LOG_ERR("Not implemented");
989
990 return 0;
991 }
992
993 /* Callbacks from the STM32 Cube HAL code */
994
HAL_PCD_ResetCallback(PCD_HandleTypeDef * hpcd)995 void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
996 {
997 int i;
998
999 LOG_DBG("");
1000
1001 HAL_PCD_EP_Open(&usb_dc_stm32_state.pcd, EP0_IN, EP0_MPS, EP_TYPE_CTRL);
1002 HAL_PCD_EP_Open(&usb_dc_stm32_state.pcd, EP0_OUT, EP0_MPS,
1003 EP_TYPE_CTRL);
1004
1005 /* The DataInCallback will never be called at this point for any pending
1006 * transactions. Reset the IN semaphores to prevent perpetual locked state.
1007 * */
1008 for (i = 0; i < USB_NUM_BIDIR_ENDPOINTS; i++) {
1009 k_sem_give(&usb_dc_stm32_state.in_ep_state[i].write_sem);
1010 }
1011
1012 if (usb_dc_stm32_state.status_cb) {
1013 usb_dc_stm32_state.status_cb(USB_DC_RESET, NULL);
1014 }
1015 }
1016
HAL_PCD_ConnectCallback(PCD_HandleTypeDef * hpcd)1017 void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
1018 {
1019 LOG_DBG("");
1020
1021 if (usb_dc_stm32_state.status_cb) {
1022 usb_dc_stm32_state.status_cb(USB_DC_CONNECTED, NULL);
1023 }
1024 }
1025
HAL_PCD_DisconnectCallback(PCD_HandleTypeDef * hpcd)1026 void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
1027 {
1028 LOG_DBG("");
1029
1030 if (usb_dc_stm32_state.status_cb) {
1031 usb_dc_stm32_state.status_cb(USB_DC_DISCONNECTED, NULL);
1032 }
1033 }
1034
HAL_PCD_SuspendCallback(PCD_HandleTypeDef * hpcd)1035 void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
1036 {
1037 LOG_DBG("");
1038
1039 if (usb_dc_stm32_state.status_cb) {
1040 usb_dc_stm32_state.status_cb(USB_DC_SUSPEND, NULL);
1041 }
1042 }
1043
HAL_PCD_ResumeCallback(PCD_HandleTypeDef * hpcd)1044 void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
1045 {
1046 LOG_DBG("");
1047
1048 if (usb_dc_stm32_state.status_cb) {
1049 usb_dc_stm32_state.status_cb(USB_DC_RESUME, NULL);
1050 }
1051 }
1052
HAL_PCD_SetupStageCallback(PCD_HandleTypeDef * hpcd)1053 void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
1054 {
1055 struct usb_setup_packet *setup = (void *)usb_dc_stm32_state.pcd.Setup;
1056 struct usb_dc_stm32_ep_state *ep_state;
1057
1058 LOG_DBG("");
1059
1060 ep_state = usb_dc_stm32_get_ep_state(EP0_OUT); /* can't fail for ep0 */
1061 __ASSERT(ep_state, "No corresponding ep_state for EP0");
1062
1063 ep_state->read_count = SETUP_SIZE;
1064 ep_state->read_offset = 0U;
1065 memcpy(&usb_dc_stm32_state.ep_buf[EP0_IDX],
1066 usb_dc_stm32_state.pcd.Setup, ep_state->read_count);
1067
1068 if (ep_state->cb) {
1069 ep_state->cb(EP0_OUT, USB_DC_EP_SETUP);
1070
1071 if (!(setup->wLength == 0U) &&
1072 usb_reqtype_is_to_device(setup)) {
1073 usb_dc_ep_start_read(EP0_OUT,
1074 usb_dc_stm32_state.ep_buf[EP0_IDX],
1075 setup->wLength);
1076 }
1077 }
1078 }
1079
HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef * hpcd,uint8_t epnum)1080 void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
1081 {
1082 uint8_t ep_idx = USB_EP_GET_IDX(epnum);
1083 uint8_t ep = ep_idx | USB_EP_DIR_OUT;
1084 struct usb_dc_stm32_ep_state *ep_state = usb_dc_stm32_get_ep_state(ep);
1085
1086 LOG_DBG("epnum 0x%02x, rx_count %u", epnum,
1087 HAL_PCD_EP_GetRxCount(&usb_dc_stm32_state.pcd, epnum));
1088
1089 /* Transaction complete, data is now stored in the buffer and ready
1090 * for the upper stack (usb_dc_ep_read to retrieve).
1091 */
1092 usb_dc_ep_get_read_count(ep, &ep_state->read_count);
1093 ep_state->read_offset = 0U;
1094
1095 if (ep_state->cb) {
1096 ep_state->cb(ep, USB_DC_EP_DATA_OUT);
1097 }
1098 }
1099
HAL_PCD_DataInStageCallback(PCD_HandleTypeDef * hpcd,uint8_t epnum)1100 void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
1101 {
1102 uint8_t ep_idx = USB_EP_GET_IDX(epnum);
1103 uint8_t ep = ep_idx | USB_EP_DIR_IN;
1104 struct usb_dc_stm32_ep_state *ep_state = usb_dc_stm32_get_ep_state(ep);
1105
1106 LOG_DBG("epnum 0x%02x", epnum);
1107
1108 __ASSERT(ep_state, "No corresponding ep_state for ep");
1109
1110 k_sem_give(&ep_state->write_sem);
1111
1112 if (ep_state->cb) {
1113 ep_state->cb(ep, USB_DC_EP_DATA_IN);
1114 }
1115 }
1116
1117 #if (defined(USB) || defined(USB_DRD_FS)) && DT_INST_NODE_HAS_PROP(0, disconnect_gpios)
HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef * hpcd,uint8_t state)1118 void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state)
1119 {
1120 struct gpio_dt_spec usb_disconnect = GPIO_DT_SPEC_INST_GET(0, disconnect_gpios);
1121
1122 gpio_pin_configure_dt(&usb_disconnect,
1123 (state ? GPIO_OUTPUT_ACTIVE : GPIO_OUTPUT_INACTIVE));
1124 }
1125 #endif /* USB && DT_INST_NODE_HAS_PROP(0, disconnect_gpios) */
1126
