1 /*
2 * Copyright (c) 2020 ITE Corporation. All Rights Reserved.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT ite_it8xxx2_i2c
8
9 #include <zephyr/drivers/gpio.h>
10 #include <zephyr/drivers/i2c.h>
11 #include <zephyr/drivers/pinctrl.h>
12 #include <zephyr/irq.h>
13 #include <zephyr/kernel.h>
14 #include <errno.h>
15 #include <ilm.h>
16 #include <soc.h>
17 #include <soc_dt.h>
18 #include <zephyr/dt-bindings/i2c/it8xxx2-i2c.h>
19 #include <zephyr/pm/policy.h>
20 #include <zephyr/sys/util.h>
21
22 #include <zephyr/logging/log.h>
23 LOG_MODULE_REGISTER(i2c_ite_it8xxx2, CONFIG_I2C_LOG_LEVEL);
24
25 #include "i2c-priv.h"
26
27 /* Start smbus session from idle state */
28 #define I2C_MSG_START BIT(5)
29
30 #define I2C_LINE_SCL_HIGH BIT(0)
31 #define I2C_LINE_SDA_HIGH BIT(1)
32 #define I2C_LINE_IDLE (I2C_LINE_SCL_HIGH | I2C_LINE_SDA_HIGH)
33
34 #ifdef CONFIG_I2C_IT8XXX2_FIFO_MODE
35 #define I2C_FIFO_MODE_MAX_SIZE 32
36 #define I2C_FIFO_MODE_TOTAL_LEN 255
37 #define I2C_MSG_BURST_READ_MASK (I2C_MSG_RESTART | I2C_MSG_STOP | I2C_MSG_READ)
38 #endif
39
40 struct i2c_it8xxx2_config {
41 void (*irq_config_func)(void);
42 uint32_t bitrate;
43 uint8_t *base;
44 uint8_t *reg_mstfctrl;
45 uint8_t i2c_irq_base;
46 uint8_t port;
47 uint8_t channel_switch_sel;
48 /* SCL GPIO cells */
49 struct gpio_dt_spec scl_gpios;
50 /* SDA GPIO cells */
51 struct gpio_dt_spec sda_gpios;
52 /* I2C alternate configuration */
53 const struct pinctrl_dev_config *pcfg;
54 uint32_t clock_gate_offset;
55 bool fifo_enable;
56 };
57
58 enum i2c_pin_fun {
59 SCL = 0,
60 SDA,
61 };
62
63 enum i2c_ch_status {
64 I2C_CH_NORMAL = 0,
65 I2C_CH_REPEAT_START,
66 I2C_CH_WAIT_READ,
67 I2C_CH_WAIT_NEXT_XFER,
68 };
69
70 struct i2c_it8xxx2_data {
71 enum i2c_ch_status i2ccs;
72 struct i2c_msg *active_msg;
73 struct k_mutex mutex;
74 struct k_sem device_sync_sem;
75 #ifdef CONFIG_I2C_IT8XXX2_FIFO_MODE
76 struct i2c_msg *msgs_list;
77 /* Read or write byte counts. */
78 uint32_t bytecnt;
79 /* Number of messages. */
80 uint8_t num_msgs;
81 uint8_t active_msg_index;
82 #endif
83 /* Index into output data */
84 size_t widx;
85 /* Index into input data */
86 size_t ridx;
87 /* operation freq of i2c */
88 uint32_t bus_freq;
89 /* Error code, if any */
90 uint32_t err;
91 /* address of device */
92 uint16_t addr_16bit;
93 /* Frequency setting */
94 uint8_t freq;
95 /* wait for stop bit interrupt */
96 uint8_t stop;
97 };
98
99 enum i2c_host_status {
100 /* Host busy */
101 HOSTA_HOBY = 0x01,
102 /* Finish Interrupt */
103 HOSTA_FINTR = 0x02,
104 /* Device error */
105 HOSTA_DVER = 0x04,
106 /* Bus error */
107 HOSTA_BSER = 0x08,
108 /* Fail */
109 HOSTA_FAIL = 0x10,
110 /* Not response ACK */
111 HOSTA_NACK = 0x20,
112 /* Time-out error */
113 HOSTA_TMOE = 0x40,
114 /* Byte done status */
115 HOSTA_BDS = 0x80,
116 /* Error bit is set */
117 HOSTA_ANY_ERROR = (HOSTA_DVER | HOSTA_BSER | HOSTA_FAIL |
118 HOSTA_NACK | HOSTA_TMOE),
119 /* W/C for next byte */
120 HOSTA_NEXT_BYTE = HOSTA_BDS,
121 /* W/C host status register */
122 HOSTA_ALL_WC_BIT = (HOSTA_FINTR | HOSTA_ANY_ERROR | HOSTA_BDS),
123 };
124
125 enum i2c_reset_cause {
126 I2C_RC_NO_IDLE_FOR_START = 1,
127 I2C_RC_TIMEOUT,
128 };
129
i2c_parsing_return_value(const struct device * dev)130 static int i2c_parsing_return_value(const struct device *dev)
131 {
132 const struct i2c_it8xxx2_config *config = dev->config;
133 struct i2c_it8xxx2_data *data = dev->data;
134
135 if (!data->err) {
136 return 0;
137 }
138
139 if (data->err == ETIMEDOUT) {
140 /* Connection timed out */
141 LOG_ERR("I2C ch%d Address:0x%X Transaction time out.",
142 config->port, data->addr_16bit);
143 } else {
144 LOG_DBG("I2C ch%d Address:0x%X Host error bits message:",
145 config->port, data->addr_16bit);
146 /* Host error bits message*/
147 if (data->err & HOSTA_TMOE) {
148 LOG_ERR("Time-out error: hardware time-out error.");
149 }
150 if (data->err & HOSTA_NACK) {
151 LOG_DBG("NACK error: device does not response ACK.");
152 }
153 if (data->err & HOSTA_FAIL) {
154 LOG_ERR("Fail: a processing transmission is killed.");
155 }
156 if (data->err & HOSTA_BSER) {
157 LOG_ERR("BUS error: SMBus has lost arbitration.");
158 }
159 }
160
161 return -EIO;
162 }
163
i2c_get_line_levels(const struct device * dev)164 static int i2c_get_line_levels(const struct device *dev)
165 {
166 const struct i2c_it8xxx2_config *config = dev->config;
167 uint8_t *base = config->base;
168
169 return (IT8XXX2_SMB_SMBPCTL(base) &
170 (IT8XXX2_SMB_SMBDCS | IT8XXX2_SMB_SMBCS));
171 }
172
i2c_is_busy(const struct device * dev)173 static int i2c_is_busy(const struct device *dev)
174 {
175 const struct i2c_it8xxx2_config *config = dev->config;
176 uint8_t *base = config->base;
177
178 return (IT8XXX2_SMB_HOSTA(base) &
179 (HOSTA_HOBY | HOSTA_ALL_WC_BIT));
180 }
181
i2c_bus_not_available(const struct device * dev)182 static int i2c_bus_not_available(const struct device *dev)
183 {
184 if (i2c_is_busy(dev) ||
185 (i2c_get_line_levels(dev) != I2C_LINE_IDLE)) {
186 return -EIO;
187 }
188
189 return 0;
190 }
191
i2c_reset(const struct device * dev)192 static void i2c_reset(const struct device *dev)
193 {
194 const struct i2c_it8xxx2_config *config = dev->config;
195 uint8_t *base = config->base;
196
197 /* bit1, kill current transaction. */
198 IT8XXX2_SMB_HOCTL(base) = IT8XXX2_SMB_KILL;
199 IT8XXX2_SMB_HOCTL(base) = 0;
200 /* W/C host status register */
201 IT8XXX2_SMB_HOSTA(base) = HOSTA_ALL_WC_BIT;
202 }
203
204 /*
205 * Set i2c standard port (A, B, or C) runs at 400kHz by using timing registers
206 * (offset 0h ~ 7h).
207 */
i2c_standard_port_timing_regs_400khz(uint8_t port)208 static void i2c_standard_port_timing_regs_400khz(uint8_t port)
209 {
210 /* Port clock frequency depends on setting of timing registers. */
211 IT8XXX2_SMB_SCLKTS(port) = 0;
212 /* Suggested setting of timing registers of 400kHz. */
213 #ifdef CONFIG_SOC_IT8XXX2_EC_BUS_24MHZ
214 IT8XXX2_SMB_4P7USL = 0x16;
215 IT8XXX2_SMB_4P0USL = 0x11;
216 IT8XXX2_SMB_300NS = 0x8;
217 IT8XXX2_SMB_250NS = 0x8;
218 IT8XXX2_SMB_45P3USL = 0xff;
219 IT8XXX2_SMB_45P3USH = 0x3;
220 IT8XXX2_SMB_4P7A4P0H = 0;
221 #else
222 IT8XXX2_SMB_4P7USL = 0x3;
223 IT8XXX2_SMB_4P0USL = 0;
224 IT8XXX2_SMB_300NS = 0x1;
225 IT8XXX2_SMB_250NS = 0x5;
226 IT8XXX2_SMB_45P3USL = 0x6a;
227 IT8XXX2_SMB_45P3USH = 0x1;
228 IT8XXX2_SMB_4P7A4P0H = 0;
229 #endif
230 }
231
232 /* Set clock frequency for i2c port A, B , or C */
i2c_standard_port_set_frequency(const struct device * dev,int freq_hz,int freq_set)233 static void i2c_standard_port_set_frequency(const struct device *dev,
234 int freq_hz, int freq_set)
235 {
236 const struct i2c_it8xxx2_config *config = dev->config;
237
238 /*
239 * If port's clock frequency is 400kHz, we use timing registers
240 * for setting. So we can adjust tlow to meet timing.
241 * The others use basic 50/100/1000 KHz setting.
242 */
243 if (freq_hz == I2C_BITRATE_FAST) {
244 i2c_standard_port_timing_regs_400khz(config->port);
245 } else {
246 IT8XXX2_SMB_SCLKTS(config->port) = freq_set;
247 }
248
249 /* This field defines the SMCLK0/1/2 clock/data low timeout. */
250 IT8XXX2_SMB_25MS = I2C_CLK_LOW_TIMEOUT;
251 }
252
i2c_it8xxx2_configure(const struct device * dev,uint32_t dev_config_raw)253 static int i2c_it8xxx2_configure(const struct device *dev,
254 uint32_t dev_config_raw)
255 {
256 const struct i2c_it8xxx2_config *config = dev->config;
257 struct i2c_it8xxx2_data *const data = dev->data;
258 uint32_t freq_set;
259
260 if (!(I2C_MODE_CONTROLLER & dev_config_raw)) {
261 return -EINVAL;
262 }
263
264 if (I2C_ADDR_10_BITS & dev_config_raw) {
265 return -EINVAL;
266 }
267
268 data->bus_freq = I2C_SPEED_GET(dev_config_raw);
269
270 switch (data->bus_freq) {
271 case I2C_SPEED_DT:
272 freq_set = IT8XXX2_SMB_SMCLKS_50K;
273 break;
274 case I2C_SPEED_STANDARD:
275 freq_set = IT8XXX2_SMB_SMCLKS_100K;
276 break;
277 case I2C_SPEED_FAST:
278 freq_set = IT8XXX2_SMB_SMCLKS_400K;
279 break;
280 case I2C_SPEED_FAST_PLUS:
281 freq_set = IT8XXX2_SMB_SMCLKS_1M;
282 break;
283 default:
284 return -EINVAL;
285 }
286
287 i2c_standard_port_set_frequency(dev, config->bitrate, freq_set);
288
289 return 0;
290 }
291
i2c_it8xxx2_get_config(const struct device * dev,uint32_t * dev_config)292 static int i2c_it8xxx2_get_config(const struct device *dev,
293 uint32_t *dev_config)
294 {
295 struct i2c_it8xxx2_data *const data = dev->data;
296 uint32_t speed;
297
298 if (!data->bus_freq) {
299 LOG_ERR("The bus frequency is not initially configured.");
300 return -EIO;
301 }
302
303 switch (data->bus_freq) {
304 case I2C_SPEED_DT:
305 case I2C_SPEED_STANDARD:
306 case I2C_SPEED_FAST:
307 case I2C_SPEED_FAST_PLUS:
308 speed = I2C_SPEED_SET(data->bus_freq);
309 break;
310 default:
311 return -ERANGE;
312 }
313
314 *dev_config = (I2C_MODE_CONTROLLER | speed);
315
316 return 0;
317 }
318
i2c_r_last_byte(const struct device * dev)319 void __soc_ram_code i2c_r_last_byte(const struct device *dev)
320 {
321 struct i2c_it8xxx2_data *data = dev->data;
322 const struct i2c_it8xxx2_config *config = dev->config;
323 uint8_t *base = config->base;
324
325 /*
326 * bit5, The firmware shall write 1 to this bit
327 * when the next byte will be the last byte for i2c read.
328 */
329 if ((data->active_msg->flags & I2C_MSG_STOP) &&
330 (data->ridx == data->active_msg->len - 1)) {
331 IT8XXX2_SMB_HOCTL(base) |= IT8XXX2_SMB_LABY;
332 }
333 }
334
i2c_w2r_change_direction(const struct device * dev)335 void __soc_ram_code i2c_w2r_change_direction(const struct device *dev)
336 {
337 const struct i2c_it8xxx2_config *config = dev->config;
338 uint8_t *base = config->base;
339
340 /* I2C switch direction */
341 if (IT8XXX2_SMB_HOCTL2(base) & IT8XXX2_SMB_I2C_SW_EN) {
342 i2c_r_last_byte(dev);
343 IT8XXX2_SMB_HOSTA(base) = HOSTA_NEXT_BYTE;
344 } else {
345 /*
346 * bit2, I2C switch direction wait.
347 * bit3, I2C switch direction enable.
348 */
349 IT8XXX2_SMB_HOCTL2(base) |= IT8XXX2_SMB_I2C_SW_EN |
350 IT8XXX2_SMB_I2C_SW_WAIT;
351 IT8XXX2_SMB_HOSTA(base) = HOSTA_NEXT_BYTE;
352 i2c_r_last_byte(dev);
353 IT8XXX2_SMB_HOCTL2(base) &= ~IT8XXX2_SMB_I2C_SW_WAIT;
354 }
355 }
356
357 #ifdef CONFIG_I2C_IT8XXX2_FIFO_MODE
i2c_fifo_en_w2r(const struct device * dev,bool enable)358 void __soc_ram_code i2c_fifo_en_w2r(const struct device *dev, bool enable)
359 {
360 const struct i2c_it8xxx2_config *config = dev->config;
361 unsigned int key = irq_lock();
362
363 if (enable) {
364 if (config->port == SMB_CHANNEL_A) {
365 IT8XXX2_SMB_I2CW2RF |= IT8XXX2_SMB_MAIF |
366 IT8XXX2_SMB_MAIFI;
367 } else if (config->port == SMB_CHANNEL_B) {
368 IT8XXX2_SMB_I2CW2RF |= IT8XXX2_SMB_MBCIF |
369 IT8XXX2_SMB_MBIFI;
370 } else if (config->port == SMB_CHANNEL_C) {
371 IT8XXX2_SMB_I2CW2RF |= IT8XXX2_SMB_MBCIF |
372 IT8XXX2_SMB_MCIFI;
373 }
374 } else {
375 if (config->port == SMB_CHANNEL_A) {
376 IT8XXX2_SMB_I2CW2RF &= ~(IT8XXX2_SMB_MAIF |
377 IT8XXX2_SMB_MAIFI);
378 } else if (config->port == SMB_CHANNEL_B) {
379 IT8XXX2_SMB_I2CW2RF &= ~(IT8XXX2_SMB_MBCIF |
380 IT8XXX2_SMB_MBIFI);
381 } else if (config->port == SMB_CHANNEL_C) {
382 IT8XXX2_SMB_I2CW2RF &= ~(IT8XXX2_SMB_MBCIF |
383 IT8XXX2_SMB_MCIFI);
384 }
385 }
386
387 irq_unlock(key);
388 }
389
i2c_tran_fifo_write_start(const struct device * dev)390 void __soc_ram_code i2c_tran_fifo_write_start(const struct device *dev)
391 {
392 struct i2c_it8xxx2_data *data = dev->data;
393 const struct i2c_it8xxx2_config *config = dev->config;
394 uint32_t i;
395 uint8_t *base = config->base;
396 volatile uint8_t *reg_mstfctrl = config->reg_mstfctrl;
397
398 /* Clear start flag. */
399 data->active_msg->flags &= ~I2C_MSG_START;
400 /* Enable SMB channel in FIFO mode. */
401 *reg_mstfctrl |= IT8XXX2_SMB_FFEN;
402 /* I2C enable. */
403 IT8XXX2_SMB_HOCTL2(base) = IT8XXX2_SMB_SMD_TO_EN |
404 IT8XXX2_SMB_I2C_EN |
405 IT8XXX2_SMB_SMHEN;
406 /* Set write byte counts. */
407 IT8XXX2_SMB_D0REG(base) = data->active_msg->len;
408 /*
409 * bit[7:1]: Address of the target.
410 * bit[0]: Direction of the host transfer.
411 */
412 IT8XXX2_SMB_TRASLA(base) = (uint8_t)data->addr_16bit << 1;
413 /* The maximum fifo size is 32 bytes. */
414 data->bytecnt = MIN(data->active_msg->len, I2C_FIFO_MODE_MAX_SIZE);
415
416 for (i = 0; i < data->bytecnt; i++) {
417 /* Set host block data byte. */
418 IT8XXX2_SMB_HOBDB(base) = *(data->active_msg->buf++);
419 }
420 /* Calculate the remaining byte counts. */
421 data->bytecnt = data->active_msg->len - data->bytecnt;
422 /*
423 * bit[6] = 1b: Start.
424 * bit[4:2] = 111b: Extend command.
425 * bit[0] = 1b: Host interrupt enable.
426 */
427 IT8XXX2_SMB_HOCTL(base) = IT8XXX2_SMB_SRT |
428 IT8XXX2_SMB_SMCD_EXTND |
429 IT8XXX2_SMB_INTREN;
430 }
431
i2c_tran_fifo_write_next_block(const struct device * dev)432 void __soc_ram_code i2c_tran_fifo_write_next_block(const struct device *dev)
433 {
434 struct i2c_it8xxx2_data *data = dev->data;
435 const struct i2c_it8xxx2_config *config = dev->config;
436 uint32_t i, _bytecnt;
437 uint8_t *base = config->base;
438 volatile uint8_t *reg_mstfctrl = config->reg_mstfctrl;
439
440 /* The maximum fifo size is 32 bytes. */
441 _bytecnt = MIN(data->bytecnt, I2C_FIFO_MODE_MAX_SIZE);
442
443 for (i = 0; i < _bytecnt; i++) {
444 /* Set host block data byte. */
445 IT8XXX2_SMB_HOBDB(base) = *(data->active_msg->buf++);
446 }
447 /* Clear FIFO block done status. */
448 *reg_mstfctrl |= IT8XXX2_SMB_BLKDS;
449 /* Calculate the remaining byte counts. */
450 data->bytecnt -= _bytecnt;
451 }
452
i2c_tran_fifo_write_finish(const struct device * dev)453 void __soc_ram_code i2c_tran_fifo_write_finish(const struct device *dev)
454 {
455 const struct i2c_it8xxx2_config *config = dev->config;
456 uint8_t *base = config->base;
457
458 /* Clear byte count register. */
459 IT8XXX2_SMB_D0REG(base) = 0;
460 /* W/C */
461 IT8XXX2_SMB_HOSTA(base) = HOSTA_ALL_WC_BIT;
462 /* Disable the SMBus host interface. */
463 IT8XXX2_SMB_HOCTL2(base) = 0x00;
464 }
465
i2c_tran_fifo_w2r_change_direction(const struct device * dev)466 int __soc_ram_code i2c_tran_fifo_w2r_change_direction(const struct device *dev)
467 {
468 struct i2c_it8xxx2_data *data = dev->data;
469 const struct i2c_it8xxx2_config *config = dev->config;
470 uint8_t *base = config->base;
471
472 if (++data->active_msg_index >= data->num_msgs) {
473 LOG_ERR("Current message index is error.");
474 data->err = EINVAL;
475 /* W/C */
476 IT8XXX2_SMB_HOSTA(base) = HOSTA_ALL_WC_BIT;
477 /* Disable the SMBus host interface. */
478 IT8XXX2_SMB_HOCTL2(base) = 0x00;
479
480 return 0;
481 }
482 /* Set I2C_SW_EN = 1 */
483 IT8XXX2_SMB_HOCTL2(base) |= IT8XXX2_SMB_I2C_SW_EN |
484 IT8XXX2_SMB_I2C_SW_WAIT;
485 IT8XXX2_SMB_HOCTL2(base) &= ~IT8XXX2_SMB_I2C_SW_WAIT;
486 /* Point to the next msg for the read location. */
487 data->active_msg = &data->msgs_list[data->active_msg_index];
488 /* Set read byte counts. */
489 IT8XXX2_SMB_D0REG(base) = data->active_msg->len;
490 data->bytecnt = data->active_msg->len;
491 /* W/C I2C W2R FIFO interrupt status. */
492 IT8XXX2_SMB_IWRFISTA = BIT(config->port);
493
494 return 1;
495 }
496
i2c_tran_fifo_read_start(const struct device * dev)497 void __soc_ram_code i2c_tran_fifo_read_start(const struct device *dev)
498 {
499 struct i2c_it8xxx2_data *data = dev->data;
500 const struct i2c_it8xxx2_config *config = dev->config;
501 uint8_t *base = config->base;
502 volatile uint8_t *reg_mstfctrl = config->reg_mstfctrl;
503
504 /* Clear start flag. */
505 data->active_msg->flags &= ~I2C_MSG_START;
506 /* Enable SMB channel in FIFO mode. */
507 *reg_mstfctrl |= IT8XXX2_SMB_FFEN;
508 /* I2C enable. */
509 IT8XXX2_SMB_HOCTL2(base) = IT8XXX2_SMB_SMD_TO_EN |
510 IT8XXX2_SMB_I2C_EN |
511 IT8XXX2_SMB_SMHEN;
512 /* Set read byte counts. */
513 IT8XXX2_SMB_D0REG(base) = data->active_msg->len;
514 /*
515 * bit[7:1]: Address of the target.
516 * bit[0]: Direction of the host transfer.
517 */
518 IT8XXX2_SMB_TRASLA(base) = (uint8_t)(data->addr_16bit << 1) |
519 IT8XXX2_SMB_DIR;
520
521 data->bytecnt = data->active_msg->len;
522 /*
523 * bit[6] = 1b: Start.
524 * bit[4:2] = 111b: Extend command.
525 * bit[0] = 1b: Host interrupt enable.
526 */
527 IT8XXX2_SMB_HOCTL(base) = IT8XXX2_SMB_SRT |
528 IT8XXX2_SMB_SMCD_EXTND |
529 IT8XXX2_SMB_INTREN;
530 }
531
i2c_tran_fifo_read_next_block(const struct device * dev)532 void __soc_ram_code i2c_tran_fifo_read_next_block(const struct device *dev)
533 {
534 struct i2c_it8xxx2_data *data = dev->data;
535 const struct i2c_it8xxx2_config *config = dev->config;
536 uint32_t i;
537 uint8_t *base = config->base;
538 volatile uint8_t *reg_mstfctrl = config->reg_mstfctrl;
539
540 for (i = 0; i < I2C_FIFO_MODE_MAX_SIZE; i++) {
541 /* To get received data. */
542 *(data->active_msg->buf++) = IT8XXX2_SMB_HOBDB(base);
543 }
544 /* Clear FIFO block done status. */
545 *reg_mstfctrl |= IT8XXX2_SMB_BLKDS;
546 /* Calculate the remaining byte counts. */
547 data->bytecnt -= I2C_FIFO_MODE_MAX_SIZE;
548 }
549
i2c_tran_fifo_read_finish(const struct device * dev)550 void __soc_ram_code i2c_tran_fifo_read_finish(const struct device *dev)
551 {
552 struct i2c_it8xxx2_data *data = dev->data;
553 const struct i2c_it8xxx2_config *config = dev->config;
554 uint32_t i;
555 uint8_t *base = config->base;
556
557 for (i = 0; i < data->bytecnt; i++) {
558 /* To get received data. */
559 *(data->active_msg->buf++) = IT8XXX2_SMB_HOBDB(base);
560 }
561 /* Clear byte count register. */
562 IT8XXX2_SMB_D0REG(base) = 0;
563 /* W/C */
564 IT8XXX2_SMB_HOSTA(base) = HOSTA_ALL_WC_BIT;
565 /* Disable the SMBus host interface. */
566 IT8XXX2_SMB_HOCTL2(base) = 0x00;
567
568 }
569
i2c_tran_fifo_write_to_read(const struct device * dev)570 int __soc_ram_code i2c_tran_fifo_write_to_read(const struct device *dev)
571 {
572 struct i2c_it8xxx2_data *data = dev->data;
573 const struct i2c_it8xxx2_config *config = dev->config;
574 uint8_t *base = config->base;
575 volatile uint8_t *reg_mstfctrl = config->reg_mstfctrl;
576 int ret = 1;
577
578 if (data->active_msg->flags & I2C_MSG_START) {
579 /* Enable I2C write to read FIFO mode. */
580 i2c_fifo_en_w2r(dev, 1);
581 i2c_tran_fifo_write_start(dev);
582 } else {
583 /* Check block done status. */
584 if (*reg_mstfctrl & IT8XXX2_SMB_BLKDS) {
585 if (IT8XXX2_SMB_HOCTL2(base) & IT8XXX2_SMB_I2C_SW_EN) {
586 i2c_tran_fifo_read_next_block(dev);
587 } else {
588 i2c_tran_fifo_write_next_block(dev);
589 }
590 } else if (IT8XXX2_SMB_IWRFISTA & BIT(config->port)) {
591 /*
592 * This function returns 0 on a failure to indicate
593 * that the current transaction is completed and
594 * returned the data->err.
595 */
596 ret = i2c_tran_fifo_w2r_change_direction(dev);
597 } else {
598 /* Wait finish. */
599 if ((IT8XXX2_SMB_HOSTA(base) & HOSTA_FINTR)) {
600 i2c_tran_fifo_read_finish(dev);
601 /* Done doing work. */
602 ret = 0;
603 }
604 }
605 }
606
607 return ret;
608 }
609
i2c_tran_fifo_read(const struct device * dev)610 int __soc_ram_code i2c_tran_fifo_read(const struct device *dev)
611 {
612 struct i2c_it8xxx2_data *data = dev->data;
613 const struct i2c_it8xxx2_config *config = dev->config;
614 uint8_t *base = config->base;
615 volatile uint8_t *reg_mstfctrl = config->reg_mstfctrl;
616
617 if (data->active_msg->flags & I2C_MSG_START) {
618 i2c_tran_fifo_read_start(dev);
619 } else {
620 /* Check block done status. */
621 if (*reg_mstfctrl & IT8XXX2_SMB_BLKDS) {
622 i2c_tran_fifo_read_next_block(dev);
623 } else {
624 /* Wait finish. */
625 if ((IT8XXX2_SMB_HOSTA(base) & HOSTA_FINTR)) {
626 i2c_tran_fifo_read_finish(dev);
627 /* Done doing work. */
628 return 0;
629 }
630 }
631 }
632
633 return 1;
634 }
635
i2c_tran_fifo_write(const struct device * dev)636 int __soc_ram_code i2c_tran_fifo_write(const struct device *dev)
637 {
638 struct i2c_it8xxx2_data *data = dev->data;
639 const struct i2c_it8xxx2_config *config = dev->config;
640 uint8_t *base = config->base;
641 volatile uint8_t *reg_mstfctrl = config->reg_mstfctrl;
642
643 if (data->active_msg->flags & I2C_MSG_START) {
644 i2c_tran_fifo_write_start(dev);
645 } else {
646 /* Check block done status. */
647 if (*reg_mstfctrl & IT8XXX2_SMB_BLKDS) {
648 i2c_tran_fifo_write_next_block(dev);
649 } else {
650 /* Wait finish. */
651 if ((IT8XXX2_SMB_HOSTA(base) & HOSTA_FINTR)) {
652 i2c_tran_fifo_write_finish(dev);
653 /* Done doing work. */
654 return 0;
655 }
656 }
657 }
658
659 return 1;
660 }
661
i2c_fifo_transaction(const struct device * dev)662 int __soc_ram_code i2c_fifo_transaction(const struct device *dev)
663 {
664 struct i2c_it8xxx2_data *data = dev->data;
665 const struct i2c_it8xxx2_config *config = dev->config;
666 uint8_t *base = config->base;
667
668 /* Any error. */
669 if (IT8XXX2_SMB_HOSTA(base) & HOSTA_ANY_ERROR) {
670 data->err = (IT8XXX2_SMB_HOSTA(base) & HOSTA_ANY_ERROR);
671 } else {
672 if (data->num_msgs == 2) {
673 return i2c_tran_fifo_write_to_read(dev);
674 } else if (data->active_msg->flags & I2C_MSG_READ) {
675 return i2c_tran_fifo_read(dev);
676 } else {
677 return i2c_tran_fifo_write(dev);
678 }
679 }
680 /* W/C */
681 IT8XXX2_SMB_HOSTA(base) = HOSTA_ALL_WC_BIT;
682 /* Disable the SMBus host interface. */
683 IT8XXX2_SMB_HOCTL2(base) = 0x00;
684
685 return 0;
686 }
687
fifo_mode_allowed(const struct device * dev,struct i2c_msg * msgs)688 bool __soc_ram_code fifo_mode_allowed(const struct device *dev,
689 struct i2c_msg *msgs)
690 {
691 struct i2c_it8xxx2_data *data = dev->data;
692 const struct i2c_it8xxx2_config *config = dev->config;
693
694 /*
695 * If the transaction of write or read is divided into two
696 * transfers(not two messages), the FIFO mode does not support.
697 */
698 if (data->i2ccs != I2C_CH_NORMAL) {
699 return false;
700 }
701 /*
702 * FIFO2 only supports one channel of B or C. If the FIFO of
703 * channel is not enabled, it will select PIO mode.
704 */
705 if (!config->fifo_enable) {
706 return false;
707 }
708 /*
709 * When there is only one message, use the FIFO mode transfer
710 * directly.
711 * Transfer payload too long (>255 bytes), use PIO mode.
712 * Write or read of I2C target address without data, used by
713 * cmd_i2c_scan. Use PIO mode.
714 */
715 if (data->num_msgs == 1 && (msgs[0].flags & I2C_MSG_STOP) &&
716 (msgs[0].len <= I2C_FIFO_MODE_TOTAL_LEN) && (msgs[0].len != 0)) {
717 return true;
718 }
719 /*
720 * When there are two messages, we need to judge whether or not there
721 * is I2C_MSG_RESTART flag from the second message, and then decide to
722 * do the FIFO mode or PIO mode transfer.
723 */
724 if (data->num_msgs == 2) {
725 /*
726 * The first of two messages must be write.
727 * Transfer payload too long (>255 bytes), use PIO mode.
728 */
729 if (((msgs[0].flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE) &&
730 (msgs[0].len <= I2C_FIFO_MODE_TOTAL_LEN)) {
731 /*
732 * The transfer is i2c_burst_read().
733 *
734 * e.g. msg[0].flags = I2C_MSG_WRITE;
735 * msg[1].flags = I2C_MSG_RESTART | I2C_MSG_READ |
736 * I2C_MSG_STOP;
737 */
738 if ((msgs[1].flags == I2C_MSG_BURST_READ_MASK) &&
739 (msgs[1].len <= I2C_FIFO_MODE_TOTAL_LEN)) {
740 return true;
741 }
742 }
743 }
744
745 return false;
746 }
747 #endif
748
i2c_tran_read(const struct device * dev)749 int __soc_ram_code i2c_tran_read(const struct device *dev)
750 {
751 struct i2c_it8xxx2_data *data = dev->data;
752 const struct i2c_it8xxx2_config *config = dev->config;
753 uint8_t *base = config->base;
754
755 if (data->active_msg->flags & I2C_MSG_START) {
756 /* i2c enable */
757 IT8XXX2_SMB_HOCTL2(base) = IT8XXX2_SMB_SMD_TO_EN |
758 IT8XXX2_SMB_I2C_EN |
759 IT8XXX2_SMB_SMHEN;
760 /*
761 * bit0, Direction of the host transfer.
762 * bit[1:7}, Address of the targeted slave.
763 */
764 IT8XXX2_SMB_TRASLA(base) = (uint8_t)(data->addr_16bit << 1) |
765 IT8XXX2_SMB_DIR;
766 /* clear start flag */
767 data->active_msg->flags &= ~I2C_MSG_START;
768 /*
769 * bit0, Host interrupt enable.
770 * bit[2:4}, Extend command.
771 * bit5, The firmware shall write 1 to this bit
772 * when the next byte will be the last byte.
773 * bit6, start.
774 */
775 if ((data->active_msg->len == 1) &&
776 (data->active_msg->flags & I2C_MSG_STOP)) {
777 IT8XXX2_SMB_HOCTL(base) = IT8XXX2_SMB_SRT |
778 IT8XXX2_SMB_LABY |
779 IT8XXX2_SMB_SMCD_EXTND |
780 IT8XXX2_SMB_INTREN;
781 } else {
782 IT8XXX2_SMB_HOCTL(base) = IT8XXX2_SMB_SRT |
783 IT8XXX2_SMB_SMCD_EXTND |
784 IT8XXX2_SMB_INTREN;
785 }
786 } else {
787 if ((data->i2ccs == I2C_CH_REPEAT_START) ||
788 (data->i2ccs == I2C_CH_WAIT_READ)) {
789 if (data->i2ccs == I2C_CH_REPEAT_START) {
790 /* write to read */
791 i2c_w2r_change_direction(dev);
792 } else {
793 /* For last byte */
794 i2c_r_last_byte(dev);
795 /* W/C for next byte */
796 IT8XXX2_SMB_HOSTA(base) = HOSTA_NEXT_BYTE;
797 }
798 data->i2ccs = I2C_CH_NORMAL;
799 } else if (IT8XXX2_SMB_HOSTA(base) & HOSTA_BDS) {
800 if (data->ridx < data->active_msg->len) {
801 /* To get received data. */
802 *(data->active_msg->buf++) = IT8XXX2_SMB_HOBDB(base);
803 data->ridx++;
804 /* For last byte */
805 i2c_r_last_byte(dev);
806 /* done */
807 if (data->ridx == data->active_msg->len) {
808 data->active_msg->len = 0;
809 if (data->active_msg->flags & I2C_MSG_STOP) {
810 /* W/C for finish */
811 IT8XXX2_SMB_HOSTA(base) =
812 HOSTA_NEXT_BYTE;
813
814 data->stop = 1;
815 } else {
816 data->i2ccs = I2C_CH_WAIT_READ;
817 return 0;
818 }
819 } else {
820 /* W/C for next byte */
821 IT8XXX2_SMB_HOSTA(base) =
822 HOSTA_NEXT_BYTE;
823 }
824 }
825 }
826 }
827 return 1;
828
829 }
830
i2c_tran_write(const struct device * dev)831 int __soc_ram_code i2c_tran_write(const struct device *dev)
832 {
833 struct i2c_it8xxx2_data *data = dev->data;
834 const struct i2c_it8xxx2_config *config = dev->config;
835 uint8_t *base = config->base;
836
837 if (data->active_msg->flags & I2C_MSG_START) {
838 /* i2c enable */
839 IT8XXX2_SMB_HOCTL2(base) = IT8XXX2_SMB_SMD_TO_EN |
840 IT8XXX2_SMB_I2C_EN |
841 IT8XXX2_SMB_SMHEN;
842 /*
843 * bit0, Direction of the host transfer.
844 * bit[1:7}, Address of the targeted slave.
845 */
846 IT8XXX2_SMB_TRASLA(base) = (uint8_t)data->addr_16bit << 1;
847 /* Send first byte */
848 IT8XXX2_SMB_HOBDB(base) = *(data->active_msg->buf++);
849
850 data->widx++;
851 /* clear start flag */
852 data->active_msg->flags &= ~I2C_MSG_START;
853 /*
854 * bit0, Host interrupt enable.
855 * bit[2:4}, Extend command.
856 * bit6, start.
857 */
858 IT8XXX2_SMB_HOCTL(base) = IT8XXX2_SMB_SRT |
859 IT8XXX2_SMB_SMCD_EXTND |
860 IT8XXX2_SMB_INTREN;
861 } else {
862 /* Host has completed the transmission of a byte */
863 if (IT8XXX2_SMB_HOSTA(base) & HOSTA_BDS) {
864 if (data->widx < data->active_msg->len) {
865 /* Send next byte */
866 IT8XXX2_SMB_HOBDB(base) = *(data->active_msg->buf++);
867
868 data->widx++;
869 /* W/C byte done for next byte */
870 IT8XXX2_SMB_HOSTA(base) = HOSTA_NEXT_BYTE;
871
872 if (data->i2ccs == I2C_CH_REPEAT_START) {
873 data->i2ccs = I2C_CH_NORMAL;
874 }
875 } else {
876 /* done */
877 data->active_msg->len = 0;
878 if (data->active_msg->flags & I2C_MSG_STOP) {
879 /* set I2C_EN = 0 */
880 IT8XXX2_SMB_HOCTL2(base) = IT8XXX2_SMB_SMD_TO_EN |
881 IT8XXX2_SMB_SMHEN;
882 /* W/C byte done for finish */
883 IT8XXX2_SMB_HOSTA(base) = HOSTA_NEXT_BYTE;
884
885 data->stop = 1;
886 } else {
887 data->i2ccs = I2C_CH_REPEAT_START;
888 return 0;
889 }
890 }
891 }
892 }
893 return 1;
894
895 }
896
i2c_pio_transaction(const struct device * dev)897 int __soc_ram_code i2c_pio_transaction(const struct device *dev)
898 {
899 struct i2c_it8xxx2_data *data = dev->data;
900 const struct i2c_it8xxx2_config *config = dev->config;
901 uint8_t *base = config->base;
902
903 /* any error */
904 if (IT8XXX2_SMB_HOSTA(base) & HOSTA_ANY_ERROR) {
905 data->err = (IT8XXX2_SMB_HOSTA(base) & HOSTA_ANY_ERROR);
906 } else {
907 if (!data->stop) {
908 /*
909 * The return value indicates if there is more data
910 * to be read or written. If the return value = 1,
911 * it means that the interrupt cannot be disable and
912 * continue to transmit data.
913 */
914 if (data->active_msg->flags & I2C_MSG_READ) {
915 return i2c_tran_read(dev);
916 } else {
917 return i2c_tran_write(dev);
918 }
919 }
920 /* wait finish */
921 if (!(IT8XXX2_SMB_HOSTA(base) & HOSTA_FINTR)) {
922 return 1;
923 }
924 }
925 /* W/C */
926 IT8XXX2_SMB_HOSTA(base) = HOSTA_ALL_WC_BIT;
927 /* disable the SMBus host interface */
928 IT8XXX2_SMB_HOCTL2(base) = 0x00;
929
930 data->stop = 0;
931 /* done doing work */
932 return 0;
933 }
934
i2c_it8xxx2_transfer(const struct device * dev,struct i2c_msg * msgs,uint8_t num_msgs,uint16_t addr)935 static int i2c_it8xxx2_transfer(const struct device *dev, struct i2c_msg *msgs,
936 uint8_t num_msgs, uint16_t addr)
937 {
938 struct i2c_it8xxx2_data *data = dev->data;
939 const struct i2c_it8xxx2_config *config = dev->config;
940 int res, ret;
941
942 /* Lock mutex of i2c controller */
943 k_mutex_lock(&data->mutex, K_FOREVER);
944 /*
945 * If the transaction of write to read is divided into two
946 * transfers, the repeat start transfer uses this flag to
947 * exclude checking bus busy.
948 */
949 if (data->i2ccs == I2C_CH_NORMAL) {
950 struct i2c_msg *start_msg = &msgs[0];
951
952 /* Make sure we're in a good state to start */
953 if (i2c_bus_not_available(dev)) {
954 /* Recovery I2C bus */
955 i2c_recover_bus(dev);
956 /*
957 * After resetting I2C bus, if I2C bus is not available
958 * (No external pull-up), drop the transaction.
959 */
960 if (i2c_bus_not_available(dev)) {
961 /* Unlock mutex of i2c controller */
962 k_mutex_unlock(&data->mutex);
963 return -EIO;
964 }
965 }
966
967 start_msg->flags |= I2C_MSG_START;
968 }
969 #ifdef CONFIG_I2C_IT8XXX2_FIFO_MODE
970 /* Store num_msgs to data struct. */
971 data->num_msgs = num_msgs;
972 /* Store msgs to data struct. */
973 data->msgs_list = msgs;
974 bool fifo_mode_enable = fifo_mode_allowed(dev, msgs);
975
976 if (fifo_mode_enable) {
977 /* Block to enter power policy. */
978 pm_policy_state_lock_get(PM_STATE_STANDBY, PM_ALL_SUBSTATES);
979 }
980 #endif
981 for (int i = 0; i < num_msgs; i++) {
982
983 data->widx = 0;
984 data->ridx = 0;
985 data->err = 0;
986 data->active_msg = &msgs[i];
987 data->addr_16bit = addr;
988
989 #ifdef CONFIG_I2C_IT8XXX2_FIFO_MODE
990 data->active_msg_index = 0;
991 /*
992 * Start transaction.
993 * The return value indicates if the initial configuration
994 * of I2C transaction for read or write has been completed.
995 */
996 if (fifo_mode_enable) {
997 if (i2c_fifo_transaction(dev)) {
998 /* Enable i2c interrupt */
999 irq_enable(config->i2c_irq_base);
1000 }
1001 } else
1002 #endif
1003 {
1004 if (i2c_pio_transaction(dev)) {
1005 /* Enable i2c interrupt */
1006 irq_enable(config->i2c_irq_base);
1007 }
1008 }
1009 /* Wait for the transfer to complete */
1010 /* TODO: the timeout should be adjustable */
1011 res = k_sem_take(&data->device_sync_sem, K_MSEC(100));
1012 /*
1013 * The irq will be enabled at the condition of start or
1014 * repeat start of I2C. If timeout occurs without being
1015 * wake up during suspend(ex: interrupt is not fired),
1016 * the irq should be disabled immediately.
1017 */
1018 irq_disable(config->i2c_irq_base);
1019 /*
1020 * The transaction is dropped on any error(timeout, NACK, fail,
1021 * bus error, device error).
1022 */
1023 if (data->err) {
1024 break;
1025 }
1026
1027 if (res != 0) {
1028 data->err = ETIMEDOUT;
1029 /* reset i2c port */
1030 i2c_reset(dev);
1031 LOG_ERR("I2C ch%d:0x%X reset cause %d",
1032 config->port, data->addr_16bit, I2C_RC_TIMEOUT);
1033 /* If this message is sent fail, drop the transaction. */
1034 break;
1035 }
1036
1037 #ifdef CONFIG_I2C_IT8XXX2_FIFO_MODE
1038 /*
1039 * In FIFO mode, messages are compressed into a single
1040 * transaction.
1041 */
1042 if (fifo_mode_enable) {
1043 break;
1044 }
1045 #endif
1046 }
1047 #ifdef CONFIG_I2C_IT8XXX2_FIFO_MODE
1048 if (fifo_mode_enable) {
1049 volatile uint8_t *reg_mstfctrl = config->reg_mstfctrl;
1050
1051 /* Disable SMB channels in FIFO mode. */
1052 *reg_mstfctrl &= ~IT8XXX2_SMB_FFEN;
1053 /* Disable I2C write to read FIFO mode. */
1054 if (data->num_msgs == 2) {
1055 i2c_fifo_en_w2r(dev, 0);
1056 }
1057 /* Permit to enter power policy. */
1058 pm_policy_state_lock_put(PM_STATE_STANDBY, PM_ALL_SUBSTATES);
1059 }
1060 #endif
1061 /* reset i2c channel status */
1062 if (data->err || (data->active_msg->flags & I2C_MSG_STOP)) {
1063 data->i2ccs = I2C_CH_NORMAL;
1064 }
1065 /* Save return value. */
1066 ret = i2c_parsing_return_value(dev);
1067 /* Unlock mutex of i2c controller */
1068 k_mutex_unlock(&data->mutex);
1069
1070 return ret;
1071 }
1072
i2c_it8xxx2_isr(const struct device * dev)1073 static void i2c_it8xxx2_isr(const struct device *dev)
1074 {
1075 struct i2c_it8xxx2_data *data = dev->data;
1076 const struct i2c_it8xxx2_config *config = dev->config;
1077
1078 #ifdef CONFIG_I2C_IT8XXX2_FIFO_MODE
1079 volatile uint8_t *reg_mstfctrl = config->reg_mstfctrl;
1080
1081 /* If done doing work, wake up the task waiting for the transfer. */
1082 if (config->fifo_enable && (*reg_mstfctrl & IT8XXX2_SMB_FFEN)) {
1083 if (i2c_fifo_transaction(dev)) {
1084 return;
1085 }
1086 } else
1087 #endif
1088 {
1089 if (i2c_pio_transaction(dev)) {
1090 return;
1091 }
1092 }
1093 irq_disable(config->i2c_irq_base);
1094 k_sem_give(&data->device_sync_sem);
1095 }
1096
i2c_it8xxx2_init(const struct device * dev)1097 static int i2c_it8xxx2_init(const struct device *dev)
1098 {
1099 struct i2c_it8xxx2_data *data = dev->data;
1100 const struct i2c_it8xxx2_config *config = dev->config;
1101 uint8_t *base = config->base;
1102 uint32_t bitrate_cfg;
1103 int error, status;
1104
1105 /* Initialize mutex and semaphore */
1106 k_mutex_init(&data->mutex);
1107 k_sem_init(&data->device_sync_sem, 0, K_SEM_MAX_LIMIT);
1108
1109 /* Enable clock to specified peripheral */
1110 volatile uint8_t *reg = (volatile uint8_t *)
1111 (IT8XXX2_ECPM_BASE + (config->clock_gate_offset >> 8));
1112 uint8_t reg_mask = config->clock_gate_offset & 0xff;
1113 *reg &= ~reg_mask;
1114
1115 /* Enable SMBus function */
1116 /*
1117 * bit0, The SMBus host interface is enabled.
1118 * bit1, Enable to communicate with I2C device
1119 * and support I2C-compatible cycles.
1120 * bit4, This bit controls the reset mechanism
1121 * of SMBus master to handle the SMDAT
1122 * line low if 25ms reg timeout.
1123 */
1124 IT8XXX2_SMB_HOCTL2(base) = IT8XXX2_SMB_SMD_TO_EN | IT8XXX2_SMB_SMHEN;
1125 /*
1126 * bit1, Kill SMBus host transaction.
1127 * bit0, Enable the interrupt for the master interface.
1128 */
1129 IT8XXX2_SMB_HOCTL(base) = IT8XXX2_SMB_KILL | IT8XXX2_SMB_SMHEN;
1130 IT8XXX2_SMB_HOCTL(base) = IT8XXX2_SMB_SMHEN;
1131
1132 /* W/C host status register */
1133 IT8XXX2_SMB_HOSTA(base) = HOSTA_ALL_WC_BIT;
1134 IT8XXX2_SMB_HOCTL2(base) = 0x00;
1135
1136 #ifdef CONFIG_I2C_IT8XXX2_FIFO_MODE
1137 volatile uint8_t *reg_mstfctrl = config->reg_mstfctrl;
1138
1139 if (config->port == SMB_CHANNEL_B && config->fifo_enable) {
1140 /* Select channel B in FIFO2. */
1141 *reg_mstfctrl = IT8XXX2_SMB_FFCHSEL2_B;
1142 } else if (config->port == SMB_CHANNEL_C && config->fifo_enable) {
1143 /* Select channel C in FIFO2. */
1144 *reg_mstfctrl = IT8XXX2_SMB_FFCHSEL2_C;
1145 }
1146 #endif
1147
1148 /* ChannelA-C switch selection of I2C pin */
1149 if (config->port == SMB_CHANNEL_A) {
1150 IT8XXX2_SMB_SMB01CHS = (IT8XXX2_SMB_SMB01CHS &= ~GENMASK(2, 0)) |
1151 config->channel_switch_sel;
1152 } else if (config->port == SMB_CHANNEL_B) {
1153 IT8XXX2_SMB_SMB01CHS = (config->channel_switch_sel << 4) |
1154 (IT8XXX2_SMB_SMB01CHS &= ~GENMASK(6, 4));
1155 } else if (config->port == SMB_CHANNEL_C) {
1156 IT8XXX2_SMB_SMB23CHS = (IT8XXX2_SMB_SMB23CHS &= ~GENMASK(2, 0)) |
1157 config->channel_switch_sel;
1158 }
1159
1160 /* Set clock frequency for I2C ports */
1161 if (config->bitrate == I2C_BITRATE_STANDARD ||
1162 config->bitrate == I2C_BITRATE_FAST ||
1163 config->bitrate == I2C_BITRATE_FAST_PLUS) {
1164 bitrate_cfg = i2c_map_dt_bitrate(config->bitrate);
1165 } else {
1166 /* Device tree specified speed */
1167 bitrate_cfg = I2C_SPEED_DT << I2C_SPEED_SHIFT;
1168 }
1169
1170 error = i2c_it8xxx2_configure(dev, I2C_MODE_CONTROLLER | bitrate_cfg);
1171 data->i2ccs = I2C_CH_NORMAL;
1172
1173 if (error) {
1174 LOG_ERR("i2c: failure initializing");
1175 return error;
1176 }
1177
1178 /* Set the pin to I2C alternate function. */
1179 status = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
1180 if (status < 0) {
1181 LOG_ERR("Failed to configure I2C pins");
1182 return status;
1183 }
1184
1185 return 0;
1186 }
1187
i2c_it8xxx2_recover_bus(const struct device * dev)1188 static int i2c_it8xxx2_recover_bus(const struct device *dev)
1189 {
1190 const struct i2c_it8xxx2_config *config = dev->config;
1191 int i, status;
1192
1193 /* Set SCL of I2C as GPIO pin */
1194 gpio_pin_configure_dt(&config->scl_gpios, GPIO_OUTPUT);
1195 /* Set SDA of I2C as GPIO pin */
1196 gpio_pin_configure_dt(&config->sda_gpios, GPIO_OUTPUT);
1197
1198 /*
1199 * In I2C recovery bus, 1ms sleep interval for bitbanging i2c
1200 * is mainly to ensure that gpio has enough time to go from
1201 * low to high or high to low.
1202 */
1203 /* Pull SCL and SDA pin to high */
1204 gpio_pin_set_dt(&config->scl_gpios, 1);
1205 gpio_pin_set_dt(&config->sda_gpios, 1);
1206 k_msleep(1);
1207
1208 /* Start condition */
1209 gpio_pin_set_dt(&config->sda_gpios, 0);
1210 k_msleep(1);
1211 gpio_pin_set_dt(&config->scl_gpios, 0);
1212 k_msleep(1);
1213
1214 /* 9 cycles of SCL with SDA held high */
1215 for (i = 0; i < 9; i++) {
1216 /* SDA */
1217 gpio_pin_set_dt(&config->sda_gpios, 1);
1218 /* SCL */
1219 gpio_pin_set_dt(&config->scl_gpios, 1);
1220 k_msleep(1);
1221 /* SCL */
1222 gpio_pin_set_dt(&config->scl_gpios, 0);
1223 k_msleep(1);
1224 }
1225 /* SDA */
1226 gpio_pin_set_dt(&config->sda_gpios, 0);
1227 k_msleep(1);
1228
1229 /* Stop condition */
1230 gpio_pin_set_dt(&config->scl_gpios, 1);
1231 k_msleep(1);
1232 gpio_pin_set_dt(&config->sda_gpios, 1);
1233 k_msleep(1);
1234
1235 /* Set GPIO back to I2C alternate function of SCL */
1236 status = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
1237 if (status < 0) {
1238 LOG_ERR("Failed to configure I2C pins");
1239 return status;
1240 }
1241
1242 /* reset i2c port */
1243 i2c_reset(dev);
1244 LOG_ERR("I2C ch%d reset cause %d", config->port,
1245 I2C_RC_NO_IDLE_FOR_START);
1246
1247 return 0;
1248 }
1249
1250 static const struct i2c_driver_api i2c_it8xxx2_driver_api = {
1251 .configure = i2c_it8xxx2_configure,
1252 .get_config = i2c_it8xxx2_get_config,
1253 .transfer = i2c_it8xxx2_transfer,
1254 .recover_bus = i2c_it8xxx2_recover_bus,
1255 };
1256
1257 #ifdef CONFIG_I2C_IT8XXX2_FIFO_MODE
1258 /*
1259 * Sometimes, channel C may write wrong register to the target device.
1260 * This issue occurs when FIFO2 is enabled on channel C. The problem
1261 * arises because FIFO2 is shared between channel B and channel C.
1262 * FIFO2 will be disabled when data access is completed, at which point
1263 * FIFO2 is set to the default configuration for channel B.
1264 * The byte counter of FIFO2 may be affected by channel B. There is a chance
1265 * that channel C may encounter wrong register being written due to FIFO2
1266 * byte counter wrong write after channel B's write operation.
1267 */
1268 BUILD_ASSERT((DT_PROP(DT_NODELABEL(i2c2), fifo_enable) == false),
1269 "Channel C cannot use FIFO mode.");
1270 #endif
1271
1272 #ifdef CONFIG_SOC_IT8XXX2_EC_BUS_24MHZ
1273 #define I2C_IT8XXX2_CHECK_SUPPORTED_CLOCK(inst) \
1274 BUILD_ASSERT((DT_INST_PROP(inst, clock_frequency) == \
1275 I2C_BITRATE_FAST), "Only supports 400 KHz");
1276
1277 DT_INST_FOREACH_STATUS_OKAY(I2C_IT8XXX2_CHECK_SUPPORTED_CLOCK)
1278 #endif
1279
1280 #define I2C_ITE_IT8XXX2_INIT(inst) \
1281 PINCTRL_DT_INST_DEFINE(inst); \
1282 BUILD_ASSERT((DT_INST_PROP(inst, clock_frequency) == \
1283 50000) || \
1284 (DT_INST_PROP(inst, clock_frequency) == \
1285 I2C_BITRATE_STANDARD) || \
1286 (DT_INST_PROP(inst, clock_frequency) == \
1287 I2C_BITRATE_FAST) || \
1288 (DT_INST_PROP(inst, clock_frequency) == \
1289 I2C_BITRATE_FAST_PLUS), "Not support I2C bit rate value"); \
1290 static void i2c_it8xxx2_config_func_##inst(void); \
1291 \
1292 static const struct i2c_it8xxx2_config i2c_it8xxx2_cfg_##inst = { \
1293 .base = (uint8_t *)(DT_INST_REG_ADDR_BY_IDX(inst, 0)), \
1294 .reg_mstfctrl = (uint8_t *)(DT_INST_REG_ADDR_BY_IDX(inst, 1)), \
1295 .irq_config_func = i2c_it8xxx2_config_func_##inst, \
1296 .bitrate = DT_INST_PROP(inst, clock_frequency), \
1297 .i2c_irq_base = DT_INST_IRQN(inst), \
1298 .port = DT_INST_PROP(inst, port_num), \
1299 .channel_switch_sel = DT_INST_PROP(inst, channel_switch_sel), \
1300 .scl_gpios = GPIO_DT_SPEC_INST_GET(inst, scl_gpios), \
1301 .sda_gpios = GPIO_DT_SPEC_INST_GET(inst, sda_gpios), \
1302 .clock_gate_offset = DT_INST_PROP(inst, clock_gate_offset), \
1303 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
1304 .fifo_enable = DT_INST_PROP(inst, fifo_enable), \
1305 }; \
1306 \
1307 static struct i2c_it8xxx2_data i2c_it8xxx2_data_##inst; \
1308 \
1309 I2C_DEVICE_DT_INST_DEFINE(inst, i2c_it8xxx2_init, \
1310 NULL, \
1311 &i2c_it8xxx2_data_##inst, \
1312 &i2c_it8xxx2_cfg_##inst, \
1313 POST_KERNEL, \
1314 CONFIG_I2C_INIT_PRIORITY, \
1315 &i2c_it8xxx2_driver_api); \
1316 \
1317 static void i2c_it8xxx2_config_func_##inst(void) \
1318 { \
1319 IRQ_CONNECT(DT_INST_IRQN(inst), \
1320 0, \
1321 i2c_it8xxx2_isr, \
1322 DEVICE_DT_INST_GET(inst), 0); \
1323 }
1324
1325 DT_INST_FOREACH_STATUS_OKAY(I2C_ITE_IT8XXX2_INIT)
1326
