1 /*
2 * Copyright (c) 2020 ITE Corporation. All Rights Reserved.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT ite_it8xxx2_i2c
8
9 #include <drivers/gpio.h>
10 #include <drivers/i2c.h>
11 #include <drivers/pinmux.h>
12 #include <errno.h>
13 #include <logging/log.h>
14 LOG_MODULE_REGISTER(i2c_ite_it8xxx2);
15 #include "i2c-priv.h"
16 #include <soc.h>
17 #include <soc_dt.h>
18 #include <sys/util.h>
19
20 #define DEV_CFG(dev) \
21 ((const struct i2c_it8xxx2_config * const)(dev)->config)
22 #define DEV_DATA(dev) \
23 ((struct i2c_it8xxx2_data * const)(dev)->data)
24
25 #define I2C_STANDARD_PORT_COUNT 3
26 /* Default PLL frequency. */
27 #define PLL_CLOCK 48000000
28
29 /*
30 * Structure i2c_alts_cfg is about the alternate function
31 * setting of i2c, this config will be used at initial
32 * time and recover bus.
33 */
34 struct i2c_alts_cfg {
35 /* Pinmux control group */
36 const struct device *pinctrls;
37 /* GPIO pin */
38 uint8_t pin;
39 /* Alternate function */
40 uint8_t alt_fun;
41 };
42
43 struct i2c_it8xxx2_config {
44 void (*irq_config_func)(void);
45 uint32_t bitrate;
46 uint8_t *base;
47 uint8_t i2c_irq_base;
48 uint8_t port;
49 /* I2C alternate configuration */
50 const struct i2c_alts_cfg *alts_list;
51 /* GPIO handle */
52 const struct device *gpio_dev;
53 };
54
55 enum i2c_pin_fun {
56 SCL = 0,
57 SDA,
58 };
59
60 enum i2c_ch_status {
61 I2C_CH_NORMAL = 0,
62 I2C_CH_REPEAT_START,
63 I2C_CH_WAIT_READ,
64 I2C_CH_WAIT_NEXT_XFER,
65 };
66
67 struct i2c_it8xxx2_data {
68 enum i2c_ch_status i2ccs;
69 struct i2c_msg *msgs;
70 struct k_mutex mutex;
71 struct k_sem device_sync_sem;
72 /* Index into output data */
73 size_t widx;
74 /* Index into input data */
75 size_t ridx;
76 /* Error code, if any */
77 uint32_t err;
78 /* address of device */
79 uint16_t addr_16bit;
80 /* Frequency setting */
81 uint8_t freq;
82 /* wait for stop bit interrupt */
83 uint8_t stop;
84 };
85
86 enum enhanced_i2c_transfer_direct {
87 TX_DIRECT,
88 RX_DIRECT,
89 };
90
91 enum enhanced_i2c_ctl {
92 /* Hardware reset */
93 E_HW_RST = 0x01,
94 /* Stop */
95 E_STOP = 0x02,
96 /* Start & Repeat start */
97 E_START = 0x04,
98 /* Acknowledge */
99 E_ACK = 0x08,
100 /* State reset */
101 E_STS_RST = 0x10,
102 /* Mode select */
103 E_MODE_SEL = 0x20,
104 /* I2C interrupt enable */
105 E_INT_EN = 0x40,
106 /* 0 : Standard mode , 1 : Receive mode */
107 E_RX_MODE = 0x80,
108 /* State reset and hardware reset */
109 E_STS_AND_HW_RST = (E_STS_RST | E_HW_RST),
110 /* Generate start condition and transmit slave address */
111 E_START_ID = (E_INT_EN | E_MODE_SEL | E_ACK | E_START | E_HW_RST),
112 /* Generate stop condition */
113 E_FINISH = (E_INT_EN | E_MODE_SEL | E_ACK | E_STOP | E_HW_RST),
114 };
115
116 enum enhanced_i2c_host_status {
117 /* ACK receive */
118 E_HOSTA_ACK = 0x01,
119 /* Interrupt pending */
120 E_HOSTA_INTP = 0x02,
121 /* Read/Write */
122 E_HOSTA_RW = 0x04,
123 /* Time out error */
124 E_HOSTA_TMOE = 0x08,
125 /* Arbitration lost */
126 E_HOSTA_ARB = 0x10,
127 /* Bus busy */
128 E_HOSTA_BB = 0x20,
129 /* Address match */
130 E_HOSTA_AM = 0x40,
131 /* Byte done status */
132 E_HOSTA_BDS = 0x80,
133 /* time out or lost arbitration */
134 E_HOSTA_ANY_ERROR = (E_HOSTA_TMOE | E_HOSTA_ARB),
135 /* Byte transfer done and ACK receive */
136 E_HOSTA_BDS_AND_ACK = (E_HOSTA_BDS | E_HOSTA_ACK),
137 };
138
139 enum i2c_reset_cause {
140 I2C_RC_NO_IDLE_FOR_START = 1,
141 I2C_RC_TIMEOUT,
142 };
143
144 /* Start smbus session from idle state */
145 #define I2C_MSG_START BIT(5)
146
147 #define I2C_LINE_SCL_HIGH BIT(0)
148 #define I2C_LINE_SDA_HIGH BIT(1)
149 #define I2C_LINE_IDLE (I2C_LINE_SCL_HIGH | I2C_LINE_SDA_HIGH)
150
151 struct i2c_pin {
152 volatile uint8_t *mirror_clk;
153 volatile uint8_t *mirror_data;
154 uint8_t clk_mask;
155 uint8_t data_mask;
156 };
157
158 static const struct i2c_pin i2c_pin_regs[] = {
159 { &GPDMRB, &GPDMRB, 0x08, 0x10},
160 { &GPDMRC, &GPDMRC, 0x02, 0x04},
161 { &GPDMRF, &GPDMRF, 0x40, 0x80},
162 { &GPDMRH, &GPDMRH, 0x02, 0x04},
163 { &GPDMRE, &GPDMRE, 0x01, 0x80},
164 { &GPDMRA, &GPDMRA, 0x10, 0x20},
165 };
166
i2c_parsing_return_value(const struct device * dev)167 static int i2c_parsing_return_value(const struct device *dev)
168 {
169 struct i2c_it8xxx2_data *data = DEV_DATA(dev);
170 const struct i2c_it8xxx2_config *config = DEV_CFG(dev);
171
172 if (!data->err)
173 return 0;
174
175 /* Connection timed out */
176 if (data->err == ETIMEDOUT)
177 return -ETIMEDOUT;
178
179 if (config->port < I2C_STANDARD_PORT_COUNT) {
180 /* The device does not respond ACK */
181 if (data->err == HOSTA_NACK)
182 return -ENXIO;
183 else
184 return -EIO;
185 } else {
186 /* The device does not respond ACK */
187 if (data->err == E_HOSTA_ACK)
188 return -ENXIO;
189 else
190 return -EIO;
191 }
192 }
193
i2c_get_line_levels(const struct device * dev)194 static int i2c_get_line_levels(const struct device *dev)
195 {
196 const struct i2c_it8xxx2_config *config = DEV_CFG(dev);
197 uint8_t *base = config->base;
198 int pin_sts = 0;
199
200 if (config->port < I2C_STANDARD_PORT_COUNT) {
201 return IT83XX_SMB_SMBPCTL(base) & 0x03;
202 }
203
204 if (*i2c_pin_regs[config->port].mirror_clk &
205 i2c_pin_regs[config->port].clk_mask) {
206 pin_sts |= I2C_LINE_SCL_HIGH;
207 }
208 if (*i2c_pin_regs[config->port].mirror_data &
209 i2c_pin_regs[config->port].data_mask) {
210 pin_sts |= I2C_LINE_SDA_HIGH;
211 }
212
213 return pin_sts;
214 }
215
i2c_is_busy(const struct device * dev)216 static int i2c_is_busy(const struct device *dev)
217 {
218 const struct i2c_it8xxx2_config *config = DEV_CFG(dev);
219 uint8_t *base = config->base;
220
221 if (config->port < I2C_STANDARD_PORT_COUNT) {
222 return (IT83XX_SMB_HOSTA(base) &
223 (HOSTA_HOBY | HOSTA_ALL_WC_BIT));
224 }
225
226 return (IT83XX_I2C_STR(base) & E_HOSTA_BB);
227 }
228
i2c_bus_not_available(const struct device * dev)229 static int i2c_bus_not_available(const struct device *dev)
230 {
231 if (i2c_is_busy(dev) ||
232 (i2c_get_line_levels(dev) != I2C_LINE_IDLE)) {
233 return -EIO;
234 }
235
236 return 0;
237 }
238
i2c_reset(const struct device * dev)239 static void i2c_reset(const struct device *dev)
240 {
241 const struct i2c_it8xxx2_config *config = DEV_CFG(dev);
242 uint8_t *base = config->base;
243
244 if (config->port < I2C_STANDARD_PORT_COUNT) {
245 /* bit1, kill current transaction. */
246 IT83XX_SMB_HOCTL(base) = 0x2;
247 IT83XX_SMB_HOCTL(base) = 0;
248 /* W/C host status register */
249 IT83XX_SMB_HOSTA(base) = HOSTA_ALL_WC_BIT;
250 } else {
251 /* State reset and hardware reset */
252 IT83XX_I2C_CTR(base) = E_STS_AND_HW_RST;
253 }
254 }
255
256 /*
257 * Set i2c standard port (A, B, or C) runs at 400kHz by using timing registers
258 * (offset 0h ~ 7h).
259 */
i2c_standard_port_timing_regs_400khz(uint8_t port)260 static void i2c_standard_port_timing_regs_400khz(uint8_t port)
261 {
262 /* Port clock frequency depends on setting of timing registers. */
263 IT83XX_SMB_SCLKTS(port) = 0;
264 /* Suggested setting of timing registers of 400kHz. */
265 IT83XX_SMB_4P7USL = 0x6;
266 IT83XX_SMB_4P0USL = 0;
267 IT83XX_SMB_300NS = 0x1;
268 IT83XX_SMB_250NS = 0x2;
269 IT83XX_SMB_45P3USL = 0x6a;
270 IT83XX_SMB_45P3USH = 0x1;
271 IT83XX_SMB_4P7A4P0H = 0;
272 }
273
274 /* Set clock frequency for i2c port A, B , or C */
i2c_standard_port_set_frequency(const struct device * dev,int freq_khz,int freq_set)275 static void i2c_standard_port_set_frequency(const struct device *dev,
276 int freq_khz, int freq_set)
277 {
278 const struct i2c_it8xxx2_config *config = DEV_CFG(dev);
279
280 /*
281 * If port's clock frequency is 400kHz, we use timing registers
282 * for setting. So we can adjust tlow to meet timing.
283 * The others use basic 50/100/1000 KHz setting.
284 */
285 if (freq_khz == 400) {
286 i2c_standard_port_timing_regs_400khz(config->port);
287 } else {
288 IT83XX_SMB_SCLKTS(config->port) = freq_set;
289 }
290
291 /* This field defines the SMCLK0/1/2 clock/data low timeout. */
292 IT83XX_SMB_25MS = I2C_CLK_LOW_TIMEOUT;
293 }
294
295 /* Set clock frequency for i2c port D, E , or F */
i2c_enhanced_port_set_frequency(const struct device * dev,int freq_khz)296 static void i2c_enhanced_port_set_frequency(const struct device *dev,
297 int freq_khz)
298 {
299 struct i2c_it8xxx2_data *data = DEV_DATA(dev);
300 const struct i2c_it8xxx2_config *config = DEV_CFG(dev);
301 uint32_t clk_div, psr;
302 uint8_t *base = config->base;
303
304 /*
305 * Let psr(Prescale) = IT83XX_I2C_PSR(p_ch)
306 * Then, 1 SCL cycle = 2 x (psr + 2) x SMBus clock cycle
307 * SMBus clock = PLL_CLOCK / clk_div
308 * SMBus clock cycle = 1 / SMBus clock
309 * 1 SCL cycle = 1 / (1000 x freq)
310 * 1 / (1000 x freq) =
311 * 2 x (psr + 2) x (1 / (PLL_CLOCK / clk_div))
312 * psr = ((PLL_CLOCK / clk_div) x
313 * (1 / (1000 x freq)) x (1 / 2)) - 2
314 */
315 if (freq_khz) {
316 /* Get SMBus clock divide value */
317 clk_div = (SCDCR2 & 0x0F) + 1U;
318 /* Calculate PSR value */
319 psr = (PLL_CLOCK / (clk_div * (2U * 1000U * freq_khz))) - 2U;
320 /* Set psr value under 0xFD */
321 if (psr > 0xFD) {
322 psr = 0xFD;
323 }
324
325 /* Set I2C Speed */
326 IT83XX_I2C_PSR(base) = psr & 0xFF;
327 IT83XX_I2C_HSPR(base) = psr & 0xFF;
328 /* Backup */
329 data->freq = psr & 0xFF;
330 }
331
332 }
333
i2c_it8xxx2_configure(const struct device * dev,uint32_t dev_config_raw)334 static int i2c_it8xxx2_configure(const struct device *dev,
335 uint32_t dev_config_raw)
336 {
337 const struct i2c_it8xxx2_config *config = DEV_CFG(dev);
338 uint32_t freq, freq_set;
339
340 if (!(I2C_MODE_MASTER & dev_config_raw)) {
341 return -EINVAL;
342 }
343
344 if (I2C_ADDR_10_BITS & dev_config_raw) {
345 return -EINVAL;
346 }
347
348 switch (I2C_SPEED_GET(dev_config_raw)) {
349 case I2C_SPEED_STANDARD:
350 freq = 100;
351 freq_set = 2;
352 break;
353 case I2C_SPEED_FAST:
354 freq = 400;
355 freq_set = 3;
356 break;
357 case I2C_SPEED_FAST_PLUS:
358 freq = 1000;
359 freq_set = 4;
360 break;
361 default:
362 return -EINVAL;
363 }
364
365 if (config->port < I2C_STANDARD_PORT_COUNT) {
366 i2c_standard_port_set_frequency(dev, freq, freq_set);
367 } else {
368 i2c_enhanced_port_set_frequency(dev, freq);
369 }
370
371 return 0;
372 }
373
enhanced_i2c_error(const struct device * dev)374 static int enhanced_i2c_error(const struct device *dev)
375 {
376 struct i2c_it8xxx2_data *data = DEV_DATA(dev);
377 const struct i2c_it8xxx2_config *config = DEV_CFG(dev);
378 uint8_t *base = config->base;
379 uint32_t i2c_str = IT83XX_I2C_STR(base);
380
381 if (i2c_str & E_HOSTA_ANY_ERROR) {
382 data->err = i2c_str & E_HOSTA_ANY_ERROR;
383 /* device does not respond ACK */
384 } else if ((i2c_str & E_HOSTA_BDS_AND_ACK) == E_HOSTA_BDS) {
385 if (IT83XX_I2C_CTR(base) & E_ACK)
386 data->err = E_HOSTA_ACK;
387 }
388
389 return data->err;
390 }
391
enhanced_i2c_start(const struct device * dev)392 static void enhanced_i2c_start(const struct device *dev)
393 {
394 struct i2c_it8xxx2_data *data = DEV_DATA(dev);
395 const struct i2c_it8xxx2_config *config = DEV_CFG(dev);
396 uint8_t *base = config->base;
397
398 /* State reset and hardware reset */
399 IT83XX_I2C_CTR(base) = E_STS_AND_HW_RST;
400 /* Set i2c frequency */
401 IT83XX_I2C_PSR(base) = data->freq;
402 IT83XX_I2C_HSPR(base) = data->freq;
403 /*
404 * Set time out register.
405 * I2C D/E/F clock/data low timeout.
406 */
407 IT83XX_I2C_TOR(base) = I2C_CLK_LOW_TIMEOUT;
408 /* bit1: Enable enhanced i2c module */
409 IT83XX_I2C_CTR1(base) = BIT(1);
410 }
411
i2c_pio_trans_data(const struct device * dev,enum enhanced_i2c_transfer_direct direct,uint16_t trans_data,int first_byte)412 static void i2c_pio_trans_data(const struct device *dev,
413 enum enhanced_i2c_transfer_direct direct,
414 uint16_t trans_data, int first_byte)
415 {
416 struct i2c_it8xxx2_data *data = DEV_DATA(dev);
417 const struct i2c_it8xxx2_config *config = DEV_CFG(dev);
418 uint8_t *base = config->base;
419 uint32_t nack = 0;
420
421 if (first_byte) {
422 /* First byte must be slave address. */
423 IT83XX_I2C_DTR(base) = trans_data |
424 (direct == RX_DIRECT ? BIT(0) : 0);
425 /* start or repeat start signal. */
426 IT83XX_I2C_CTR(base) = E_START_ID;
427 } else {
428 if (direct == TX_DIRECT) {
429 /* Transmit data */
430 IT83XX_I2C_DTR(base) = (uint8_t)trans_data;
431 } else {
432 /*
433 * Receive data.
434 * Last byte should be NACK in the end of read cycle
435 */
436 if (((data->ridx + 1) == data->msgs->len) &&
437 (data->msgs->flags & I2C_MSG_STOP)) {
438 nack = 1;
439 }
440 }
441 /* Set hardware reset to start next transmission */
442 IT83XX_I2C_CTR(base) = E_INT_EN | E_MODE_SEL |
443 E_HW_RST | (nack ? 0 : E_ACK);
444 }
445 }
446
enhanced_i2c_tran_read(const struct device * dev)447 static int enhanced_i2c_tran_read(const struct device *dev)
448 {
449 struct i2c_it8xxx2_data *data = DEV_DATA(dev);
450 const struct i2c_it8xxx2_config *config = DEV_CFG(dev);
451 uint8_t *base = config->base;
452 uint8_t in_data = 0;
453
454 if (data->msgs->flags & I2C_MSG_START) {
455 /* clear start flag */
456 data->msgs->flags &= ~I2C_MSG_START;
457 enhanced_i2c_start(dev);
458 /* Direct read */
459 data->i2ccs = I2C_CH_WAIT_READ;
460 /* Send ID */
461 i2c_pio_trans_data(dev, RX_DIRECT, data->addr_16bit << 1, 1);
462 } else {
463 if (data->i2ccs) {
464 if (data->i2ccs == I2C_CH_WAIT_READ) {
465 data->i2ccs = I2C_CH_NORMAL;
466 /* Receive data */
467 i2c_pio_trans_data(dev, RX_DIRECT, in_data, 0);
468
469 /* data->msgs->flags == I2C_MSG_RESTART */
470 } else {
471 /* Write to read */
472 data->i2ccs = I2C_CH_WAIT_READ;
473 /* Send ID */
474 i2c_pio_trans_data(dev, RX_DIRECT,
475 data->addr_16bit << 1, 1);
476 }
477 /* Turn on irq before next direct read */
478 irq_enable(config->i2c_irq_base);
479 } else {
480 if (data->ridx < data->msgs->len) {
481 /* read data */
482 *(data->msgs->buf++) = IT83XX_I2C_DRR(base);
483 data->ridx++;
484 /* done */
485 if (data->ridx == data->msgs->len) {
486 data->msgs->len = 0;
487 if (data->msgs->flags & I2C_MSG_STOP) {
488 data->i2ccs = I2C_CH_NORMAL;
489 IT83XX_I2C_CTR(base) = E_FINISH;
490 /* wait for stop bit interrupt */
491 data->stop = 1;
492 return 1;
493 }
494 /* End the transaction */
495 data->i2ccs = I2C_CH_WAIT_READ;
496 return 0;
497 }
498 /* read next byte */
499 i2c_pio_trans_data(dev, RX_DIRECT, in_data, 0);
500 }
501 }
502 }
503 return 1;
504 }
505
enhanced_i2c_tran_write(const struct device * dev)506 static int enhanced_i2c_tran_write(const struct device *dev)
507 {
508 struct i2c_it8xxx2_data *data = DEV_DATA(dev);
509 const struct i2c_it8xxx2_config *config = DEV_CFG(dev);
510 uint8_t *base = config->base;
511 uint8_t out_data;
512
513 if (data->msgs->flags & I2C_MSG_START) {
514 /* Clear start bit */
515 data->msgs->flags &= ~I2C_MSG_START;
516 enhanced_i2c_start(dev);
517 /* Send ID */
518 i2c_pio_trans_data(dev, TX_DIRECT, data->addr_16bit << 1, 1);
519 } else {
520 /* Host has completed the transmission of a byte */
521 if (data->widx < data->msgs->len) {
522 out_data = *(data->msgs->buf++);
523 data->widx++;
524
525 /* Send Byte */
526 i2c_pio_trans_data(dev, TX_DIRECT, out_data, 0);
527 if (data->i2ccs == I2C_CH_WAIT_NEXT_XFER) {
528 data->i2ccs = I2C_CH_NORMAL;
529 irq_enable(config->i2c_irq_base);
530 }
531 } else {
532 /* done */
533 data->msgs->len = 0;
534 if (data->msgs->flags & I2C_MSG_STOP) {
535 IT83XX_I2C_CTR(base) = E_FINISH;
536 /* wait for stop bit interrupt */
537 data->stop = 1;
538 } else {
539 /* Direct write with direct read */
540 data->i2ccs = I2C_CH_WAIT_NEXT_XFER;
541 return 0;
542 }
543 }
544 }
545 return 1;
546 }
547
i2c_r_last_byte(const struct device * dev)548 static void i2c_r_last_byte(const struct device *dev)
549 {
550 struct i2c_it8xxx2_data *data = DEV_DATA(dev);
551 const struct i2c_it8xxx2_config *config = DEV_CFG(dev);
552 uint8_t *base = config->base;
553
554 /*
555 * bit5, The firmware shall write 1 to this bit
556 * when the next byte will be the last byte for i2c read.
557 */
558 if ((data->msgs->flags & I2C_MSG_STOP) &&
559 (data->ridx == data->msgs->len - 1)) {
560 IT83XX_SMB_HOCTL(base) |= 0x20;
561 }
562 }
563
i2c_w2r_change_direction(const struct device * dev)564 static void i2c_w2r_change_direction(const struct device *dev)
565 {
566 const struct i2c_it8xxx2_config *config = DEV_CFG(dev);
567 uint8_t *base = config->base;
568
569 /* I2C switch direction */
570 if (IT83XX_SMB_HOCTL2(base) & 0x08) {
571 i2c_r_last_byte(dev);
572 IT83XX_SMB_HOSTA(base) = HOSTA_NEXT_BYTE;
573 } else {
574 /*
575 * bit2, I2C switch direction wait.
576 * bit3, I2C switch direction enable.
577 */
578 IT83XX_SMB_HOCTL2(base) |= 0x0C;
579 IT83XX_SMB_HOSTA(base) = HOSTA_NEXT_BYTE;
580 i2c_r_last_byte(dev);
581 IT83XX_SMB_HOCTL2(base) &= ~0x04;
582 }
583 }
584
i2c_tran_read(const struct device * dev)585 static int i2c_tran_read(const struct device *dev)
586 {
587 struct i2c_it8xxx2_data *data = DEV_DATA(dev);
588 const struct i2c_it8xxx2_config *config = DEV_CFG(dev);
589 uint8_t *base = config->base;
590
591 if (data->msgs->flags & I2C_MSG_START) {
592 /* i2c enable */
593 IT83XX_SMB_HOCTL2(base) = 0x13;
594 /*
595 * bit0, Direction of the host transfer.
596 * bit[1:7}, Address of the targeted slave.
597 */
598 IT83XX_SMB_TRASLA(base) = (uint8_t)(data->addr_16bit << 1) | 0x01;
599 /* clear start flag */
600 data->msgs->flags &= ~I2C_MSG_START;
601 /*
602 * bit0, Host interrupt enable.
603 * bit[2:4}, Extend command.
604 * bit5, The firmware shall write 1 to this bit
605 * when the next byte will be the last byte.
606 * bit6, start.
607 */
608 if ((data->msgs->len == 1) &&
609 (data->msgs->flags & I2C_MSG_STOP)) {
610 IT83XX_SMB_HOCTL(base) = 0x7D;
611 } else {
612 IT83XX_SMB_HOCTL(base) = 0x5D;
613 }
614 } else {
615 if ((data->i2ccs == I2C_CH_REPEAT_START) ||
616 (data->i2ccs == I2C_CH_WAIT_READ)) {
617 if (data->i2ccs == I2C_CH_REPEAT_START) {
618 /* write to read */
619 i2c_w2r_change_direction(dev);
620 } else {
621 /* For last byte */
622 i2c_r_last_byte(dev);
623 /* W/C for next byte */
624 IT83XX_SMB_HOSTA(base) = HOSTA_NEXT_BYTE;
625 }
626 data->i2ccs = I2C_CH_NORMAL;
627 irq_enable(config->i2c_irq_base);
628 } else if (IT83XX_SMB_HOSTA(base) & HOSTA_BDS) {
629 if (data->ridx < data->msgs->len) {
630 /* To get received data. */
631 *(data->msgs->buf++) = IT83XX_SMB_HOBDB(base);
632 data->ridx++;
633 /* For last byte */
634 i2c_r_last_byte(dev);
635 /* done */
636 if (data->ridx == data->msgs->len) {
637 data->msgs->len = 0;
638 if (data->msgs->flags & I2C_MSG_STOP) {
639 /* W/C for finish */
640 IT83XX_SMB_HOSTA(base) =
641 HOSTA_NEXT_BYTE;
642
643 data->stop = 1;
644 } else {
645 data->i2ccs = I2C_CH_WAIT_READ;
646 return 0;
647 }
648 } else {
649 /* W/C for next byte */
650 IT83XX_SMB_HOSTA(base) =
651 HOSTA_NEXT_BYTE;
652 }
653 }
654 }
655 }
656 return 1;
657
658 }
659
i2c_tran_write(const struct device * dev)660 static int i2c_tran_write(const struct device *dev)
661 {
662 struct i2c_it8xxx2_data *data = DEV_DATA(dev);
663 const struct i2c_it8xxx2_config *config = DEV_CFG(dev);
664 uint8_t *base = config->base;
665
666 if (data->msgs->flags & I2C_MSG_START) {
667 /* i2c enable */
668 IT83XX_SMB_HOCTL2(base) = 0x13;
669 /*
670 * bit0, Direction of the host transfer.
671 * bit[1:7}, Address of the targeted slave.
672 */
673 IT83XX_SMB_TRASLA(base) = (uint8_t)data->addr_16bit << 1;
674 /* Send first byte */
675 IT83XX_SMB_HOBDB(base) = *(data->msgs->buf++);
676
677 data->widx++;
678 /* clear start flag */
679 data->msgs->flags &= ~I2C_MSG_START;
680 /*
681 * bit0, Host interrupt enable.
682 * bit[2:4}, Extend command.
683 * bit6, start.
684 */
685 IT83XX_SMB_HOCTL(base) = 0x5D;
686 } else {
687 /* Host has completed the transmission of a byte */
688 if (IT83XX_SMB_HOSTA(base) & HOSTA_BDS) {
689 if (data->widx < data->msgs->len) {
690 /* Send next byte */
691 IT83XX_SMB_HOBDB(base) = *(data->msgs->buf++);
692
693 data->widx++;
694 /* W/C byte done for next byte */
695 IT83XX_SMB_HOSTA(base) = HOSTA_NEXT_BYTE;
696
697 if (data->i2ccs == I2C_CH_REPEAT_START) {
698 data->i2ccs = I2C_CH_NORMAL;
699 irq_enable(config->i2c_irq_base);
700 }
701 } else {
702 /* done */
703 data->msgs->len = 0;
704 if (data->msgs->flags & I2C_MSG_STOP) {
705 /* set I2C_EN = 0 */
706 IT83XX_SMB_HOCTL2(base) = 0x11;
707 /* W/C byte done for finish */
708 IT83XX_SMB_HOSTA(base) =
709 HOSTA_NEXT_BYTE;
710
711 data->stop = 1;
712 } else {
713 data->i2ccs = I2C_CH_REPEAT_START;
714 return 0;
715 }
716 }
717 }
718 }
719 return 1;
720
721 }
722
i2c_transaction(const struct device * dev)723 static int i2c_transaction(const struct device *dev)
724 {
725 struct i2c_it8xxx2_data *data = DEV_DATA(dev);
726 const struct i2c_it8xxx2_config *config = DEV_CFG(dev);
727 uint8_t *base = config->base;
728
729 if (config->port < I2C_STANDARD_PORT_COUNT) {
730 /* any error */
731 if (IT83XX_SMB_HOSTA(base) & HOSTA_ANY_ERROR) {
732 data->err = (IT83XX_SMB_HOSTA(base) & HOSTA_ANY_ERROR);
733 } else {
734 if (!data->stop) {
735 if (data->msgs->flags & I2C_MSG_READ) {
736 return i2c_tran_read(dev);
737 } else {
738 return i2c_tran_write(dev);
739 }
740 }
741 /* wait finish */
742 if (!(IT83XX_SMB_HOSTA(base) & HOSTA_FINTR)) {
743 return 1;
744 }
745 }
746 /* W/C */
747 IT83XX_SMB_HOSTA(base) = HOSTA_ALL_WC_BIT;
748 /* disable the SMBus host interface */
749 IT83XX_SMB_HOCTL2(base) = 0x00;
750 } else {
751
752 /* no error */
753 if (!(enhanced_i2c_error(dev))) {
754 if (!data->stop) {
755 /* i2c read */
756 if (data->msgs->flags & I2C_MSG_READ) {
757 return enhanced_i2c_tran_read(dev);
758 /* i2c write */
759 } else {
760 return enhanced_i2c_tran_write(dev);
761 }
762 }
763 }
764 IT83XX_I2C_CTR(base) = E_STS_AND_HW_RST;
765 IT83XX_I2C_CTR1(base) = 0;
766 }
767 data->stop = 0;
768 /* done doing work */
769 return 0;
770 }
771
i2c_it8xxx2_transfer(const struct device * dev,struct i2c_msg * msgs,uint8_t num_msgs,uint16_t addr)772 static int i2c_it8xxx2_transfer(const struct device *dev, struct i2c_msg *msgs,
773 uint8_t num_msgs, uint16_t addr)
774 {
775 struct i2c_it8xxx2_data *data = DEV_DATA(dev);
776 const struct i2c_it8xxx2_config *config = DEV_CFG(dev);
777 int res;
778
779 /* Check for NULL pointers */
780 if (dev == NULL) {
781 LOG_ERR("Device handle is NULL");
782 return -EINVAL;
783 }
784 if (msgs == NULL) {
785 LOG_ERR("Device message is NULL");
786 return -EINVAL;
787 }
788
789 /* Lock mutex of i2c controller */
790 k_mutex_lock(&data->mutex, K_FOREVER);
791 /*
792 * If the transaction of write to read is divided into two
793 * transfers, the repeat start transfer uses this flag to
794 * exclude checking bus busy.
795 */
796 if (data->i2ccs == I2C_CH_NORMAL) {
797 /* Make sure we're in a good state to start */
798 if (i2c_bus_not_available(dev)) {
799 /* Recovery I2C bus */
800 i2c_recover_bus(dev);
801 /*
802 * After resetting I2C bus, if I2C bus is not available
803 * (No external pull-up), drop the transaction.
804 */
805 if (i2c_bus_not_available(dev)) {
806 /* Unlock mutex of i2c controller */
807 k_mutex_unlock(&data->mutex);
808 return -EIO;
809 }
810 }
811
812 msgs->flags |= I2C_MSG_START;
813 }
814
815 for (int i = 0; i < num_msgs; i++) {
816
817 data->widx = 0;
818 data->ridx = 0;
819 data->err = 0;
820 data->msgs = &(msgs[i]);
821 data->addr_16bit = addr;
822
823 if (msgs->flags & I2C_MSG_START) {
824 data->i2ccs = I2C_CH_NORMAL;
825 /* enable i2c interrupt */
826 irq_enable(config->i2c_irq_base);
827 }
828 /* Start transaction */
829 i2c_transaction(dev);
830 /* Wait for the transfer to complete */
831 /* TODO: the timeout should be adjustable */
832 res = k_sem_take(&data->device_sync_sem, K_MSEC(100));
833 /*
834 * The irq will be enabled at the condition of start or
835 * repeat start of I2C. If timeout occurs without being
836 * wake up during suspend(ex: interrupt is not fired),
837 * the irq should be disabled immediately.
838 */
839 irq_disable(config->i2c_irq_base);
840 /*
841 * The transaction is dropped on any error(timeout, NACK, fail,
842 * bus error, device error).
843 */
844 if (data->err)
845 break;
846
847 if (res != 0) {
848 data->err = ETIMEDOUT;
849 /* reset i2c port */
850 i2c_reset(dev);
851 printk("I2C ch%d:0x%X reset cause %d\n",
852 config->port, data->addr_16bit, I2C_RC_TIMEOUT);
853 /* If this message is sent fail, drop the transaction. */
854 break;
855 }
856 }
857
858 /* reset i2c channel status */
859 if (data->err || (msgs->flags & I2C_MSG_STOP)) {
860 data->i2ccs = I2C_CH_NORMAL;
861 }
862 /* Unlock mutex of i2c controller */
863 k_mutex_unlock(&data->mutex);
864
865 return i2c_parsing_return_value(dev);
866 }
867
i2c_it8xxx2_isr(void * arg)868 static void i2c_it8xxx2_isr(void *arg)
869 {
870 struct device *dev = (struct device *)arg;
871 struct i2c_it8xxx2_data *data = DEV_DATA(dev);
872 const struct i2c_it8xxx2_config *config = DEV_CFG(dev);
873
874 /* If done doing work, wake up the task waiting for the transfer */
875 if (!i2c_transaction(dev)) {
876 k_sem_give(&data->device_sync_sem);
877 irq_disable(config->i2c_irq_base);
878 }
879 }
880
i2c_it8xxx2_init(const struct device * dev)881 static int i2c_it8xxx2_init(const struct device *dev)
882 {
883 struct i2c_it8xxx2_data *data = DEV_DATA(dev);
884 const struct i2c_it8xxx2_config *config = DEV_CFG(dev);
885 uint8_t *base = config->base;
886 uint32_t bitrate_cfg, offset = 0;
887 int error;
888
889 /* Initialize mutex and semaphore */
890 k_mutex_init(&data->mutex);
891 k_sem_init(&data->device_sync_sem, 0, K_SEM_MAX_LIMIT);
892
893 switch ((uint32_t)base) {
894 case DT_REG_ADDR(DT_NODELABEL(i2c0)):
895 offset = CGC_OFFSET_SMBA;
896 break;
897 case DT_REG_ADDR(DT_NODELABEL(i2c1)):
898 offset = CGC_OFFSET_SMBB;
899 break;
900 case DT_REG_ADDR(DT_NODELABEL(i2c2)):
901 offset = CGC_OFFSET_SMBC;
902 break;
903 case DT_REG_ADDR(DT_NODELABEL(i2c3)):
904 offset = CGC_OFFSET_SMBD;
905 /* Enable SMBus D channel */
906 GCR2 |= SMB3E;
907 break;
908 case DT_REG_ADDR(DT_NODELABEL(i2c4)):
909 offset = CGC_OFFSET_SMBE;
910 /* Enable SMBus E channel */
911 PMER1 |= 0x01;
912 break;
913 case DT_REG_ADDR(DT_NODELABEL(i2c5)):
914 offset = CGC_OFFSET_SMBF;
915 /* Enable SMBus F channel */
916 PMER1 |= 0x02;
917 break;
918 }
919
920 /* Enable I2C function. */
921 volatile uint8_t *reg = (volatile uint8_t *)
922 (IT83XX_ECPM_BASE + (offset >> 8));
923 uint8_t reg_mask = offset & 0xff;
924 *reg &= ~reg_mask;
925
926 if (config->port < I2C_STANDARD_PORT_COUNT) {
927 /*
928 * bit0, The SMBus host interface is enabled.
929 * bit1, Enable to communicate with I2C device
930 * and support I2C-compatible cycles.
931 * bit4, This bit controls the reset mechanism
932 * of SMBus master to handle the SMDAT
933 * line low if 25ms reg timeout.
934 */
935 IT83XX_SMB_HOCTL2(base) = 0x11;
936 /*
937 * bit1, Kill SMBus host transaction.
938 * bit0, Enable the interrupt for the master interface.
939 */
940 IT83XX_SMB_HOCTL(base) = 0x03;
941 IT83XX_SMB_HOCTL(base) = 0x01;
942
943 /* W/C host status register */
944 IT83XX_SMB_HOSTA(base) = HOSTA_ALL_WC_BIT;
945 IT83XX_SMB_HOCTL2(base) = 0x00;
946
947 } else {
948 /* Software reset */
949 IT83XX_I2C_DHTR(base) |= 0x80;
950 IT83XX_I2C_DHTR(base) &= 0x7F;
951 /* State reset and hardware reset */
952 IT83XX_I2C_CTR(base) = E_STS_AND_HW_RST;
953 /* bit1, Module enable */
954 IT83XX_I2C_CTR1(base) = 0;
955 }
956
957 bitrate_cfg = i2c_map_dt_bitrate(config->bitrate);
958 error = i2c_it8xxx2_configure(dev, I2C_MODE_MASTER | bitrate_cfg);
959 data->i2ccs = I2C_CH_NORMAL;
960
961 if (error) {
962 LOG_ERR("i2c: failure initializing");
963 return error;
964 }
965
966 /* The pin is set to I2C alternate function of SCL */
967 pinmux_pin_set(config->alts_list[SCL].pinctrls,
968 config->alts_list[SCL].pin,
969 config->alts_list[SCL].alt_fun);
970 /* The pin is set to I2C alternate function of SDA */
971 pinmux_pin_set(config->alts_list[SDA].pinctrls,
972 config->alts_list[SDA].pin,
973 config->alts_list[SDA].alt_fun);
974
975 return 0;
976 }
977
i2c_it8xxx2_recover_bus(const struct device * dev)978 static int i2c_it8xxx2_recover_bus(const struct device *dev)
979 {
980 const struct i2c_it8xxx2_config *config = DEV_CFG(dev);
981 int i;
982
983 /* Set SCL of I2C as GPIO pin */
984 pinmux_pin_input_enable(config->alts_list[SCL].pinctrls,
985 config->alts_list[SCL].pin,
986 PINMUX_OUTPUT_ENABLED);
987 /* Set SDA of I2C as GPIO pin */
988 pinmux_pin_input_enable(config->alts_list[SDA].pinctrls,
989 config->alts_list[SDA].pin,
990 PINMUX_OUTPUT_ENABLED);
991
992 /* Pull SCL and SDA pin to high */
993 gpio_pin_set(config->gpio_dev, config->alts_list[SCL].pin, 1);
994 gpio_pin_set(config->gpio_dev, config->alts_list[SDA].pin, 1);
995 k_msleep(1);
996
997 /* Start condition */
998 gpio_pin_set(config->gpio_dev, config->alts_list[SDA].pin, 0);
999 k_msleep(1);
1000 gpio_pin_set(config->gpio_dev, config->alts_list[SCL].pin, 0);
1001 k_msleep(1);
1002
1003 /* 9 cycles of SCL with SDA held high */
1004 for (i = 0; i < 9; i++) {
1005 /* SDA */
1006 gpio_pin_set(config->gpio_dev, config->alts_list[SDA].pin, 1);
1007 /* SCL */
1008 gpio_pin_set(config->gpio_dev, config->alts_list[SCL].pin, 1);
1009 k_msleep(1);
1010 /* SCL */
1011 gpio_pin_set(config->gpio_dev, config->alts_list[SCL].pin, 0);
1012 k_msleep(1);
1013 }
1014 /* SDA */
1015 gpio_pin_set(config->gpio_dev, config->alts_list[SDA].pin, 0);
1016 k_msleep(1);
1017
1018 /* Stop condition */
1019 gpio_pin_set(config->gpio_dev, config->alts_list[SCL].pin, 1);
1020 k_msleep(1);
1021 gpio_pin_set(config->gpio_dev, config->alts_list[SDA].pin, 1);
1022 k_msleep(1);
1023
1024 /* Set GPIO back to I2C alternate function of SCL */
1025 pinmux_pin_set(config->alts_list[SCL].pinctrls,
1026 config->alts_list[SCL].pin,
1027 config->alts_list[SCL].alt_fun);
1028 /* Set GPIO back to I2C alternate function of SDA */
1029 pinmux_pin_set(config->alts_list[SDA].pinctrls,
1030 config->alts_list[SDA].pin,
1031 config->alts_list[SDA].alt_fun);
1032
1033 /* reset i2c port */
1034 i2c_reset(dev);
1035 printk("I2C ch%d reset cause %d\n", config->port,
1036 I2C_RC_NO_IDLE_FOR_START);
1037
1038 return 0;
1039 }
1040
1041 static const struct i2c_driver_api i2c_it8xxx2_driver_api = {
1042 .configure = i2c_it8xxx2_configure,
1043 .transfer = i2c_it8xxx2_transfer,
1044 .recover_bus = i2c_it8xxx2_recover_bus,
1045 };
1046
1047 #define I2C_ITE_IT8XXX2_INIT(idx) \
1048 static void i2c_it8xxx2_config_func_##idx(void); \
1049 static const struct i2c_alts_cfg \
1050 i2c_alts_##idx[DT_INST_NUM_PINCTRLS_BY_IDX(idx, 0)] = \
1051 IT8XXX2_DT_ALT_ITEMS_LIST(idx); \
1052 \
1053 static const struct i2c_it8xxx2_config i2c_it8xxx2_cfg_##idx = { \
1054 .base = (uint8_t *)(DT_INST_REG_ADDR(idx)), \
1055 .irq_config_func = i2c_it8xxx2_config_func_##idx, \
1056 .bitrate = DT_INST_PROP(idx, clock_frequency), \
1057 .i2c_irq_base = DT_INST_IRQN(idx), \
1058 .port = DT_INST_PROP(idx, port_num), \
1059 .alts_list = i2c_alts_##idx, \
1060 .gpio_dev = DEVICE_DT_GET(DT_INST_PHANDLE(idx, gpio_dev)), \
1061 }; \
1062 \
1063 static struct i2c_it8xxx2_data i2c_it8xxx2_data_##idx; \
1064 \
1065 DEVICE_DT_INST_DEFINE(idx, \
1066 &i2c_it8xxx2_init, NULL, \
1067 &i2c_it8xxx2_data_##idx, \
1068 &i2c_it8xxx2_cfg_##idx, POST_KERNEL, \
1069 CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
1070 &i2c_it8xxx2_driver_api); \
1071 \
1072 static void i2c_it8xxx2_config_func_##idx(void) \
1073 { \
1074 IRQ_CONNECT(DT_INST_IRQN(idx), \
1075 0, \
1076 i2c_it8xxx2_isr, \
1077 DEVICE_DT_INST_GET(idx), 0); \
1078 }
1079
1080 DT_INST_FOREACH_STATUS_OKAY(I2C_ITE_IT8XXX2_INIT)
1081
