1# Copyright (c) 2020 ITE Corporation. All Rights Reserved.
2# SPDX-License-Identifier: Apache-2.0
3
4config I2C_ITE_IT8XXX2
5	bool "ITE IT8XXX2 I2C driver"
6	default y
7	depends on DT_HAS_ITE_IT8XXX2_I2C_ENABLED
8	help
9	  Enable I2C support on it8xxx2_evb.
10	  Supported Speeds: 100kHz, 400kHz and 1MHz.
11	  This driver supports repeated start.
12
13if I2C_ITE_IT8XXX2
14
15config I2C_IT8XXX2_FIFO_MODE
16	bool "IT8XXX2 I2C FIFO mode"
17	default y
18	help
19	  This is an option to enable FIFO mode which can reduce
20	  the time between each byte to improve the I2C bus clock
21	  stretching during I2C transaction.
22	  The I2C controller supports two 32-bytes FIFOs,
23	  FIFO1 supports channel A. FIFO2 supports channel B.
24	  I2C FIFO mode of it8xxx2 can support I2C APIs including:
25	  i2c_write(), i2c_read(), i2c_burst_read.
26
27endif # I2C_ITE_IT8XXX2
28
29config I2C_ITE_ENHANCE
30	bool "ITE IT8XXX2 I2C enhance driver"
31	default y
32	depends on DT_HAS_ITE_ENHANCE_I2C_ENABLED
33	help
34	  This option can enable the enhance I2C
35	  of IT8XXX2 and support three channels.
36
37if I2C_ITE_ENHANCE
38
39config I2C_IT8XXX2_CQ_MODE
40	bool "IT8XXX2 I2C command queue mode"
41	default y
42	select SOC_IT8XXX2_CPU_IDLE_GATING
43	help
44	  This is an option to enable command queue mode which can
45	  reduce the time between each byte to improve the I2C bus
46	  clock stretching during I2C transaction.
47	  I2C command queue mode of it8xxx2 can support I2C APIs
48	  including: i2c_write(), i2c_read(), i2c_burst_read.
49
50config I2C_CQ_MODE_MAX_PAYLOAD_SIZE
51	int "It is allowed to configure the size up to 2K bytes."
52	range 32 2048
53	default 64
54	help
55	  This is the command queue mode payload size which size
56	  up to 2k bytes.
57
58endif # I2C_ITE_ENHANCE
59
60if I2C_TARGET
61
62config I2C_TARGET_IT8XXX2_MAX_BUF_SIZE
63	int "It is allowed to configure the size up to 2044 bytes."
64	range 4 2044
65	default 256
66
67config I2C_TARGET_BUFFER_MODE
68	default y
69
70endif # I2C_TARGET
71