1 /*
2  * Copyright 2022 NXP
3  * All rights reserved.
4  *
5  *
6  * SPDX-License-Identifier: BSD-3-Clause
7  */
8 
9 #include "fsl_eim.h"
10 
11 /*******************************************************************************
12  * Definitions
13  ******************************************************************************/
14 
15 /* Component ID definition, used by tools. */
16 #ifndef FSL_COMPONENT_ID
17 #define FSL_COMPONENT_ID "platform.drivers.eim"
18 #endif
19 
20 /*******************************************************************************
21  * Prototypes
22  ******************************************************************************/
23 
24 /*******************************************************************************
25  * Variables
26  ******************************************************************************/
27 /*! @brief Pointers to EIM bases for each instance. */
28 static EIM_Type *const s_eimBases[] = EIM_BASE_PTRS;
29 
30 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
31 /*! @brief Pointers to EIM clocks for each instance. */
32 static const clock_ip_name_t s_eimClocks[] = EIM_CLOCKS;
33 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
34 /*******************************************************************************
35  * Code
36  ******************************************************************************/
EIM_GetInstance(EIM_Type * base)37 static uint32_t EIM_GetInstance(EIM_Type *base)
38 {
39     uint32_t instance;
40 
41     /* Find the instance index from base address mappings. */
42     for (instance = 0; instance < ARRAY_SIZE(s_eimBases); instance++)
43     {
44         if (s_eimBases[instance] == base)
45         {
46             break;
47         }
48     }
49 
50     assert(instance < ARRAY_SIZE(s_eimBases));
51 
52     return instance;
53 }
54 
55 /*!
56  * brief EIM module initialization function.
57  *
58  * param base EIM base address.
59  */
EIM_Init(EIM_Type * base)60 void EIM_Init(EIM_Type *base)
61 {
62 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
63     /* Ungate EIM clock. */
64     CLOCK_EnableClock(s_eimClocks[EIM_GetInstance(base)]);
65 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
66 
67     base->EIMCR  = 0x00U;
68     base->EICHEN = 0x00U;
69 }
70 
71 /*!
72  * brief Deinitializes the EIM.
73  *
74  */
EIM_Deinit(EIM_Type * base)75 void EIM_Deinit(EIM_Type *base)
76 {
77 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
78     /* Ungate EIM clock. */
79     CLOCK_DisableClock(s_eimClocks[EIM_GetInstance(base)]);
80 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
81 }
82 
EIM_InjectCheckBitError(EIM_Type * base,eim_memory_channel_t channel,uint8_t mask)83 void EIM_InjectCheckBitError(EIM_Type *base, eim_memory_channel_t channel, uint8_t mask)
84 {
85     switch ((uint8_t)channel)
86     {
87         case 0U:
88             base->EICHD0_WORD0 = EIM_EICHD0_WORD0_CHKBIT_MASK(mask);
89             break;
90 #ifdef EIM_EICHEN_EICH1EN_MASK
91         case 1U:
92             base->EICHD1_WORD0 = EIM_EICHD1_WORD0_CHKBIT_MASK(mask);
93             break;
94 #endif
95 
96 #ifdef EIM_EICHEN_EICH2EN_MASK
97         case 2U:
98             base->EICHD2_WORD0 = EIM_EICHD2_WORD0_CHKBIT_MASK(mask);
99             break;
100 #endif
101 #ifdef EIM_EICHEN_EICH3EN_MASK
102         case 3U:
103             base->EICHD3_WORD0 = EIM_EICHD3_WORD0_CHKBIT_MASK(mask);
104             break;
105 #endif
106 #ifdef EIM_EICHEN_EICH4EN_MASK
107         case 4U:
108             base->EICHD4_WORD0 = EIM_EICHD4_WORD0_CHKBIT_MASK(mask);
109             break;
110 #endif
111 #ifdef EIM_EICHEN_EICH5EN_MASK
112         case 5U:
113             base->EICHD5_WORD0 = EIM_EICHD5_WORD0_CHKBIT_MASK(mask);
114             break;
115 #endif
116 #ifdef EIM_EICHEN_EICH6EN_MASK
117         case 6U:
118             base->EICHD6_WORD0 = EIM_EICHD6_WORD0_CHKBIT_MASK(mask);
119             break;
120 #endif
121 #ifdef EIM_EICHEN_EICH7EN_MASK
122         case 7U:
123             base->EICHD7_WORD0 = EIM_EICHD7_WORD0_CHKBIT_MASK(mask);
124             break;
125 #endif
126 #ifdef EIM_EICHEN_EICH8EN_MASK
127         case 8U:
128             base->EICHD8_WORD0 = EIM_EICHD8_WORD0_CHKBIT_MASK(mask);
129             break;
130 #endif
131         default:
132             assert(NULL);
133             break;
134     }
135 }
136 
EIM_GetCheckBitMask(EIM_Type * base,eim_memory_channel_t channel)137 uint8_t EIM_GetCheckBitMask(EIM_Type *base, eim_memory_channel_t channel)
138 {
139     uint8_t mask = 0x00U;
140 
141     switch ((uint8_t)channel)
142     {
143         case 0U:
144             mask = (uint8_t)((base->EICHD0_WORD0 & EIM_EICHD0_WORD0_CHKBIT_MASK_MASK) >>
145                              EIM_EICHD0_WORD0_CHKBIT_MASK_SHIFT);
146             break;
147 #ifdef EIM_EICHEN_EICH1EN_MASK
148         case 1U:
149             mask = (uint8_t)((base->EICHD1_WORD0 & EIM_EICHD1_WORD0_CHKBIT_MASK_MASK) >>
150                              EIM_EICHD1_WORD0_CHKBIT_MASK_SHIFT);
151             break;
152 #endif
153 #ifdef EIM_EICHEN_EICH2EN_MASK
154         case 2U:
155             mask = (uint8_t)((base->EICHD2_WORD0 & EIM_EICHD2_WORD0_CHKBIT_MASK_MASK) >>
156                              EIM_EICHD2_WORD0_CHKBIT_MASK_SHIFT);
157             break;
158 #endif
159 #ifdef EIM_EICHEN_EICH3EN_MASK
160         case 3U:
161             mask = (uint8_t)((base->EICHD3_WORD0 & EIM_EICHD3_WORD0_CHKBIT_MASK_MASK) >>
162                              EIM_EICHD3_WORD0_CHKBIT_MASK_SHIFT);
163             break;
164 #endif
165 #ifdef EIM_EICHEN_EICH4EN_MASK
166         case 4U:
167             mask = (uint8_t)((base->EICHD4_WORD0 & EIM_EICHD4_WORD0_CHKBIT_MASK_MASK) >>
168                              EIM_EICHD4_WORD0_CHKBIT_MASK_SHIFT);
169             break;
170 #endif
171 #ifdef EIM_EICHEN_EICH5EN_MASK
172         case 5U:
173             mask = (uint8_t)((base->EICHD5_WORD0 & EIM_EICHD5_WORD0_CHKBIT_MASK_MASK) >>
174                              EIM_EICHD5_WORD0_CHKBIT_MASK_SHIFT);
175             break;
176 #endif
177 #ifdef EIM_EICHEN_EICH6EN_MASK
178         case 6U:
179             mask = (uint8_t)((base->EICHD6_WORD0 & EIM_EICHD6_WORD0_CHKBIT_MASK_MASK) >>
180                              EIM_EICHD6_WORD0_CHKBIT_MASK_SHIFT);
181             break;
182 #endif
183 #ifdef EIM_EICHEN_EICH7EN_MASK
184         case 7U:
185             mask = (uint8_t)((base->EICHD7_WORD0 & EIM_EICHD7_WORD0_CHKBIT_MASK_MASK) >>
186                              EIM_EICHD7_WORD0_CHKBIT_MASK_SHIFT);
187             break;
188 #endif
189 #ifdef EIM_EICHEN_EICH8EN_MASK
190         case 8U:
191             mask = (uint8_t)((base->EICHD8_WORD0 & EIM_EICHD8_WORD0_CHKBIT_MASK_MASK) >>
192                              EIM_EICHD8_WORD0_CHKBIT_MASK_SHIFT);
193             break;
194 #endif
195         default:
196             assert(NULL);
197             break;
198     }
199 
200     return mask;
201 }
202 
EIM_InjectDataBitError(EIM_Type * base,eim_memory_channel_t channel,uint8_t mask)203 void EIM_InjectDataBitError(EIM_Type *base, eim_memory_channel_t channel, uint8_t mask)
204 {
205     switch ((uint8_t)channel)
206     {
207         case 0U:
208             base->EICHD0_WORD1 = mask;
209             break;
210 #ifdef EIM_EICHEN_EICH1EN_MASK
211         case 1U:
212             base->EICHD1_WORD1 = mask;
213             break;
214 #endif
215 #ifdef EIM_EICHEN_EICH2EN_MASK
216         case 2U:
217             base->EICHD2_WORD1 = mask;
218             break;
219 #endif
220 #ifdef EIM_EICHEN_EICH3EN_MASK
221         case kEIM_MemoryChannelRAMC:
222             base->EICHD3_WORD1 = mask;
223             break;
224 #endif
225 #ifdef EIM_EICHEN_EICH4EN_MASK
226         case kEIM_MemoryChannelRAMD:
227             base->EICHD4_WORD1 = mask;
228             break;
229 #endif
230 #ifdef EIM_EICHEN_EICH5EN_MASK
231         case kEIM_MemoryChannelRAME:
232             base->EICHD5_WORD1 = mask;
233             break;
234 #endif
235 #ifdef EIM_EICHEN_EICH6EN_MASK
236         case kEIM_MemoryChannelRAMF:
237             base->EICHD6_WORD1 = mask;
238             break;
239 #endif
240 #ifdef EIM_EICHEN_EICH7EN_MASK
241         case kEIM_MemoryChannelLPCACRAM:
242             base->EICHD7_WORD1 = mask;
243             break;
244 #endif
245 #ifdef EIM_EICHEN_EICH8EN_MASK
246         case kEIM_MemoryChannelPKCRAM:
247             base->EICHD8_WORD1 = mask;
248             break;
249 #endif
250         default:
251             assert(NULL);
252             break;
253     }
254 }
255 
EIM_GetDataBitMask(EIM_Type * base,eim_memory_channel_t channel)256 uint32_t EIM_GetDataBitMask(EIM_Type *base, eim_memory_channel_t channel)
257 {
258     uint32_t mask = 0x00U;
259 
260     switch ((uint8_t)channel)
261     {
262         case 0U:
263             mask = (base->EICHD0_WORD0 & EIM_EICHD0_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD0_WORD1_B0_3DATA_MASK_SHIFT;
264             break;
265 
266 #ifdef EIM_EICHEN_EICH1EN_MASK
267         case 1U:
268             mask = (base->EICHD1_WORD0 & EIM_EICHD1_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD1_WORD1_B0_3DATA_MASK_SHIFT;
269             break;
270 #endif
271 #ifdef EIM_EICHEN_EICH2EN_MASK
272         case 2U:
273             mask = (base->EICHD2_WORD0 & EIM_EICHD2_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD2_WORD1_B0_3DATA_MASK_SHIFT;
274             break;
275 #endif
276 #ifdef EIM_EICHEN_EICH3EN_MASK
277         case 3U:
278             mask = (base->EICHD3_WORD0 & EIM_EICHD3_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD3_WORD1_B0_3DATA_MASK_SHIFT;
279             break;
280 #endif
281 #ifdef EIM_EICHEN_EICH4EN_MASK
282         case 4U:
283             mask = (base->EICHD4_WORD0 & EIM_EICHD4_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD4_WORD1_B0_3DATA_MASK_SHIFT;
284             break;
285 #endif
286 #ifdef EIM_EICHEN_EICH5EN_MASK
287         case 5U:
288             mask = (base->EICHD5_WORD0 & EIM_EICHD5_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD5_WORD1_B0_3DATA_MASK_SHIFT;
289             break;
290 #endif
291 #ifdef EIM_EICHEN_EICH6EN_MASK
292         case 6U:
293             mask = (base->EICHD6_WORD0 & EIM_EICHD6_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD6_WORD1_B0_3DATA_MASK_SHIFT;
294             break;
295 #endif
296 #ifdef EIM_EICHEN_EICH7EN_MASK
297         case 7U:
298             mask = (base->EICHD7_WORD0 & EIM_EICHD7_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD7_WORD1_B0_3DATA_MASK_SHIFT;
299             break;
300 #endif
301 #ifdef EIM_EICHEN_EICH8EN_MASK
302         case 8U:
303             mask = (base->EICHD8_WORD1 & EIM_EICHD8_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD8_WORD1_B0_3DATA_MASK_SHIFT;
304             break;
305 #endif
306         default:
307             assert(NULL);
308             break;
309     }
310 
311     return mask;
312 }
313