1 /*
2 * Copyright (c) 2020 Amarula Solutions.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT st_stm32_sdmmc
8
9 #include <zephyr/devicetree.h>
10 #include <zephyr/drivers/disk.h>
11 #include <zephyr/drivers/clock_control.h>
12 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
13 #include <zephyr/drivers/pinctrl.h>
14 #include <zephyr/drivers/gpio.h>
15 #include <zephyr/drivers/reset.h>
16 #include <zephyr/logging/log.h>
17 #include <zephyr/irq.h>
18 #include <soc.h>
19 #include <stm32_ll_rcc.h>
20
21 LOG_MODULE_REGISTER(stm32_sdmmc, CONFIG_SDMMC_LOG_LEVEL);
22
23 #define STM32_SDMMC_USE_DMA DT_NODE_HAS_PROP(DT_DRV_INST(0), dmas)
24
25 #if STM32_SDMMC_USE_DMA
26 #include <zephyr/drivers/dma.h>
27 #include <zephyr/drivers/dma/dma_stm32.h>
28 #include <stm32_ll_dma.h>
29 #endif
30
31 #ifndef MMC_TypeDef
32 #define MMC_TypeDef SDMMC_TypeDef
33 #endif
34
35 #ifndef SDMMC_BUS_WIDE_1B
36 #define SDMMC_BUS_WIDE_1B SDIO_BUS_WIDE_1B
37 #endif
38
39 #ifndef SDMMC_BUS_WIDE_4B
40 #define SDMMC_BUS_WIDE_4B SDIO_BUS_WIDE_4B
41 #endif
42
43 #ifndef SDMMC_BUS_WIDE_8B
44 #define SDMMC_BUS_WIDE_8B SDIO_BUS_WIDE_8B
45 #endif
46
47 typedef void (*irq_config_func_t)(const struct device *dev);
48
49 #if STM32_SDMMC_USE_DMA
50
51 static const uint32_t table_priority[] = {
52 DMA_PRIORITY_LOW,
53 DMA_PRIORITY_MEDIUM,
54 DMA_PRIORITY_HIGH,
55 DMA_PRIORITY_VERY_HIGH
56 };
57
58 struct sdmmc_dma_stream {
59 const struct device *dev;
60 uint32_t channel;
61 uint32_t channel_nb;
62 DMA_TypeDef *reg;
63 struct dma_config cfg;
64 };
65 #endif
66
67 #ifdef CONFIG_SDMMC_STM32_EMMC
68 typedef MMC_HandleTypeDef HandleTypeDef;
69 typedef HAL_MMC_CardInfoTypeDef CardInfoTypeDef;
70 #else
71 typedef SD_HandleTypeDef HandleTypeDef;
72 typedef HAL_SD_CardInfoTypeDef CardInfoTypeDef;
73 #endif
74
75 struct stm32_sdmmc_priv {
76 irq_config_func_t irq_config;
77 struct k_sem thread_lock;
78 struct k_sem sync;
79 HandleTypeDef hsd;
80 int status;
81 struct k_work work;
82 struct gpio_callback cd_cb;
83 struct gpio_dt_spec cd;
84 struct gpio_dt_spec pe;
85 struct stm32_pclken *pclken;
86 const struct pinctrl_dev_config *pcfg;
87 const struct reset_dt_spec reset;
88
89 #if STM32_SDMMC_USE_DMA
90 struct sdmmc_dma_stream dma_rx;
91 struct sdmmc_dma_stream dma_tx;
92 #endif
93 };
94
95 #ifdef CONFIG_SDMMC_STM32_HWFC
stm32_sdmmc_fc_enable(struct stm32_sdmmc_priv * priv)96 static void stm32_sdmmc_fc_enable(struct stm32_sdmmc_priv *priv)
97 {
98 MMC_TypeDef *sdmmcx = priv->hsd.Instance;
99
100 sdmmcx->CLKCR |= SDMMC_CLKCR_HWFC_EN;
101 }
102 #endif
103
stm32_sdmmc_isr(const struct device * dev)104 static void stm32_sdmmc_isr(const struct device *dev)
105 {
106 struct stm32_sdmmc_priv *priv = dev->data;
107
108 #ifdef CONFIG_SDMMC_STM32_EMMC
109 HAL_MMC_IRQHandler(&priv->hsd);
110 #else
111 HAL_SD_IRQHandler(&priv->hsd);
112 #endif
113 }
114
115 #define DEFINE_HAL_CALLBACK(name) \
116 void name(HandleTypeDef *hsd) \
117 { \
118 struct stm32_sdmmc_priv *priv = CONTAINER_OF(hsd, struct stm32_sdmmc_priv, hsd); \
119 \
120 priv->status = hsd->ErrorCode; \
121 \
122 k_sem_give(&priv->sync); \
123 }
124
125 #ifdef CONFIG_SDMMC_STM32_EMMC
126 DEFINE_HAL_CALLBACK(HAL_MMC_TxCpltCallback);
127 DEFINE_HAL_CALLBACK(HAL_MMC_RxCpltCallback);
128 DEFINE_HAL_CALLBACK(HAL_MMC_ErrorCallback);
129 #else
130 DEFINE_HAL_CALLBACK(HAL_SD_TxCpltCallback);
131 DEFINE_HAL_CALLBACK(HAL_SD_RxCpltCallback);
132 DEFINE_HAL_CALLBACK(HAL_SD_ErrorCallback);
133 #endif
134
stm32_sdmmc_clock_enable(struct stm32_sdmmc_priv * priv)135 static int stm32_sdmmc_clock_enable(struct stm32_sdmmc_priv *priv)
136 {
137 const struct device *clock;
138
139 /* HSI48 Clock is enabled through using the device tree */
140 clock = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
141
142 if (DT_INST_NUM_CLOCKS(0) > 1) {
143 if (clock_control_configure(clock,
144 (clock_control_subsys_t)&priv->pclken[1],
145 NULL) != 0) {
146 LOG_ERR("Failed to enable SDMMC domain clock");
147 return -EIO;
148 }
149 }
150
151 if (IS_ENABLED(CONFIG_SDMMC_STM32_CLOCK_CHECK)) {
152 uint32_t sdmmc_clock_rate;
153
154 if (clock_control_get_rate(clock,
155 (clock_control_subsys_t)&priv->pclken[1],
156 &sdmmc_clock_rate) != 0) {
157 LOG_ERR("Failed to get SDMMC domain clock rate");
158 return -EIO;
159 }
160
161 if (sdmmc_clock_rate != MHZ(48)) {
162 LOG_ERR("SDMMC Clock is not 48MHz (%d)", sdmmc_clock_rate);
163 return -ENOTSUP;
164 }
165 }
166
167 /* Enable the APB clock for stm32_sdmmc */
168 return clock_control_on(clock, (clock_control_subsys_t)&priv->pclken[0]);
169 }
170
171 #if !defined(CONFIG_SDMMC_STM32_EMMC)
stm32_sdmmc_clock_disable(struct stm32_sdmmc_priv * priv)172 static int stm32_sdmmc_clock_disable(struct stm32_sdmmc_priv *priv)
173 {
174 const struct device *clock;
175
176 clock = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
177
178 return clock_control_off(clock,
179 (clock_control_subsys_t)&priv->pclken);
180 }
181 #endif
182
183 #if STM32_SDMMC_USE_DMA
184
stm32_sdmmc_dma_cb(const struct device * dev,void * arg,uint32_t channel,int status)185 static void stm32_sdmmc_dma_cb(const struct device *dev, void *arg,
186 uint32_t channel, int status)
187 {
188 DMA_HandleTypeDef *hdma = arg;
189
190 if (status != 0) {
191 LOG_ERR("DMA callback error with channel %d.", channel);
192
193 }
194
195 HAL_DMA_IRQHandler(hdma);
196 }
197
stm32_sdmmc_configure_dma(DMA_HandleTypeDef * handle,struct sdmmc_dma_stream * dma)198 static int stm32_sdmmc_configure_dma(DMA_HandleTypeDef *handle, struct sdmmc_dma_stream *dma)
199 {
200 int ret;
201
202 if (!device_is_ready(dma->dev)) {
203 LOG_ERR("Failed to get dma dev");
204 return -ENODEV;
205 }
206
207 dma->cfg.user_data = handle;
208
209 ret = dma_config(dma->dev, dma->channel, &dma->cfg);
210 if (ret != 0) {
211 LOG_ERR("Failed to conig");
212 return ret;
213 }
214
215 handle->Instance = __LL_DMA_GET_STREAM_INSTANCE(dma->reg, dma->channel_nb);
216 handle->Init.Channel = dma->cfg.dma_slot * DMA_CHANNEL_1;
217 handle->Init.PeriphInc = DMA_PINC_DISABLE;
218 handle->Init.MemInc = DMA_MINC_ENABLE;
219 handle->Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
220 handle->Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
221 handle->Init.Mode = DMA_PFCTRL;
222 handle->Init.Priority = table_priority[dma->cfg.channel_priority],
223 handle->Init.FIFOMode = DMA_FIFOMODE_ENABLE;
224 handle->Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
225 handle->Init.MemBurst = DMA_MBURST_INC4;
226 handle->Init.PeriphBurst = DMA_PBURST_INC4;
227
228 return ret;
229 }
230
stm32_sdmmc_dma_init(struct stm32_sdmmc_priv * priv)231 static int stm32_sdmmc_dma_init(struct stm32_sdmmc_priv *priv)
232 {
233 static DMA_HandleTypeDef dma_tx_handle;
234 static DMA_HandleTypeDef dma_rx_handle;
235 int err;
236
237 LOG_DBG("using dma");
238
239 err = stm32_sdmmc_configure_dma(&dma_tx_handle, &priv->dma_tx);
240 if (err) {
241 LOG_ERR("failed to init tx dma");
242 return err;
243 }
244 __HAL_LINKDMA(&priv->hsd, hdmatx, dma_tx_handle);
245 HAL_DMA_DeInit(&dma_tx_handle);
246 HAL_DMA_Init(&dma_tx_handle);
247
248 err = stm32_sdmmc_configure_dma(&dma_rx_handle, &priv->dma_rx);
249 if (err) {
250 LOG_ERR("failed to init rx dma");
251 return err;
252 }
253 __HAL_LINKDMA(&priv->hsd, hdmarx, dma_rx_handle);
254 HAL_DMA_DeInit(&dma_rx_handle);
255 HAL_DMA_Init(&dma_rx_handle);
256
257 return err;
258 }
259
260 #endif
261
stm32_sdmmc_access_init(struct disk_info * disk)262 static int stm32_sdmmc_access_init(struct disk_info *disk)
263 {
264 const struct device *dev = disk->dev;
265 struct stm32_sdmmc_priv *priv = dev->data;
266 int err;
267
268 if (priv->status == DISK_STATUS_NOMEDIA) {
269 return -ENODEV;
270 }
271
272 #if STM32_SDMMC_USE_DMA
273 err = stm32_sdmmc_dma_init(priv);
274 if (err) {
275 LOG_ERR("DMA init failed");
276 return err;
277 }
278 #endif
279
280 err = stm32_sdmmc_clock_enable(priv);
281 if (err) {
282 LOG_ERR("failed to init clocks");
283 return err;
284 }
285
286 err = reset_line_toggle_dt(&priv->reset);
287 if (err) {
288 LOG_ERR("failed to reset peripheral");
289 return err;
290 }
291
292 #ifdef CONFIG_SDMMC_STM32_EMMC
293 err = HAL_MMC_Init(&priv->hsd);
294 #else
295 err = HAL_SD_Init(&priv->hsd);
296 #endif
297 if (err != HAL_OK) {
298 LOG_ERR("failed to init stm32_sdmmc (ErrorCode 0x%X)", priv->hsd.ErrorCode);
299 return -EIO;
300 }
301
302 #ifdef CONFIG_SDMMC_STM32_HWFC
303 stm32_sdmmc_fc_enable(priv);
304 #endif
305
306 priv->status = DISK_STATUS_OK;
307 return 0;
308 }
309
stm32_sdmmc_access_deinit(struct stm32_sdmmc_priv * priv)310 static int stm32_sdmmc_access_deinit(struct stm32_sdmmc_priv *priv)
311 {
312 #if defined(CONFIG_SDMMC_STM32_EMMC)
313 HAL_MMC_DeInit(&priv->hsd);
314 #else
315 HAL_SD_DeInit(&priv->hsd);
316
317 stm32_sdmmc_clock_disable(priv);
318 #endif
319 priv->status = DISK_STATUS_UNINIT;
320 return 0;
321 }
322
stm32_sdmmc_access_status(struct disk_info * disk)323 static int stm32_sdmmc_access_status(struct disk_info *disk)
324 {
325 const struct device *dev = disk->dev;
326 struct stm32_sdmmc_priv *priv = dev->data;
327
328 return priv->status;
329 }
330
stm32_sdmmc_is_card_in_transfer(HandleTypeDef * hsd)331 static int stm32_sdmmc_is_card_in_transfer(HandleTypeDef *hsd)
332 {
333 #ifdef CONFIG_SDMMC_STM32_EMMC
334 return HAL_MMC_GetCardState(hsd) == HAL_MMC_CARD_TRANSFER;
335 #else
336 return HAL_SD_GetCardState(hsd) == HAL_SD_CARD_TRANSFER;
337 #endif
338 }
339
stm32_sdmmc_read_blocks(HandleTypeDef * hsd,uint8_t * data_buf,uint32_t start_sector,uint32_t num_sector)340 static int stm32_sdmmc_read_blocks(HandleTypeDef *hsd, uint8_t *data_buf,
341 uint32_t start_sector, uint32_t num_sector)
342 {
343 #if STM32_SDMMC_USE_DMA || IS_ENABLED(DT_PROP(DT_DRV_INST(0), idma))
344
345 #ifdef CONFIG_SDMMC_STM32_EMMC
346 return HAL_MMC_ReadBlocks_DMA(hsd, data_buf, start_sector, num_sector);
347 #else
348 return HAL_SD_ReadBlocks_DMA(hsd, data_buf, start_sector, num_sector);
349 #endif
350
351 #else
352
353 #ifdef CONFIG_SDMMC_STM32_EMMC
354 return HAL_MMC_ReadBlocks_IT(hsd, data_buf, start_sector, num_sector);
355 #else
356 return HAL_SD_ReadBlocks_IT(hsd, data_buf, start_sector, num_sector);
357 #endif
358
359 #endif
360 }
361
stm32_sdmmc_access_read(struct disk_info * disk,uint8_t * data_buf,uint32_t start_sector,uint32_t num_sector)362 static int stm32_sdmmc_access_read(struct disk_info *disk, uint8_t *data_buf,
363 uint32_t start_sector, uint32_t num_sector)
364 {
365 const struct device *dev = disk->dev;
366 struct stm32_sdmmc_priv *priv = dev->data;
367 int err;
368
369 k_sem_take(&priv->thread_lock, K_FOREVER);
370
371 err = stm32_sdmmc_read_blocks(&priv->hsd, data_buf, start_sector, num_sector);
372 if (err != HAL_OK) {
373 LOG_ERR("sd read block failed %d", err);
374 err = -EIO;
375 goto end;
376 }
377
378 k_sem_take(&priv->sync, K_FOREVER);
379
380 if (priv->status != DISK_STATUS_OK) {
381 LOG_ERR("sd read error %d", priv->status);
382 err = -EIO;
383 goto end;
384 }
385
386 while (!stm32_sdmmc_is_card_in_transfer(&priv->hsd)) {
387 }
388
389 end:
390 k_sem_give(&priv->thread_lock);
391 return err;
392 }
393
stm32_sdmmc_write_blocks(HandleTypeDef * hsd,uint8_t * data_buf,uint32_t start_sector,uint32_t num_sector)394 static int stm32_sdmmc_write_blocks(HandleTypeDef *hsd,
395 uint8_t *data_buf,
396 uint32_t start_sector, uint32_t num_sector)
397 {
398 #if STM32_SDMMC_USE_DMA || IS_ENABLED(DT_PROP(DT_DRV_INST(0), idma))
399
400 #ifdef CONFIG_SDMMC_STM32_EMMC
401 return HAL_MMC_WriteBlocks_DMA(hsd, data_buf, start_sector, num_sector);
402 #else
403 return HAL_SD_WriteBlocks_DMA(hsd, data_buf, start_sector, num_sector);
404 #endif
405
406 #else
407
408 #ifdef CONFIG_SDMMC_STM32_EMMC
409 return HAL_MMC_WriteBlocks_IT(hsd, data_buf, start_sector, num_sector);
410 #else
411 return HAL_SD_WriteBlocks_IT(hsd, data_buf, start_sector, num_sector);
412 #endif
413
414 #endif
415 }
416
stm32_sdmmc_access_write(struct disk_info * disk,const uint8_t * data_buf,uint32_t start_sector,uint32_t num_sector)417 static int stm32_sdmmc_access_write(struct disk_info *disk,
418 const uint8_t *data_buf,
419 uint32_t start_sector, uint32_t num_sector)
420 {
421 const struct device *dev = disk->dev;
422 struct stm32_sdmmc_priv *priv = dev->data;
423 int err;
424
425 k_sem_take(&priv->thread_lock, K_FOREVER);
426
427 err = stm32_sdmmc_write_blocks(&priv->hsd, (uint8_t *)data_buf, start_sector, num_sector);
428 if (err != HAL_OK) {
429 LOG_ERR("sd write block failed %d", err);
430 err = -EIO;
431 goto end;
432 }
433
434 k_sem_take(&priv->sync, K_FOREVER);
435
436 if (priv->status != DISK_STATUS_OK) {
437 LOG_ERR("sd write error %d", priv->status);
438 err = -EIO;
439 goto end;
440 }
441
442 while (!stm32_sdmmc_is_card_in_transfer(&priv->hsd)) {
443 }
444
445 end:
446 k_sem_give(&priv->thread_lock);
447 return err;
448 }
449
stm32_sdmmc_get_card_info(HandleTypeDef * hsd,CardInfoTypeDef * info)450 static int stm32_sdmmc_get_card_info(HandleTypeDef *hsd, CardInfoTypeDef *info)
451 {
452 #ifdef CONFIG_SDMMC_STM32_EMMC
453 return HAL_MMC_GetCardInfo(hsd, info);
454 #else
455 return HAL_SD_GetCardInfo(hsd, info);
456 #endif
457 }
458
stm32_sdmmc_access_ioctl(struct disk_info * disk,uint8_t cmd,void * buff)459 static int stm32_sdmmc_access_ioctl(struct disk_info *disk, uint8_t cmd,
460 void *buff)
461 {
462 const struct device *dev = disk->dev;
463 struct stm32_sdmmc_priv *priv = dev->data;
464 CardInfoTypeDef info;
465 int err;
466
467 switch (cmd) {
468 case DISK_IOCTL_GET_SECTOR_COUNT:
469 err = stm32_sdmmc_get_card_info(&priv->hsd, &info);
470 if (err != HAL_OK) {
471 return -EIO;
472 }
473 *(uint32_t *)buff = info.LogBlockNbr;
474 break;
475 case DISK_IOCTL_GET_SECTOR_SIZE:
476 err = stm32_sdmmc_get_card_info(&priv->hsd, &info);
477 if (err != HAL_OK) {
478 return -EIO;
479 }
480 *(uint32_t *)buff = info.LogBlockSize;
481 break;
482 case DISK_IOCTL_GET_ERASE_BLOCK_SZ:
483 *(uint32_t *)buff = 1;
484 break;
485 case DISK_IOCTL_CTRL_SYNC:
486 /* we use a blocking API, so nothing to do for sync */
487 break;
488 case DISK_IOCTL_CTRL_INIT:
489 return stm32_sdmmc_access_init(disk);
490 case DISK_IOCTL_CTRL_DEINIT:
491 return stm32_sdmmc_access_deinit(priv);
492 default:
493 return -EINVAL;
494 }
495 return 0;
496 }
497
498 static const struct disk_operations stm32_sdmmc_ops = {
499 .init = stm32_sdmmc_access_init,
500 .status = stm32_sdmmc_access_status,
501 .read = stm32_sdmmc_access_read,
502 .write = stm32_sdmmc_access_write,
503 .ioctl = stm32_sdmmc_access_ioctl,
504 };
505
506 static struct disk_info stm32_sdmmc_info = {
507 .name = CONFIG_SDMMC_VOLUME_NAME,
508 .ops = &stm32_sdmmc_ops,
509 };
510
511
512 #ifdef CONFIG_SDMMC_STM32_EMMC
stm32_sdmmc_card_present(struct stm32_sdmmc_priv * priv)513 static bool stm32_sdmmc_card_present(struct stm32_sdmmc_priv *priv)
514 {
515 return true;
516 }
517 #else /* CONFIG_SDMMC_STM32_EMMC */
518 /*
519 * Check if the card is present or not. If no card detect gpio is set, assume
520 * the card is present. If reading the gpio fails for some reason, assume the
521 * card is there.
522 */
stm32_sdmmc_card_present(struct stm32_sdmmc_priv * priv)523 static bool stm32_sdmmc_card_present(struct stm32_sdmmc_priv *priv)
524 {
525 int err;
526
527 if (!priv->cd.port) {
528 return true;
529 }
530
531 err = gpio_pin_get_dt(&priv->cd);
532 if (err < 0) {
533 LOG_WRN("reading card detect failed %d", err);
534 return true;
535 }
536 return err;
537 }
538
stm32_sdmmc_cd_handler(struct k_work * item)539 static void stm32_sdmmc_cd_handler(struct k_work *item)
540 {
541 struct stm32_sdmmc_priv *priv = CONTAINER_OF(item,
542 struct stm32_sdmmc_priv,
543 work);
544
545 if (stm32_sdmmc_card_present(priv)) {
546 LOG_DBG("card inserted");
547 priv->status = DISK_STATUS_UNINIT;
548 } else {
549 LOG_DBG("card removed");
550 stm32_sdmmc_access_deinit(priv);
551 priv->status = DISK_STATUS_NOMEDIA;
552 }
553 }
554
stm32_sdmmc_cd_callback(const struct device * gpiodev,struct gpio_callback * cb,uint32_t pin)555 static void stm32_sdmmc_cd_callback(const struct device *gpiodev,
556 struct gpio_callback *cb,
557 uint32_t pin)
558 {
559 struct stm32_sdmmc_priv *priv = CONTAINER_OF(cb,
560 struct stm32_sdmmc_priv,
561 cd_cb);
562
563 k_work_submit(&priv->work);
564 }
565
stm32_sdmmc_card_detect_init(struct stm32_sdmmc_priv * priv)566 static int stm32_sdmmc_card_detect_init(struct stm32_sdmmc_priv *priv)
567 {
568 int err;
569
570 if (!priv->cd.port) {
571 return 0;
572 }
573
574 if (!gpio_is_ready_dt(&priv->cd)) {
575 return -ENODEV;
576 }
577
578 gpio_init_callback(&priv->cd_cb, stm32_sdmmc_cd_callback,
579 1 << priv->cd.pin);
580
581 err = gpio_add_callback(priv->cd.port, &priv->cd_cb);
582 if (err) {
583 return err;
584 }
585
586 err = gpio_pin_configure_dt(&priv->cd, GPIO_INPUT);
587 if (err) {
588 goto remove_callback;
589 }
590
591 err = gpio_pin_interrupt_configure_dt(&priv->cd, GPIO_INT_EDGE_BOTH);
592 if (err) {
593 goto unconfigure_pin;
594 }
595 return 0;
596
597 unconfigure_pin:
598 gpio_pin_configure_dt(&priv->cd, GPIO_DISCONNECTED);
599 remove_callback:
600 gpio_remove_callback(priv->cd.port, &priv->cd_cb);
601 return err;
602 }
603
stm32_sdmmc_card_detect_uninit(struct stm32_sdmmc_priv * priv)604 static int stm32_sdmmc_card_detect_uninit(struct stm32_sdmmc_priv *priv)
605 {
606 if (!priv->cd.port) {
607 return 0;
608 }
609
610 gpio_pin_interrupt_configure_dt(&priv->cd, GPIO_INT_MODE_DISABLED);
611 gpio_pin_configure_dt(&priv->cd, GPIO_DISCONNECTED);
612 gpio_remove_callback(priv->cd.port, &priv->cd_cb);
613 return 0;
614 }
615 #endif /* !CONFIG_SDMMC_STM32_EMMC */
616
stm32_sdmmc_pwr_init(struct stm32_sdmmc_priv * priv)617 static int stm32_sdmmc_pwr_init(struct stm32_sdmmc_priv *priv)
618 {
619 int err;
620
621 if (!priv->pe.port) {
622 return 0;
623 }
624
625 if (!gpio_is_ready_dt(&priv->pe)) {
626 return -ENODEV;
627 }
628
629 err = gpio_pin_configure_dt(&priv->pe, GPIO_OUTPUT_ACTIVE);
630 if (err) {
631 return err;
632 }
633
634 k_sleep(K_MSEC(50));
635
636 return 0;
637 }
638
stm32_sdmmc_pwr_uninit(struct stm32_sdmmc_priv * priv)639 static int stm32_sdmmc_pwr_uninit(struct stm32_sdmmc_priv *priv)
640 {
641 if (!priv->pe.port) {
642 return 0;
643 }
644
645 gpio_pin_configure_dt(&priv->pe, GPIO_DISCONNECTED);
646 return 0;
647 }
648
disk_stm32_sdmmc_init(const struct device * dev)649 static int disk_stm32_sdmmc_init(const struct device *dev)
650 {
651 struct stm32_sdmmc_priv *priv = dev->data;
652 const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
653 int err;
654
655 if (!device_is_ready(clk)) {
656 LOG_ERR("clock control device not ready");
657 return -ENODEV;
658 }
659
660 if (!device_is_ready(priv->reset.dev)) {
661 LOG_ERR("reset control device not ready");
662 return -ENODEV;
663 }
664
665 /* Configure dt provided device signals when available */
666 err = pinctrl_apply_state(priv->pcfg, PINCTRL_STATE_DEFAULT);
667 if (err < 0) {
668 return err;
669 }
670
671 priv->irq_config(dev);
672
673 /* Initialize semaphores */
674 k_sem_init(&priv->thread_lock, 1, 1);
675 k_sem_init(&priv->sync, 0, 1);
676
677 #if !defined(CONFIG_SDMMC_STM32_EMMC)
678 k_work_init(&priv->work, stm32_sdmmc_cd_handler);
679
680 err = stm32_sdmmc_card_detect_init(priv);
681 if (err) {
682 return err;
683 }
684 #endif
685
686 err = stm32_sdmmc_pwr_init(priv);
687 if (err) {
688 goto err_card_detect;
689 }
690
691 if (stm32_sdmmc_card_present(priv)) {
692 priv->status = DISK_STATUS_UNINIT;
693 } else {
694 priv->status = DISK_STATUS_NOMEDIA;
695 }
696
697 stm32_sdmmc_info.dev = dev;
698 err = disk_access_register(&stm32_sdmmc_info);
699 if (err) {
700 goto err_pwr;
701 }
702 return 0;
703
704 err_pwr:
705 stm32_sdmmc_pwr_uninit(priv);
706 err_card_detect:
707 #if !defined(CONFIG_SDMMC_STM32_EMMC)
708 stm32_sdmmc_card_detect_uninit(priv);
709 #endif
710 return err;
711 }
712
713 #if DT_NODE_HAS_STATUS(DT_DRV_INST(0), okay)
714
715 #if STM32_SDMMC_USE_DMA
716
717 #define SDMMC_DMA_CHANNEL_INIT(dir, dir_cap) \
718 .dev = DEVICE_DT_GET(STM32_DMA_CTLR(0, dir)), \
719 .channel = DT_INST_DMAS_CELL_BY_NAME(0, dir, channel), \
720 .channel_nb = DT_DMAS_CELL_BY_NAME( \
721 DT_DRV_INST(0), dir, channel), \
722 .reg = (DMA_TypeDef *)DT_REG_ADDR( \
723 DT_PHANDLE_BY_NAME(DT_DRV_INST(0), dmas, dir)), \
724 .cfg = { \
725 .dma_slot = STM32_DMA_SLOT(0, dir, slot), \
726 .channel_priority = STM32_DMA_CONFIG_PRIORITY( \
727 STM32_DMA_CHANNEL_CONFIG(0, dir)), \
728 .dma_callback = stm32_sdmmc_dma_cb, \
729 .linked_channel = STM32_DMA_HAL_OVERRIDE, \
730 }, \
731
732
733 #define SDMMC_DMA_CHANNEL(dir, DIR) \
734 .dma_##dir = { \
735 COND_CODE_1(DT_INST_DMAS_HAS_NAME(0, dir), \
736 (SDMMC_DMA_CHANNEL_INIT(dir, DIR)), \
737 (NULL)) \
738 },
739
740 #else
741 #define SDMMC_DMA_CHANNEL(dir, DIR)
742 #endif
743
744 PINCTRL_DT_INST_DEFINE(0);
745
stm32_sdmmc_irq_config_func(const struct device * dev)746 static void stm32_sdmmc_irq_config_func(const struct device *dev)
747 {
748 IRQ_CONNECT(DT_INST_IRQN(0),
749 DT_INST_IRQ(0, priority),
750 stm32_sdmmc_isr, DEVICE_DT_INST_GET(0),
751 0);
752 irq_enable(DT_INST_IRQN(0));
753 }
754
755 #if DT_INST_PROP(0, bus_width) == 1
756 #define SDMMC_BUS_WIDTH SDMMC_BUS_WIDE_1B
757 #elif DT_INST_PROP(0, bus_width) == 4
758 #define SDMMC_BUS_WIDTH SDMMC_BUS_WIDE_4B
759 #elif DT_INST_PROP(0, bus_width) == 8
760 #define SDMMC_BUS_WIDTH SDMMC_BUS_WIDE_8B
761 #endif /* DT_INST_PROP(0, bus_width) */
762
763 static struct stm32_pclken pclken_sdmmc[] = STM32_DT_INST_CLOCKS(0);
764
765 static struct stm32_sdmmc_priv stm32_sdmmc_priv_1 = {
766 .irq_config = stm32_sdmmc_irq_config_func,
767 .hsd = {
768 .Instance = (MMC_TypeDef *)DT_INST_REG_ADDR(0),
769 .Init.BusWide = SDMMC_BUS_WIDTH,
770 #if DT_INST_NODE_HAS_PROP(0, clk_div)
771 .Init.ClockDiv = DT_INST_PROP(0, clk_div),
772 #endif
773 },
774 #if DT_INST_NODE_HAS_PROP(0, cd_gpios)
775 .cd = GPIO_DT_SPEC_INST_GET(0, cd_gpios),
776 #endif
777 #if DT_INST_NODE_HAS_PROP(0, pwr_gpios)
778 .pe = GPIO_DT_SPEC_INST_GET(0, pwr_gpios),
779 #endif
780 .pclken = pclken_sdmmc,
781 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
782 .reset = RESET_DT_SPEC_INST_GET(0),
783 SDMMC_DMA_CHANNEL(rx, RX)
784 SDMMC_DMA_CHANNEL(tx, TX)
785 };
786
787 DEVICE_DT_INST_DEFINE(0, disk_stm32_sdmmc_init, NULL,
788 &stm32_sdmmc_priv_1, NULL, POST_KERNEL,
789 CONFIG_SD_INIT_PRIORITY,
790 NULL);
791 #endif
792
